1 /* 2 ** DINO manager 3 ** 4 ** (c) Copyright 1999 Red Hat Software 5 ** (c) Copyright 1999 SuSE GmbH 6 ** (c) Copyright 1999,2000 Hewlett-Packard Company 7 ** (c) Copyright 2000 Grant Grundler 8 ** 9 ** This program is free software; you can redistribute it and/or modify 10 ** it under the terms of the GNU General Public License as published by 11 ** the Free Software Foundation; either version 2 of the License, or 12 ** (at your option) any later version. 13 ** 14 ** This module provides access to Dino PCI bus (config/IOport spaces) 15 ** and helps manage Dino IRQ lines. 16 ** 17 ** Dino interrupt handling is a bit complicated. 18 ** Dino always writes to the broadcast EIR via irr0 for now. 19 ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!) 20 ** Only one processor interrupt is used for the 11 IRQ line 21 ** inputs to dino. 22 ** 23 ** The different between Built-in Dino and Card-Mode 24 ** dino is in chip initialization and pci device initialization. 25 ** 26 ** Linux drivers can only use Card-Mode Dino if pci devices I/O port 27 ** BARs are configured and used by the driver. Programming MMIO address 28 ** requires substantial knowledge of available Host I/O address ranges 29 ** is currently not supported. Port/Config accessor functions are the 30 ** same. "BIOS" differences are handled within the existing routines. 31 */ 32 33 /* Changes : 34 ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr) 35 ** - added support for the integrated RS232. 36 */ 37 38 /* 39 ** TODO: create a virtual address for each Dino HPA. 40 ** GSC code might be able to do this since IODC data tells us 41 ** how many pages are used. PCI subsystem could (must?) do this 42 ** for PCI drivers devices which implement/use MMIO registers. 43 */ 44 45 #include <linux/config.h> 46 #include <linux/delay.h> 47 #include <linux/types.h> 48 #include <linux/kernel.h> 49 #include <linux/pci.h> 50 #include <linux/init.h> 51 #include <linux/ioport.h> 52 #include <linux/slab.h> 53 #include <linux/interrupt.h> /* for struct irqaction */ 54 #include <linux/spinlock.h> /* for spinlock_t and prototypes */ 55 56 #include <asm/pdc.h> 57 #include <asm/page.h> 58 #include <asm/system.h> 59 #include <asm/io.h> 60 #include <asm/hardware.h> 61 62 #include "gsc.h" 63 64 #undef DINO_DEBUG 65 66 #ifdef DINO_DEBUG 67 #define DBG(x...) printk(x) 68 #else 69 #define DBG(x...) 70 #endif 71 72 /* 73 ** Config accessor functions only pass in the 8-bit bus number 74 ** and not the 8-bit "PCI Segment" number. Each Dino will be 75 ** assigned a PCI bus number based on "when" it's discovered. 76 ** 77 ** The "secondary" bus number is set to this before calling 78 ** pci_scan_bus(). If any PPB's are present, the scan will 79 ** discover them and update the "secondary" and "subordinate" 80 ** fields in Dino's pci_bus structure. 81 ** 82 ** Changes in the configuration *will* result in a different 83 ** bus number for each dino. 84 */ 85 86 #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA) 87 88 #define DINO_IAR0 0x004 89 #define DINO_IODC_ADDR 0x008 90 #define DINO_IODC_DATA_0 0x008 91 #define DINO_IODC_DATA_1 0x008 92 #define DINO_IRR0 0x00C 93 #define DINO_IAR1 0x010 94 #define DINO_IRR1 0x014 95 #define DINO_IMR 0x018 96 #define DINO_IPR 0x01C 97 #define DINO_TOC_ADDR 0x020 98 #define DINO_ICR 0x024 99 #define DINO_ILR 0x028 100 #define DINO_IO_COMMAND 0x030 101 #define DINO_IO_STATUS 0x034 102 #define DINO_IO_CONTROL 0x038 103 #define DINO_IO_GSC_ERR_RESP 0x040 104 #define DINO_IO_ERR_INFO 0x044 105 #define DINO_IO_PCI_ERR_RESP 0x048 106 #define DINO_IO_FBB_EN 0x05c 107 #define DINO_IO_ADDR_EN 0x060 108 #define DINO_PCI_ADDR 0x064 109 #define DINO_CONFIG_DATA 0x068 110 #define DINO_IO_DATA 0x06c 111 #define DINO_MEM_DATA 0x070 /* Dino 3.x only */ 112 #define DINO_GSC2X_CONFIG 0x7b4 113 #define DINO_GMASK 0x800 114 #define DINO_PAMR 0x804 115 #define DINO_PAPR 0x808 116 #define DINO_DAMODE 0x80c 117 #define DINO_PCICMD 0x810 118 #define DINO_PCISTS 0x814 119 #define DINO_MLTIM 0x81c 120 #define DINO_BRDG_FEAT 0x820 121 #define DINO_PCIROR 0x824 122 #define DINO_PCIWOR 0x828 123 #define DINO_TLTIM 0x830 124 125 #define DINO_IRQS 11 /* bits 0-10 are architected */ 126 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ 127 128 #define DINO_MASK_IRQ(x) (1<<(x)) 129 130 #define PCIINTA 0x001 131 #define PCIINTB 0x002 132 #define PCIINTC 0x004 133 #define PCIINTD 0x008 134 #define PCIINTE 0x010 135 #define PCIINTF 0x020 136 #define GSCEXTINT 0x040 137 /* #define xxx 0x080 - bit 7 is "default" */ 138 /* #define xxx 0x100 - bit 8 not used */ 139 /* #define xxx 0x200 - bit 9 not used */ 140 #define RS232INT 0x400 141 142 struct dino_device 143 { 144 struct pci_hba_data hba; /* 'C' inheritance - must be first */ 145 spinlock_t dinosaur_pen; 146 unsigned long txn_addr; /* EIR addr to generate interrupt */ 147 u32 txn_data; /* EIR data assign to each dino */ 148 u32 imr; /* IRQ's which are enabled */ 149 int global_irq[12]; /* map IMR bit to global irq */ 150 #ifdef DINO_DEBUG 151 unsigned int dino_irr0; /* save most recent IRQ line stat */ 152 #endif 153 }; 154 155 /* Looks nice and keeps the compiler happy */ 156 #define DINO_DEV(d) ((struct dino_device *) d) 157 158 159 /* 160 * Dino Configuration Space Accessor Functions 161 */ 162 163 #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos))) 164 165 /* 166 * keep the current highest bus count to assist in allocating busses. This 167 * tries to keep a global bus count total so that when we discover an 168 * entirely new bus, it can be given a unique bus number. 169 */ 170 static int dino_current_bus = 0; 171 172 static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where, 173 int size, u32 *val) 174 { 175 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 176 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 177 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 178 void __iomem *base_addr = d->hba.base_addr; 179 unsigned long flags; 180 181 spin_lock_irqsave(&d->dinosaur_pen, flags); 182 183 /* tell HW which CFG address */ 184 __raw_writel(v, base_addr + DINO_PCI_ADDR); 185 186 /* generate cfg read cycle */ 187 if (size == 1) { 188 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); 189 } else if (size == 2) { 190 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); 191 } else if (size == 4) { 192 *val = readl(base_addr + DINO_CONFIG_DATA); 193 } 194 195 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 196 return 0; 197 } 198 199 /* 200 * Dino address stepping "feature": 201 * When address stepping, Dino attempts to drive the bus one cycle too soon 202 * even though the type of cycle (config vs. MMIO) might be different. 203 * The read of Ven/Prod ID is harmless and avoids Dino's address stepping. 204 */ 205 static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where, 206 int size, u32 val) 207 { 208 struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge)); 209 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 210 u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3); 211 void __iomem *base_addr = d->hba.base_addr; 212 unsigned long flags; 213 214 spin_lock_irqsave(&d->dinosaur_pen, flags); 215 216 /* avoid address stepping feature */ 217 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); 218 __raw_readl(base_addr + DINO_CONFIG_DATA); 219 220 /* tell HW which CFG address */ 221 __raw_writel(v, base_addr + DINO_PCI_ADDR); 222 /* generate cfg read cycle */ 223 if (size == 1) { 224 writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3)); 225 } else if (size == 2) { 226 writew(val, base_addr + DINO_CONFIG_DATA + (where & 2)); 227 } else if (size == 4) { 228 writel(val, base_addr + DINO_CONFIG_DATA); 229 } 230 231 spin_unlock_irqrestore(&d->dinosaur_pen, flags); 232 return 0; 233 } 234 235 static struct pci_ops dino_cfg_ops = { 236 .read = dino_cfg_read, 237 .write = dino_cfg_write, 238 }; 239 240 241 /* 242 * Dino "I/O Port" Space Accessor Functions 243 * 244 * Many PCI devices don't require use of I/O port space (eg Tulip, 245 * NCR720) since they export the same registers to both MMIO and 246 * I/O port space. Performance is going to stink if drivers use 247 * I/O port instead of MMIO. 248 */ 249 250 #define DINO_PORT_IN(type, size, mask) \ 251 static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \ 252 { \ 253 u##size v; \ 254 unsigned long flags; \ 255 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 256 /* tell HW which IO Port address */ \ 257 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 258 /* generate I/O PORT read cycle */ \ 259 v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \ 260 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 261 return v; \ 262 } 263 264 DINO_PORT_IN(b, 8, 3) 265 DINO_PORT_IN(w, 16, 2) 266 DINO_PORT_IN(l, 32, 0) 267 268 #define DINO_PORT_OUT(type, size, mask) \ 269 static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 270 { \ 271 unsigned long flags; \ 272 spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \ 273 /* tell HW which IO port address */ \ 274 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \ 275 /* generate cfg write cycle */ \ 276 write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \ 277 spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \ 278 } 279 280 DINO_PORT_OUT(b, 8, 3) 281 DINO_PORT_OUT(w, 16, 2) 282 DINO_PORT_OUT(l, 32, 0) 283 284 struct pci_port_ops dino_port_ops = { 285 .inb = dino_in8, 286 .inw = dino_in16, 287 .inl = dino_in32, 288 .outb = dino_out8, 289 .outw = dino_out16, 290 .outl = dino_out32 291 }; 292 293 static void dino_disable_irq(unsigned int irq) 294 { 295 struct dino_device *dino_dev = irq_desc[irq].handler_data; 296 int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, irq); 297 298 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, irq_dev, irq); 299 300 /* Clear the matching bit in the IMR register */ 301 dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq)); 302 __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 303 } 304 305 static void dino_enable_irq(unsigned int irq) 306 { 307 struct dino_device *dino_dev = irq_desc[irq].handler_data; 308 int local_irq = gsc_find_local_irq(irq, dino_dev->global_irq, irq); 309 u32 tmp; 310 311 DBG(KERN_WARNING "%s(0x%p, %d)\n", __FUNCTION__, irq_dev, irq); 312 313 /* 314 ** clear pending IRQ bits 315 ** 316 ** This does NOT change ILR state! 317 ** See comment below for ILR usage. 318 */ 319 __raw_readl(dino_dev->hba.base_addr+DINO_IPR); 320 321 /* set the matching bit in the IMR register */ 322 dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */ 323 __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); 324 325 /* Emulate "Level Triggered" Interrupt 326 ** Basically, a driver is blowing it if the IRQ line is asserted 327 ** while the IRQ is disabled. But tulip.c seems to do that.... 328 ** Give 'em a kluge award and a nice round of applause! 329 ** 330 ** The gsc_write will generate an interrupt which invokes dino_isr(). 331 ** dino_isr() will read IPR and find nothing. But then catch this 332 ** when it also checks ILR. 333 */ 334 tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR); 335 if (tmp & DINO_MASK_IRQ(local_irq)) { 336 DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n", 337 __FUNCTION__, tmp); 338 gsc_writel(dino_dev->txn_data, dino_dev->txn_addr); 339 } 340 } 341 342 static unsigned int dino_startup_irq(unsigned int irq) 343 { 344 dino_enable_irq(irq); 345 return 0; 346 } 347 348 static struct hw_interrupt_type dino_interrupt_type = { 349 .typename = "GSC-PCI", 350 .startup = dino_startup_irq, 351 .shutdown = dino_disable_irq, 352 .enable = dino_enable_irq, 353 .disable = dino_disable_irq, 354 .ack = no_ack_irq, 355 .end = no_end_irq, 356 }; 357 358 359 /* 360 * Handle a Processor interrupt generated by Dino. 361 * 362 * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from 363 * wedging the CPU. Could be removed or made optional at some point. 364 */ 365 static irqreturn_t 366 dino_isr(int irq, void *intr_dev, struct pt_regs *regs) 367 { 368 struct dino_device *dino_dev = intr_dev; 369 u32 mask; 370 int ilr_loop = 100; 371 372 /* read and acknowledge pending interrupts */ 373 #ifdef DINO_DEBUG 374 dino_dev->dino_irr0 = 375 #endif 376 mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK; 377 378 if (mask == 0) 379 return IRQ_NONE; 380 381 ilr_again: 382 do { 383 int local_irq = __ffs(mask); 384 int irq = dino_dev->global_irq[local_irq]; 385 DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n", 386 __FUNCTION__, irq, intr_dev, mask); 387 __do_IRQ(irq, regs); 388 mask &= ~(1 << local_irq); 389 } while (mask); 390 391 /* Support for level triggered IRQ lines. 392 ** 393 ** Dropping this support would make this routine *much* faster. 394 ** But since PCI requires level triggered IRQ line to share lines... 395 ** device drivers may assume lines are level triggered (and not 396 ** edge triggered like EISA/ISA can be). 397 */ 398 mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr; 399 if (mask) { 400 if (--ilr_loop > 0) 401 goto ilr_again; 402 printk(KERN_ERR "Dino 0x%p: stuck interrupt %d\n", 403 dino_dev->hba.base_addr, mask); 404 return IRQ_NONE; 405 } 406 return IRQ_HANDLED; 407 } 408 409 static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp) 410 { 411 int irq = gsc_assign_irq(&dino_interrupt_type, dino); 412 if (irq == NO_IRQ) 413 return; 414 415 *irqp = irq; 416 dino->global_irq[local_irq] = irq; 417 } 418 419 static void dino_choose_irq(struct parisc_device *dev, void *ctrl) 420 { 421 int irq; 422 struct dino_device *dino = ctrl; 423 424 switch (dev->id.sversion) { 425 case 0x00084: irq = 8; break; /* PS/2 */ 426 case 0x0008c: irq = 10; break; /* RS232 */ 427 case 0x00096: irq = 8; break; /* PS/2 */ 428 default: return; /* Unknown */ 429 } 430 431 dino_assign_irq(dino, irq, &dev->irq); 432 } 433 434 static void __init 435 dino_bios_init(void) 436 { 437 DBG("dino_bios_init\n"); 438 } 439 440 /* 441 * dino_card_setup - Set up the memory space for a Dino in card mode. 442 * @bus: the bus under this dino 443 * 444 * Claim an 8MB chunk of unused IO space and call the generic PCI routines 445 * to set up the addresses of the devices on this bus. 446 */ 447 #define _8MB 0x00800000UL 448 static void __init 449 dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) 450 { 451 int i; 452 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 453 struct resource *res; 454 char name[128]; 455 int size; 456 457 res = &dino_dev->hba.lmmio_space; 458 res->flags = IORESOURCE_MEM; 459 size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", 460 bus->bridge->bus_id); 461 res->name = kmalloc(size+1, GFP_KERNEL); 462 if(res->name) 463 strcpy((char *)res->name, name); 464 else 465 res->name = dino_dev->hba.lmmio_space.name; 466 467 468 if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB, 469 F_EXTEND(0xf0000000UL) | _8MB, 470 F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) { 471 struct list_head *ln, *tmp_ln; 472 473 printk(KERN_ERR "Dino: cannot attach bus %s\n", 474 bus->bridge->bus_id); 475 /* kill the bus, we can't do anything with it */ 476 list_for_each_safe(ln, tmp_ln, &bus->devices) { 477 struct pci_dev *dev = pci_dev_b(ln); 478 479 list_del(&dev->global_list); 480 list_del(&dev->bus_list); 481 } 482 483 return; 484 } 485 bus->resource[1] = res; 486 bus->resource[0] = &(dino_dev->hba.io_space); 487 488 /* Now tell dino what range it has */ 489 for (i = 1; i < 31; i++) { 490 if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB))) 491 break; 492 } 493 DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %lx\n", 494 i, res->start, base_addr + DINO_IO_ADDR_EN); 495 __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN); 496 } 497 498 static void __init 499 dino_card_fixup(struct pci_dev *dev) 500 { 501 u32 irq_pin; 502 503 /* 504 ** REVISIT: card-mode PCI-PCI expansion chassis do exist. 505 ** Not sure they were ever productized. 506 ** Die here since we'll die later in dino_inb() anyway. 507 */ 508 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 509 panic("Card-Mode Dino: PCI-PCI Bridge not supported\n"); 510 } 511 512 /* 513 ** Set Latency Timer to 0xff (not a shared bus) 514 ** Set CACHELINE_SIZE. 515 */ 516 dino_cfg_write(dev->bus, dev->devfn, 517 PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4); 518 519 /* 520 ** Program INT_LINE for card-mode devices. 521 ** The cards are hardwired according to this algorithm. 522 ** And it doesn't matter if PPB's are present or not since 523 ** the IRQ lines bypass the PPB. 524 ** 525 ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range. 526 ** The additional "-1" adjusts for skewing the IRQ<->slot. 527 */ 528 dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin); 529 dev->irq = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ; 530 531 /* Shouldn't really need to do this but it's in case someone tries 532 ** to bypass PCI services and look at the card themselves. 533 */ 534 dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq); 535 } 536 537 /* The alignment contraints for PCI bridges under dino */ 538 #define DINO_BRIDGE_ALIGN 0x100000 539 540 541 static void __init 542 dino_fixup_bus(struct pci_bus *bus) 543 { 544 struct list_head *ln; 545 struct pci_dev *dev; 546 struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge)); 547 int port_base = HBA_PORT_BASE(dino_dev->hba.hba_num); 548 549 DBG(KERN_WARNING "%s(0x%p) bus %d platform_data 0x%p\n", 550 __FUNCTION__, bus, bus->secondary, 551 bus->bridge->platform_data); 552 553 /* Firmware doesn't set up card-mode dino, so we have to */ 554 if (is_card_dino(&dino_dev->hba.dev->id)) { 555 dino_card_setup(bus, dino_dev->hba.base_addr); 556 } else if(bus->parent == NULL) { 557 /* must have a dino above it, reparent the resources 558 * into the dino window */ 559 int i; 560 struct resource *res = &dino_dev->hba.lmmio_space; 561 562 bus->resource[0] = &(dino_dev->hba.io_space); 563 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 564 if(res[i].flags == 0) 565 break; 566 bus->resource[i+1] = &res[i]; 567 } 568 569 } else if(bus->self) { 570 int i; 571 572 pci_read_bridge_bases(bus); 573 574 575 for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { 576 if((bus->self->resource[i].flags & 577 (IORESOURCE_IO | IORESOURCE_MEM)) == 0) 578 continue; 579 580 if(bus->self->resource[i].flags & IORESOURCE_MEM) { 581 /* There's a quirk to alignment of 582 * bridge memory resources: the start 583 * is the alignment and start-end is 584 * the size. However, firmware will 585 * have assigned start and end, so we 586 * need to take this into account */ 587 bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN; 588 bus->self->resource[i].start = DINO_BRIDGE_ALIGN; 589 590 } 591 592 DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n", 593 bus->self->dev.bus_id, i, 594 bus->self->resource[i].start, 595 bus->self->resource[i].end); 596 pci_assign_resource(bus->self, i); 597 DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n", 598 bus->self->dev.bus_id, i, 599 bus->self->resource[i].start, 600 bus->self->resource[i].end); 601 } 602 } 603 604 605 list_for_each(ln, &bus->devices) { 606 int i; 607 608 dev = pci_dev_b(ln); 609 if (is_card_dino(&dino_dev->hba.dev->id)) 610 dino_card_fixup(dev); 611 612 /* 613 ** P2PB's only have 2 BARs, no IRQs. 614 ** I'd like to just ignore them for now. 615 */ 616 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) 617 continue; 618 619 /* Adjust the I/O Port space addresses */ 620 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 621 struct resource *res = &dev->resource[i]; 622 if (res->flags & IORESOURCE_IO) { 623 res->start |= port_base; 624 res->end |= port_base; 625 } 626 #ifdef __LP64__ 627 /* Sign Extend MMIO addresses */ 628 else if (res->flags & IORESOURCE_MEM) { 629 res->start |= F_EXTEND(0UL); 630 res->end |= F_EXTEND(0UL); 631 } 632 #endif 633 } 634 /* null out the ROM resource if there is one (we don't 635 * care about an expansion rom on parisc, since it 636 * usually contains (x86) bios code) */ 637 dev->resource[PCI_ROM_RESOURCE].flags = 0; 638 639 if(dev->irq == 255) { 640 641 #define DINO_FIX_UNASSIGNED_INTERRUPTS 642 #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS 643 644 /* This code tries to assign an unassigned 645 * interrupt. Leave it disabled unless you 646 * *really* know what you're doing since the 647 * pin<->interrupt line mapping varies by bus 648 * and machine */ 649 650 u32 irq_pin; 651 652 dino_cfg_read(dev->bus, dev->devfn, 653 PCI_INTERRUPT_PIN, 1, &irq_pin); 654 irq_pin = (irq_pin + PCI_SLOT(dev->devfn) - 1) % 4 ; 655 printk(KERN_WARNING "Device %s has undefined IRQ, " 656 "setting to %d\n", pci_name(dev), irq_pin); 657 dino_cfg_write(dev->bus, dev->devfn, 658 PCI_INTERRUPT_LINE, 1, irq_pin); 659 dino_assign_irq(dino_dev, irq_pin, &dev->irq); 660 #else 661 dev->irq = 65535; 662 printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev)); 663 #endif 664 } else { 665 666 /* Adjust INT_LINE for that busses region */ 667 dino_assign_irq(dino_dev, dev->irq, &dev->irq); 668 } 669 } 670 } 671 672 673 struct pci_bios_ops dino_bios_ops = { 674 .init = dino_bios_init, 675 .fixup_bus = dino_fixup_bus 676 }; 677 678 679 /* 680 * Initialise a DINO controller chip 681 */ 682 static void __init 683 dino_card_init(struct dino_device *dino_dev) 684 { 685 u32 brdg_feat = 0x00784e05; 686 687 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK); 688 __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN); 689 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR); 690 691 #if 1 692 /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */ 693 /* 694 ** PCX-L processors don't support XQL like Dino wants it. 695 ** PCX-L2 ignore XQL signal and it doesn't matter. 696 */ 697 brdg_feat &= ~0x4; /* UXQL */ 698 #endif 699 __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT); 700 701 /* 702 ** Don't enable address decoding until we know which I/O range 703 ** currently is available from the host. Only affects MMIO 704 ** and not I/O port space. 705 */ 706 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN); 707 708 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE); 709 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR); 710 __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR); 711 712 __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM); 713 __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL); 714 __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM); 715 716 /* Disable PAMR before writing PAPR */ 717 __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR); 718 __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR); 719 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR); 720 721 /* 722 ** Dino ERS encourages enabling FBB (0x6f). 723 ** We can't until we know *all* devices below us can support it. 724 ** (Something in device configuration header tells us). 725 */ 726 __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD); 727 728 /* Somewhere, the PCI spec says give devices 1 second 729 ** to recover from the #RESET being de-asserted. 730 ** Experience shows most devices only need 10ms. 731 ** This short-cut speeds up booting significantly. 732 */ 733 mdelay(pci_post_reset_delay); 734 } 735 736 static int __init 737 dino_bridge_init(struct dino_device *dino_dev, const char *name) 738 { 739 unsigned long io_addr; 740 int result, i, count=0; 741 struct resource *res, *prevres = NULL; 742 /* 743 * Decoding IO_ADDR_EN only works for Built-in Dino 744 * since PDC has already initialized this. 745 */ 746 747 io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN); 748 if (io_addr == 0) { 749 printk(KERN_WARNING "%s: No PCI devices enabled.\n", name); 750 return -ENODEV; 751 } 752 753 res = &dino_dev->hba.lmmio_space; 754 for (i = 0; i < 32; i++) { 755 unsigned long start, end; 756 757 if((io_addr & (1 << i)) == 0) 758 continue; 759 760 start = (unsigned long)(signed int)(0xf0000000 | (i << 23)); 761 end = start + 8 * 1024 * 1024 - 1; 762 763 DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count, 764 start, end); 765 766 if(prevres && prevres->end + 1 == start) { 767 prevres->end = end; 768 } else { 769 if(count >= DINO_MAX_LMMIO_RESOURCES) { 770 printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end); 771 break; 772 } 773 prevres = res; 774 res->start = start; 775 res->end = end; 776 res->flags = IORESOURCE_MEM; 777 res->name = kmalloc(64, GFP_KERNEL); 778 if(res->name) 779 snprintf((char *)res->name, 64, "%s LMMIO %d", 780 name, count); 781 res++; 782 count++; 783 } 784 } 785 786 res = &dino_dev->hba.lmmio_space; 787 788 for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) { 789 if(res[i].flags == 0) 790 break; 791 792 result = ccio_request_resource(dino_dev->hba.dev, &res[i]); 793 if (result < 0) { 794 printk(KERN_ERR "%s: failed to claim PCI Bus address space %d (0x%lx-0x%lx)!\n", name, i, res[i].start, res[i].end); 795 return result; 796 } 797 } 798 return 0; 799 } 800 801 static int __init dino_common_init(struct parisc_device *dev, 802 struct dino_device *dino_dev, const char *name) 803 { 804 int status; 805 u32 eim; 806 struct gsc_irq gsc_irq; 807 struct resource *res; 808 809 pcibios_register_hba(&dino_dev->hba); 810 811 pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */ 812 pci_port = &dino_port_ops; 813 814 /* 815 ** Note: SMP systems can make use of IRR1/IAR1 registers 816 ** But it won't buy much performance except in very 817 ** specific applications/configurations. Note Dino 818 ** still only has 11 IRQ input lines - just map some of them 819 ** to a different processor. 820 */ 821 dev->irq = gsc_alloc_irq(&gsc_irq); 822 dino_dev->txn_addr = gsc_irq.txn_addr; 823 dino_dev->txn_data = gsc_irq.txn_data; 824 eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data; 825 826 /* 827 ** Dino needs a PA "IRQ" to get a processor's attention. 828 ** arch/parisc/kernel/irq.c returns an EIRR bit. 829 */ 830 if (dev->irq < 0) { 831 printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name); 832 return 1; 833 } 834 835 status = request_irq(dev->irq, dino_isr, 0, name, dino_dev); 836 if (status) { 837 printk(KERN_WARNING "%s: request_irq() failed with %d\n", 838 name, status); 839 return 1; 840 } 841 842 /* Support the serial port which is sometimes attached on built-in 843 * Dino / Cujo chips. 844 */ 845 846 gsc_fixup_irqs(dev, dino_dev, dino_choose_irq); 847 848 /* 849 ** This enables DINO to generate interrupts when it sees 850 ** any of its inputs *change*. Just asserting an IRQ 851 ** before it's enabled (ie unmasked) isn't good enough. 852 */ 853 __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0); 854 855 /* 856 ** Some platforms don't clear Dino's IRR0 register at boot time. 857 ** Reading will clear it now. 858 */ 859 __raw_readl(dino_dev->hba.base_addr+DINO_IRR0); 860 861 /* allocate I/O Port resource region */ 862 res = &dino_dev->hba.io_space; 863 if (dev->id.hversion == 0x680 || is_card_dino(&dev->id)) { 864 res->name = "Dino I/O Port"; 865 } else { 866 res->name = "Cujo I/O Port"; 867 } 868 res->start = HBA_PORT_BASE(dino_dev->hba.hba_num); 869 res->end = res->start + (HBA_PORT_SPACE_SIZE - 1); 870 res->flags = IORESOURCE_IO; /* do not mark it busy ! */ 871 if (request_resource(&ioport_resource, res) < 0) { 872 printk(KERN_ERR "%s: request I/O Port region failed " 873 "0x%lx/%lx (hpa 0x%p)\n", 874 name, res->start, res->end, dino_dev->hba.base_addr); 875 return 1; 876 } 877 878 return 0; 879 } 880 881 #define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL) 882 #define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL) 883 #define CUJO_RAVEN_BADPAGE 0x01003000UL 884 #define CUJO_FIREHAWK_BADPAGE 0x01607000UL 885 886 static const char *dino_vers[] = { 887 "2.0", 888 "2.1", 889 "3.0", 890 "3.1" 891 }; 892 893 static const char *cujo_vers[] = { 894 "1.0", 895 "2.0" 896 }; 897 898 void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp); 899 900 /* 901 ** Determine if dino should claim this chip (return 0) or not (return 1). 902 ** If so, initialize the chip appropriately (card-mode vs bridge mode). 903 ** Much of the initialization is common though. 904 */ 905 static int __init 906 dino_driver_callback(struct parisc_device *dev) 907 { 908 struct dino_device *dino_dev; // Dino specific control struct 909 const char *version = "unknown"; 910 char *name; 911 int is_cujo = 0; 912 struct pci_bus *bus; 913 914 name = "Dino"; 915 if (is_card_dino(&dev->id)) { 916 version = "3.x (card mode)"; 917 } else { 918 if(dev->id.hversion == 0x680) { 919 if (dev->id.hversion_rev < 4) { 920 version = dino_vers[dev->id.hversion_rev]; 921 } 922 } else { 923 name = "Cujo"; 924 is_cujo = 1; 925 if (dev->id.hversion_rev < 2) { 926 version = cujo_vers[dev->id.hversion_rev]; 927 } 928 } 929 } 930 931 printk("%s version %s found at 0x%lx\n", name, version, dev->hpa); 932 933 if (!request_mem_region(dev->hpa, PAGE_SIZE, name)) { 934 printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%ld)!\n", 935 dev->hpa); 936 return 1; 937 } 938 939 /* Check for bugs */ 940 if (is_cujo && dev->id.hversion_rev == 1) { 941 #ifdef CONFIG_IOMMU_CCIO 942 printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n"); 943 if (dev->hpa == (unsigned long)CUJO_RAVEN_ADDR) { 944 ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE); 945 } else if (dev->hpa == (unsigned long)CUJO_FIREHAWK_ADDR) { 946 ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE); 947 } else { 948 printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", dev->hpa); 949 } 950 #endif 951 } else if (!is_cujo && !is_card_dino(&dev->id) && 952 dev->id.hversion_rev < 3) { 953 printk(KERN_WARNING 954 "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n" 955 "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n" 956 "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n" 957 "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n", 958 dev->id.hversion_rev); 959 /* REVISIT: why are C200/C240 listed in the README table but not 960 ** "Models affected"? Could be an omission in the original literature. 961 */ 962 } 963 964 dino_dev = kmalloc(sizeof(struct dino_device), GFP_KERNEL); 965 if (!dino_dev) { 966 printk("dino_init_chip - couldn't alloc dino_device\n"); 967 return 1; 968 } 969 970 memset(dino_dev, 0, sizeof(struct dino_device)); 971 972 dino_dev->hba.dev = dev; 973 dino_dev->hba.base_addr = ioremap(dev->hpa, 4096); /* faster access */ 974 dino_dev->hba.lmmio_space_offset = 0; /* CPU addrs == bus addrs */ 975 spin_lock_init(&dino_dev->dinosaur_pen); 976 dino_dev->hba.iommu = ccio_get_iommu(dev); 977 978 if (is_card_dino(&dev->id)) { 979 dino_card_init(dino_dev); 980 } else { 981 dino_bridge_init(dino_dev, name); 982 } 983 984 if (dino_common_init(dev, dino_dev, name)) 985 return 1; 986 987 dev->dev.platform_data = dino_dev; 988 989 /* 990 ** It's not used to avoid chicken/egg problems 991 ** with configuration accessor functions. 992 */ 993 bus = pci_scan_bus_parented(&dev->dev, dino_current_bus, 994 &dino_cfg_ops, NULL); 995 if(bus) { 996 pci_bus_add_devices(bus); 997 /* This code *depends* on scanning being single threaded 998 * if it isn't, this global bus number count will fail 999 */ 1000 dino_current_bus = bus->subordinate + 1; 1001 pci_bus_assign_resources(bus); 1002 } else { 1003 printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n", dev->dev.bus_id, dino_current_bus); 1004 /* increment the bus number in case of duplicates */ 1005 dino_current_bus++; 1006 } 1007 dino_dev->hba.hba_bus = bus; 1008 return 0; 1009 } 1010 1011 /* 1012 * Normally, we would just test sversion. But the Elroy PCI adapter has 1013 * the same sversion as Dino, so we have to check hversion as well. 1014 * Unfortunately, the J2240 PDC reports the wrong hversion for the first 1015 * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240. 1016 * For card-mode Dino, most machines report an sversion of 9D. But 715 1017 * and 725 firmware misreport it as 0x08080 for no adequately explained 1018 * reason. 1019 */ 1020 static struct parisc_device_id dino_tbl[] = { 1021 { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */ 1022 { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */ 1023 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */ 1024 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */ 1025 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */ 1026 { 0, } 1027 }; 1028 1029 static struct parisc_driver dino_driver = { 1030 .name = "dino", 1031 .id_table = dino_tbl, 1032 .probe = dino_probe, 1033 }; 1034 1035 /* 1036 * One time initialization to let the world know Dino is here. 1037 * This is the only routine which is NOT static. 1038 * Must be called exactly once before pci_init(). 1039 */ 1040 int __init dino_init(void) 1041 { 1042 register_parisc_driver(&dino_driver); 1043 return 0; 1044 } 1045 1046