103a69568SZhengShunQian /* 203a69568SZhengShunQian * Rockchip eFuse Driver 303a69568SZhengShunQian * 403a69568SZhengShunQian * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 503a69568SZhengShunQian * Author: Caesar Wang <wxt@rock-chips.com> 603a69568SZhengShunQian * 703a69568SZhengShunQian * This program is free software; you can redistribute it and/or modify it 803a69568SZhengShunQian * under the terms of version 2 of the GNU General Public License as 903a69568SZhengShunQian * published by the Free Software Foundation. 1003a69568SZhengShunQian * 1103a69568SZhengShunQian * This program is distributed in the hope that it will be useful, but WITHOUT 1203a69568SZhengShunQian * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1303a69568SZhengShunQian * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1403a69568SZhengShunQian * more details. 1503a69568SZhengShunQian */ 1603a69568SZhengShunQian 17c37ff3fbSCaesar Wang #include <linux/clk.h> 18c37ff3fbSCaesar Wang #include <linux/delay.h> 1903a69568SZhengShunQian #include <linux/device.h> 2003a69568SZhengShunQian #include <linux/io.h> 2103a69568SZhengShunQian #include <linux/module.h> 22c37ff3fbSCaesar Wang #include <linux/nvmem-provider.h> 23c37ff3fbSCaesar Wang #include <linux/slab.h> 2403a69568SZhengShunQian #include <linux/of.h> 2502baff32SFinley Xiao #include <linux/of_platform.h> 26c37ff3fbSCaesar Wang #include <linux/platform_device.h> 2703a69568SZhengShunQian 2802baff32SFinley Xiao #define RK3288_A_SHIFT 6 2902baff32SFinley Xiao #define RK3288_A_MASK 0x3ff 3002baff32SFinley Xiao #define RK3288_PGENB BIT(3) 3102baff32SFinley Xiao #define RK3288_LOAD BIT(2) 3202baff32SFinley Xiao #define RK3288_STROBE BIT(1) 3302baff32SFinley Xiao #define RK3288_CSB BIT(0) 3402baff32SFinley Xiao 3502baff32SFinley Xiao #define RK3399_A_SHIFT 16 3602baff32SFinley Xiao #define RK3399_A_MASK 0x3ff 3702baff32SFinley Xiao #define RK3399_NBYTES 4 3802baff32SFinley Xiao #define RK3399_STROBSFTSEL BIT(9) 3902baff32SFinley Xiao #define RK3399_RSB BIT(7) 4002baff32SFinley Xiao #define RK3399_PD BIT(5) 4102baff32SFinley Xiao #define RK3399_PGENB BIT(3) 4202baff32SFinley Xiao #define RK3399_LOAD BIT(2) 4302baff32SFinley Xiao #define RK3399_STROBE BIT(1) 4402baff32SFinley Xiao #define RK3399_CSB BIT(0) 4503a69568SZhengShunQian 4603a69568SZhengShunQian #define REG_EFUSE_CTRL 0x0000 4703a69568SZhengShunQian #define REG_EFUSE_DOUT 0x0004 4803a69568SZhengShunQian 49c37ff3fbSCaesar Wang struct rockchip_efuse_chip { 5003a69568SZhengShunQian struct device *dev; 5103a69568SZhengShunQian void __iomem *base; 52c37ff3fbSCaesar Wang struct clk *clk; 5303a69568SZhengShunQian }; 5403a69568SZhengShunQian 5502baff32SFinley Xiao static int rockchip_rk3288_efuse_read(void *context, unsigned int offset, 56cc907553SSrinivas Kandagatla void *val, size_t bytes) 5703a69568SZhengShunQian { 58c37ff3fbSCaesar Wang struct rockchip_efuse_chip *efuse = context; 5903a69568SZhengShunQian u8 *buf = val; 6003a69568SZhengShunQian int ret; 6103a69568SZhengShunQian 62c37ff3fbSCaesar Wang ret = clk_prepare_enable(efuse->clk); 6303a69568SZhengShunQian if (ret < 0) { 64c37ff3fbSCaesar Wang dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); 6503a69568SZhengShunQian return ret; 6603a69568SZhengShunQian } 6703a69568SZhengShunQian 6802baff32SFinley Xiao writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); 6903a69568SZhengShunQian udelay(1); 70cc907553SSrinivas Kandagatla while (bytes--) { 71c37ff3fbSCaesar Wang writel(readl(efuse->base + REG_EFUSE_CTRL) & 7202baff32SFinley Xiao (~(RK3288_A_MASK << RK3288_A_SHIFT)), 73c37ff3fbSCaesar Wang efuse->base + REG_EFUSE_CTRL); 74c37ff3fbSCaesar Wang writel(readl(efuse->base + REG_EFUSE_CTRL) | 7502baff32SFinley Xiao ((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT), 76c37ff3fbSCaesar Wang efuse->base + REG_EFUSE_CTRL); 7703a69568SZhengShunQian udelay(1); 78c37ff3fbSCaesar Wang writel(readl(efuse->base + REG_EFUSE_CTRL) | 7902baff32SFinley Xiao RK3288_STROBE, efuse->base + REG_EFUSE_CTRL); 8003a69568SZhengShunQian udelay(1); 81c37ff3fbSCaesar Wang *buf++ = readb(efuse->base + REG_EFUSE_DOUT); 82c37ff3fbSCaesar Wang writel(readl(efuse->base + REG_EFUSE_CTRL) & 8302baff32SFinley Xiao (~RK3288_STROBE), efuse->base + REG_EFUSE_CTRL); 8403a69568SZhengShunQian udelay(1); 8503a69568SZhengShunQian } 8603a69568SZhengShunQian 8703a69568SZhengShunQian /* Switch to standby mode */ 8802baff32SFinley Xiao writel(RK3288_PGENB | RK3288_CSB, efuse->base + REG_EFUSE_CTRL); 8902baff32SFinley Xiao 9002baff32SFinley Xiao clk_disable_unprepare(efuse->clk); 9102baff32SFinley Xiao 9202baff32SFinley Xiao return 0; 9302baff32SFinley Xiao } 9402baff32SFinley Xiao 9502baff32SFinley Xiao static int rockchip_rk3399_efuse_read(void *context, unsigned int offset, 9602baff32SFinley Xiao void *val, size_t bytes) 9702baff32SFinley Xiao { 9802baff32SFinley Xiao struct rockchip_efuse_chip *efuse = context; 9902baff32SFinley Xiao unsigned int addr_start, addr_end, addr_offset, addr_len; 10002baff32SFinley Xiao u32 out_value; 10102baff32SFinley Xiao u8 *buf; 10202baff32SFinley Xiao int ret, i = 0; 10302baff32SFinley Xiao 10402baff32SFinley Xiao ret = clk_prepare_enable(efuse->clk); 10502baff32SFinley Xiao if (ret < 0) { 10602baff32SFinley Xiao dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); 10702baff32SFinley Xiao return ret; 10802baff32SFinley Xiao } 10902baff32SFinley Xiao 11002baff32SFinley Xiao addr_start = rounddown(offset, RK3399_NBYTES) / RK3399_NBYTES; 11102baff32SFinley Xiao addr_end = roundup(offset + bytes, RK3399_NBYTES) / RK3399_NBYTES; 11202baff32SFinley Xiao addr_offset = offset % RK3399_NBYTES; 11302baff32SFinley Xiao addr_len = addr_end - addr_start; 11402baff32SFinley Xiao 11502baff32SFinley Xiao buf = kzalloc(sizeof(*buf) * addr_len * RK3399_NBYTES, GFP_KERNEL); 11602baff32SFinley Xiao if (!buf) { 11702baff32SFinley Xiao clk_disable_unprepare(efuse->clk); 11802baff32SFinley Xiao return -ENOMEM; 11902baff32SFinley Xiao } 12002baff32SFinley Xiao 12102baff32SFinley Xiao writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB, 12202baff32SFinley Xiao efuse->base + REG_EFUSE_CTRL); 12302baff32SFinley Xiao udelay(1); 12402baff32SFinley Xiao while (addr_len--) { 12502baff32SFinley Xiao writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE | 12602baff32SFinley Xiao ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT), 12702baff32SFinley Xiao efuse->base + REG_EFUSE_CTRL); 12802baff32SFinley Xiao udelay(1); 12902baff32SFinley Xiao out_value = readl(efuse->base + REG_EFUSE_DOUT); 13002baff32SFinley Xiao writel(readl(efuse->base + REG_EFUSE_CTRL) & (~RK3399_STROBE), 13102baff32SFinley Xiao efuse->base + REG_EFUSE_CTRL); 13202baff32SFinley Xiao udelay(1); 13302baff32SFinley Xiao 13402baff32SFinley Xiao memcpy(&buf[i], &out_value, RK3399_NBYTES); 13502baff32SFinley Xiao i += RK3399_NBYTES; 13602baff32SFinley Xiao } 13702baff32SFinley Xiao 13802baff32SFinley Xiao /* Switch to standby mode */ 13902baff32SFinley Xiao writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL); 14002baff32SFinley Xiao 14102baff32SFinley Xiao memcpy(val, buf + addr_offset, bytes); 14202baff32SFinley Xiao 14302baff32SFinley Xiao kfree(buf); 14403a69568SZhengShunQian 145c37ff3fbSCaesar Wang clk_disable_unprepare(efuse->clk); 14603a69568SZhengShunQian 14703a69568SZhengShunQian return 0; 14803a69568SZhengShunQian } 14903a69568SZhengShunQian 15003a69568SZhengShunQian static struct nvmem_config econfig = { 15103a69568SZhengShunQian .name = "rockchip-efuse", 15203a69568SZhengShunQian .owner = THIS_MODULE, 153cc907553SSrinivas Kandagatla .stride = 1, 154cc907553SSrinivas Kandagatla .word_size = 1, 15503a69568SZhengShunQian .read_only = true, 15603a69568SZhengShunQian }; 15703a69568SZhengShunQian 15803a69568SZhengShunQian static const struct of_device_id rockchip_efuse_match[] = { 15902baff32SFinley Xiao /* deprecated but kept around for dts binding compatibility */ 16002baff32SFinley Xiao { 16102baff32SFinley Xiao .compatible = "rockchip,rockchip-efuse", 16202baff32SFinley Xiao .data = (void *)&rockchip_rk3288_efuse_read, 16302baff32SFinley Xiao }, 16402baff32SFinley Xiao { 16502baff32SFinley Xiao .compatible = "rockchip,rk3066a-efuse", 16602baff32SFinley Xiao .data = (void *)&rockchip_rk3288_efuse_read, 16702baff32SFinley Xiao }, 16802baff32SFinley Xiao { 16902baff32SFinley Xiao .compatible = "rockchip,rk3188-efuse", 17002baff32SFinley Xiao .data = (void *)&rockchip_rk3288_efuse_read, 17102baff32SFinley Xiao }, 17202baff32SFinley Xiao { 173*d6e4bd1bSFrank Wang .compatible = "rockchip,rk3228-efuse", 174820de1fbSFinley Xiao .data = (void *)&rockchip_rk3288_efuse_read, 175820de1fbSFinley Xiao }, 176820de1fbSFinley Xiao { 17702baff32SFinley Xiao .compatible = "rockchip,rk3288-efuse", 17802baff32SFinley Xiao .data = (void *)&rockchip_rk3288_efuse_read, 17902baff32SFinley Xiao }, 18002baff32SFinley Xiao { 18102baff32SFinley Xiao .compatible = "rockchip,rk3399-efuse", 18202baff32SFinley Xiao .data = (void *)&rockchip_rk3399_efuse_read, 18302baff32SFinley Xiao }, 18403a69568SZhengShunQian { /* sentinel */}, 18503a69568SZhengShunQian }; 18603a69568SZhengShunQian MODULE_DEVICE_TABLE(of, rockchip_efuse_match); 18703a69568SZhengShunQian 1887e532f79Skbuild test robot static int rockchip_efuse_probe(struct platform_device *pdev) 18903a69568SZhengShunQian { 19003a69568SZhengShunQian struct resource *res; 19103a69568SZhengShunQian struct nvmem_device *nvmem; 192c37ff3fbSCaesar Wang struct rockchip_efuse_chip *efuse; 19302baff32SFinley Xiao const struct of_device_id *match; 19402baff32SFinley Xiao struct device *dev = &pdev->dev; 19502baff32SFinley Xiao 19602baff32SFinley Xiao match = of_match_device(dev->driver->of_match_table, dev); 19702baff32SFinley Xiao if (!match || !match->data) { 19802baff32SFinley Xiao dev_err(dev, "failed to get match data\n"); 19902baff32SFinley Xiao return -EINVAL; 20002baff32SFinley Xiao } 201c37ff3fbSCaesar Wang 202c37ff3fbSCaesar Wang efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip), 203c37ff3fbSCaesar Wang GFP_KERNEL); 204c37ff3fbSCaesar Wang if (!efuse) 205c37ff3fbSCaesar Wang return -ENOMEM; 20603a69568SZhengShunQian 20703a69568SZhengShunQian res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 208c37ff3fbSCaesar Wang efuse->base = devm_ioremap_resource(&pdev->dev, res); 209c37ff3fbSCaesar Wang if (IS_ERR(efuse->base)) 210c37ff3fbSCaesar Wang return PTR_ERR(efuse->base); 21103a69568SZhengShunQian 212c37ff3fbSCaesar Wang efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse"); 213c37ff3fbSCaesar Wang if (IS_ERR(efuse->clk)) 214c37ff3fbSCaesar Wang return PTR_ERR(efuse->clk); 21503a69568SZhengShunQian 216c37ff3fbSCaesar Wang efuse->dev = &pdev->dev; 217cc907553SSrinivas Kandagatla econfig.size = resource_size(res); 21802baff32SFinley Xiao econfig.reg_read = match->data; 219cc907553SSrinivas Kandagatla econfig.priv = efuse; 220c37ff3fbSCaesar Wang econfig.dev = efuse->dev; 22103a69568SZhengShunQian nvmem = nvmem_register(&econfig); 22203a69568SZhengShunQian if (IS_ERR(nvmem)) 22303a69568SZhengShunQian return PTR_ERR(nvmem); 22403a69568SZhengShunQian 22503a69568SZhengShunQian platform_set_drvdata(pdev, nvmem); 22603a69568SZhengShunQian 22703a69568SZhengShunQian return 0; 22803a69568SZhengShunQian } 22903a69568SZhengShunQian 2307e532f79Skbuild test robot static int rockchip_efuse_remove(struct platform_device *pdev) 23103a69568SZhengShunQian { 23203a69568SZhengShunQian struct nvmem_device *nvmem = platform_get_drvdata(pdev); 23303a69568SZhengShunQian 23403a69568SZhengShunQian return nvmem_unregister(nvmem); 23503a69568SZhengShunQian } 23603a69568SZhengShunQian 23703a69568SZhengShunQian static struct platform_driver rockchip_efuse_driver = { 23803a69568SZhengShunQian .probe = rockchip_efuse_probe, 23903a69568SZhengShunQian .remove = rockchip_efuse_remove, 24003a69568SZhengShunQian .driver = { 24103a69568SZhengShunQian .name = "rockchip-efuse", 24203a69568SZhengShunQian .of_match_table = rockchip_efuse_match, 24303a69568SZhengShunQian }, 24403a69568SZhengShunQian }; 24503a69568SZhengShunQian 24603a69568SZhengShunQian module_platform_driver(rockchip_efuse_driver); 24703a69568SZhengShunQian MODULE_DESCRIPTION("rockchip_efuse driver"); 24803a69568SZhengShunQian MODULE_LICENSE("GPL v2"); 249