xref: /openbmc/linux/drivers/nvmem/qoriq-efuse.c (revision c900529f3d9161bfde5cca0754f83b4d3c3e0220)
1*0861110bSRichard Alpe // SPDX-License-Identifier: GPL-2.0
2*0861110bSRichard Alpe /*
3*0861110bSRichard Alpe  *  Copyright (C) 2023  Westermo Network Technologies AB
4*0861110bSRichard Alpe  */
5*0861110bSRichard Alpe 
6*0861110bSRichard Alpe #include <linux/device.h>
7*0861110bSRichard Alpe #include <linux/io.h>
8*0861110bSRichard Alpe #include <linux/module.h>
9*0861110bSRichard Alpe #include <linux/mod_devicetable.h>
10*0861110bSRichard Alpe #include <linux/nvmem-provider.h>
11*0861110bSRichard Alpe #include <linux/platform_device.h>
12*0861110bSRichard Alpe 
13*0861110bSRichard Alpe struct qoriq_efuse_priv {
14*0861110bSRichard Alpe 	void __iomem *base;
15*0861110bSRichard Alpe };
16*0861110bSRichard Alpe 
qoriq_efuse_read(void * context,unsigned int offset,void * val,size_t bytes)17*0861110bSRichard Alpe static int qoriq_efuse_read(void *context, unsigned int offset, void *val,
18*0861110bSRichard Alpe 			    size_t bytes)
19*0861110bSRichard Alpe {
20*0861110bSRichard Alpe 	struct qoriq_efuse_priv *priv = context;
21*0861110bSRichard Alpe 
22*0861110bSRichard Alpe 	/* .stride = 4 so offset is guaranteed to be aligned */
23*0861110bSRichard Alpe 	__ioread32_copy(val, priv->base + offset, bytes / 4);
24*0861110bSRichard Alpe 
25*0861110bSRichard Alpe 	/* Ignore trailing bytes (there shouldn't be any) */
26*0861110bSRichard Alpe 
27*0861110bSRichard Alpe 	return 0;
28*0861110bSRichard Alpe }
29*0861110bSRichard Alpe 
qoriq_efuse_probe(struct platform_device * pdev)30*0861110bSRichard Alpe static int qoriq_efuse_probe(struct platform_device *pdev)
31*0861110bSRichard Alpe {
32*0861110bSRichard Alpe 	struct nvmem_config config = {
33*0861110bSRichard Alpe 		.dev = &pdev->dev,
34*0861110bSRichard Alpe 		.read_only = true,
35*0861110bSRichard Alpe 		.reg_read = qoriq_efuse_read,
36*0861110bSRichard Alpe 		.stride = sizeof(u32),
37*0861110bSRichard Alpe 		.word_size = sizeof(u32),
38*0861110bSRichard Alpe 		.name = "qoriq_efuse_read",
39*0861110bSRichard Alpe 		.id = NVMEM_DEVID_AUTO,
40*0861110bSRichard Alpe 		.root_only = true,
41*0861110bSRichard Alpe 	};
42*0861110bSRichard Alpe 	struct qoriq_efuse_priv *priv;
43*0861110bSRichard Alpe 	struct nvmem_device *nvmem;
44*0861110bSRichard Alpe 	struct resource *res;
45*0861110bSRichard Alpe 
46*0861110bSRichard Alpe 	priv = devm_kzalloc(config.dev, sizeof(*priv), GFP_KERNEL);
47*0861110bSRichard Alpe 	if (!priv)
48*0861110bSRichard Alpe 		return -ENOMEM;
49*0861110bSRichard Alpe 
50*0861110bSRichard Alpe 	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
51*0861110bSRichard Alpe 	if (IS_ERR(priv->base))
52*0861110bSRichard Alpe 		return PTR_ERR(priv->base);
53*0861110bSRichard Alpe 
54*0861110bSRichard Alpe 	config.size = resource_size(res);
55*0861110bSRichard Alpe 	config.priv = priv;
56*0861110bSRichard Alpe 	nvmem = devm_nvmem_register(config.dev, &config);
57*0861110bSRichard Alpe 
58*0861110bSRichard Alpe 	return PTR_ERR_OR_ZERO(nvmem);
59*0861110bSRichard Alpe }
60*0861110bSRichard Alpe 
61*0861110bSRichard Alpe static const struct of_device_id qoriq_efuse_of_match[] = {
62*0861110bSRichard Alpe 	{ .compatible = "fsl,t1023-sfp", },
63*0861110bSRichard Alpe 	{/* sentinel */},
64*0861110bSRichard Alpe };
65*0861110bSRichard Alpe MODULE_DEVICE_TABLE(of, qoriq_efuse_of_match);
66*0861110bSRichard Alpe 
67*0861110bSRichard Alpe static struct platform_driver qoriq_efuse_driver = {
68*0861110bSRichard Alpe 	.probe = qoriq_efuse_probe,
69*0861110bSRichard Alpe 	.driver = {
70*0861110bSRichard Alpe 		.name = "qoriq-efuse",
71*0861110bSRichard Alpe 		.of_match_table = qoriq_efuse_of_match,
72*0861110bSRichard Alpe 	},
73*0861110bSRichard Alpe };
74*0861110bSRichard Alpe module_platform_driver(qoriq_efuse_driver);
75*0861110bSRichard Alpe 
76*0861110bSRichard Alpe MODULE_AUTHOR("Richard Alpe <richard.alpe@bit42.se>");
77*0861110bSRichard Alpe MODULE_DESCRIPTION("NXP QorIQ Security Fuse Processor (SFP) Reader");
78*0861110bSRichard Alpe MODULE_LICENSE("GPL");
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