1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/device.h> 8 #include <linux/io.h> 9 #include <linux/iopoll.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/nvmem-provider.h> 14 #include <linux/platform_device.h> 15 #include <linux/property.h> 16 #include <linux/regulator/consumer.h> 17 18 /* Blow timer clock frequency in Mhz */ 19 #define QFPROM_BLOW_TIMER_OFFSET 0x03c 20 21 /* Amount of time required to hold charge to blow fuse in micro-seconds */ 22 #define QFPROM_FUSE_BLOW_POLL_US 100 23 #define QFPROM_FUSE_BLOW_TIMEOUT_US 1000 24 25 #define QFPROM_BLOW_STATUS_OFFSET 0x048 26 #define QFPROM_BLOW_STATUS_BUSY 0x1 27 #define QFPROM_BLOW_STATUS_READY 0x0 28 29 #define QFPROM_ACCEL_OFFSET 0x044 30 31 #define QFPROM_VERSION_OFFSET 0x0 32 #define QFPROM_MAJOR_VERSION_SHIFT 28 33 #define QFPROM_MAJOR_VERSION_MASK GENMASK(31, QFPROM_MAJOR_VERSION_SHIFT) 34 #define QFPROM_MINOR_VERSION_SHIFT 16 35 #define QFPROM_MINOR_VERSION_MASK GENMASK(27, QFPROM_MINOR_VERSION_SHIFT) 36 37 static bool read_raw_data; 38 module_param(read_raw_data, bool, 0644); 39 MODULE_PARM_DESC(read_raw_data, "Read raw instead of corrected data"); 40 41 /** 42 * struct qfprom_soc_data - config that varies from SoC to SoC. 43 * 44 * @accel_value: Should contain qfprom accel value. 45 * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow. 46 * @qfprom_blow_set_freq: The frequency required to set when we start the 47 * fuse blowing. 48 */ 49 struct qfprom_soc_data { 50 u32 accel_value; 51 u32 qfprom_blow_timer_value; 52 u32 qfprom_blow_set_freq; 53 }; 54 55 /** 56 * struct qfprom_priv - structure holding qfprom attributes 57 * 58 * @qfpraw: iomapped memory space for qfprom-efuse raw address space. 59 * @qfpconf: iomapped memory space for qfprom-efuse configuration address 60 * space. 61 * @qfpcorrected: iomapped memory space for qfprom corrected address space. 62 * @qfpsecurity: iomapped memory space for qfprom security control space. 63 * @dev: qfprom device structure. 64 * @secclk: Clock supply. 65 * @vcc: Regulator supply. 66 * @soc_data: Data that for things that varies from SoC to SoC. 67 */ 68 struct qfprom_priv { 69 void __iomem *qfpraw; 70 void __iomem *qfpconf; 71 void __iomem *qfpcorrected; 72 void __iomem *qfpsecurity; 73 struct device *dev; 74 struct clk *secclk; 75 struct regulator *vcc; 76 const struct qfprom_soc_data *soc_data; 77 }; 78 79 /** 80 * struct qfprom_touched_values - saved values to restore after blowing 81 * 82 * @clk_rate: The rate the clock was at before blowing. 83 * @accel_val: The value of the accel reg before blowing. 84 * @timer_val: The value of the timer before blowing. 85 */ 86 struct qfprom_touched_values { 87 unsigned long clk_rate; 88 u32 accel_val; 89 u32 timer_val; 90 }; 91 92 /** 93 * struct qfprom_soc_compatible_data - Data matched against the SoC 94 * compatible string. 95 * 96 * @keepout: Array of keepout regions for this SoC. 97 * @nkeepout: Number of elements in the keepout array. 98 */ 99 struct qfprom_soc_compatible_data { 100 const struct nvmem_keepout *keepout; 101 unsigned int nkeepout; 102 }; 103 104 static const struct nvmem_keepout sc7180_qfprom_keepout[] = { 105 {.start = 0x128, .end = 0x148}, 106 {.start = 0x220, .end = 0x228} 107 }; 108 109 static const struct qfprom_soc_compatible_data sc7180_qfprom = { 110 .keepout = sc7180_qfprom_keepout, 111 .nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout) 112 }; 113 114 /** 115 * qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing. 116 * @priv: Our driver data. 117 * @old: The data that was stashed from before fuse blowing. 118 * 119 * Resets the value of the blow timer, accel register and the clock 120 * and voltage settings. 121 * 122 * Prints messages if there are errors but doesn't return an error code 123 * since there's not much we can do upon failure. 124 */ 125 static void qfprom_disable_fuse_blowing(const struct qfprom_priv *priv, 126 const struct qfprom_touched_values *old) 127 { 128 int ret; 129 130 /* 131 * This may be a shared rail and may be able to run at a lower rate 132 * when we're not blowing fuses. At the moment, the regulator framework 133 * applies voltage constraints even on disabled rails, so remove our 134 * constraints and allow the rail to be adjusted by other users. 135 */ 136 ret = regulator_set_voltage(priv->vcc, 0, INT_MAX); 137 if (ret) 138 dev_warn(priv->dev, "Failed to set 0 voltage (ignoring)\n"); 139 140 ret = regulator_disable(priv->vcc); 141 if (ret) 142 dev_warn(priv->dev, "Failed to disable regulator (ignoring)\n"); 143 144 ret = clk_set_rate(priv->secclk, old->clk_rate); 145 if (ret) 146 dev_warn(priv->dev, 147 "Failed to set clock rate for disable (ignoring)\n"); 148 149 clk_disable_unprepare(priv->secclk); 150 151 writel(old->timer_val, priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET); 152 writel(old->accel_val, priv->qfpconf + QFPROM_ACCEL_OFFSET); 153 } 154 155 /** 156 * qfprom_enable_fuse_blowing() - Enable fuse blowing. 157 * @priv: Our driver data. 158 * @old: We'll stash stuff here to use when disabling. 159 * 160 * Sets the value of the blow timer, accel register and the clock 161 * and voltage settings. 162 * 163 * Prints messages if there are errors so caller doesn't need to. 164 * 165 * Return: 0 or -err. 166 */ 167 static int qfprom_enable_fuse_blowing(const struct qfprom_priv *priv, 168 struct qfprom_touched_values *old) 169 { 170 int ret; 171 172 ret = clk_prepare_enable(priv->secclk); 173 if (ret) { 174 dev_err(priv->dev, "Failed to enable clock\n"); 175 return ret; 176 } 177 178 old->clk_rate = clk_get_rate(priv->secclk); 179 ret = clk_set_rate(priv->secclk, priv->soc_data->qfprom_blow_set_freq); 180 if (ret) { 181 dev_err(priv->dev, "Failed to set clock rate for enable\n"); 182 goto err_clk_prepared; 183 } 184 185 /* 186 * Hardware requires 1.8V min for fuse blowing; this may be 187 * a rail shared do don't specify a max--regulator constraints 188 * will handle. 189 */ 190 ret = regulator_set_voltage(priv->vcc, 1800000, INT_MAX); 191 if (ret) { 192 dev_err(priv->dev, "Failed to set 1.8 voltage\n"); 193 goto err_clk_rate_set; 194 } 195 196 ret = regulator_enable(priv->vcc); 197 if (ret) { 198 dev_err(priv->dev, "Failed to enable regulator\n"); 199 goto err_clk_rate_set; 200 } 201 202 old->timer_val = readl(priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET); 203 old->accel_val = readl(priv->qfpconf + QFPROM_ACCEL_OFFSET); 204 writel(priv->soc_data->qfprom_blow_timer_value, 205 priv->qfpconf + QFPROM_BLOW_TIMER_OFFSET); 206 writel(priv->soc_data->accel_value, 207 priv->qfpconf + QFPROM_ACCEL_OFFSET); 208 209 return 0; 210 211 err_clk_rate_set: 212 clk_set_rate(priv->secclk, old->clk_rate); 213 err_clk_prepared: 214 clk_disable_unprepare(priv->secclk); 215 return ret; 216 } 217 218 /** 219 * qfprom_efuse_reg_write() - Write to fuses. 220 * @context: Our driver data. 221 * @reg: The offset to write at. 222 * @_val: Pointer to data to write. 223 * @bytes: The number of bytes to write. 224 * 225 * Writes to fuses. WARNING: THIS IS PERMANENT. 226 * 227 * Return: 0 or -err. 228 */ 229 static int qfprom_reg_write(void *context, unsigned int reg, void *_val, 230 size_t bytes) 231 { 232 struct qfprom_priv *priv = context; 233 struct qfprom_touched_values old; 234 int words = bytes / 4; 235 u32 *value = _val; 236 u32 blow_status; 237 int ret; 238 int i; 239 240 dev_dbg(priv->dev, 241 "Writing to raw qfprom region : %#010x of size: %zu\n", 242 reg, bytes); 243 244 /* 245 * The hardware only allows us to write word at a time, but we can 246 * read byte at a time. Until the nvmem framework allows a separate 247 * word_size and stride for reading vs. writing, we'll enforce here. 248 */ 249 if (bytes % 4) { 250 dev_err(priv->dev, 251 "%zu is not an integral number of words\n", bytes); 252 return -EINVAL; 253 } 254 if (reg % 4) { 255 dev_err(priv->dev, 256 "Invalid offset: %#x. Must be word aligned\n", reg); 257 return -EINVAL; 258 } 259 260 ret = qfprom_enable_fuse_blowing(priv, &old); 261 if (ret) 262 return ret; 263 264 ret = readl_relaxed_poll_timeout( 265 priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET, 266 blow_status, blow_status == QFPROM_BLOW_STATUS_READY, 267 QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US); 268 269 if (ret) { 270 dev_err(priv->dev, 271 "Timeout waiting for initial ready; aborting.\n"); 272 goto exit_enabled_fuse_blowing; 273 } 274 275 for (i = 0; i < words; i++) 276 writel(value[i], priv->qfpraw + reg + (i * 4)); 277 278 ret = readl_relaxed_poll_timeout( 279 priv->qfpconf + QFPROM_BLOW_STATUS_OFFSET, 280 blow_status, blow_status == QFPROM_BLOW_STATUS_READY, 281 QFPROM_FUSE_BLOW_POLL_US, QFPROM_FUSE_BLOW_TIMEOUT_US); 282 283 /* Give an error, but not much we can do in this case */ 284 if (ret) 285 dev_err(priv->dev, "Timeout waiting for finish.\n"); 286 287 exit_enabled_fuse_blowing: 288 qfprom_disable_fuse_blowing(priv, &old); 289 290 return ret; 291 } 292 293 static int qfprom_reg_read(void *context, 294 unsigned int reg, void *_val, size_t bytes) 295 { 296 struct qfprom_priv *priv = context; 297 u8 *val = _val; 298 int i = 0, words = bytes; 299 void __iomem *base = priv->qfpcorrected; 300 301 if (read_raw_data && priv->qfpraw) 302 base = priv->qfpraw; 303 304 while (words--) 305 *val++ = readb(base + reg + i++); 306 307 return 0; 308 } 309 310 static const struct qfprom_soc_data qfprom_7_8_data = { 311 .accel_value = 0xD10, 312 .qfprom_blow_timer_value = 25, 313 .qfprom_blow_set_freq = 4800000, 314 }; 315 316 static int qfprom_probe(struct platform_device *pdev) 317 { 318 struct nvmem_config econfig = { 319 .name = "qfprom", 320 .stride = 1, 321 .word_size = 1, 322 .id = NVMEM_DEVID_AUTO, 323 .reg_read = qfprom_reg_read, 324 }; 325 struct device *dev = &pdev->dev; 326 struct resource *res; 327 struct nvmem_device *nvmem; 328 const struct qfprom_soc_compatible_data *soc_data; 329 struct qfprom_priv *priv; 330 int ret; 331 332 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 333 if (!priv) 334 return -ENOMEM; 335 336 /* The corrected section is always provided */ 337 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 338 priv->qfpcorrected = devm_ioremap_resource(dev, res); 339 if (IS_ERR(priv->qfpcorrected)) 340 return PTR_ERR(priv->qfpcorrected); 341 342 econfig.size = resource_size(res); 343 econfig.dev = dev; 344 econfig.priv = priv; 345 346 priv->dev = dev; 347 soc_data = device_get_match_data(dev); 348 if (soc_data) { 349 econfig.keepout = soc_data->keepout; 350 econfig.nkeepout = soc_data->nkeepout; 351 } 352 353 /* 354 * If more than one region is provided then the OS has the ability 355 * to write. 356 */ 357 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 358 if (res) { 359 u32 version; 360 int major_version, minor_version; 361 362 priv->qfpraw = devm_ioremap_resource(dev, res); 363 if (IS_ERR(priv->qfpraw)) 364 return PTR_ERR(priv->qfpraw); 365 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 366 priv->qfpconf = devm_ioremap_resource(dev, res); 367 if (IS_ERR(priv->qfpconf)) 368 return PTR_ERR(priv->qfpconf); 369 res = platform_get_resource(pdev, IORESOURCE_MEM, 3); 370 priv->qfpsecurity = devm_ioremap_resource(dev, res); 371 if (IS_ERR(priv->qfpsecurity)) 372 return PTR_ERR(priv->qfpsecurity); 373 374 version = readl(priv->qfpsecurity + QFPROM_VERSION_OFFSET); 375 major_version = (version & QFPROM_MAJOR_VERSION_MASK) >> 376 QFPROM_MAJOR_VERSION_SHIFT; 377 minor_version = (version & QFPROM_MINOR_VERSION_MASK) >> 378 QFPROM_MINOR_VERSION_SHIFT; 379 380 if (major_version == 7 && minor_version == 8) 381 priv->soc_data = &qfprom_7_8_data; 382 383 priv->vcc = devm_regulator_get(&pdev->dev, "vcc"); 384 if (IS_ERR(priv->vcc)) 385 return PTR_ERR(priv->vcc); 386 387 priv->secclk = devm_clk_get(dev, "core"); 388 if (IS_ERR(priv->secclk)) { 389 ret = PTR_ERR(priv->secclk); 390 if (ret != -EPROBE_DEFER) 391 dev_err(dev, "Error getting clock: %d\n", ret); 392 return ret; 393 } 394 395 /* Only enable writing if we have SoC data. */ 396 if (priv->soc_data) 397 econfig.reg_write = qfprom_reg_write; 398 } 399 400 nvmem = devm_nvmem_register(dev, &econfig); 401 402 return PTR_ERR_OR_ZERO(nvmem); 403 } 404 405 static const struct of_device_id qfprom_of_match[] = { 406 { .compatible = "qcom,qfprom",}, 407 { .compatible = "qcom,sc7180-qfprom", .data = &sc7180_qfprom}, 408 {/* sentinel */}, 409 }; 410 MODULE_DEVICE_TABLE(of, qfprom_of_match); 411 412 static struct platform_driver qfprom_driver = { 413 .probe = qfprom_probe, 414 .driver = { 415 .name = "qcom,qfprom", 416 .of_match_table = qfprom_of_match, 417 }, 418 }; 419 module_platform_driver(qfprom_driver); 420 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); 421 MODULE_DESCRIPTION("Qualcomm QFPROM driver"); 422 MODULE_LICENSE("GPL v2"); 423