xref: /openbmc/linux/drivers/nvmem/jz4780-efuse.c (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
14a2addc2SPrasannaKumar Muralidharan // SPDX-License-Identifier: GPL-2.0-or-later
24a2addc2SPrasannaKumar Muralidharan /*
34a2addc2SPrasannaKumar Muralidharan  * JZ4780 EFUSE Memory Support driver
44a2addc2SPrasannaKumar Muralidharan  *
54a2addc2SPrasannaKumar Muralidharan  * Copyright (c) 2017 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
64a2addc2SPrasannaKumar Muralidharan  * Copyright (c) 2020 H. Nikolaus Schaller <hns@goldelico.com>
74a2addc2SPrasannaKumar Muralidharan  */
84a2addc2SPrasannaKumar Muralidharan 
94a2addc2SPrasannaKumar Muralidharan /*
104a2addc2SPrasannaKumar Muralidharan  * Currently supports JZ4780 efuse which has 8K programmable bit.
114a2addc2SPrasannaKumar Muralidharan  * Efuse is separated into seven segments as below:
124a2addc2SPrasannaKumar Muralidharan  *
134a2addc2SPrasannaKumar Muralidharan  * -----------------------------------------------------------------------
144a2addc2SPrasannaKumar Muralidharan  * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit |
154a2addc2SPrasannaKumar Muralidharan  * -----------------------------------------------------------------------
164a2addc2SPrasannaKumar Muralidharan  *
174a2addc2SPrasannaKumar Muralidharan  * The rom itself is accessed using a 9 bit address line and an 8 word wide bus
184a2addc2SPrasannaKumar Muralidharan  * which reads/writes based on strobes. The strobe is configured in the config
194a2addc2SPrasannaKumar Muralidharan  * register and is based on number of cycles of the bus clock.
204a2addc2SPrasannaKumar Muralidharan  *
214a2addc2SPrasannaKumar Muralidharan  * Driver supports read only as the writes are done in the Factory.
224a2addc2SPrasannaKumar Muralidharan  */
234a2addc2SPrasannaKumar Muralidharan 
244a2addc2SPrasannaKumar Muralidharan #include <linux/bitops.h>
254a2addc2SPrasannaKumar Muralidharan #include <linux/clk.h>
264a2addc2SPrasannaKumar Muralidharan #include <linux/module.h>
274a2addc2SPrasannaKumar Muralidharan #include <linux/nvmem-provider.h>
284a2addc2SPrasannaKumar Muralidharan #include <linux/of.h>
294a2addc2SPrasannaKumar Muralidharan #include <linux/platform_device.h>
304a2addc2SPrasannaKumar Muralidharan #include <linux/regmap.h>
314a2addc2SPrasannaKumar Muralidharan #include <linux/timer.h>
324a2addc2SPrasannaKumar Muralidharan 
334a2addc2SPrasannaKumar Muralidharan #define JZ_EFUCTRL		(0x0)	/* Control Register */
344a2addc2SPrasannaKumar Muralidharan #define JZ_EFUCFG		(0x4)	/* Configure Register*/
354a2addc2SPrasannaKumar Muralidharan #define JZ_EFUSTATE		(0x8)	/* Status Register */
364a2addc2SPrasannaKumar Muralidharan #define JZ_EFUDATA(n)		(0xC + (n) * 4)
374a2addc2SPrasannaKumar Muralidharan 
384a2addc2SPrasannaKumar Muralidharan /* We read 32 byte chunks to avoid complexity in the driver. */
394a2addc2SPrasannaKumar Muralidharan #define JZ_EFU_READ_SIZE 32
404a2addc2SPrasannaKumar Muralidharan 
414a2addc2SPrasannaKumar Muralidharan #define EFUCTRL_ADDR_MASK	0x3FF
424a2addc2SPrasannaKumar Muralidharan #define EFUCTRL_ADDR_SHIFT	21
434a2addc2SPrasannaKumar Muralidharan #define EFUCTRL_LEN_MASK	0x1F
444a2addc2SPrasannaKumar Muralidharan #define EFUCTRL_LEN_SHIFT	16
454a2addc2SPrasannaKumar Muralidharan #define EFUCTRL_PG_EN		BIT(15)
464a2addc2SPrasannaKumar Muralidharan #define EFUCTRL_WR_EN		BIT(1)
474a2addc2SPrasannaKumar Muralidharan #define EFUCTRL_RD_EN		BIT(0)
484a2addc2SPrasannaKumar Muralidharan 
494a2addc2SPrasannaKumar Muralidharan #define EFUCFG_INT_EN		BIT(31)
504a2addc2SPrasannaKumar Muralidharan #define EFUCFG_RD_ADJ_MASK	0xF
514a2addc2SPrasannaKumar Muralidharan #define EFUCFG_RD_ADJ_SHIFT	20
524a2addc2SPrasannaKumar Muralidharan #define EFUCFG_RD_STR_MASK	0xF
534a2addc2SPrasannaKumar Muralidharan #define EFUCFG_RD_STR_SHIFT	16
544a2addc2SPrasannaKumar Muralidharan #define EFUCFG_WR_ADJ_MASK	0xF
554a2addc2SPrasannaKumar Muralidharan #define EFUCFG_WR_ADJ_SHIFT	12
564a2addc2SPrasannaKumar Muralidharan #define EFUCFG_WR_STR_MASK	0xFFF
574a2addc2SPrasannaKumar Muralidharan #define EFUCFG_WR_STR_SHIFT	0
584a2addc2SPrasannaKumar Muralidharan 
594a2addc2SPrasannaKumar Muralidharan #define EFUSTATE_WR_DONE	BIT(1)
604a2addc2SPrasannaKumar Muralidharan #define EFUSTATE_RD_DONE	BIT(0)
614a2addc2SPrasannaKumar Muralidharan 
624a2addc2SPrasannaKumar Muralidharan struct jz4780_efuse {
634a2addc2SPrasannaKumar Muralidharan 	struct device *dev;
644a2addc2SPrasannaKumar Muralidharan 	struct regmap *map;
654a2addc2SPrasannaKumar Muralidharan 	struct clk *clk;
664a2addc2SPrasannaKumar Muralidharan };
674a2addc2SPrasannaKumar Muralidharan 
684a2addc2SPrasannaKumar Muralidharan /* main entry point */
jz4780_efuse_read(void * context,unsigned int offset,void * val,size_t bytes)694a2addc2SPrasannaKumar Muralidharan static int jz4780_efuse_read(void *context, unsigned int offset,
704a2addc2SPrasannaKumar Muralidharan 			     void *val, size_t bytes)
714a2addc2SPrasannaKumar Muralidharan {
724a2addc2SPrasannaKumar Muralidharan 	struct jz4780_efuse *efuse = context;
734a2addc2SPrasannaKumar Muralidharan 
744a2addc2SPrasannaKumar Muralidharan 	while (bytes > 0) {
75ba2bb5f7SH. Nikolaus Schaller 		size_t start = offset & ~(JZ_EFU_READ_SIZE - 1);
76ba2bb5f7SH. Nikolaus Schaller 		size_t chunk = min(bytes, (start + JZ_EFU_READ_SIZE)
774a2addc2SPrasannaKumar Muralidharan 				    - offset);
784a2addc2SPrasannaKumar Muralidharan 		char buf[JZ_EFU_READ_SIZE];
794a2addc2SPrasannaKumar Muralidharan 		unsigned int tmp;
804a2addc2SPrasannaKumar Muralidharan 		u32 ctrl;
814a2addc2SPrasannaKumar Muralidharan 		int ret;
824a2addc2SPrasannaKumar Muralidharan 
834a2addc2SPrasannaKumar Muralidharan 		ctrl = (start << EFUCTRL_ADDR_SHIFT)
844a2addc2SPrasannaKumar Muralidharan 			| ((JZ_EFU_READ_SIZE - 1) << EFUCTRL_LEN_SHIFT)
854a2addc2SPrasannaKumar Muralidharan 			| EFUCTRL_RD_EN;
864a2addc2SPrasannaKumar Muralidharan 
874a2addc2SPrasannaKumar Muralidharan 		regmap_update_bits(efuse->map, JZ_EFUCTRL,
884a2addc2SPrasannaKumar Muralidharan 				   (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |
894a2addc2SPrasannaKumar Muralidharan 				   (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |
904a2addc2SPrasannaKumar Muralidharan 				   EFUCTRL_PG_EN | EFUCTRL_WR_EN |
914a2addc2SPrasannaKumar Muralidharan 				   EFUCTRL_RD_EN,
924a2addc2SPrasannaKumar Muralidharan 				   ctrl);
934a2addc2SPrasannaKumar Muralidharan 
944a2addc2SPrasannaKumar Muralidharan 		ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
954a2addc2SPrasannaKumar Muralidharan 					       tmp, tmp & EFUSTATE_RD_DONE,
964a2addc2SPrasannaKumar Muralidharan 					       1 * MSEC_PER_SEC,
974a2addc2SPrasannaKumar Muralidharan 					       50 * MSEC_PER_SEC);
984a2addc2SPrasannaKumar Muralidharan 		if (ret < 0) {
994a2addc2SPrasannaKumar Muralidharan 			dev_err(efuse->dev, "Time out while reading efuse data");
1004a2addc2SPrasannaKumar Muralidharan 			return ret;
1014a2addc2SPrasannaKumar Muralidharan 		}
1024a2addc2SPrasannaKumar Muralidharan 
1034a2addc2SPrasannaKumar Muralidharan 		ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
1044a2addc2SPrasannaKumar Muralidharan 				       buf, JZ_EFU_READ_SIZE / sizeof(u32));
1054a2addc2SPrasannaKumar Muralidharan 		if (ret < 0)
1064a2addc2SPrasannaKumar Muralidharan 			return ret;
1074a2addc2SPrasannaKumar Muralidharan 
1084a2addc2SPrasannaKumar Muralidharan 		memcpy(val, &buf[offset - start], chunk);
1094a2addc2SPrasannaKumar Muralidharan 
1104a2addc2SPrasannaKumar Muralidharan 		val += chunk;
1114a2addc2SPrasannaKumar Muralidharan 		offset += chunk;
1124a2addc2SPrasannaKumar Muralidharan 		bytes -= chunk;
1134a2addc2SPrasannaKumar Muralidharan 	}
1144a2addc2SPrasannaKumar Muralidharan 
1154a2addc2SPrasannaKumar Muralidharan 	return 0;
1164a2addc2SPrasannaKumar Muralidharan }
1174a2addc2SPrasannaKumar Muralidharan 
1184a2addc2SPrasannaKumar Muralidharan static struct nvmem_config jz4780_efuse_nvmem_config = {
1194a2addc2SPrasannaKumar Muralidharan 	.name = "jz4780-efuse",
1204a2addc2SPrasannaKumar Muralidharan 	.size = 1024,
1214a2addc2SPrasannaKumar Muralidharan 	.word_size = 1,
1224a2addc2SPrasannaKumar Muralidharan 	.stride = 1,
1234a2addc2SPrasannaKumar Muralidharan 	.owner = THIS_MODULE,
1244a2addc2SPrasannaKumar Muralidharan 	.reg_read = jz4780_efuse_read,
1254a2addc2SPrasannaKumar Muralidharan };
1264a2addc2SPrasannaKumar Muralidharan 
1274a2addc2SPrasannaKumar Muralidharan static const struct regmap_config jz4780_efuse_regmap_config = {
1284a2addc2SPrasannaKumar Muralidharan 	.reg_bits = 32,
1294a2addc2SPrasannaKumar Muralidharan 	.val_bits = 32,
1304a2addc2SPrasannaKumar Muralidharan 	.reg_stride = 4,
1314a2addc2SPrasannaKumar Muralidharan 	.max_register = JZ_EFUDATA(7),
1324a2addc2SPrasannaKumar Muralidharan };
1334a2addc2SPrasannaKumar Muralidharan 
clk_disable_unprepare_helper(void * clock)1344a2addc2SPrasannaKumar Muralidharan static void clk_disable_unprepare_helper(void *clock)
1354a2addc2SPrasannaKumar Muralidharan {
1364a2addc2SPrasannaKumar Muralidharan 	clk_disable_unprepare(clock);
1374a2addc2SPrasannaKumar Muralidharan }
1384a2addc2SPrasannaKumar Muralidharan 
jz4780_efuse_probe(struct platform_device * pdev)1394a2addc2SPrasannaKumar Muralidharan static int jz4780_efuse_probe(struct platform_device *pdev)
1404a2addc2SPrasannaKumar Muralidharan {
1414a2addc2SPrasannaKumar Muralidharan 	struct nvmem_device *nvmem;
1424a2addc2SPrasannaKumar Muralidharan 	struct jz4780_efuse *efuse;
1434a2addc2SPrasannaKumar Muralidharan 	struct nvmem_config cfg;
1444a2addc2SPrasannaKumar Muralidharan 	unsigned long clk_rate;
1454a2addc2SPrasannaKumar Muralidharan 	unsigned long rd_adj;
1464a2addc2SPrasannaKumar Muralidharan 	unsigned long rd_strobe;
1474a2addc2SPrasannaKumar Muralidharan 	struct device *dev = &pdev->dev;
1484a2addc2SPrasannaKumar Muralidharan 	void __iomem *regs;
1494a2addc2SPrasannaKumar Muralidharan 	int ret;
1504a2addc2SPrasannaKumar Muralidharan 
1514a2addc2SPrasannaKumar Muralidharan 	efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
1524a2addc2SPrasannaKumar Muralidharan 	if (!efuse)
1534a2addc2SPrasannaKumar Muralidharan 		return -ENOMEM;
1544a2addc2SPrasannaKumar Muralidharan 
1554a2addc2SPrasannaKumar Muralidharan 	regs = devm_platform_ioremap_resource(pdev, 0);
1564a2addc2SPrasannaKumar Muralidharan 	if (IS_ERR(regs))
1574a2addc2SPrasannaKumar Muralidharan 		return PTR_ERR(regs);
1584a2addc2SPrasannaKumar Muralidharan 
1594a2addc2SPrasannaKumar Muralidharan 	efuse->map = devm_regmap_init_mmio(dev, regs,
1604a2addc2SPrasannaKumar Muralidharan 					   &jz4780_efuse_regmap_config);
1614a2addc2SPrasannaKumar Muralidharan 	if (IS_ERR(efuse->map))
1624a2addc2SPrasannaKumar Muralidharan 		return PTR_ERR(efuse->map);
1634a2addc2SPrasannaKumar Muralidharan 
1644a2addc2SPrasannaKumar Muralidharan 	efuse->clk = devm_clk_get(&pdev->dev, NULL);
1654a2addc2SPrasannaKumar Muralidharan 	if (IS_ERR(efuse->clk))
1664a2addc2SPrasannaKumar Muralidharan 		return PTR_ERR(efuse->clk);
1674a2addc2SPrasannaKumar Muralidharan 
1684a2addc2SPrasannaKumar Muralidharan 	ret = clk_prepare_enable(efuse->clk);
1694a2addc2SPrasannaKumar Muralidharan 	if (ret < 0)
1704a2addc2SPrasannaKumar Muralidharan 		return ret;
1714a2addc2SPrasannaKumar Muralidharan 
1724a2addc2SPrasannaKumar Muralidharan 	ret = devm_add_action_or_reset(&pdev->dev,
1734a2addc2SPrasannaKumar Muralidharan 				       clk_disable_unprepare_helper,
1744a2addc2SPrasannaKumar Muralidharan 				       efuse->clk);
1754a2addc2SPrasannaKumar Muralidharan 	if (ret < 0)
1764a2addc2SPrasannaKumar Muralidharan 		return ret;
1774a2addc2SPrasannaKumar Muralidharan 
1784a2addc2SPrasannaKumar Muralidharan 	clk_rate = clk_get_rate(efuse->clk);
1794a2addc2SPrasannaKumar Muralidharan 
1804a2addc2SPrasannaKumar Muralidharan 	efuse->dev = dev;
1814a2addc2SPrasannaKumar Muralidharan 
1824a2addc2SPrasannaKumar Muralidharan 	/*
1834a2addc2SPrasannaKumar Muralidharan 	 * rd_adj and rd_strobe are 4 bit values
1844a2addc2SPrasannaKumar Muralidharan 	 * conditions:
1854a2addc2SPrasannaKumar Muralidharan 	 *   bus clk_period * (rd_adj + 1) > 6.5ns
1864a2addc2SPrasannaKumar Muralidharan 	 *   bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
1874a2addc2SPrasannaKumar Muralidharan 	 *   i.e. rd_adj >= 6.5ns / clk_period
1884a2addc2SPrasannaKumar Muralidharan 	 *   i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
1894a2addc2SPrasannaKumar Muralidharan 	 * constants:
1904a2addc2SPrasannaKumar Muralidharan 	 *   1 / 6.5ns == 153846154 Hz
1914a2addc2SPrasannaKumar Muralidharan 	 *   1 / 35ns == 28571429 Hz
1924a2addc2SPrasannaKumar Muralidharan 	 */
1934a2addc2SPrasannaKumar Muralidharan 
1944a2addc2SPrasannaKumar Muralidharan 	rd_adj = clk_rate / 153846154;
1954a2addc2SPrasannaKumar Muralidharan 	rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
1964a2addc2SPrasannaKumar Muralidharan 
1974a2addc2SPrasannaKumar Muralidharan 	if (rd_adj > EFUCFG_RD_ADJ_MASK ||
1984a2addc2SPrasannaKumar Muralidharan 	    rd_strobe > EFUCFG_RD_STR_MASK) {
1994a2addc2SPrasannaKumar Muralidharan 		dev_err(&pdev->dev, "Cannot set clock configuration\n");
2004a2addc2SPrasannaKumar Muralidharan 		return -EINVAL;
2014a2addc2SPrasannaKumar Muralidharan 	}
2024a2addc2SPrasannaKumar Muralidharan 
2034a2addc2SPrasannaKumar Muralidharan 	regmap_update_bits(efuse->map, JZ_EFUCFG,
2044a2addc2SPrasannaKumar Muralidharan 			   (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |
2054a2addc2SPrasannaKumar Muralidharan 			   (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),
2064a2addc2SPrasannaKumar Muralidharan 			   (rd_adj << EFUCFG_RD_ADJ_SHIFT) |
2074a2addc2SPrasannaKumar Muralidharan 			   (rd_strobe << EFUCFG_RD_STR_SHIFT));
2084a2addc2SPrasannaKumar Muralidharan 
2094a2addc2SPrasannaKumar Muralidharan 	cfg = jz4780_efuse_nvmem_config;
2104a2addc2SPrasannaKumar Muralidharan 	cfg.dev = &pdev->dev;
2114a2addc2SPrasannaKumar Muralidharan 	cfg.priv = efuse;
2124a2addc2SPrasannaKumar Muralidharan 
2134a2addc2SPrasannaKumar Muralidharan 	nvmem = devm_nvmem_register(dev, &cfg);
2144a2addc2SPrasannaKumar Muralidharan 
215*e270df39SSamuel Zou 	return PTR_ERR_OR_ZERO(nvmem);
2164a2addc2SPrasannaKumar Muralidharan }
2174a2addc2SPrasannaKumar Muralidharan 
2184a2addc2SPrasannaKumar Muralidharan static const struct of_device_id jz4780_efuse_match[] = {
2194a2addc2SPrasannaKumar Muralidharan 	{ .compatible = "ingenic,jz4780-efuse" },
2204a2addc2SPrasannaKumar Muralidharan 	{ /* sentinel */ },
2214a2addc2SPrasannaKumar Muralidharan };
2224a2addc2SPrasannaKumar Muralidharan MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
2234a2addc2SPrasannaKumar Muralidharan 
2244a2addc2SPrasannaKumar Muralidharan static struct platform_driver jz4780_efuse_driver = {
2254a2addc2SPrasannaKumar Muralidharan 	.probe  = jz4780_efuse_probe,
2264a2addc2SPrasannaKumar Muralidharan 	.driver = {
2274a2addc2SPrasannaKumar Muralidharan 		.name = "jz4780-efuse",
2284a2addc2SPrasannaKumar Muralidharan 		.of_match_table = jz4780_efuse_match,
2294a2addc2SPrasannaKumar Muralidharan 	},
2304a2addc2SPrasannaKumar Muralidharan };
2314a2addc2SPrasannaKumar Muralidharan module_platform_driver(jz4780_efuse_driver);
2324a2addc2SPrasannaKumar Muralidharan 
2334a2addc2SPrasannaKumar Muralidharan MODULE_AUTHOR("PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>");
2344a2addc2SPrasannaKumar Muralidharan MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
2354a2addc2SPrasannaKumar Muralidharan MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
2364a2addc2SPrasannaKumar Muralidharan MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
2374a2addc2SPrasannaKumar Muralidharan MODULE_LICENSE("GPL v2");
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