1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/aer.h> 9 #include <linux/async.h> 10 #include <linux/blkdev.h> 11 #include <linux/blk-mq.h> 12 #include <linux/blk-mq-pci.h> 13 #include <linux/blk-integrity.h> 14 #include <linux/dmi.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kstrtox.h> 19 #include <linux/memremap.h> 20 #include <linux/mm.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/once.h> 24 #include <linux/pci.h> 25 #include <linux/suspend.h> 26 #include <linux/t10-pi.h> 27 #include <linux/types.h> 28 #include <linux/io-64-nonatomic-lo-hi.h> 29 #include <linux/io-64-nonatomic-hi-lo.h> 30 #include <linux/sed-opal.h> 31 #include <linux/pci-p2pdma.h> 32 33 #include "trace.h" 34 #include "nvme.h" 35 36 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 37 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 38 39 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 40 41 /* 42 * These can be higher, but we need to ensure that any command doesn't 43 * require an sg allocation that needs more than a page of data. 44 */ 45 #define NVME_MAX_KB_SZ 4096 46 #define NVME_MAX_SEGS 127 47 48 static int use_threaded_interrupts; 49 module_param(use_threaded_interrupts, int, 0444); 50 51 static bool use_cmb_sqes = true; 52 module_param(use_cmb_sqes, bool, 0444); 53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 54 55 static unsigned int max_host_mem_size_mb = 128; 56 module_param(max_host_mem_size_mb, uint, 0444); 57 MODULE_PARM_DESC(max_host_mem_size_mb, 58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 59 60 static unsigned int sgl_threshold = SZ_32K; 61 module_param(sgl_threshold, uint, 0644); 62 MODULE_PARM_DESC(sgl_threshold, 63 "Use SGLs when average request segment size is larger or equal to " 64 "this size. Use 0 to disable SGLs."); 65 66 #define NVME_PCI_MIN_QUEUE_SIZE 2 67 #define NVME_PCI_MAX_QUEUE_SIZE 4095 68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 69 static const struct kernel_param_ops io_queue_depth_ops = { 70 .set = io_queue_depth_set, 71 .get = param_get_uint, 72 }; 73 74 static unsigned int io_queue_depth = 1024; 75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 77 78 static int io_queue_count_set(const char *val, const struct kernel_param *kp) 79 { 80 unsigned int n; 81 int ret; 82 83 ret = kstrtouint(val, 10, &n); 84 if (ret != 0 || n > num_possible_cpus()) 85 return -EINVAL; 86 return param_set_uint(val, kp); 87 } 88 89 static const struct kernel_param_ops io_queue_count_ops = { 90 .set = io_queue_count_set, 91 .get = param_get_uint, 92 }; 93 94 static unsigned int write_queues; 95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 96 MODULE_PARM_DESC(write_queues, 97 "Number of queues to use for writes. If not set, reads and writes " 98 "will share a queue set."); 99 100 static unsigned int poll_queues; 101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 103 104 static bool noacpi; 105 module_param(noacpi, bool, 0444); 106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 107 108 struct nvme_dev; 109 struct nvme_queue; 110 111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 112 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 113 114 /* 115 * Represents an NVM Express device. Each nvme_dev is a PCI function. 116 */ 117 struct nvme_dev { 118 struct nvme_queue *queues; 119 struct blk_mq_tag_set tagset; 120 struct blk_mq_tag_set admin_tagset; 121 u32 __iomem *dbs; 122 struct device *dev; 123 struct dma_pool *prp_page_pool; 124 struct dma_pool *prp_small_pool; 125 unsigned online_queues; 126 unsigned max_qid; 127 unsigned io_queues[HCTX_MAX_TYPES]; 128 unsigned int num_vecs; 129 u32 q_depth; 130 int io_sqes; 131 u32 db_stride; 132 void __iomem *bar; 133 unsigned long bar_mapped_size; 134 struct mutex shutdown_lock; 135 bool subsystem; 136 u64 cmb_size; 137 bool cmb_use_sqes; 138 u32 cmbsz; 139 u32 cmbloc; 140 struct nvme_ctrl ctrl; 141 u32 last_ps; 142 bool hmb; 143 144 mempool_t *iod_mempool; 145 146 /* shadow doorbell buffer support: */ 147 u32 *dbbuf_dbs; 148 dma_addr_t dbbuf_dbs_dma_addr; 149 u32 *dbbuf_eis; 150 dma_addr_t dbbuf_eis_dma_addr; 151 152 /* host memory buffer support: */ 153 u64 host_mem_size; 154 u32 nr_host_mem_descs; 155 dma_addr_t host_mem_descs_dma; 156 struct nvme_host_mem_buf_desc *host_mem_descs; 157 void **host_mem_desc_bufs; 158 unsigned int nr_allocated_queues; 159 unsigned int nr_write_queues; 160 unsigned int nr_poll_queues; 161 }; 162 163 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 164 { 165 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 166 NVME_PCI_MAX_QUEUE_SIZE); 167 } 168 169 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 170 { 171 return qid * 2 * stride; 172 } 173 174 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 175 { 176 return (qid * 2 + 1) * stride; 177 } 178 179 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 180 { 181 return container_of(ctrl, struct nvme_dev, ctrl); 182 } 183 184 /* 185 * An NVM Express queue. Each device has at least two (one for admin 186 * commands and one for I/O commands). 187 */ 188 struct nvme_queue { 189 struct nvme_dev *dev; 190 spinlock_t sq_lock; 191 void *sq_cmds; 192 /* only used for poll queues: */ 193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 194 struct nvme_completion *cqes; 195 dma_addr_t sq_dma_addr; 196 dma_addr_t cq_dma_addr; 197 u32 __iomem *q_db; 198 u32 q_depth; 199 u16 cq_vector; 200 u16 sq_tail; 201 u16 last_sq_tail; 202 u16 cq_head; 203 u16 qid; 204 u8 cq_phase; 205 u8 sqes; 206 unsigned long flags; 207 #define NVMEQ_ENABLED 0 208 #define NVMEQ_SQ_CMB 1 209 #define NVMEQ_DELETE_ERROR 2 210 #define NVMEQ_POLLED 3 211 u32 *dbbuf_sq_db; 212 u32 *dbbuf_cq_db; 213 u32 *dbbuf_sq_ei; 214 u32 *dbbuf_cq_ei; 215 struct completion delete_done; 216 }; 217 218 /* 219 * The nvme_iod describes the data in an I/O. 220 * 221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 222 * to the actual struct scatterlist. 223 */ 224 struct nvme_iod { 225 struct nvme_request req; 226 struct nvme_command cmd; 227 bool use_sgl; 228 bool aborted; 229 s8 nr_allocations; /* PRP list pool allocations. 0 means small 230 pool in use */ 231 unsigned int dma_len; /* length of single DMA segment mapping */ 232 dma_addr_t first_dma; 233 dma_addr_t meta_dma; 234 struct sg_table sgt; 235 }; 236 237 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 238 { 239 return dev->nr_allocated_queues * 8 * dev->db_stride; 240 } 241 242 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 243 { 244 unsigned int mem_size = nvme_dbbuf_size(dev); 245 246 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP)) 247 return; 248 249 if (dev->dbbuf_dbs) { 250 /* 251 * Clear the dbbuf memory so the driver doesn't observe stale 252 * values from the previous instantiation. 253 */ 254 memset(dev->dbbuf_dbs, 0, mem_size); 255 memset(dev->dbbuf_eis, 0, mem_size); 256 return; 257 } 258 259 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 260 &dev->dbbuf_dbs_dma_addr, 261 GFP_KERNEL); 262 if (!dev->dbbuf_dbs) 263 goto fail; 264 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 265 &dev->dbbuf_eis_dma_addr, 266 GFP_KERNEL); 267 if (!dev->dbbuf_eis) 268 goto fail_free_dbbuf_dbs; 269 return; 270 271 fail_free_dbbuf_dbs: 272 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs, 273 dev->dbbuf_dbs_dma_addr); 274 dev->dbbuf_dbs = NULL; 275 fail: 276 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n"); 277 } 278 279 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 280 { 281 unsigned int mem_size = nvme_dbbuf_size(dev); 282 283 if (dev->dbbuf_dbs) { 284 dma_free_coherent(dev->dev, mem_size, 285 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 286 dev->dbbuf_dbs = NULL; 287 } 288 if (dev->dbbuf_eis) { 289 dma_free_coherent(dev->dev, mem_size, 290 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 291 dev->dbbuf_eis = NULL; 292 } 293 } 294 295 static void nvme_dbbuf_init(struct nvme_dev *dev, 296 struct nvme_queue *nvmeq, int qid) 297 { 298 if (!dev->dbbuf_dbs || !qid) 299 return; 300 301 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 302 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 303 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 304 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 305 } 306 307 static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 308 { 309 if (!nvmeq->qid) 310 return; 311 312 nvmeq->dbbuf_sq_db = NULL; 313 nvmeq->dbbuf_cq_db = NULL; 314 nvmeq->dbbuf_sq_ei = NULL; 315 nvmeq->dbbuf_cq_ei = NULL; 316 } 317 318 static void nvme_dbbuf_set(struct nvme_dev *dev) 319 { 320 struct nvme_command c = { }; 321 unsigned int i; 322 323 if (!dev->dbbuf_dbs) 324 return; 325 326 c.dbbuf.opcode = nvme_admin_dbbuf; 327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 329 330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 332 /* Free memory and continue on */ 333 nvme_dbbuf_dma_free(dev); 334 335 for (i = 1; i <= dev->online_queues; i++) 336 nvme_dbbuf_free(&dev->queues[i]); 337 } 338 } 339 340 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 341 { 342 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 343 } 344 345 /* Update dbbuf and return true if an MMIO is required */ 346 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 347 volatile u32 *dbbuf_ei) 348 { 349 if (dbbuf_db) { 350 u16 old_value; 351 352 /* 353 * Ensure that the queue is written before updating 354 * the doorbell in memory 355 */ 356 wmb(); 357 358 old_value = *dbbuf_db; 359 *dbbuf_db = value; 360 361 /* 362 * Ensure that the doorbell is updated before reading the event 363 * index from memory. The controller needs to provide similar 364 * ordering to ensure the envent index is updated before reading 365 * the doorbell. 366 */ 367 mb(); 368 369 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 370 return false; 371 } 372 373 return true; 374 } 375 376 /* 377 * Will slightly overestimate the number of pages needed. This is OK 378 * as it only leads to a small amount of wasted memory for the lifetime of 379 * the I/O. 380 */ 381 static int nvme_pci_npages_prp(void) 382 { 383 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 384 NVME_CTRL_PAGE_SIZE); 385 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 386 } 387 388 /* 389 * Calculates the number of pages needed for the SGL segments. For example a 4k 390 * page can accommodate 256 SGL descriptors. 391 */ 392 static int nvme_pci_npages_sgl(void) 393 { 394 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 395 PAGE_SIZE); 396 } 397 398 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 399 unsigned int hctx_idx) 400 { 401 struct nvme_dev *dev = data; 402 struct nvme_queue *nvmeq = &dev->queues[0]; 403 404 WARN_ON(hctx_idx != 0); 405 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 406 407 hctx->driver_data = nvmeq; 408 return 0; 409 } 410 411 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 412 unsigned int hctx_idx) 413 { 414 struct nvme_dev *dev = data; 415 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 416 417 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 418 hctx->driver_data = nvmeq; 419 return 0; 420 } 421 422 static int nvme_pci_init_request(struct blk_mq_tag_set *set, 423 struct request *req, unsigned int hctx_idx, 424 unsigned int numa_node) 425 { 426 struct nvme_dev *dev = set->driver_data; 427 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 428 429 nvme_req(req)->ctrl = &dev->ctrl; 430 nvme_req(req)->cmd = &iod->cmd; 431 return 0; 432 } 433 434 static int queue_irq_offset(struct nvme_dev *dev) 435 { 436 /* if we have more than 1 vec, admin queue offsets us by 1 */ 437 if (dev->num_vecs > 1) 438 return 1; 439 440 return 0; 441 } 442 443 static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 444 { 445 struct nvme_dev *dev = set->driver_data; 446 int i, qoff, offset; 447 448 offset = queue_irq_offset(dev); 449 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 450 struct blk_mq_queue_map *map = &set->map[i]; 451 452 map->nr_queues = dev->io_queues[i]; 453 if (!map->nr_queues) { 454 BUG_ON(i == HCTX_TYPE_DEFAULT); 455 continue; 456 } 457 458 /* 459 * The poll queue(s) doesn't have an IRQ (and hence IRQ 460 * affinity), so use the regular blk-mq cpu mapping 461 */ 462 map->queue_offset = qoff; 463 if (i != HCTX_TYPE_POLL && offset) 464 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 465 else 466 blk_mq_map_queues(map); 467 qoff += map->nr_queues; 468 offset += map->nr_queues; 469 } 470 } 471 472 /* 473 * Write sq tail if we are asked to, or if the next command would wrap. 474 */ 475 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 476 { 477 if (!write_sq) { 478 u16 next_tail = nvmeq->sq_tail + 1; 479 480 if (next_tail == nvmeq->q_depth) 481 next_tail = 0; 482 if (next_tail != nvmeq->last_sq_tail) 483 return; 484 } 485 486 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 487 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 488 writel(nvmeq->sq_tail, nvmeq->q_db); 489 nvmeq->last_sq_tail = nvmeq->sq_tail; 490 } 491 492 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 493 struct nvme_command *cmd) 494 { 495 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 496 absolute_pointer(cmd), sizeof(*cmd)); 497 if (++nvmeq->sq_tail == nvmeq->q_depth) 498 nvmeq->sq_tail = 0; 499 } 500 501 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 502 { 503 struct nvme_queue *nvmeq = hctx->driver_data; 504 505 spin_lock(&nvmeq->sq_lock); 506 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 507 nvme_write_sq_db(nvmeq, true); 508 spin_unlock(&nvmeq->sq_lock); 509 } 510 511 static void **nvme_pci_iod_list(struct request *req) 512 { 513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 514 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req)); 515 } 516 517 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 518 { 519 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 520 int nseg = blk_rq_nr_phys_segments(req); 521 unsigned int avg_seg_size; 522 523 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 524 525 if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 526 return false; 527 if (!nvmeq->qid) 528 return false; 529 if (!sgl_threshold || avg_seg_size < sgl_threshold) 530 return false; 531 return true; 532 } 533 534 static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 535 { 536 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 537 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 538 dma_addr_t dma_addr = iod->first_dma; 539 int i; 540 541 for (i = 0; i < iod->nr_allocations; i++) { 542 __le64 *prp_list = nvme_pci_iod_list(req)[i]; 543 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 544 545 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 546 dma_addr = next_dma_addr; 547 } 548 } 549 550 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 551 { 552 const int last_sg = SGES_PER_PAGE - 1; 553 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 554 dma_addr_t dma_addr = iod->first_dma; 555 int i; 556 557 for (i = 0; i < iod->nr_allocations; i++) { 558 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 559 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 560 561 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 562 dma_addr = next_dma_addr; 563 } 564 } 565 566 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 567 { 568 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 569 570 if (iod->dma_len) { 571 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 572 rq_dma_dir(req)); 573 return; 574 } 575 576 WARN_ON_ONCE(!iod->sgt.nents); 577 578 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 579 580 if (iod->nr_allocations == 0) 581 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 582 iod->first_dma); 583 else if (iod->use_sgl) 584 nvme_free_sgls(dev, req); 585 else 586 nvme_free_prps(dev, req); 587 mempool_free(iod->sgt.sgl, dev->iod_mempool); 588 } 589 590 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 591 { 592 int i; 593 struct scatterlist *sg; 594 595 for_each_sg(sgl, sg, nents, i) { 596 dma_addr_t phys = sg_phys(sg); 597 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 598 "dma_address:%pad dma_length:%d\n", 599 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 600 sg_dma_len(sg)); 601 } 602 } 603 604 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 605 struct request *req, struct nvme_rw_command *cmnd) 606 { 607 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 608 struct dma_pool *pool; 609 int length = blk_rq_payload_bytes(req); 610 struct scatterlist *sg = iod->sgt.sgl; 611 int dma_len = sg_dma_len(sg); 612 u64 dma_addr = sg_dma_address(sg); 613 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 614 __le64 *prp_list; 615 void **list = nvme_pci_iod_list(req); 616 dma_addr_t prp_dma; 617 int nprps, i; 618 619 length -= (NVME_CTRL_PAGE_SIZE - offset); 620 if (length <= 0) { 621 iod->first_dma = 0; 622 goto done; 623 } 624 625 dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 626 if (dma_len) { 627 dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 628 } else { 629 sg = sg_next(sg); 630 dma_addr = sg_dma_address(sg); 631 dma_len = sg_dma_len(sg); 632 } 633 634 if (length <= NVME_CTRL_PAGE_SIZE) { 635 iod->first_dma = dma_addr; 636 goto done; 637 } 638 639 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 640 if (nprps <= (256 / 8)) { 641 pool = dev->prp_small_pool; 642 iod->nr_allocations = 0; 643 } else { 644 pool = dev->prp_page_pool; 645 iod->nr_allocations = 1; 646 } 647 648 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 649 if (!prp_list) { 650 iod->nr_allocations = -1; 651 return BLK_STS_RESOURCE; 652 } 653 list[0] = prp_list; 654 iod->first_dma = prp_dma; 655 i = 0; 656 for (;;) { 657 if (i == NVME_CTRL_PAGE_SIZE >> 3) { 658 __le64 *old_prp_list = prp_list; 659 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 660 if (!prp_list) 661 goto free_prps; 662 list[iod->nr_allocations++] = prp_list; 663 prp_list[0] = old_prp_list[i - 1]; 664 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 665 i = 1; 666 } 667 prp_list[i++] = cpu_to_le64(dma_addr); 668 dma_len -= NVME_CTRL_PAGE_SIZE; 669 dma_addr += NVME_CTRL_PAGE_SIZE; 670 length -= NVME_CTRL_PAGE_SIZE; 671 if (length <= 0) 672 break; 673 if (dma_len > 0) 674 continue; 675 if (unlikely(dma_len < 0)) 676 goto bad_sgl; 677 sg = sg_next(sg); 678 dma_addr = sg_dma_address(sg); 679 dma_len = sg_dma_len(sg); 680 } 681 done: 682 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 683 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 684 return BLK_STS_OK; 685 free_prps: 686 nvme_free_prps(dev, req); 687 return BLK_STS_RESOURCE; 688 bad_sgl: 689 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 690 "Invalid SGL for payload:%d nents:%d\n", 691 blk_rq_payload_bytes(req), iod->sgt.nents); 692 return BLK_STS_IOERR; 693 } 694 695 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 696 struct scatterlist *sg) 697 { 698 sge->addr = cpu_to_le64(sg_dma_address(sg)); 699 sge->length = cpu_to_le32(sg_dma_len(sg)); 700 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 701 } 702 703 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 704 dma_addr_t dma_addr, int entries) 705 { 706 sge->addr = cpu_to_le64(dma_addr); 707 if (entries < SGES_PER_PAGE) { 708 sge->length = cpu_to_le32(entries * sizeof(*sge)); 709 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 710 } else { 711 sge->length = cpu_to_le32(PAGE_SIZE); 712 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 713 } 714 } 715 716 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 717 struct request *req, struct nvme_rw_command *cmd) 718 { 719 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 720 struct dma_pool *pool; 721 struct nvme_sgl_desc *sg_list; 722 struct scatterlist *sg = iod->sgt.sgl; 723 unsigned int entries = iod->sgt.nents; 724 dma_addr_t sgl_dma; 725 int i = 0; 726 727 /* setting the transfer type as SGL */ 728 cmd->flags = NVME_CMD_SGL_METABUF; 729 730 if (entries == 1) { 731 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 732 return BLK_STS_OK; 733 } 734 735 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 736 pool = dev->prp_small_pool; 737 iod->nr_allocations = 0; 738 } else { 739 pool = dev->prp_page_pool; 740 iod->nr_allocations = 1; 741 } 742 743 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 744 if (!sg_list) { 745 iod->nr_allocations = -1; 746 return BLK_STS_RESOURCE; 747 } 748 749 nvme_pci_iod_list(req)[0] = sg_list; 750 iod->first_dma = sgl_dma; 751 752 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 753 754 do { 755 if (i == SGES_PER_PAGE) { 756 struct nvme_sgl_desc *old_sg_desc = sg_list; 757 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 758 759 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 760 if (!sg_list) 761 goto free_sgls; 762 763 i = 0; 764 nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list; 765 sg_list[i++] = *link; 766 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 767 } 768 769 nvme_pci_sgl_set_data(&sg_list[i++], sg); 770 sg = sg_next(sg); 771 } while (--entries > 0); 772 773 return BLK_STS_OK; 774 free_sgls: 775 nvme_free_sgls(dev, req); 776 return BLK_STS_RESOURCE; 777 } 778 779 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 780 struct request *req, struct nvme_rw_command *cmnd, 781 struct bio_vec *bv) 782 { 783 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 784 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 785 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 786 787 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 788 if (dma_mapping_error(dev->dev, iod->first_dma)) 789 return BLK_STS_RESOURCE; 790 iod->dma_len = bv->bv_len; 791 792 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 793 if (bv->bv_len > first_prp_len) 794 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 795 return BLK_STS_OK; 796 } 797 798 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 799 struct request *req, struct nvme_rw_command *cmnd, 800 struct bio_vec *bv) 801 { 802 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 803 804 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 805 if (dma_mapping_error(dev->dev, iod->first_dma)) 806 return BLK_STS_RESOURCE; 807 iod->dma_len = bv->bv_len; 808 809 cmnd->flags = NVME_CMD_SGL_METABUF; 810 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 811 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 812 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 813 return BLK_STS_OK; 814 } 815 816 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 817 struct nvme_command *cmnd) 818 { 819 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 820 blk_status_t ret = BLK_STS_RESOURCE; 821 int rc; 822 823 if (blk_rq_nr_phys_segments(req) == 1) { 824 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 825 struct bio_vec bv = req_bvec(req); 826 827 if (!is_pci_p2pdma_page(bv.bv_page)) { 828 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 829 return nvme_setup_prp_simple(dev, req, 830 &cmnd->rw, &bv); 831 832 if (nvmeq->qid && sgl_threshold && 833 nvme_ctrl_sgl_supported(&dev->ctrl)) 834 return nvme_setup_sgl_simple(dev, req, 835 &cmnd->rw, &bv); 836 } 837 } 838 839 iod->dma_len = 0; 840 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 841 if (!iod->sgt.sgl) 842 return BLK_STS_RESOURCE; 843 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 844 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 845 if (!iod->sgt.orig_nents) 846 goto out_free_sg; 847 848 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 849 DMA_ATTR_NO_WARN); 850 if (rc) { 851 if (rc == -EREMOTEIO) 852 ret = BLK_STS_TARGET; 853 goto out_free_sg; 854 } 855 856 iod->use_sgl = nvme_pci_use_sgls(dev, req); 857 if (iod->use_sgl) 858 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 859 else 860 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 861 if (ret != BLK_STS_OK) 862 goto out_unmap_sg; 863 return BLK_STS_OK; 864 865 out_unmap_sg: 866 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 867 out_free_sg: 868 mempool_free(iod->sgt.sgl, dev->iod_mempool); 869 return ret; 870 } 871 872 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 873 struct nvme_command *cmnd) 874 { 875 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 876 877 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 878 rq_dma_dir(req), 0); 879 if (dma_mapping_error(dev->dev, iod->meta_dma)) 880 return BLK_STS_IOERR; 881 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 882 return BLK_STS_OK; 883 } 884 885 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 886 { 887 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 888 blk_status_t ret; 889 890 iod->aborted = false; 891 iod->nr_allocations = -1; 892 iod->sgt.nents = 0; 893 894 ret = nvme_setup_cmd(req->q->queuedata, req); 895 if (ret) 896 return ret; 897 898 if (blk_rq_nr_phys_segments(req)) { 899 ret = nvme_map_data(dev, req, &iod->cmd); 900 if (ret) 901 goto out_free_cmd; 902 } 903 904 if (blk_integrity_rq(req)) { 905 ret = nvme_map_metadata(dev, req, &iod->cmd); 906 if (ret) 907 goto out_unmap_data; 908 } 909 910 nvme_start_request(req); 911 return BLK_STS_OK; 912 out_unmap_data: 913 nvme_unmap_data(dev, req); 914 out_free_cmd: 915 nvme_cleanup_cmd(req); 916 return ret; 917 } 918 919 /* 920 * NOTE: ns is NULL when called on the admin queue. 921 */ 922 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 923 const struct blk_mq_queue_data *bd) 924 { 925 struct nvme_queue *nvmeq = hctx->driver_data; 926 struct nvme_dev *dev = nvmeq->dev; 927 struct request *req = bd->rq; 928 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 929 blk_status_t ret; 930 931 /* 932 * We should not need to do this, but we're still using this to 933 * ensure we can drain requests on a dying queue. 934 */ 935 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 936 return BLK_STS_IOERR; 937 938 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 939 return nvme_fail_nonready_command(&dev->ctrl, req); 940 941 ret = nvme_prep_rq(dev, req); 942 if (unlikely(ret)) 943 return ret; 944 spin_lock(&nvmeq->sq_lock); 945 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 946 nvme_write_sq_db(nvmeq, bd->last); 947 spin_unlock(&nvmeq->sq_lock); 948 return BLK_STS_OK; 949 } 950 951 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 952 { 953 spin_lock(&nvmeq->sq_lock); 954 while (!rq_list_empty(*rqlist)) { 955 struct request *req = rq_list_pop(rqlist); 956 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 957 958 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 959 } 960 nvme_write_sq_db(nvmeq, true); 961 spin_unlock(&nvmeq->sq_lock); 962 } 963 964 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 965 { 966 /* 967 * We should not need to do this, but we're still using this to 968 * ensure we can drain requests on a dying queue. 969 */ 970 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 971 return false; 972 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 973 return false; 974 975 req->mq_hctx->tags->rqs[req->tag] = req; 976 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 977 } 978 979 static void nvme_queue_rqs(struct request **rqlist) 980 { 981 struct request *req, *next, *prev = NULL; 982 struct request *requeue_list = NULL; 983 984 rq_list_for_each_safe(rqlist, req, next) { 985 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 986 987 if (!nvme_prep_rq_batch(nvmeq, req)) { 988 /* detach 'req' and add to remainder list */ 989 rq_list_move(rqlist, &requeue_list, req, prev); 990 991 req = prev; 992 if (!req) 993 continue; 994 } 995 996 if (!next || req->mq_hctx != next->mq_hctx) { 997 /* detach rest of list, and submit */ 998 req->rq_next = NULL; 999 nvme_submit_cmds(nvmeq, rqlist); 1000 *rqlist = next; 1001 prev = NULL; 1002 } else 1003 prev = req; 1004 } 1005 1006 *rqlist = requeue_list; 1007 } 1008 1009 static __always_inline void nvme_pci_unmap_rq(struct request *req) 1010 { 1011 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1012 struct nvme_dev *dev = nvmeq->dev; 1013 1014 if (blk_integrity_rq(req)) { 1015 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1016 1017 dma_unmap_page(dev->dev, iod->meta_dma, 1018 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1019 } 1020 1021 if (blk_rq_nr_phys_segments(req)) 1022 nvme_unmap_data(dev, req); 1023 } 1024 1025 static void nvme_pci_complete_rq(struct request *req) 1026 { 1027 nvme_pci_unmap_rq(req); 1028 nvme_complete_rq(req); 1029 } 1030 1031 static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1032 { 1033 nvme_complete_batch(iob, nvme_pci_unmap_rq); 1034 } 1035 1036 /* We read the CQE phase first to check if the rest of the entry is valid */ 1037 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1038 { 1039 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 1040 1041 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1042 } 1043 1044 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 1045 { 1046 u16 head = nvmeq->cq_head; 1047 1048 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1049 nvmeq->dbbuf_cq_ei)) 1050 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1051 } 1052 1053 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1054 { 1055 if (!nvmeq->qid) 1056 return nvmeq->dev->admin_tagset.tags[0]; 1057 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1058 } 1059 1060 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1061 struct io_comp_batch *iob, u16 idx) 1062 { 1063 struct nvme_completion *cqe = &nvmeq->cqes[idx]; 1064 __u16 command_id = READ_ONCE(cqe->command_id); 1065 struct request *req; 1066 1067 /* 1068 * AEN requests are special as they don't time out and can 1069 * survive any kind of queue freeze and often don't respond to 1070 * aborts. We don't even bother to allocate a struct request 1071 * for them but rather special case them here. 1072 */ 1073 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 1074 nvme_complete_async_event(&nvmeq->dev->ctrl, 1075 cqe->status, &cqe->result); 1076 return; 1077 } 1078 1079 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 1080 if (unlikely(!req)) { 1081 dev_warn(nvmeq->dev->ctrl.device, 1082 "invalid id %d completed on queue %d\n", 1083 command_id, le16_to_cpu(cqe->sq_id)); 1084 return; 1085 } 1086 1087 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1088 if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1089 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1090 nvme_pci_complete_batch)) 1091 nvme_pci_complete_rq(req); 1092 } 1093 1094 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 1095 { 1096 u32 tmp = nvmeq->cq_head + 1; 1097 1098 if (tmp == nvmeq->q_depth) { 1099 nvmeq->cq_head = 0; 1100 nvmeq->cq_phase ^= 1; 1101 } else { 1102 nvmeq->cq_head = tmp; 1103 } 1104 } 1105 1106 static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1107 struct io_comp_batch *iob) 1108 { 1109 int found = 0; 1110 1111 while (nvme_cqe_pending(nvmeq)) { 1112 found++; 1113 /* 1114 * load-load control dependency between phase and the rest of 1115 * the cqe requires a full read memory barrier 1116 */ 1117 dma_rmb(); 1118 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 1119 nvme_update_cq_head(nvmeq); 1120 } 1121 1122 if (found) 1123 nvme_ring_cq_doorbell(nvmeq); 1124 return found; 1125 } 1126 1127 static irqreturn_t nvme_irq(int irq, void *data) 1128 { 1129 struct nvme_queue *nvmeq = data; 1130 DEFINE_IO_COMP_BATCH(iob); 1131 1132 if (nvme_poll_cq(nvmeq, &iob)) { 1133 if (!rq_list_empty(iob.req_list)) 1134 nvme_pci_complete_batch(&iob); 1135 return IRQ_HANDLED; 1136 } 1137 return IRQ_NONE; 1138 } 1139 1140 static irqreturn_t nvme_irq_check(int irq, void *data) 1141 { 1142 struct nvme_queue *nvmeq = data; 1143 1144 if (nvme_cqe_pending(nvmeq)) 1145 return IRQ_WAKE_THREAD; 1146 return IRQ_NONE; 1147 } 1148 1149 /* 1150 * Poll for completions for any interrupt driven queue 1151 * Can be called from any context. 1152 */ 1153 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1154 { 1155 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1156 1157 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1158 1159 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1160 nvme_poll_cq(nvmeq, NULL); 1161 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1162 } 1163 1164 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 1165 { 1166 struct nvme_queue *nvmeq = hctx->driver_data; 1167 bool found; 1168 1169 if (!nvme_cqe_pending(nvmeq)) 1170 return 0; 1171 1172 spin_lock(&nvmeq->cq_poll_lock); 1173 found = nvme_poll_cq(nvmeq, iob); 1174 spin_unlock(&nvmeq->cq_poll_lock); 1175 1176 return found; 1177 } 1178 1179 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1180 { 1181 struct nvme_dev *dev = to_nvme_dev(ctrl); 1182 struct nvme_queue *nvmeq = &dev->queues[0]; 1183 struct nvme_command c = { }; 1184 1185 c.common.opcode = nvme_admin_async_event; 1186 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1187 1188 spin_lock(&nvmeq->sq_lock); 1189 nvme_sq_copy_cmd(nvmeq, &c); 1190 nvme_write_sq_db(nvmeq, true); 1191 spin_unlock(&nvmeq->sq_lock); 1192 } 1193 1194 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1195 { 1196 struct nvme_command c = { }; 1197 1198 c.delete_queue.opcode = opcode; 1199 c.delete_queue.qid = cpu_to_le16(id); 1200 1201 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1202 } 1203 1204 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1205 struct nvme_queue *nvmeq, s16 vector) 1206 { 1207 struct nvme_command c = { }; 1208 int flags = NVME_QUEUE_PHYS_CONTIG; 1209 1210 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1211 flags |= NVME_CQ_IRQ_ENABLED; 1212 1213 /* 1214 * Note: we (ab)use the fact that the prp fields survive if no data 1215 * is attached to the request. 1216 */ 1217 c.create_cq.opcode = nvme_admin_create_cq; 1218 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1219 c.create_cq.cqid = cpu_to_le16(qid); 1220 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1221 c.create_cq.cq_flags = cpu_to_le16(flags); 1222 c.create_cq.irq_vector = cpu_to_le16(vector); 1223 1224 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1225 } 1226 1227 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1228 struct nvme_queue *nvmeq) 1229 { 1230 struct nvme_ctrl *ctrl = &dev->ctrl; 1231 struct nvme_command c = { }; 1232 int flags = NVME_QUEUE_PHYS_CONTIG; 1233 1234 /* 1235 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1236 * set. Since URGENT priority is zeroes, it makes all queues 1237 * URGENT. 1238 */ 1239 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1240 flags |= NVME_SQ_PRIO_MEDIUM; 1241 1242 /* 1243 * Note: we (ab)use the fact that the prp fields survive if no data 1244 * is attached to the request. 1245 */ 1246 c.create_sq.opcode = nvme_admin_create_sq; 1247 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1248 c.create_sq.sqid = cpu_to_le16(qid); 1249 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1250 c.create_sq.sq_flags = cpu_to_le16(flags); 1251 c.create_sq.cqid = cpu_to_le16(qid); 1252 1253 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1254 } 1255 1256 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1257 { 1258 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1259 } 1260 1261 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1262 { 1263 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1264 } 1265 1266 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 1267 { 1268 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1269 1270 dev_warn(nvmeq->dev->ctrl.device, 1271 "Abort status: 0x%x", nvme_req(req)->status); 1272 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1273 blk_mq_free_request(req); 1274 return RQ_END_IO_NONE; 1275 } 1276 1277 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1278 { 1279 /* If true, indicates loss of adapter communication, possibly by a 1280 * NVMe Subsystem reset. 1281 */ 1282 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1283 1284 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1285 switch (dev->ctrl.state) { 1286 case NVME_CTRL_RESETTING: 1287 case NVME_CTRL_CONNECTING: 1288 return false; 1289 default: 1290 break; 1291 } 1292 1293 /* We shouldn't reset unless the controller is on fatal error state 1294 * _or_ if we lost the communication with it. 1295 */ 1296 if (!(csts & NVME_CSTS_CFS) && !nssro) 1297 return false; 1298 1299 return true; 1300 } 1301 1302 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1303 { 1304 /* Read a config register to help see what died. */ 1305 u16 pci_status; 1306 int result; 1307 1308 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1309 &pci_status); 1310 if (result == PCIBIOS_SUCCESSFUL) 1311 dev_warn(dev->ctrl.device, 1312 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1313 csts, pci_status); 1314 else 1315 dev_warn(dev->ctrl.device, 1316 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1317 csts, result); 1318 1319 if (csts != ~0) 1320 return; 1321 1322 dev_warn(dev->ctrl.device, 1323 "Does your device have a faulty power saving mode enabled?\n"); 1324 dev_warn(dev->ctrl.device, 1325 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1326 } 1327 1328 static enum blk_eh_timer_return nvme_timeout(struct request *req) 1329 { 1330 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1331 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1332 struct nvme_dev *dev = nvmeq->dev; 1333 struct request *abort_req; 1334 struct nvme_command cmd = { }; 1335 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1336 1337 /* If PCI error recovery process is happening, we cannot reset or 1338 * the recovery mechanism will surely fail. 1339 */ 1340 mb(); 1341 if (pci_channel_offline(to_pci_dev(dev->dev))) 1342 return BLK_EH_RESET_TIMER; 1343 1344 /* 1345 * Reset immediately if the controller is failed 1346 */ 1347 if (nvme_should_reset(dev, csts)) { 1348 nvme_warn_reset(dev, csts); 1349 nvme_dev_disable(dev, false); 1350 nvme_reset_ctrl(&dev->ctrl); 1351 return BLK_EH_DONE; 1352 } 1353 1354 /* 1355 * Did we miss an interrupt? 1356 */ 1357 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1358 nvme_poll(req->mq_hctx, NULL); 1359 else 1360 nvme_poll_irqdisable(nvmeq); 1361 1362 if (blk_mq_request_completed(req)) { 1363 dev_warn(dev->ctrl.device, 1364 "I/O %d QID %d timeout, completion polled\n", 1365 req->tag, nvmeq->qid); 1366 return BLK_EH_DONE; 1367 } 1368 1369 /* 1370 * Shutdown immediately if controller times out while starting. The 1371 * reset work will see the pci device disabled when it gets the forced 1372 * cancellation error. All outstanding requests are completed on 1373 * shutdown, so we return BLK_EH_DONE. 1374 */ 1375 switch (dev->ctrl.state) { 1376 case NVME_CTRL_CONNECTING: 1377 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1378 fallthrough; 1379 case NVME_CTRL_DELETING: 1380 dev_warn_ratelimited(dev->ctrl.device, 1381 "I/O %d QID %d timeout, disable controller\n", 1382 req->tag, nvmeq->qid); 1383 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1384 nvme_dev_disable(dev, true); 1385 return BLK_EH_DONE; 1386 case NVME_CTRL_RESETTING: 1387 return BLK_EH_RESET_TIMER; 1388 default: 1389 break; 1390 } 1391 1392 /* 1393 * Shutdown the controller immediately and schedule a reset if the 1394 * command was already aborted once before and still hasn't been 1395 * returned to the driver, or if this is the admin queue. 1396 */ 1397 if (!nvmeq->qid || iod->aborted) { 1398 dev_warn(dev->ctrl.device, 1399 "I/O %d QID %d timeout, reset controller\n", 1400 req->tag, nvmeq->qid); 1401 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1402 nvme_dev_disable(dev, false); 1403 nvme_reset_ctrl(&dev->ctrl); 1404 1405 return BLK_EH_DONE; 1406 } 1407 1408 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1409 atomic_inc(&dev->ctrl.abort_limit); 1410 return BLK_EH_RESET_TIMER; 1411 } 1412 iod->aborted = true; 1413 1414 cmd.abort.opcode = nvme_admin_abort_cmd; 1415 cmd.abort.cid = nvme_cid(req); 1416 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1417 1418 dev_warn(nvmeq->dev->ctrl.device, 1419 "I/O %d (%s) QID %d timeout, aborting\n", 1420 req->tag, 1421 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 1422 nvmeq->qid); 1423 1424 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 1425 BLK_MQ_REQ_NOWAIT); 1426 if (IS_ERR(abort_req)) { 1427 atomic_inc(&dev->ctrl.abort_limit); 1428 return BLK_EH_RESET_TIMER; 1429 } 1430 nvme_init_request(abort_req, &cmd); 1431 1432 abort_req->end_io = abort_endio; 1433 abort_req->end_io_data = NULL; 1434 abort_req->rq_flags |= RQF_QUIET; 1435 blk_execute_rq_nowait(abort_req, false); 1436 1437 /* 1438 * The aborted req will be completed on receiving the abort req. 1439 * We enable the timer again. If hit twice, it'll cause a device reset, 1440 * as the device then is in a faulty state. 1441 */ 1442 return BLK_EH_RESET_TIMER; 1443 } 1444 1445 static void nvme_free_queue(struct nvme_queue *nvmeq) 1446 { 1447 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1448 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1449 if (!nvmeq->sq_cmds) 1450 return; 1451 1452 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1453 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1454 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1455 } else { 1456 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1457 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1458 } 1459 } 1460 1461 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1462 { 1463 int i; 1464 1465 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1466 dev->ctrl.queue_count--; 1467 nvme_free_queue(&dev->queues[i]); 1468 } 1469 } 1470 1471 /** 1472 * nvme_suspend_queue - put queue into suspended state 1473 * @nvmeq: queue to suspend 1474 */ 1475 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1476 { 1477 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1478 return 1; 1479 1480 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1481 mb(); 1482 1483 nvmeq->dev->online_queues--; 1484 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1485 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl); 1486 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1487 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1488 return 0; 1489 } 1490 1491 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1492 { 1493 int i; 1494 1495 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1496 nvme_suspend_queue(&dev->queues[i]); 1497 } 1498 1499 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1500 { 1501 struct nvme_queue *nvmeq = &dev->queues[0]; 1502 1503 if (shutdown) 1504 nvme_shutdown_ctrl(&dev->ctrl); 1505 else 1506 nvme_disable_ctrl(&dev->ctrl); 1507 1508 nvme_poll_irqdisable(nvmeq); 1509 } 1510 1511 /* 1512 * Called only on a device that has been disabled and after all other threads 1513 * that can check this device's completion queues have synced, except 1514 * nvme_poll(). This is the last chance for the driver to see a natural 1515 * completion before nvme_cancel_request() terminates all incomplete requests. 1516 */ 1517 static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1518 { 1519 int i; 1520 1521 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1522 spin_lock(&dev->queues[i].cq_poll_lock); 1523 nvme_poll_cq(&dev->queues[i], NULL); 1524 spin_unlock(&dev->queues[i].cq_poll_lock); 1525 } 1526 } 1527 1528 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1529 int entry_size) 1530 { 1531 int q_depth = dev->q_depth; 1532 unsigned q_size_aligned = roundup(q_depth * entry_size, 1533 NVME_CTRL_PAGE_SIZE); 1534 1535 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1536 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1537 1538 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 1539 q_depth = div_u64(mem_per_q, entry_size); 1540 1541 /* 1542 * Ensure the reduced q_depth is above some threshold where it 1543 * would be better to map queues in system memory with the 1544 * original depth 1545 */ 1546 if (q_depth < 64) 1547 return -ENOMEM; 1548 } 1549 1550 return q_depth; 1551 } 1552 1553 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1554 int qid) 1555 { 1556 struct pci_dev *pdev = to_pci_dev(dev->dev); 1557 1558 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1559 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1560 if (nvmeq->sq_cmds) { 1561 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1562 nvmeq->sq_cmds); 1563 if (nvmeq->sq_dma_addr) { 1564 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1565 return 0; 1566 } 1567 1568 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1569 } 1570 } 1571 1572 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1573 &nvmeq->sq_dma_addr, GFP_KERNEL); 1574 if (!nvmeq->sq_cmds) 1575 return -ENOMEM; 1576 return 0; 1577 } 1578 1579 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1580 { 1581 struct nvme_queue *nvmeq = &dev->queues[qid]; 1582 1583 if (dev->ctrl.queue_count > qid) 1584 return 0; 1585 1586 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1587 nvmeq->q_depth = depth; 1588 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1589 &nvmeq->cq_dma_addr, GFP_KERNEL); 1590 if (!nvmeq->cqes) 1591 goto free_nvmeq; 1592 1593 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1594 goto free_cqdma; 1595 1596 nvmeq->dev = dev; 1597 spin_lock_init(&nvmeq->sq_lock); 1598 spin_lock_init(&nvmeq->cq_poll_lock); 1599 nvmeq->cq_head = 0; 1600 nvmeq->cq_phase = 1; 1601 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1602 nvmeq->qid = qid; 1603 dev->ctrl.queue_count++; 1604 1605 return 0; 1606 1607 free_cqdma: 1608 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1609 nvmeq->cq_dma_addr); 1610 free_nvmeq: 1611 return -ENOMEM; 1612 } 1613 1614 static int queue_request_irq(struct nvme_queue *nvmeq) 1615 { 1616 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1617 int nr = nvmeq->dev->ctrl.instance; 1618 1619 if (use_threaded_interrupts) { 1620 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1621 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1622 } else { 1623 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1624 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1625 } 1626 } 1627 1628 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1629 { 1630 struct nvme_dev *dev = nvmeq->dev; 1631 1632 nvmeq->sq_tail = 0; 1633 nvmeq->last_sq_tail = 0; 1634 nvmeq->cq_head = 0; 1635 nvmeq->cq_phase = 1; 1636 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1637 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1638 nvme_dbbuf_init(dev, nvmeq, qid); 1639 dev->online_queues++; 1640 wmb(); /* ensure the first interrupt sees the initialization */ 1641 } 1642 1643 /* 1644 * Try getting shutdown_lock while setting up IO queues. 1645 */ 1646 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1647 { 1648 /* 1649 * Give up if the lock is being held by nvme_dev_disable. 1650 */ 1651 if (!mutex_trylock(&dev->shutdown_lock)) 1652 return -ENODEV; 1653 1654 /* 1655 * Controller is in wrong state, fail early. 1656 */ 1657 if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1658 mutex_unlock(&dev->shutdown_lock); 1659 return -ENODEV; 1660 } 1661 1662 return 0; 1663 } 1664 1665 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1666 { 1667 struct nvme_dev *dev = nvmeq->dev; 1668 int result; 1669 u16 vector = 0; 1670 1671 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1672 1673 /* 1674 * A queue's vector matches the queue identifier unless the controller 1675 * has only one vector available. 1676 */ 1677 if (!polled) 1678 vector = dev->num_vecs == 1 ? 0 : qid; 1679 else 1680 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1681 1682 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1683 if (result) 1684 return result; 1685 1686 result = adapter_alloc_sq(dev, qid, nvmeq); 1687 if (result < 0) 1688 return result; 1689 if (result) 1690 goto release_cq; 1691 1692 nvmeq->cq_vector = vector; 1693 1694 result = nvme_setup_io_queues_trylock(dev); 1695 if (result) 1696 return result; 1697 nvme_init_queue(nvmeq, qid); 1698 if (!polled) { 1699 result = queue_request_irq(nvmeq); 1700 if (result < 0) 1701 goto release_sq; 1702 } 1703 1704 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1705 mutex_unlock(&dev->shutdown_lock); 1706 return result; 1707 1708 release_sq: 1709 dev->online_queues--; 1710 mutex_unlock(&dev->shutdown_lock); 1711 adapter_delete_sq(dev, qid); 1712 release_cq: 1713 adapter_delete_cq(dev, qid); 1714 return result; 1715 } 1716 1717 static const struct blk_mq_ops nvme_mq_admin_ops = { 1718 .queue_rq = nvme_queue_rq, 1719 .complete = nvme_pci_complete_rq, 1720 .init_hctx = nvme_admin_init_hctx, 1721 .init_request = nvme_pci_init_request, 1722 .timeout = nvme_timeout, 1723 }; 1724 1725 static const struct blk_mq_ops nvme_mq_ops = { 1726 .queue_rq = nvme_queue_rq, 1727 .queue_rqs = nvme_queue_rqs, 1728 .complete = nvme_pci_complete_rq, 1729 .commit_rqs = nvme_commit_rqs, 1730 .init_hctx = nvme_init_hctx, 1731 .init_request = nvme_pci_init_request, 1732 .map_queues = nvme_pci_map_queues, 1733 .timeout = nvme_timeout, 1734 .poll = nvme_poll, 1735 }; 1736 1737 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1738 { 1739 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1740 /* 1741 * If the controller was reset during removal, it's possible 1742 * user requests may be waiting on a stopped queue. Start the 1743 * queue to flush these to completion. 1744 */ 1745 nvme_unquiesce_admin_queue(&dev->ctrl); 1746 blk_mq_destroy_queue(dev->ctrl.admin_q); 1747 blk_put_queue(dev->ctrl.admin_q); 1748 blk_mq_free_tag_set(&dev->admin_tagset); 1749 } 1750 } 1751 1752 static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev) 1753 { 1754 struct blk_mq_tag_set *set = &dev->admin_tagset; 1755 1756 set->ops = &nvme_mq_admin_ops; 1757 set->nr_hw_queues = 1; 1758 1759 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1760 set->timeout = NVME_ADMIN_TIMEOUT; 1761 set->numa_node = dev->ctrl.numa_node; 1762 set->cmd_size = sizeof(struct nvme_iod); 1763 set->flags = BLK_MQ_F_NO_SCHED; 1764 set->driver_data = dev; 1765 1766 if (blk_mq_alloc_tag_set(set)) 1767 return -ENOMEM; 1768 dev->ctrl.admin_tagset = set; 1769 1770 dev->ctrl.admin_q = blk_mq_init_queue(set); 1771 if (IS_ERR(dev->ctrl.admin_q)) { 1772 blk_mq_free_tag_set(set); 1773 dev->ctrl.admin_q = NULL; 1774 return -ENOMEM; 1775 } 1776 return 0; 1777 } 1778 1779 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1780 { 1781 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1782 } 1783 1784 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1785 { 1786 struct pci_dev *pdev = to_pci_dev(dev->dev); 1787 1788 if (size <= dev->bar_mapped_size) 1789 return 0; 1790 if (size > pci_resource_len(pdev, 0)) 1791 return -ENOMEM; 1792 if (dev->bar) 1793 iounmap(dev->bar); 1794 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1795 if (!dev->bar) { 1796 dev->bar_mapped_size = 0; 1797 return -ENOMEM; 1798 } 1799 dev->bar_mapped_size = size; 1800 dev->dbs = dev->bar + NVME_REG_DBS; 1801 1802 return 0; 1803 } 1804 1805 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1806 { 1807 int result; 1808 u32 aqa; 1809 struct nvme_queue *nvmeq; 1810 1811 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1812 if (result < 0) 1813 return result; 1814 1815 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1816 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1817 1818 if (dev->subsystem && 1819 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1820 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1821 1822 result = nvme_disable_ctrl(&dev->ctrl); 1823 if (result < 0) 1824 return result; 1825 1826 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1827 if (result) 1828 return result; 1829 1830 dev->ctrl.numa_node = dev_to_node(dev->dev); 1831 1832 nvmeq = &dev->queues[0]; 1833 aqa = nvmeq->q_depth - 1; 1834 aqa |= aqa << 16; 1835 1836 writel(aqa, dev->bar + NVME_REG_AQA); 1837 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1838 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1839 1840 result = nvme_enable_ctrl(&dev->ctrl); 1841 if (result) 1842 return result; 1843 1844 nvmeq->cq_vector = 0; 1845 nvme_init_queue(nvmeq, 0); 1846 result = queue_request_irq(nvmeq); 1847 if (result) { 1848 dev->online_queues--; 1849 return result; 1850 } 1851 1852 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1853 return result; 1854 } 1855 1856 static int nvme_create_io_queues(struct nvme_dev *dev) 1857 { 1858 unsigned i, max, rw_queues; 1859 int ret = 0; 1860 1861 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1862 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1863 ret = -ENOMEM; 1864 break; 1865 } 1866 } 1867 1868 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1869 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1870 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1871 dev->io_queues[HCTX_TYPE_READ]; 1872 } else { 1873 rw_queues = max; 1874 } 1875 1876 for (i = dev->online_queues; i <= max; i++) { 1877 bool polled = i > rw_queues; 1878 1879 ret = nvme_create_queue(&dev->queues[i], i, polled); 1880 if (ret) 1881 break; 1882 } 1883 1884 /* 1885 * Ignore failing Create SQ/CQ commands, we can continue with less 1886 * than the desired amount of queues, and even a controller without 1887 * I/O queues can still be used to issue admin commands. This might 1888 * be useful to upgrade a buggy firmware for example. 1889 */ 1890 return ret >= 0 ? 0 : ret; 1891 } 1892 1893 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1894 { 1895 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1896 1897 return 1ULL << (12 + 4 * szu); 1898 } 1899 1900 static u32 nvme_cmb_size(struct nvme_dev *dev) 1901 { 1902 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1903 } 1904 1905 static void nvme_map_cmb(struct nvme_dev *dev) 1906 { 1907 u64 size, offset; 1908 resource_size_t bar_size; 1909 struct pci_dev *pdev = to_pci_dev(dev->dev); 1910 int bar; 1911 1912 if (dev->cmb_size) 1913 return; 1914 1915 if (NVME_CAP_CMBS(dev->ctrl.cap)) 1916 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 1917 1918 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1919 if (!dev->cmbsz) 1920 return; 1921 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1922 1923 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1924 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1925 bar = NVME_CMB_BIR(dev->cmbloc); 1926 bar_size = pci_resource_len(pdev, bar); 1927 1928 if (offset > bar_size) 1929 return; 1930 1931 /* 1932 * Tell the controller about the host side address mapping the CMB, 1933 * and enable CMB decoding for the NVMe 1.4+ scheme: 1934 */ 1935 if (NVME_CAP_CMBS(dev->ctrl.cap)) { 1936 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 1937 (pci_bus_address(pdev, bar) + offset), 1938 dev->bar + NVME_REG_CMBMSC); 1939 } 1940 1941 /* 1942 * Controllers may support a CMB size larger than their BAR, 1943 * for example, due to being behind a bridge. Reduce the CMB to 1944 * the reported size of the BAR 1945 */ 1946 if (size > bar_size - offset) 1947 size = bar_size - offset; 1948 1949 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1950 dev_warn(dev->ctrl.device, 1951 "failed to register the CMB\n"); 1952 return; 1953 } 1954 1955 dev->cmb_size = size; 1956 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1957 1958 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1959 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1960 pci_p2pmem_publish(pdev, true); 1961 } 1962 1963 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1964 { 1965 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 1966 u64 dma_addr = dev->host_mem_descs_dma; 1967 struct nvme_command c = { }; 1968 int ret; 1969 1970 c.features.opcode = nvme_admin_set_features; 1971 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1972 c.features.dword11 = cpu_to_le32(bits); 1973 c.features.dword12 = cpu_to_le32(host_mem_size); 1974 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1975 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1976 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1977 1978 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1979 if (ret) { 1980 dev_warn(dev->ctrl.device, 1981 "failed to set host mem (err %d, flags %#x).\n", 1982 ret, bits); 1983 } else 1984 dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1985 1986 return ret; 1987 } 1988 1989 static void nvme_free_host_mem(struct nvme_dev *dev) 1990 { 1991 int i; 1992 1993 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1994 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1995 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 1996 1997 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1998 le64_to_cpu(desc->addr), 1999 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2000 } 2001 2002 kfree(dev->host_mem_desc_bufs); 2003 dev->host_mem_desc_bufs = NULL; 2004 dma_free_coherent(dev->dev, 2005 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 2006 dev->host_mem_descs, dev->host_mem_descs_dma); 2007 dev->host_mem_descs = NULL; 2008 dev->nr_host_mem_descs = 0; 2009 } 2010 2011 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 2012 u32 chunk_size) 2013 { 2014 struct nvme_host_mem_buf_desc *descs; 2015 u32 max_entries, len; 2016 dma_addr_t descs_dma; 2017 int i = 0; 2018 void **bufs; 2019 u64 size, tmp; 2020 2021 tmp = (preferred + chunk_size - 1); 2022 do_div(tmp, chunk_size); 2023 max_entries = tmp; 2024 2025 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2026 max_entries = dev->ctrl.hmmaxd; 2027 2028 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 2029 &descs_dma, GFP_KERNEL); 2030 if (!descs) 2031 goto out; 2032 2033 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 2034 if (!bufs) 2035 goto out_free_descs; 2036 2037 for (size = 0; size < preferred && i < max_entries; size += len) { 2038 dma_addr_t dma_addr; 2039 2040 len = min_t(u64, chunk_size, preferred - size); 2041 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 2042 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2043 if (!bufs[i]) 2044 break; 2045 2046 descs[i].addr = cpu_to_le64(dma_addr); 2047 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 2048 i++; 2049 } 2050 2051 if (!size) 2052 goto out_free_bufs; 2053 2054 dev->nr_host_mem_descs = i; 2055 dev->host_mem_size = size; 2056 dev->host_mem_descs = descs; 2057 dev->host_mem_descs_dma = descs_dma; 2058 dev->host_mem_desc_bufs = bufs; 2059 return 0; 2060 2061 out_free_bufs: 2062 while (--i >= 0) { 2063 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 2064 2065 dma_free_attrs(dev->dev, size, bufs[i], 2066 le64_to_cpu(descs[i].addr), 2067 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2068 } 2069 2070 kfree(bufs); 2071 out_free_descs: 2072 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 2073 descs_dma); 2074 out: 2075 dev->host_mem_descs = NULL; 2076 return -ENOMEM; 2077 } 2078 2079 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 2080 { 2081 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 2082 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 2083 u64 chunk_size; 2084 2085 /* start big and work our way down */ 2086 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 2087 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 2088 if (!min || dev->host_mem_size >= min) 2089 return 0; 2090 nvme_free_host_mem(dev); 2091 } 2092 } 2093 2094 return -ENOMEM; 2095 } 2096 2097 static int nvme_setup_host_mem(struct nvme_dev *dev) 2098 { 2099 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 2100 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 2101 u64 min = (u64)dev->ctrl.hmmin * 4096; 2102 u32 enable_bits = NVME_HOST_MEM_ENABLE; 2103 int ret; 2104 2105 if (!dev->ctrl.hmpre) 2106 return 0; 2107 2108 preferred = min(preferred, max); 2109 if (min > max) { 2110 dev_warn(dev->ctrl.device, 2111 "min host memory (%lld MiB) above limit (%d MiB).\n", 2112 min >> ilog2(SZ_1M), max_host_mem_size_mb); 2113 nvme_free_host_mem(dev); 2114 return 0; 2115 } 2116 2117 /* 2118 * If we already have a buffer allocated check if we can reuse it. 2119 */ 2120 if (dev->host_mem_descs) { 2121 if (dev->host_mem_size >= min) 2122 enable_bits |= NVME_HOST_MEM_RETURN; 2123 else 2124 nvme_free_host_mem(dev); 2125 } 2126 2127 if (!dev->host_mem_descs) { 2128 if (nvme_alloc_host_mem(dev, min, preferred)) { 2129 dev_warn(dev->ctrl.device, 2130 "failed to allocate host memory buffer.\n"); 2131 return 0; /* controller must work without HMB */ 2132 } 2133 2134 dev_info(dev->ctrl.device, 2135 "allocated %lld MiB host memory buffer.\n", 2136 dev->host_mem_size >> ilog2(SZ_1M)); 2137 } 2138 2139 ret = nvme_set_host_mem(dev, enable_bits); 2140 if (ret) 2141 nvme_free_host_mem(dev); 2142 return ret; 2143 } 2144 2145 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 2146 char *buf) 2147 { 2148 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2149 2150 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 2151 ndev->cmbloc, ndev->cmbsz); 2152 } 2153 static DEVICE_ATTR_RO(cmb); 2154 2155 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 2156 char *buf) 2157 { 2158 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2159 2160 return sysfs_emit(buf, "%u\n", ndev->cmbloc); 2161 } 2162 static DEVICE_ATTR_RO(cmbloc); 2163 2164 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 2165 char *buf) 2166 { 2167 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2168 2169 return sysfs_emit(buf, "%u\n", ndev->cmbsz); 2170 } 2171 static DEVICE_ATTR_RO(cmbsz); 2172 2173 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2174 char *buf) 2175 { 2176 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2177 2178 return sysfs_emit(buf, "%d\n", ndev->hmb); 2179 } 2180 2181 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2182 const char *buf, size_t count) 2183 { 2184 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2185 bool new; 2186 int ret; 2187 2188 if (kstrtobool(buf, &new) < 0) 2189 return -EINVAL; 2190 2191 if (new == ndev->hmb) 2192 return count; 2193 2194 if (new) { 2195 ret = nvme_setup_host_mem(ndev); 2196 } else { 2197 ret = nvme_set_host_mem(ndev, 0); 2198 if (!ret) 2199 nvme_free_host_mem(ndev); 2200 } 2201 2202 if (ret < 0) 2203 return ret; 2204 2205 return count; 2206 } 2207 static DEVICE_ATTR_RW(hmb); 2208 2209 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 2210 struct attribute *a, int n) 2211 { 2212 struct nvme_ctrl *ctrl = 2213 dev_get_drvdata(container_of(kobj, struct device, kobj)); 2214 struct nvme_dev *dev = to_nvme_dev(ctrl); 2215 2216 if (a == &dev_attr_cmb.attr || 2217 a == &dev_attr_cmbloc.attr || 2218 a == &dev_attr_cmbsz.attr) { 2219 if (!dev->cmbsz) 2220 return 0; 2221 } 2222 if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2223 return 0; 2224 2225 return a->mode; 2226 } 2227 2228 static struct attribute *nvme_pci_attrs[] = { 2229 &dev_attr_cmb.attr, 2230 &dev_attr_cmbloc.attr, 2231 &dev_attr_cmbsz.attr, 2232 &dev_attr_hmb.attr, 2233 NULL, 2234 }; 2235 2236 static const struct attribute_group nvme_pci_dev_attrs_group = { 2237 .attrs = nvme_pci_attrs, 2238 .is_visible = nvme_pci_attrs_are_visible, 2239 }; 2240 2241 static const struct attribute_group *nvme_pci_dev_attr_groups[] = { 2242 &nvme_dev_attrs_group, 2243 &nvme_pci_dev_attrs_group, 2244 NULL, 2245 }; 2246 2247 /* 2248 * nirqs is the number of interrupts available for write and read 2249 * queues. The core already reserved an interrupt for the admin queue. 2250 */ 2251 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2252 { 2253 struct nvme_dev *dev = affd->priv; 2254 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2255 2256 /* 2257 * If there is no interrupt available for queues, ensure that 2258 * the default queue is set to 1. The affinity set size is 2259 * also set to one, but the irq core ignores it for this case. 2260 * 2261 * If only one interrupt is available or 'write_queue' == 0, combine 2262 * write and read queues. 2263 * 2264 * If 'write_queues' > 0, ensure it leaves room for at least one read 2265 * queue. 2266 */ 2267 if (!nrirqs) { 2268 nrirqs = 1; 2269 nr_read_queues = 0; 2270 } else if (nrirqs == 1 || !nr_write_queues) { 2271 nr_read_queues = 0; 2272 } else if (nr_write_queues >= nrirqs) { 2273 nr_read_queues = 1; 2274 } else { 2275 nr_read_queues = nrirqs - nr_write_queues; 2276 } 2277 2278 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2279 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2280 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2281 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2282 affd->nr_sets = nr_read_queues ? 2 : 1; 2283 } 2284 2285 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2286 { 2287 struct pci_dev *pdev = to_pci_dev(dev->dev); 2288 struct irq_affinity affd = { 2289 .pre_vectors = 1, 2290 .calc_sets = nvme_calc_irq_sets, 2291 .priv = dev, 2292 }; 2293 unsigned int irq_queues, poll_queues; 2294 2295 /* 2296 * Poll queues don't need interrupts, but we need at least one I/O queue 2297 * left over for non-polled I/O. 2298 */ 2299 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 2300 dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 2301 2302 /* 2303 * Initialize for the single interrupt case, will be updated in 2304 * nvme_calc_irq_sets(). 2305 */ 2306 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2307 dev->io_queues[HCTX_TYPE_READ] = 0; 2308 2309 /* 2310 * We need interrupts for the admin queue and each non-polled I/O queue, 2311 * but some Apple controllers require all queues to use the first 2312 * vector. 2313 */ 2314 irq_queues = 1; 2315 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 2316 irq_queues += (nr_io_queues - poll_queues); 2317 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2318 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2319 } 2320 2321 static void nvme_disable_io_queues(struct nvme_dev *dev) 2322 { 2323 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2324 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2325 } 2326 2327 static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 2328 { 2329 /* 2330 * If tags are shared with admin queue (Apple bug), then 2331 * make sure we only use one IO queue. 2332 */ 2333 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2334 return 1; 2335 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 2336 } 2337 2338 static int nvme_setup_io_queues(struct nvme_dev *dev) 2339 { 2340 struct nvme_queue *adminq = &dev->queues[0]; 2341 struct pci_dev *pdev = to_pci_dev(dev->dev); 2342 unsigned int nr_io_queues; 2343 unsigned long size; 2344 int result; 2345 2346 /* 2347 * Sample the module parameters once at reset time so that we have 2348 * stable values to work with. 2349 */ 2350 dev->nr_write_queues = write_queues; 2351 dev->nr_poll_queues = poll_queues; 2352 2353 nr_io_queues = dev->nr_allocated_queues - 1; 2354 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2355 if (result < 0) 2356 return result; 2357 2358 if (nr_io_queues == 0) 2359 return 0; 2360 2361 /* 2362 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2363 * from set to unset. If there is a window to it is truely freed, 2364 * pci_free_irq_vectors() jumping into this window will crash. 2365 * And take lock to avoid racing with pci_free_irq_vectors() in 2366 * nvme_dev_disable() path. 2367 */ 2368 result = nvme_setup_io_queues_trylock(dev); 2369 if (result) 2370 return result; 2371 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2372 pci_free_irq(pdev, 0, adminq); 2373 2374 if (dev->cmb_use_sqes) { 2375 result = nvme_cmb_qdepth(dev, nr_io_queues, 2376 sizeof(struct nvme_command)); 2377 if (result > 0) 2378 dev->q_depth = result; 2379 else 2380 dev->cmb_use_sqes = false; 2381 } 2382 2383 do { 2384 size = db_bar_size(dev, nr_io_queues); 2385 result = nvme_remap_bar(dev, size); 2386 if (!result) 2387 break; 2388 if (!--nr_io_queues) { 2389 result = -ENOMEM; 2390 goto out_unlock; 2391 } 2392 } while (1); 2393 adminq->q_db = dev->dbs; 2394 2395 retry: 2396 /* Deregister the admin queue's interrupt */ 2397 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2398 pci_free_irq(pdev, 0, adminq); 2399 2400 /* 2401 * If we enable msix early due to not intx, disable it again before 2402 * setting up the full range we need. 2403 */ 2404 pci_free_irq_vectors(pdev); 2405 2406 result = nvme_setup_irqs(dev, nr_io_queues); 2407 if (result <= 0) { 2408 result = -EIO; 2409 goto out_unlock; 2410 } 2411 2412 dev->num_vecs = result; 2413 result = max(result - 1, 1); 2414 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2415 2416 /* 2417 * Should investigate if there's a performance win from allocating 2418 * more queues than interrupt vectors; it might allow the submission 2419 * path to scale better, even if the receive path is limited by the 2420 * number of interrupts. 2421 */ 2422 result = queue_request_irq(adminq); 2423 if (result) 2424 goto out_unlock; 2425 set_bit(NVMEQ_ENABLED, &adminq->flags); 2426 mutex_unlock(&dev->shutdown_lock); 2427 2428 result = nvme_create_io_queues(dev); 2429 if (result || dev->online_queues < 2) 2430 return result; 2431 2432 if (dev->online_queues - 1 < dev->max_qid) { 2433 nr_io_queues = dev->online_queues - 1; 2434 nvme_disable_io_queues(dev); 2435 result = nvme_setup_io_queues_trylock(dev); 2436 if (result) 2437 return result; 2438 nvme_suspend_io_queues(dev); 2439 goto retry; 2440 } 2441 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2442 dev->io_queues[HCTX_TYPE_DEFAULT], 2443 dev->io_queues[HCTX_TYPE_READ], 2444 dev->io_queues[HCTX_TYPE_POLL]); 2445 return 0; 2446 out_unlock: 2447 mutex_unlock(&dev->shutdown_lock); 2448 return result; 2449 } 2450 2451 static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2452 blk_status_t error) 2453 { 2454 struct nvme_queue *nvmeq = req->end_io_data; 2455 2456 blk_mq_free_request(req); 2457 complete(&nvmeq->delete_done); 2458 return RQ_END_IO_NONE; 2459 } 2460 2461 static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2462 blk_status_t error) 2463 { 2464 struct nvme_queue *nvmeq = req->end_io_data; 2465 2466 if (error) 2467 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2468 2469 return nvme_del_queue_end(req, error); 2470 } 2471 2472 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2473 { 2474 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2475 struct request *req; 2476 struct nvme_command cmd = { }; 2477 2478 cmd.delete_queue.opcode = opcode; 2479 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2480 2481 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2482 if (IS_ERR(req)) 2483 return PTR_ERR(req); 2484 nvme_init_request(req, &cmd); 2485 2486 if (opcode == nvme_admin_delete_cq) 2487 req->end_io = nvme_del_cq_end; 2488 else 2489 req->end_io = nvme_del_queue_end; 2490 req->end_io_data = nvmeq; 2491 2492 init_completion(&nvmeq->delete_done); 2493 req->rq_flags |= RQF_QUIET; 2494 blk_execute_rq_nowait(req, false); 2495 return 0; 2496 } 2497 2498 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2499 { 2500 int nr_queues = dev->online_queues - 1, sent = 0; 2501 unsigned long timeout; 2502 2503 retry: 2504 timeout = NVME_ADMIN_TIMEOUT; 2505 while (nr_queues > 0) { 2506 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2507 break; 2508 nr_queues--; 2509 sent++; 2510 } 2511 while (sent) { 2512 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2513 2514 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2515 timeout); 2516 if (timeout == 0) 2517 return false; 2518 2519 sent--; 2520 if (nr_queues) 2521 goto retry; 2522 } 2523 return true; 2524 } 2525 2526 static void nvme_pci_alloc_tag_set(struct nvme_dev *dev) 2527 { 2528 struct blk_mq_tag_set * set = &dev->tagset; 2529 int ret; 2530 2531 set->ops = &nvme_mq_ops; 2532 set->nr_hw_queues = dev->online_queues - 1; 2533 set->nr_maps = 1; 2534 if (dev->io_queues[HCTX_TYPE_READ]) 2535 set->nr_maps = 2; 2536 if (dev->io_queues[HCTX_TYPE_POLL]) 2537 set->nr_maps = 3; 2538 set->timeout = NVME_IO_TIMEOUT; 2539 set->numa_node = dev->ctrl.numa_node; 2540 set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2541 set->cmd_size = sizeof(struct nvme_iod); 2542 set->flags = BLK_MQ_F_SHOULD_MERGE; 2543 set->driver_data = dev; 2544 2545 /* 2546 * Some Apple controllers requires tags to be unique 2547 * across admin and IO queue, so reserve the first 32 2548 * tags of the IO queue. 2549 */ 2550 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2551 set->reserved_tags = NVME_AQ_DEPTH; 2552 2553 ret = blk_mq_alloc_tag_set(set); 2554 if (ret) { 2555 dev_warn(dev->ctrl.device, 2556 "IO queues tagset allocation failed %d\n", ret); 2557 return; 2558 } 2559 dev->ctrl.tagset = set; 2560 } 2561 2562 static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 2563 { 2564 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2565 /* free previously allocated queues that are no longer usable */ 2566 nvme_free_queues(dev, dev->online_queues); 2567 } 2568 2569 static int nvme_pci_enable(struct nvme_dev *dev) 2570 { 2571 int result = -ENOMEM; 2572 struct pci_dev *pdev = to_pci_dev(dev->dev); 2573 int dma_address_bits = 64; 2574 2575 if (pci_enable_device_mem(pdev)) 2576 return result; 2577 2578 pci_set_master(pdev); 2579 2580 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 2581 dma_address_bits = 48; 2582 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 2583 goto disable; 2584 2585 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2586 result = -ENODEV; 2587 goto disable; 2588 } 2589 2590 /* 2591 * Some devices and/or platforms don't advertise or work with INTx 2592 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2593 * adjust this later. 2594 */ 2595 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2596 if (result < 0) 2597 return result; 2598 2599 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2600 2601 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2602 io_queue_depth); 2603 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2604 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2605 dev->dbs = dev->bar + 4096; 2606 2607 /* 2608 * Some Apple controllers require a non-standard SQE size. 2609 * Interestingly they also seem to ignore the CC:IOSQES register 2610 * so we don't bother updating it here. 2611 */ 2612 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2613 dev->io_sqes = 7; 2614 else 2615 dev->io_sqes = NVME_NVM_IOSQES; 2616 2617 /* 2618 * Temporary fix for the Apple controller found in the MacBook8,1 and 2619 * some MacBook7,1 to avoid controller resets and data loss. 2620 */ 2621 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2622 dev->q_depth = 2; 2623 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2624 "set queue depth=%u to work around controller resets\n", 2625 dev->q_depth); 2626 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2627 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2628 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2629 dev->q_depth = 64; 2630 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2631 "set queue depth=%u\n", dev->q_depth); 2632 } 2633 2634 /* 2635 * Controllers with the shared tags quirk need the IO queue to be 2636 * big enough so that we get 32 tags for the admin queue 2637 */ 2638 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2639 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2640 dev->q_depth = NVME_AQ_DEPTH + 2; 2641 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2642 dev->q_depth); 2643 } 2644 2645 2646 nvme_map_cmb(dev); 2647 2648 pci_enable_pcie_error_reporting(pdev); 2649 pci_save_state(pdev); 2650 2651 return nvme_pci_configure_admin_queue(dev); 2652 2653 disable: 2654 pci_disable_device(pdev); 2655 return result; 2656 } 2657 2658 static void nvme_dev_unmap(struct nvme_dev *dev) 2659 { 2660 if (dev->bar) 2661 iounmap(dev->bar); 2662 pci_release_mem_regions(to_pci_dev(dev->dev)); 2663 } 2664 2665 static void nvme_pci_disable(struct nvme_dev *dev) 2666 { 2667 struct pci_dev *pdev = to_pci_dev(dev->dev); 2668 2669 pci_free_irq_vectors(pdev); 2670 2671 if (pci_is_enabled(pdev)) { 2672 pci_disable_pcie_error_reporting(pdev); 2673 pci_disable_device(pdev); 2674 } 2675 } 2676 2677 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2678 { 2679 bool dead = true, freeze = false; 2680 struct pci_dev *pdev = to_pci_dev(dev->dev); 2681 2682 mutex_lock(&dev->shutdown_lock); 2683 if (pci_is_enabled(pdev)) { 2684 u32 csts; 2685 2686 if (pci_device_is_present(pdev)) 2687 csts = readl(dev->bar + NVME_REG_CSTS); 2688 else 2689 csts = ~0; 2690 2691 if (dev->ctrl.state == NVME_CTRL_LIVE || 2692 dev->ctrl.state == NVME_CTRL_RESETTING) { 2693 freeze = true; 2694 nvme_start_freeze(&dev->ctrl); 2695 } 2696 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2697 pdev->error_state != pci_channel_io_normal); 2698 } 2699 2700 /* 2701 * Give the controller a chance to complete all entered requests if 2702 * doing a safe shutdown. 2703 */ 2704 if (!dead && shutdown && freeze) 2705 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2706 2707 nvme_quiesce_io_queues(&dev->ctrl); 2708 2709 if (!dead && dev->ctrl.queue_count > 0) { 2710 nvme_disable_io_queues(dev); 2711 nvme_disable_admin_queue(dev, shutdown); 2712 } 2713 nvme_suspend_io_queues(dev); 2714 nvme_suspend_queue(&dev->queues[0]); 2715 nvme_pci_disable(dev); 2716 nvme_reap_pending_cqes(dev); 2717 2718 nvme_cancel_tagset(&dev->ctrl); 2719 nvme_cancel_admin_tagset(&dev->ctrl); 2720 2721 /* 2722 * The driver will not be starting up queues again if shutting down so 2723 * must flush all entered requests to their failed completion to avoid 2724 * deadlocking blk-mq hot-cpu notifier. 2725 */ 2726 if (shutdown) { 2727 nvme_unquiesce_io_queues(&dev->ctrl); 2728 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2729 nvme_unquiesce_admin_queue(&dev->ctrl); 2730 } 2731 mutex_unlock(&dev->shutdown_lock); 2732 } 2733 2734 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2735 { 2736 if (!nvme_wait_reset(&dev->ctrl)) 2737 return -EBUSY; 2738 nvme_dev_disable(dev, shutdown); 2739 return 0; 2740 } 2741 2742 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2743 { 2744 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2745 NVME_CTRL_PAGE_SIZE, 2746 NVME_CTRL_PAGE_SIZE, 0); 2747 if (!dev->prp_page_pool) 2748 return -ENOMEM; 2749 2750 /* Optimisation for I/Os between 4k and 128k */ 2751 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2752 256, 256, 0); 2753 if (!dev->prp_small_pool) { 2754 dma_pool_destroy(dev->prp_page_pool); 2755 return -ENOMEM; 2756 } 2757 return 0; 2758 } 2759 2760 static void nvme_release_prp_pools(struct nvme_dev *dev) 2761 { 2762 dma_pool_destroy(dev->prp_page_pool); 2763 dma_pool_destroy(dev->prp_small_pool); 2764 } 2765 2766 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2767 { 2768 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 2769 size_t alloc_size = sizeof(__le64 *) * npages + 2770 sizeof(struct scatterlist) * NVME_MAX_SEGS; 2771 2772 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2773 dev->iod_mempool = mempool_create_node(1, 2774 mempool_kmalloc, mempool_kfree, 2775 (void *)alloc_size, GFP_KERNEL, 2776 dev_to_node(dev->dev)); 2777 if (!dev->iod_mempool) 2778 return -ENOMEM; 2779 return 0; 2780 } 2781 2782 static void nvme_free_tagset(struct nvme_dev *dev) 2783 { 2784 if (dev->tagset.tags) 2785 blk_mq_free_tag_set(&dev->tagset); 2786 dev->ctrl.tagset = NULL; 2787 } 2788 2789 /* pairs with nvme_pci_alloc_dev */ 2790 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2791 { 2792 struct nvme_dev *dev = to_nvme_dev(ctrl); 2793 2794 nvme_free_tagset(dev); 2795 put_device(dev->dev); 2796 kfree(dev->queues); 2797 kfree(dev); 2798 } 2799 2800 static void nvme_reset_work(struct work_struct *work) 2801 { 2802 struct nvme_dev *dev = 2803 container_of(work, struct nvme_dev, ctrl.reset_work); 2804 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2805 int result; 2806 2807 if (dev->ctrl.state != NVME_CTRL_RESETTING) { 2808 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 2809 dev->ctrl.state); 2810 result = -ENODEV; 2811 goto out; 2812 } 2813 2814 /* 2815 * If we're called to reset a live controller first shut it down before 2816 * moving on. 2817 */ 2818 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2819 nvme_dev_disable(dev, false); 2820 nvme_sync_queues(&dev->ctrl); 2821 2822 mutex_lock(&dev->shutdown_lock); 2823 result = nvme_pci_enable(dev); 2824 if (result) 2825 goto out_unlock; 2826 nvme_unquiesce_admin_queue(&dev->ctrl); 2827 mutex_unlock(&dev->shutdown_lock); 2828 2829 /* 2830 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2831 * initializing procedure here. 2832 */ 2833 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2834 dev_warn(dev->ctrl.device, 2835 "failed to mark controller CONNECTING\n"); 2836 result = -EBUSY; 2837 goto out; 2838 } 2839 2840 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); 2841 if (result) 2842 goto out; 2843 2844 nvme_dbbuf_dma_alloc(dev); 2845 2846 result = nvme_setup_host_mem(dev); 2847 if (result < 0) 2848 goto out; 2849 2850 result = nvme_setup_io_queues(dev); 2851 if (result) 2852 goto out; 2853 2854 /* 2855 * Freeze and update the number of I/O queues as thos might have 2856 * changed. If there are no I/O queues left after this reset, keep the 2857 * controller around but remove all namespaces. 2858 */ 2859 if (dev->online_queues > 1) { 2860 nvme_unquiesce_io_queues(&dev->ctrl); 2861 nvme_wait_freeze(&dev->ctrl); 2862 nvme_pci_update_nr_queues(dev); 2863 nvme_dbbuf_set(dev); 2864 nvme_unfreeze(&dev->ctrl); 2865 } else { 2866 dev_warn(dev->ctrl.device, "IO queues lost\n"); 2867 nvme_mark_namespaces_dead(&dev->ctrl); 2868 nvme_unquiesce_io_queues(&dev->ctrl); 2869 nvme_remove_namespaces(&dev->ctrl); 2870 nvme_free_tagset(dev); 2871 } 2872 2873 /* 2874 * If only admin queue live, keep it to do further investigation or 2875 * recovery. 2876 */ 2877 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2878 dev_warn(dev->ctrl.device, 2879 "failed to mark controller live state\n"); 2880 result = -ENODEV; 2881 goto out; 2882 } 2883 2884 nvme_start_ctrl(&dev->ctrl); 2885 return; 2886 2887 out_unlock: 2888 mutex_unlock(&dev->shutdown_lock); 2889 out: 2890 /* 2891 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2892 * may be holding this pci_dev's device lock. 2893 */ 2894 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n", 2895 result); 2896 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2897 nvme_dev_disable(dev, true); 2898 nvme_mark_namespaces_dead(&dev->ctrl); 2899 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2900 } 2901 2902 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2903 { 2904 *val = readl(to_nvme_dev(ctrl)->bar + off); 2905 return 0; 2906 } 2907 2908 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2909 { 2910 writel(val, to_nvme_dev(ctrl)->bar + off); 2911 return 0; 2912 } 2913 2914 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2915 { 2916 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2917 return 0; 2918 } 2919 2920 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2921 { 2922 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2923 2924 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 2925 } 2926 2927 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 2928 { 2929 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2930 struct nvme_subsystem *subsys = ctrl->subsys; 2931 2932 dev_err(ctrl->device, 2933 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 2934 pdev->vendor, pdev->device, 2935 nvme_strlen(subsys->model, sizeof(subsys->model)), 2936 subsys->model, nvme_strlen(subsys->firmware_rev, 2937 sizeof(subsys->firmware_rev)), 2938 subsys->firmware_rev); 2939 } 2940 2941 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 2942 { 2943 struct nvme_dev *dev = to_nvme_dev(ctrl); 2944 2945 return dma_pci_p2pdma_supported(dev->dev); 2946 } 2947 2948 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2949 .name = "pcie", 2950 .module = THIS_MODULE, 2951 .flags = NVME_F_METADATA_SUPPORTED, 2952 .dev_attr_groups = nvme_pci_dev_attr_groups, 2953 .reg_read32 = nvme_pci_reg_read32, 2954 .reg_write32 = nvme_pci_reg_write32, 2955 .reg_read64 = nvme_pci_reg_read64, 2956 .free_ctrl = nvme_pci_free_ctrl, 2957 .submit_async_event = nvme_pci_submit_async_event, 2958 .get_address = nvme_pci_get_address, 2959 .print_device_info = nvme_pci_print_device_info, 2960 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 2961 }; 2962 2963 static int nvme_dev_map(struct nvme_dev *dev) 2964 { 2965 struct pci_dev *pdev = to_pci_dev(dev->dev); 2966 2967 if (pci_request_mem_regions(pdev, "nvme")) 2968 return -ENODEV; 2969 2970 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2971 goto release; 2972 2973 return 0; 2974 release: 2975 pci_release_mem_regions(pdev); 2976 return -ENODEV; 2977 } 2978 2979 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2980 { 2981 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2982 /* 2983 * Several Samsung devices seem to drop off the PCIe bus 2984 * randomly when APST is on and uses the deepest sleep state. 2985 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2986 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2987 * 950 PRO 256GB", but it seems to be restricted to two Dell 2988 * laptops. 2989 */ 2990 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2991 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2992 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2993 return NVME_QUIRK_NO_DEEPEST_PS; 2994 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2995 /* 2996 * Samsung SSD 960 EVO drops off the PCIe bus after system 2997 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2998 * within few minutes after bootup on a Coffee Lake board - 2999 * ASUS PRIME Z370-A 3000 */ 3001 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 3002 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 3003 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 3004 return NVME_QUIRK_NO_APST; 3005 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 3006 pdev->device == 0xa808 || pdev->device == 0xa809)) || 3007 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 3008 /* 3009 * Forcing to use host managed nvme power settings for 3010 * lowest idle power with quick resume latency on 3011 * Samsung and Toshiba SSDs based on suspend behavior 3012 * on Coffee Lake board for LENOVO C640 3013 */ 3014 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 3015 dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 3016 return NVME_QUIRK_SIMPLE_SUSPEND; 3017 } 3018 3019 return 0; 3020 } 3021 3022 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 3023 const struct pci_device_id *id) 3024 { 3025 unsigned long quirks = id->driver_data; 3026 int node = dev_to_node(&pdev->dev); 3027 struct nvme_dev *dev; 3028 int ret = -ENOMEM; 3029 3030 if (node == NUMA_NO_NODE) 3031 set_dev_node(&pdev->dev, first_memory_node); 3032 3033 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 3034 if (!dev) 3035 return NULL; 3036 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 3037 mutex_init(&dev->shutdown_lock); 3038 3039 dev->nr_write_queues = write_queues; 3040 dev->nr_poll_queues = poll_queues; 3041 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 3042 dev->queues = kcalloc_node(dev->nr_allocated_queues, 3043 sizeof(struct nvme_queue), GFP_KERNEL, node); 3044 if (!dev->queues) 3045 goto out_free_dev; 3046 3047 dev->dev = get_device(&pdev->dev); 3048 3049 quirks |= check_vendor_combination_bug(pdev); 3050 if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3051 /* 3052 * Some systems use a bios work around to ask for D3 on 3053 * platforms that support kernel managed suspend. 3054 */ 3055 dev_info(&pdev->dev, 3056 "platform quirk: setting simple suspend\n"); 3057 quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3058 } 3059 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3060 quirks); 3061 if (ret) 3062 goto out_put_device; 3063 3064 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); 3065 dma_set_max_seg_size(&pdev->dev, 0xffffffff); 3066 3067 /* 3068 * Limit the max command size to prevent iod->sg allocations going 3069 * over a single page. 3070 */ 3071 dev->ctrl.max_hw_sectors = min_t(u32, 3072 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9); 3073 dev->ctrl.max_segments = NVME_MAX_SEGS; 3074 3075 /* 3076 * There is no support for SGLs for metadata (yet), so we are limited to 3077 * a single integrity segment for the separate metadata pointer. 3078 */ 3079 dev->ctrl.max_integrity_segments = 1; 3080 return dev; 3081 3082 out_put_device: 3083 put_device(dev->dev); 3084 kfree(dev->queues); 3085 out_free_dev: 3086 kfree(dev); 3087 return ERR_PTR(ret); 3088 } 3089 3090 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3091 { 3092 struct nvme_dev *dev; 3093 int result = -ENOMEM; 3094 3095 dev = nvme_pci_alloc_dev(pdev, id); 3096 if (!dev) 3097 return -ENOMEM; 3098 3099 result = nvme_dev_map(dev); 3100 if (result) 3101 goto out_uninit_ctrl; 3102 3103 result = nvme_setup_prp_pools(dev); 3104 if (result) 3105 goto out_dev_unmap; 3106 3107 result = nvme_pci_alloc_iod_mempool(dev); 3108 if (result) 3109 goto out_release_prp_pools; 3110 3111 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 3112 3113 result = nvme_pci_enable(dev); 3114 if (result) 3115 goto out_release_iod_mempool; 3116 3117 result = nvme_pci_alloc_admin_tag_set(dev); 3118 if (result) 3119 goto out_disable; 3120 3121 /* 3122 * Mark the controller as connecting before sending admin commands to 3123 * allow the timeout handler to do the right thing. 3124 */ 3125 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 3126 dev_warn(dev->ctrl.device, 3127 "failed to mark controller CONNECTING\n"); 3128 result = -EBUSY; 3129 goto out_disable; 3130 } 3131 3132 result = nvme_init_ctrl_finish(&dev->ctrl, false); 3133 if (result) 3134 goto out_disable; 3135 3136 nvme_dbbuf_dma_alloc(dev); 3137 3138 result = nvme_setup_host_mem(dev); 3139 if (result < 0) 3140 goto out_disable; 3141 3142 result = nvme_setup_io_queues(dev); 3143 if (result) 3144 goto out_disable; 3145 3146 if (dev->online_queues > 1) { 3147 nvme_pci_alloc_tag_set(dev); 3148 nvme_dbbuf_set(dev); 3149 } else { 3150 dev_warn(dev->ctrl.device, "IO queues not created\n"); 3151 } 3152 3153 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 3154 dev_warn(dev->ctrl.device, 3155 "failed to mark controller live state\n"); 3156 result = -ENODEV; 3157 goto out_disable; 3158 } 3159 3160 pci_set_drvdata(pdev, dev); 3161 3162 nvme_start_ctrl(&dev->ctrl); 3163 nvme_put_ctrl(&dev->ctrl); 3164 return 0; 3165 3166 out_disable: 3167 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3168 nvme_dev_disable(dev, true); 3169 nvme_free_host_mem(dev); 3170 nvme_dev_remove_admin(dev); 3171 nvme_dbbuf_dma_free(dev); 3172 nvme_free_queues(dev, 0); 3173 out_release_iod_mempool: 3174 mempool_destroy(dev->iod_mempool); 3175 out_release_prp_pools: 3176 nvme_release_prp_pools(dev); 3177 out_dev_unmap: 3178 nvme_dev_unmap(dev); 3179 out_uninit_ctrl: 3180 nvme_uninit_ctrl(&dev->ctrl); 3181 return result; 3182 } 3183 3184 static void nvme_reset_prepare(struct pci_dev *pdev) 3185 { 3186 struct nvme_dev *dev = pci_get_drvdata(pdev); 3187 3188 /* 3189 * We don't need to check the return value from waiting for the reset 3190 * state as pci_dev device lock is held, making it impossible to race 3191 * with ->remove(). 3192 */ 3193 nvme_disable_prepare_reset(dev, false); 3194 nvme_sync_queues(&dev->ctrl); 3195 } 3196 3197 static void nvme_reset_done(struct pci_dev *pdev) 3198 { 3199 struct nvme_dev *dev = pci_get_drvdata(pdev); 3200 3201 if (!nvme_try_sched_reset(&dev->ctrl)) 3202 flush_work(&dev->ctrl.reset_work); 3203 } 3204 3205 static void nvme_shutdown(struct pci_dev *pdev) 3206 { 3207 struct nvme_dev *dev = pci_get_drvdata(pdev); 3208 3209 nvme_disable_prepare_reset(dev, true); 3210 } 3211 3212 /* 3213 * The driver's remove may be called on a device in a partially initialized 3214 * state. This function must not have any dependencies on the device state in 3215 * order to proceed. 3216 */ 3217 static void nvme_remove(struct pci_dev *pdev) 3218 { 3219 struct nvme_dev *dev = pci_get_drvdata(pdev); 3220 3221 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3222 pci_set_drvdata(pdev, NULL); 3223 3224 if (!pci_device_is_present(pdev)) { 3225 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 3226 nvme_dev_disable(dev, true); 3227 } 3228 3229 flush_work(&dev->ctrl.reset_work); 3230 nvme_stop_ctrl(&dev->ctrl); 3231 nvme_remove_namespaces(&dev->ctrl); 3232 nvme_dev_disable(dev, true); 3233 nvme_free_host_mem(dev); 3234 nvme_dev_remove_admin(dev); 3235 nvme_dbbuf_dma_free(dev); 3236 nvme_free_queues(dev, 0); 3237 mempool_destroy(dev->iod_mempool); 3238 nvme_release_prp_pools(dev); 3239 nvme_dev_unmap(dev); 3240 nvme_uninit_ctrl(&dev->ctrl); 3241 } 3242 3243 #ifdef CONFIG_PM_SLEEP 3244 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3245 { 3246 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3247 } 3248 3249 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3250 { 3251 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3252 } 3253 3254 static int nvme_resume(struct device *dev) 3255 { 3256 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3257 struct nvme_ctrl *ctrl = &ndev->ctrl; 3258 3259 if (ndev->last_ps == U32_MAX || 3260 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3261 goto reset; 3262 if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3263 goto reset; 3264 3265 return 0; 3266 reset: 3267 return nvme_try_sched_reset(ctrl); 3268 } 3269 3270 static int nvme_suspend(struct device *dev) 3271 { 3272 struct pci_dev *pdev = to_pci_dev(dev); 3273 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3274 struct nvme_ctrl *ctrl = &ndev->ctrl; 3275 int ret = -EBUSY; 3276 3277 ndev->last_ps = U32_MAX; 3278 3279 /* 3280 * The platform does not remove power for a kernel managed suspend so 3281 * use host managed nvme power settings for lowest idle power if 3282 * possible. This should have quicker resume latency than a full device 3283 * shutdown. But if the firmware is involved after the suspend or the 3284 * device does not support any non-default power states, shut down the 3285 * device fully. 3286 * 3287 * If ASPM is not enabled for the device, shut down the device and allow 3288 * the PCI bus layer to put it into D3 in order to take the PCIe link 3289 * down, so as to allow the platform to achieve its minimum low-power 3290 * state (which may not be possible if the link is up). 3291 */ 3292 if (pm_suspend_via_firmware() || !ctrl->npss || 3293 !pcie_aspm_enabled(pdev) || 3294 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3295 return nvme_disable_prepare_reset(ndev, true); 3296 3297 nvme_start_freeze(ctrl); 3298 nvme_wait_freeze(ctrl); 3299 nvme_sync_queues(ctrl); 3300 3301 if (ctrl->state != NVME_CTRL_LIVE) 3302 goto unfreeze; 3303 3304 /* 3305 * Host memory access may not be successful in a system suspend state, 3306 * but the specification allows the controller to access memory in a 3307 * non-operational power state. 3308 */ 3309 if (ndev->hmb) { 3310 ret = nvme_set_host_mem(ndev, 0); 3311 if (ret < 0) 3312 goto unfreeze; 3313 } 3314 3315 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3316 if (ret < 0) 3317 goto unfreeze; 3318 3319 /* 3320 * A saved state prevents pci pm from generically controlling the 3321 * device's power. If we're using protocol specific settings, we don't 3322 * want pci interfering. 3323 */ 3324 pci_save_state(pdev); 3325 3326 ret = nvme_set_power_state(ctrl, ctrl->npss); 3327 if (ret < 0) 3328 goto unfreeze; 3329 3330 if (ret) { 3331 /* discard the saved state */ 3332 pci_load_saved_state(pdev, NULL); 3333 3334 /* 3335 * Clearing npss forces a controller reset on resume. The 3336 * correct value will be rediscovered then. 3337 */ 3338 ret = nvme_disable_prepare_reset(ndev, true); 3339 ctrl->npss = 0; 3340 } 3341 unfreeze: 3342 nvme_unfreeze(ctrl); 3343 return ret; 3344 } 3345 3346 static int nvme_simple_suspend(struct device *dev) 3347 { 3348 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3349 3350 return nvme_disable_prepare_reset(ndev, true); 3351 } 3352 3353 static int nvme_simple_resume(struct device *dev) 3354 { 3355 struct pci_dev *pdev = to_pci_dev(dev); 3356 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3357 3358 return nvme_try_sched_reset(&ndev->ctrl); 3359 } 3360 3361 static const struct dev_pm_ops nvme_dev_pm_ops = { 3362 .suspend = nvme_suspend, 3363 .resume = nvme_resume, 3364 .freeze = nvme_simple_suspend, 3365 .thaw = nvme_simple_resume, 3366 .poweroff = nvme_simple_suspend, 3367 .restore = nvme_simple_resume, 3368 }; 3369 #endif /* CONFIG_PM_SLEEP */ 3370 3371 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3372 pci_channel_state_t state) 3373 { 3374 struct nvme_dev *dev = pci_get_drvdata(pdev); 3375 3376 /* 3377 * A frozen channel requires a reset. When detected, this method will 3378 * shutdown the controller to quiesce. The controller will be restarted 3379 * after the slot reset through driver's slot_reset callback. 3380 */ 3381 switch (state) { 3382 case pci_channel_io_normal: 3383 return PCI_ERS_RESULT_CAN_RECOVER; 3384 case pci_channel_io_frozen: 3385 dev_warn(dev->ctrl.device, 3386 "frozen state error detected, reset controller\n"); 3387 nvme_dev_disable(dev, false); 3388 return PCI_ERS_RESULT_NEED_RESET; 3389 case pci_channel_io_perm_failure: 3390 dev_warn(dev->ctrl.device, 3391 "failure state error detected, request disconnect\n"); 3392 return PCI_ERS_RESULT_DISCONNECT; 3393 } 3394 return PCI_ERS_RESULT_NEED_RESET; 3395 } 3396 3397 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3398 { 3399 struct nvme_dev *dev = pci_get_drvdata(pdev); 3400 3401 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3402 pci_restore_state(pdev); 3403 nvme_reset_ctrl(&dev->ctrl); 3404 return PCI_ERS_RESULT_RECOVERED; 3405 } 3406 3407 static void nvme_error_resume(struct pci_dev *pdev) 3408 { 3409 struct nvme_dev *dev = pci_get_drvdata(pdev); 3410 3411 flush_work(&dev->ctrl.reset_work); 3412 } 3413 3414 static const struct pci_error_handlers nvme_err_handler = { 3415 .error_detected = nvme_error_detected, 3416 .slot_reset = nvme_slot_reset, 3417 .resume = nvme_error_resume, 3418 .reset_prepare = nvme_reset_prepare, 3419 .reset_done = nvme_reset_done, 3420 }; 3421 3422 static const struct pci_device_id nvme_id_table[] = { 3423 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 3424 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3425 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3426 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 3427 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3428 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3429 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 3430 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3431 NVME_QUIRK_DEALLOCATE_ZEROES | 3432 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3433 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3434 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3435 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3436 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3437 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3438 NVME_QUIRK_MEDIUM_PRIO_SQ | 3439 NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3440 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3441 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3442 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3443 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3444 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3445 NVME_QUIRK_DISABLE_WRITE_ZEROES | 3446 NVME_QUIRK_BOGUS_NID, }, 3447 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 3448 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3449 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3450 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3451 NVME_QUIRK_BOGUS_NID, }, 3452 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3453 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3454 NVME_QUIRK_NO_NS_DESC_LIST, }, 3455 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3456 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3457 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3458 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3459 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3460 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3461 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3462 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3463 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3464 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3465 NVME_QUIRK_DISABLE_WRITE_ZEROES| 3466 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3467 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 3468 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3469 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3470 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3471 NVME_QUIRK_BOGUS_NID, }, 3472 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3473 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3474 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3475 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3476 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 3477 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3478 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3479 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3480 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3481 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3482 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3483 NVME_QUIRK_BOGUS_NID, }, 3484 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3485 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3486 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3487 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 3488 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 3489 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 3490 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3491 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3492 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3493 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 3494 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3495 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 3496 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3497 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 3498 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3499 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 3500 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3501 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 3502 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3503 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 3504 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3505 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3506 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3507 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3508 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3509 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3510 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3511 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3512 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3513 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3514 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3515 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3516 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3517 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3518 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3519 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 3520 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3521 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3522 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3523 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3524 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3525 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 3526 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3527 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3528 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3529 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3530 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3531 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 3532 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3533 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3534 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3535 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3536 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3537 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 3538 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3539 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 3540 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3541 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 3542 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3543 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 3544 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3545 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 3546 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3547 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 3548 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3549 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 3550 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3551 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 3552 .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3553 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3554 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3555 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3556 NVME_QUIRK_128_BYTES_SQES | 3557 NVME_QUIRK_SHARED_TAGS | 3558 NVME_QUIRK_SKIP_CID_GEN }, 3559 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3560 { 0, } 3561 }; 3562 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3563 3564 static struct pci_driver nvme_driver = { 3565 .name = "nvme", 3566 .id_table = nvme_id_table, 3567 .probe = nvme_probe, 3568 .remove = nvme_remove, 3569 .shutdown = nvme_shutdown, 3570 .driver = { 3571 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3572 #ifdef CONFIG_PM_SLEEP 3573 .pm = &nvme_dev_pm_ops, 3574 #endif 3575 }, 3576 .sriov_configure = pci_sriov_configure_simple, 3577 .err_handler = &nvme_err_handler, 3578 }; 3579 3580 static int __init nvme_init(void) 3581 { 3582 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3583 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3584 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3585 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3586 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) > 3587 S8_MAX); 3588 3589 return pci_register_driver(&nvme_driver); 3590 } 3591 3592 static void __exit nvme_exit(void) 3593 { 3594 pci_unregister_driver(&nvme_driver); 3595 flush_workqueue(nvme_wq); 3596 } 3597 3598 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3599 MODULE_LICENSE("GPL"); 3600 MODULE_VERSION("1.0"); 3601 module_init(nvme_init); 3602 module_exit(nvme_exit); 3603