1*13e920d9SHaijun Liu /* SPDX-License-Identifier: GPL-2.0-only 2*13e920d9SHaijun Liu * 3*13e920d9SHaijun Liu * Copyright (c) 2021, MediaTek Inc. 4*13e920d9SHaijun Liu * Copyright (c) 2021-2022, Intel Corporation. 5*13e920d9SHaijun Liu * 6*13e920d9SHaijun Liu * Authors: 7*13e920d9SHaijun Liu * Haijun Liu <haijun.liu@mediatek.com> 8*13e920d9SHaijun Liu * Sreehari Kancharla <sreehari.kancharla@intel.com> 9*13e920d9SHaijun Liu * 10*13e920d9SHaijun Liu * Contributors: 11*13e920d9SHaijun Liu * Moises Veleta <moises.veleta@intel.com> 12*13e920d9SHaijun Liu * Ricardo Martinez <ricardo.martinez@linux.intel.com> 13*13e920d9SHaijun Liu */ 14*13e920d9SHaijun Liu 15*13e920d9SHaijun Liu #ifndef __T7XX_PCIE_MAC_H__ 16*13e920d9SHaijun Liu #define __T7XX_PCIE_MAC_H__ 17*13e920d9SHaijun Liu 18*13e920d9SHaijun Liu #include "t7xx_pci.h" 19*13e920d9SHaijun Liu #include "t7xx_reg.h" 20*13e920d9SHaijun Liu 21*13e920d9SHaijun Liu #define IREG_BASE(t7xx_dev) ((t7xx_dev)->base_addr.pcie_mac_ireg_base) 22*13e920d9SHaijun Liu 23*13e920d9SHaijun Liu void t7xx_pcie_mac_interrupts_en(struct t7xx_pci_dev *t7xx_dev); 24*13e920d9SHaijun Liu void t7xx_pcie_mac_interrupts_dis(struct t7xx_pci_dev *t7xx_dev); 25*13e920d9SHaijun Liu void t7xx_pcie_mac_atr_init(struct t7xx_pci_dev *t7xx_dev); 26*13e920d9SHaijun Liu void t7xx_pcie_mac_clear_int(struct t7xx_pci_dev *t7xx_dev, enum t7xx_int int_type); 27*13e920d9SHaijun Liu void t7xx_pcie_mac_set_int(struct t7xx_pci_dev *t7xx_dev, enum t7xx_int int_type); 28*13e920d9SHaijun Liu void t7xx_pcie_mac_clear_int_status(struct t7xx_pci_dev *t7xx_dev, enum t7xx_int int_type); 29*13e920d9SHaijun Liu void t7xx_pcie_set_mac_msix_cfg(struct t7xx_pci_dev *t7xx_dev, unsigned int irq_count); 30*13e920d9SHaijun Liu 31*13e920d9SHaijun Liu #endif /* __T7XX_PCIE_MAC_H__ */ 32