130ebda7aSM Chetan Kumar /* SPDX-License-Identifier: GPL-2.0-only 230ebda7aSM Chetan Kumar * 330ebda7aSM Chetan Kumar * Copyright (C) 2020-21 Intel Corporation 430ebda7aSM Chetan Kumar */ 530ebda7aSM Chetan Kumar 630ebda7aSM Chetan Kumar #ifndef IOSM_IPC_CHNL_CFG_H 730ebda7aSM Chetan Kumar #define IOSM_IPC_CHNL_CFG_H 830ebda7aSM Chetan Kumar 930ebda7aSM Chetan Kumar #include "iosm_ipc_mux.h" 1030ebda7aSM Chetan Kumar 1130ebda7aSM Chetan Kumar /* Number of TDs on the trace channel */ 1230ebda7aSM Chetan Kumar #define IPC_MEM_TDS_TRC 32 1330ebda7aSM Chetan Kumar 1430ebda7aSM Chetan Kumar /* Trace channel TD buffer size. */ 1530ebda7aSM Chetan Kumar #define IPC_MEM_MAX_DL_TRC_BUF_SIZE 8192 1630ebda7aSM Chetan Kumar 1730ebda7aSM Chetan Kumar /* Channel ID */ 1830ebda7aSM Chetan Kumar enum ipc_channel_id { 1930ebda7aSM Chetan Kumar IPC_MEM_IP_CHL_ID_0 = 0, 2030ebda7aSM Chetan Kumar IPC_MEM_CTRL_CHL_ID_1, 2130ebda7aSM Chetan Kumar IPC_MEM_CTRL_CHL_ID_2, 2230ebda7aSM Chetan Kumar IPC_MEM_CTRL_CHL_ID_3, 2330ebda7aSM Chetan Kumar IPC_MEM_CTRL_CHL_ID_4, 2430ebda7aSM Chetan Kumar IPC_MEM_CTRL_CHL_ID_5, 2530ebda7aSM Chetan Kumar IPC_MEM_CTRL_CHL_ID_6, 26*8d9be063SM Chetan Kumar IPC_MEM_CTRL_CHL_ID_7, 2730ebda7aSM Chetan Kumar }; 2830ebda7aSM Chetan Kumar 2930ebda7aSM Chetan Kumar /** 3030ebda7aSM Chetan Kumar * struct ipc_chnl_cfg - IPC channel configuration structure 3130ebda7aSM Chetan Kumar * @id: Interface ID 3230ebda7aSM Chetan Kumar * @ul_pipe: Uplink datastream 3330ebda7aSM Chetan Kumar * @dl_pipe: Downlink datastream 3430ebda7aSM Chetan Kumar * @ul_nr_of_entries: Number of Transfer descriptor uplink pipe 3530ebda7aSM Chetan Kumar * @dl_nr_of_entries: Number of Transfer descriptor downlink pipe 3630ebda7aSM Chetan Kumar * @dl_buf_size: Downlink buffer size 3730ebda7aSM Chetan Kumar * @wwan_port_type: Wwan subsystem port type 3830ebda7aSM Chetan Kumar * @accumulation_backoff: Time in usec for data accumalation 3930ebda7aSM Chetan Kumar */ 4030ebda7aSM Chetan Kumar struct ipc_chnl_cfg { 4130ebda7aSM Chetan Kumar u32 id; 4230ebda7aSM Chetan Kumar u32 ul_pipe; 4330ebda7aSM Chetan Kumar u32 dl_pipe; 4430ebda7aSM Chetan Kumar u32 ul_nr_of_entries; 4530ebda7aSM Chetan Kumar u32 dl_nr_of_entries; 4630ebda7aSM Chetan Kumar u32 dl_buf_size; 4730ebda7aSM Chetan Kumar u32 wwan_port_type; 4830ebda7aSM Chetan Kumar u32 accumulation_backoff; 4930ebda7aSM Chetan Kumar }; 5030ebda7aSM Chetan Kumar 5130ebda7aSM Chetan Kumar /** 5230ebda7aSM Chetan Kumar * ipc_chnl_cfg_get - Get pipe configuration. 5330ebda7aSM Chetan Kumar * @chnl_cfg: Array of ipc_chnl_cfg struct 5430ebda7aSM Chetan Kumar * @index: Channel index (upto MAX_CHANNELS) 5530ebda7aSM Chetan Kumar * 5630ebda7aSM Chetan Kumar * Return: 0 on success and failure value on error 5730ebda7aSM Chetan Kumar */ 5830ebda7aSM Chetan Kumar int ipc_chnl_cfg_get(struct ipc_chnl_cfg *chnl_cfg, int index); 5930ebda7aSM Chetan Kumar 6030ebda7aSM Chetan Kumar #endif 61