146a1d512SLuciano Coelho /* 246a1d512SLuciano Coelho * This file is part of wl18xx 346a1d512SLuciano Coelho * 446a1d512SLuciano Coelho * Copyright (C) 2011 Texas Instruments Inc. 546a1d512SLuciano Coelho * 646a1d512SLuciano Coelho * This program is free software; you can redistribute it and/or 746a1d512SLuciano Coelho * modify it under the terms of the GNU General Public License 846a1d512SLuciano Coelho * version 2 as published by the Free Software Foundation. 946a1d512SLuciano Coelho * 1046a1d512SLuciano Coelho * This program is distributed in the hope that it will be useful, but 1146a1d512SLuciano Coelho * WITHOUT ANY WARRANTY; without even the implied warranty of 1246a1d512SLuciano Coelho * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1346a1d512SLuciano Coelho * General Public License for more details. 1446a1d512SLuciano Coelho * 1546a1d512SLuciano Coelho * You should have received a copy of the GNU General Public License 1646a1d512SLuciano Coelho * along with this program; if not, write to the Free Software 1746a1d512SLuciano Coelho * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 1846a1d512SLuciano Coelho * 02110-1301 USA 1946a1d512SLuciano Coelho * 2046a1d512SLuciano Coelho */ 2146a1d512SLuciano Coelho 2246a1d512SLuciano Coelho #ifndef __WL18XX_CONF_H__ 2346a1d512SLuciano Coelho #define __WL18XX_CONF_H__ 2446a1d512SLuciano Coelho 2518b70ac9SLuciano Coelho #define WL18XX_CONF_MAGIC 0x10e100ca 26*c68cc0f6SYair Shapira #define WL18XX_CONF_VERSION (WLCORE_CONF_VERSION | 0x0003) 2718b70ac9SLuciano Coelho #define WL18XX_CONF_MASK 0x0000ffff 2818b70ac9SLuciano Coelho #define WL18XX_CONF_SIZE (WLCORE_CONF_SIZE + \ 2918b70ac9SLuciano Coelho sizeof(struct wl18xx_priv_conf)) 3018b70ac9SLuciano Coelho 31d61c6b55SArik Nemtsov #define NUM_OF_CHANNELS_11_ABG 150 32d61c6b55SArik Nemtsov #define NUM_OF_CHANNELS_11_P 7 33d61c6b55SArik Nemtsov #define WL18XX_NUM_OF_SUB_BANDS 9 34d61c6b55SArik Nemtsov #define SRF_TABLE_LEN 16 35d61c6b55SArik Nemtsov #define PIN_MUXING_SIZE 2 36d61c6b55SArik Nemtsov 37d61c6b55SArik Nemtsov struct wl18xx_mac_and_phy_params { 3846a1d512SLuciano Coelho u8 phy_standalone; 3946a1d512SLuciano Coelho u8 rdl; 4046a1d512SLuciano Coelho u8 enable_clpc; 4146a1d512SLuciano Coelho u8 enable_tx_low_pwr_on_siso_rdl; 4246a1d512SLuciano Coelho u8 auto_detect; 4346a1d512SLuciano Coelho u8 dedicated_fem; 44d61c6b55SArik Nemtsov 4546a1d512SLuciano Coelho u8 low_band_component; 46d61c6b55SArik Nemtsov 47d61c6b55SArik Nemtsov /* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */ 4846a1d512SLuciano Coelho u8 low_band_component_type; 49d61c6b55SArik Nemtsov 5046a1d512SLuciano Coelho u8 high_band_component; 51d61c6b55SArik Nemtsov 52d61c6b55SArik Nemtsov /* Bit 0: One Hot, Bit 1: Control Enable, Bit 2: 1.8V, Bit 3: 3V */ 5346a1d512SLuciano Coelho u8 high_band_component_type; 54d61c6b55SArik Nemtsov u8 number_of_assembled_ant2_4; 55d61c6b55SArik Nemtsov u8 number_of_assembled_ant5; 56d61c6b55SArik Nemtsov u8 pin_muxing_platform_options[PIN_MUXING_SIZE]; 57d61c6b55SArik Nemtsov u8 external_pa_dc2dc; 5846a1d512SLuciano Coelho u8 tcxo_ldo_voltage; 5946a1d512SLuciano Coelho u8 xtal_itrim_val; 6046a1d512SLuciano Coelho u8 srf_state; 61d61c6b55SArik Nemtsov u8 srf1[SRF_TABLE_LEN]; 62d61c6b55SArik Nemtsov u8 srf2[SRF_TABLE_LEN]; 63d61c6b55SArik Nemtsov u8 srf3[SRF_TABLE_LEN]; 6446a1d512SLuciano Coelho u8 io_configuration; 6546a1d512SLuciano Coelho u8 sdio_configuration; 6646a1d512SLuciano Coelho u8 settings; 6746a1d512SLuciano Coelho u8 rx_profile; 68d61c6b55SArik Nemtsov u8 per_chan_pwr_limit_arr_11abg[NUM_OF_CHANNELS_11_ABG]; 69d61c6b55SArik Nemtsov u8 pwr_limit_reference_11_abg; 70d61c6b55SArik Nemtsov u8 per_chan_pwr_limit_arr_11p[NUM_OF_CHANNELS_11_P]; 71d61c6b55SArik Nemtsov u8 pwr_limit_reference_11p; 72d61c6b55SArik Nemtsov u8 per_sub_band_tx_trace_loss[WL18XX_NUM_OF_SUB_BANDS]; 73d61c6b55SArik Nemtsov u8 per_sub_band_rx_trace_loss[WL18XX_NUM_OF_SUB_BANDS]; 7446a1d512SLuciano Coelho u8 primary_clock_setting_time; 7546a1d512SLuciano Coelho u8 clock_valid_on_wake_up; 7646a1d512SLuciano Coelho u8 secondary_clock_setting_time; 77d61c6b55SArik Nemtsov u8 board_type; 78d61c6b55SArik Nemtsov /* enable point saturation */ 7916ea4733SIdo Reis u8 psat; 80d61c6b55SArik Nemtsov /* low/medium/high Tx power in dBm */ 8116ea4733SIdo Reis s8 low_power_val; 8216ea4733SIdo Reis s8 med_power_val; 8316ea4733SIdo Reis s8 high_power_val; 84d61c6b55SArik Nemtsov u8 padding[1]; 8534bacf73SLuciano Coelho } __packed; 8646a1d512SLuciano Coelho 87*c68cc0f6SYair Shapira enum wl18xx_ht_mode { 88*c68cc0f6SYair Shapira /* Default - use MIMO, fallback to SISO20 */ 89*c68cc0f6SYair Shapira HT_MODE_DEFAULT = 0, 90*c68cc0f6SYair Shapira 91*c68cc0f6SYair Shapira /* Wide - use SISO40 */ 92*c68cc0f6SYair Shapira HT_MODE_WIDE = 1, 93*c68cc0f6SYair Shapira 94*c68cc0f6SYair Shapira /* Use SISO20 */ 95*c68cc0f6SYair Shapira HT_MODE_SISO20 = 2, 96*c68cc0f6SYair Shapira }; 97*c68cc0f6SYair Shapira 98*c68cc0f6SYair Shapira struct wl18xx_ht_settings { 99*c68cc0f6SYair Shapira /* DEFAULT / WIDE / SISO20 */ 100*c68cc0f6SYair Shapira u8 mode; 101*c68cc0f6SYair Shapira } __packed; 102*c68cc0f6SYair Shapira 10323ee9bf8SLuciano Coelho struct wl18xx_priv_conf { 104*c68cc0f6SYair Shapira /* Module params structures */ 105*c68cc0f6SYair Shapira struct wl18xx_ht_settings ht; 106*c68cc0f6SYair Shapira 107d61c6b55SArik Nemtsov /* this structure is copied wholesale to FW */ 108d61c6b55SArik Nemtsov struct wl18xx_mac_and_phy_params phy; 10934bacf73SLuciano Coelho } __packed; 11046a1d512SLuciano Coelho 11146a1d512SLuciano Coelho #endif /* __WL18XX_CONF_H__ */ 112