1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "ps.h" 11 #include "reg.h" 12 #include "sar.h" 13 #include "txrx.h" 14 #include "util.h" 15 16 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 17 const struct rtw89_ra_report *report) 18 { 19 u32 bit_rate = report->bit_rate; 20 21 /* lower than ofdm, do not aggregate */ 22 if (bit_rate < 550) 23 return 1; 24 25 /* avoid AMSDU for legacy rate */ 26 if (report->might_fallback_legacy) 27 return 1; 28 29 /* lower than 20M vht 2ss mcs8, make it small */ 30 if (bit_rate < 1800) 31 return 1200; 32 33 /* lower than 40M vht 2ss mcs9, make it medium */ 34 if (bit_rate < 4000) 35 return 2600; 36 37 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 38 if (bit_rate < 7000) 39 return 3500; 40 41 return rtwdev->chip->max_amsdu_limit; 42 } 43 44 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 45 { 46 u64 ra_mask = 0; 47 u8 mcs_cap; 48 int i, nss; 49 50 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 51 mcs_cap = mcs_map & 0x3; 52 switch (mcs_cap) { 53 case 2: 54 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 55 break; 56 case 1: 57 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 58 break; 59 case 0: 60 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 61 break; 62 default: 63 break; 64 } 65 } 66 67 return ra_mask; 68 } 69 70 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 71 { 72 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 73 u16 mcs_map; 74 75 switch (sta->deflink.bandwidth) { 76 case IEEE80211_STA_RX_BW_160: 77 if (cap.he_cap_elem.phy_cap_info[0] & 78 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 79 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 80 else 81 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 82 break; 83 default: 84 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 85 } 86 87 /* MCS11, MCS9, MCS7 */ 88 return get_mcs_ra_mask(mcs_map, 11, 2); 89 } 90 91 #define RA_FLOOR_TABLE_SIZE 7 92 #define RA_FLOOR_UP_GAP 3 93 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 94 u8 ratr_state) 95 { 96 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 97 u8 rssi_lv = 0; 98 u8 i; 99 100 rssi >>= 1; 101 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 102 if (i >= ratr_state) 103 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 104 if (rssi < rssi_lv_t[i]) { 105 rssi_lv = i; 106 break; 107 } 108 } 109 if (rssi_lv == 0) 110 return 0xffffffffffffffffULL; 111 else if (rssi_lv == 1) 112 return 0xfffffffffffffff0ULL; 113 else if (rssi_lv == 2) 114 return 0xffffffffffffefe0ULL; 115 else if (rssi_lv == 3) 116 return 0xffffffffffffcfc0ULL; 117 else if (rssi_lv == 4) 118 return 0xffffffffffff8f80ULL; 119 else if (rssi_lv >= 5) 120 return 0xffffffffffff0f00ULL; 121 122 return 0xffffffffffffffffULL; 123 } 124 125 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 126 { 127 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 128 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 129 130 if (ra_mask == 0) 131 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 132 133 return ra_mask; 134 } 135 136 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 137 { 138 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 139 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 140 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 141 enum nl80211_band band; 142 u64 cfg_mask; 143 144 if (!rtwsta->use_cfg_mask) 145 return -1; 146 147 switch (chan->band_type) { 148 case RTW89_BAND_2G: 149 band = NL80211_BAND_2GHZ; 150 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 151 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 152 break; 153 case RTW89_BAND_5G: 154 band = NL80211_BAND_5GHZ; 155 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 156 RA_MASK_OFDM_RATES); 157 break; 158 case RTW89_BAND_6G: 159 band = NL80211_BAND_6GHZ; 160 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 161 RA_MASK_OFDM_RATES); 162 break; 163 default: 164 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 165 return -1; 166 } 167 168 if (sta->deflink.he_cap.has_he) { 169 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 170 RA_MASK_HE_1SS_RATES); 171 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 172 RA_MASK_HE_2SS_RATES); 173 } else if (sta->deflink.vht_cap.vht_supported) { 174 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 175 RA_MASK_VHT_1SS_RATES); 176 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 177 RA_MASK_VHT_2SS_RATES); 178 } else if (sta->deflink.ht_cap.ht_supported) { 179 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 180 RA_MASK_HT_1SS_RATES); 181 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 182 RA_MASK_HT_2SS_RATES); 183 } 184 185 return cfg_mask; 186 } 187 188 static const u64 189 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 190 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 191 static const u64 192 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 193 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 194 static const u64 195 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 196 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 197 198 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 199 struct rtw89_sta *rtwsta, 200 bool *fix_giltf_en, u8 *fix_giltf) 201 { 202 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 203 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 204 u8 band = chan->band_type; 205 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 206 u8 he_gi = mask->control[nl_band].he_gi; 207 u8 he_ltf = mask->control[nl_band].he_ltf; 208 209 if (!rtwsta->use_cfg_mask) 210 return; 211 212 if (he_ltf == 2 && he_gi == 2) { 213 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 214 } else if (he_ltf == 2 && he_gi == 0) { 215 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 216 } else if (he_ltf == 1 && he_gi == 1) { 217 *fix_giltf = RTW89_GILTF_2XHE16; 218 } else if (he_ltf == 1 && he_gi == 0) { 219 *fix_giltf = RTW89_GILTF_2XHE08; 220 } else if (he_ltf == 0 && he_gi == 1) { 221 *fix_giltf = RTW89_GILTF_1XHE16; 222 } else if (he_ltf == 0 && he_gi == 0) { 223 *fix_giltf = RTW89_GILTF_1XHE08; 224 } else { 225 *fix_giltf_en = false; 226 return; 227 } 228 229 *fix_giltf_en = true; 230 } 231 232 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 233 struct ieee80211_sta *sta, bool csi) 234 { 235 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 236 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 237 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 238 struct rtw89_ra_info *ra = &rtwsta->ra; 239 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 240 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 241 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 242 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 243 u64 ra_mask = 0; 244 u64 ra_mask_bak; 245 u8 mode = 0; 246 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 247 u8 bw_mode = 0; 248 u8 stbc_en = 0; 249 u8 ldpc_en = 0; 250 u8 fix_giltf = 0; 251 u8 i; 252 bool sgi = false; 253 bool fix_giltf_en = false; 254 255 memset(ra, 0, sizeof(*ra)); 256 /* Set the ra mask from sta's capability */ 257 if (sta->deflink.he_cap.has_he) { 258 mode |= RTW89_RA_MODE_HE; 259 csi_mode = RTW89_RA_RPT_MODE_HE; 260 ra_mask |= get_he_ra_mask(sta); 261 high_rate_masks = rtw89_ra_mask_he_rates; 262 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 263 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 264 stbc_en = 1; 265 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 266 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 267 ldpc_en = 1; 268 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, &fix_giltf_en, &fix_giltf); 269 } else if (sta->deflink.vht_cap.vht_supported) { 270 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 271 272 mode |= RTW89_RA_MODE_VHT; 273 csi_mode = RTW89_RA_RPT_MODE_VHT; 274 /* MCS9, MCS8, MCS7 */ 275 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 276 high_rate_masks = rtw89_ra_mask_vht_rates; 277 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 278 stbc_en = 1; 279 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 280 ldpc_en = 1; 281 } else if (sta->deflink.ht_cap.ht_supported) { 282 mode |= RTW89_RA_MODE_HT; 283 csi_mode = RTW89_RA_RPT_MODE_HT; 284 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 285 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 286 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 287 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 288 high_rate_masks = rtw89_ra_mask_ht_rates; 289 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 290 stbc_en = 1; 291 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 292 ldpc_en = 1; 293 } 294 295 switch (chan->band_type) { 296 case RTW89_BAND_2G: 297 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 298 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 299 mode |= RTW89_RA_MODE_CCK; 300 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 301 mode |= RTW89_RA_MODE_OFDM; 302 break; 303 case RTW89_BAND_5G: 304 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 305 mode |= RTW89_RA_MODE_OFDM; 306 break; 307 case RTW89_BAND_6G: 308 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 309 mode |= RTW89_RA_MODE_OFDM; 310 break; 311 default: 312 rtw89_err(rtwdev, "Unknown band type\n"); 313 break; 314 } 315 316 ra_mask_bak = ra_mask; 317 318 if (mode >= RTW89_RA_MODE_HT) { 319 u64 mask = 0; 320 for (i = 0; i < rtwdev->hal.tx_nss; i++) 321 mask |= high_rate_masks[i]; 322 if (mode & RTW89_RA_MODE_OFDM) 323 mask |= RA_MASK_SUBOFDM_RATES; 324 if (mode & RTW89_RA_MODE_CCK) 325 mask |= RA_MASK_SUBCCK_RATES; 326 ra_mask &= mask; 327 } else if (mode & RTW89_RA_MODE_OFDM) { 328 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 329 } 330 331 if (mode != RTW89_RA_MODE_CCK) 332 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 333 334 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 335 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 336 337 switch (sta->deflink.bandwidth) { 338 case IEEE80211_STA_RX_BW_160: 339 bw_mode = RTW89_CHANNEL_WIDTH_160; 340 sgi = sta->deflink.vht_cap.vht_supported && 341 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 342 break; 343 case IEEE80211_STA_RX_BW_80: 344 bw_mode = RTW89_CHANNEL_WIDTH_80; 345 sgi = sta->deflink.vht_cap.vht_supported && 346 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 347 break; 348 case IEEE80211_STA_RX_BW_40: 349 bw_mode = RTW89_CHANNEL_WIDTH_40; 350 sgi = sta->deflink.ht_cap.ht_supported && 351 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 352 break; 353 default: 354 bw_mode = RTW89_CHANNEL_WIDTH_20; 355 sgi = sta->deflink.ht_cap.ht_supported && 356 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 357 break; 358 } 359 360 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 361 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 362 ra->dcm_cap = 1; 363 364 if (rate_pattern->enable && !vif->p2p) { 365 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 366 ra_mask &= rate_pattern->ra_mask; 367 mode = rate_pattern->ra_mode; 368 } 369 370 ra->bw_cap = bw_mode; 371 ra->er_cap = rtwsta->er_cap; 372 ra->mode_ctrl = mode; 373 ra->macid = rtwsta->mac_id; 374 ra->stbc_cap = stbc_en; 375 ra->ldpc_cap = ldpc_en; 376 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 377 ra->en_sgi = sgi; 378 ra->ra_mask = ra_mask; 379 ra->fix_giltf_en = fix_giltf_en; 380 ra->fix_giltf = fix_giltf; 381 382 if (!csi) 383 return; 384 385 ra->fixed_csi_rate_en = false; 386 ra->ra_csi_rate_en = true; 387 ra->cr_tbl_sel = false; 388 ra->band_num = rtwvif->phy_idx; 389 ra->csi_bw = bw_mode; 390 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 391 ra->csi_mcs_ss_idx = 5; 392 ra->csi_mode = csi_mode; 393 } 394 395 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 396 u32 changed) 397 { 398 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 399 struct rtw89_ra_info *ra = &rtwsta->ra; 400 401 rtw89_phy_ra_sta_update(rtwdev, sta, false); 402 403 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 404 ra->upd_mask = 1; 405 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 406 ra->upd_bw_nss_mask = 1; 407 408 rtw89_debug(rtwdev, RTW89_DBG_RA, 409 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 410 ra->macid, 411 ra->bw_cap, 412 ra->ss_num, 413 ra->en_sgi, 414 ra->giltf); 415 416 rtw89_fw_h2c_ra(rtwdev, ra, false); 417 } 418 419 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 420 u16 rate_base, u64 ra_mask, u8 ra_mode, 421 u32 rate_ctrl, u32 ctrl_skip, bool force) 422 { 423 u8 n, c; 424 425 if (rate_ctrl == ctrl_skip) 426 return true; 427 428 n = hweight32(rate_ctrl); 429 if (n == 0) 430 return true; 431 432 if (force && n != 1) 433 return false; 434 435 if (next->enable) 436 return false; 437 438 c = __fls(rate_ctrl); 439 next->rate = rate_base + c; 440 next->ra_mode = ra_mode; 441 next->ra_mask = ra_mask; 442 next->enable = true; 443 444 return true; 445 } 446 447 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \ 448 { \ 449 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \ 450 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \ 451 } 452 453 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 454 struct ieee80211_vif *vif, 455 const struct cfg80211_bitrate_mask *mask) 456 { 457 struct ieee80211_supported_band *sband; 458 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 459 struct rtw89_phy_rate_pattern next_pattern = {0}; 460 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 461 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = { 462 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0), 463 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0), 464 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0), 465 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0), 466 }; 467 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = { 468 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0), 469 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0), 470 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0), 471 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0), 472 }; 473 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = { 474 RTW89_HW_RATE_BY_CHIP_GEN(MCS0), 475 RTW89_HW_RATE_BY_CHIP_GEN(MCS8), 476 RTW89_HW_RATE_BY_CHIP_GEN(MCS16), 477 RTW89_HW_RATE_BY_CHIP_GEN(MCS24), 478 }; 479 u8 band = chan->band_type; 480 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 481 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 482 u8 tx_nss = rtwdev->hal.tx_nss; 483 u8 i; 484 485 for (i = 0; i < tx_nss; i++) 486 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen], 487 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 488 mask->control[nl_band].he_mcs[i], 489 0, true)) 490 goto out; 491 492 for (i = 0; i < tx_nss; i++) 493 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen], 494 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 495 mask->control[nl_band].vht_mcs[i], 496 0, true)) 497 goto out; 498 499 for (i = 0; i < tx_nss; i++) 500 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen], 501 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 502 mask->control[nl_band].ht_mcs[i], 503 0, true)) 504 goto out; 505 506 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 507 * require at least one basic rate for ieee80211_set_bitrate_mask, 508 * so the decision just depends on if all bitrates are set or not. 509 */ 510 sband = rtwdev->hw->wiphy->bands[nl_band]; 511 if (band == RTW89_BAND_2G) { 512 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 513 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 514 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 515 mask->control[nl_band].legacy, 516 BIT(sband->n_bitrates) - 1, false)) 517 goto out; 518 } else { 519 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 520 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 521 mask->control[nl_band].legacy, 522 BIT(sband->n_bitrates) - 1, false)) 523 goto out; 524 } 525 526 if (!next_pattern.enable) 527 goto out; 528 529 rtwvif->rate_pattern = next_pattern; 530 rtw89_debug(rtwdev, RTW89_DBG_RA, 531 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 532 next_pattern.rate, 533 next_pattern.ra_mask, 534 next_pattern.ra_mode); 535 return; 536 537 out: 538 rtwvif->rate_pattern.enable = false; 539 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 540 } 541 542 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 543 { 544 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 545 546 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 547 } 548 549 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 550 { 551 ieee80211_iterate_stations_atomic(rtwdev->hw, 552 rtw89_phy_ra_updata_sta_iter, 553 rtwdev); 554 } 555 556 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 557 { 558 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 559 struct rtw89_ra_info *ra = &rtwsta->ra; 560 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 561 bool csi = rtw89_sta_has_beamformer_cap(sta); 562 563 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 564 565 if (rssi > 40) 566 ra->init_rate_lv = 1; 567 else if (rssi > 20) 568 ra->init_rate_lv = 2; 569 else if (rssi > 1) 570 ra->init_rate_lv = 3; 571 else 572 ra->init_rate_lv = 0; 573 ra->upd_all = 1; 574 rtw89_debug(rtwdev, RTW89_DBG_RA, 575 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 576 ra->macid, 577 ra->mode_ctrl, 578 ra->bw_cap, 579 ra->ss_num, 580 ra->init_rate_lv); 581 rtw89_debug(rtwdev, RTW89_DBG_RA, 582 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 583 ra->dcm_cap, 584 ra->er_cap, 585 ra->ldpc_cap, 586 ra->stbc_cap, 587 ra->en_sgi, 588 ra->giltf); 589 590 rtw89_fw_h2c_ra(rtwdev, ra, csi); 591 } 592 593 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 594 const struct rtw89_chan *chan, 595 enum rtw89_bandwidth dbw) 596 { 597 enum rtw89_bandwidth cbw = chan->band_width; 598 u8 pri_ch = chan->primary_channel; 599 u8 central_ch = chan->channel; 600 u8 txsc_idx = 0; 601 u8 tmp = 0; 602 603 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 604 return txsc_idx; 605 606 switch (cbw) { 607 case RTW89_CHANNEL_WIDTH_40: 608 txsc_idx = pri_ch > central_ch ? 1 : 2; 609 break; 610 case RTW89_CHANNEL_WIDTH_80: 611 if (dbw == RTW89_CHANNEL_WIDTH_20) { 612 if (pri_ch > central_ch) 613 txsc_idx = (pri_ch - central_ch) >> 1; 614 else 615 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 616 } else { 617 txsc_idx = pri_ch > central_ch ? 9 : 10; 618 } 619 break; 620 case RTW89_CHANNEL_WIDTH_160: 621 if (pri_ch > central_ch) 622 tmp = (pri_ch - central_ch) >> 1; 623 else 624 tmp = ((central_ch - pri_ch) >> 1) + 1; 625 626 if (dbw == RTW89_CHANNEL_WIDTH_20) { 627 txsc_idx = tmp; 628 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 629 if (tmp == 1 || tmp == 3) 630 txsc_idx = 9; 631 else if (tmp == 5 || tmp == 7) 632 txsc_idx = 11; 633 else if (tmp == 2 || tmp == 4) 634 txsc_idx = 10; 635 else if (tmp == 6 || tmp == 8) 636 txsc_idx = 12; 637 else 638 return 0xff; 639 } else { 640 txsc_idx = pri_ch > central_ch ? 13 : 14; 641 } 642 break; 643 case RTW89_CHANNEL_WIDTH_80_80: 644 if (dbw == RTW89_CHANNEL_WIDTH_20) { 645 if (pri_ch > central_ch) 646 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 647 else 648 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 649 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 650 txsc_idx = pri_ch > central_ch ? 10 : 12; 651 } else { 652 txsc_idx = 14; 653 } 654 break; 655 default: 656 break; 657 } 658 659 return txsc_idx; 660 } 661 EXPORT_SYMBOL(rtw89_phy_get_txsc); 662 663 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 664 { 665 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 666 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 667 } 668 669 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 670 u32 addr, u32 mask) 671 { 672 const struct rtw89_chip_info *chip = rtwdev->chip; 673 const u32 *base_addr = chip->rf_base_addr; 674 u32 val, direct_addr; 675 676 if (rf_path >= rtwdev->chip->rf_path_num) { 677 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 678 return INV_RF_DATA; 679 } 680 681 addr &= 0xff; 682 direct_addr = base_addr[rf_path] + (addr << 2); 683 mask &= RFREG_MASK; 684 685 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 686 687 return val; 688 } 689 EXPORT_SYMBOL(rtw89_phy_read_rf); 690 691 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 692 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 693 { 694 bool busy; 695 bool done; 696 u32 val; 697 int ret; 698 699 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 700 1, 30, false, rtwdev); 701 if (ret) { 702 rtw89_err(rtwdev, "read rf busy swsi\n"); 703 return INV_RF_DATA; 704 } 705 706 mask &= RFREG_MASK; 707 708 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 709 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 710 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 711 udelay(2); 712 713 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 714 30, false, rtwdev, R_SWSI_V1, 715 B_SWSI_R_DATA_DONE_V1); 716 if (ret) { 717 rtw89_err(rtwdev, "read swsi busy\n"); 718 return INV_RF_DATA; 719 } 720 721 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 722 } 723 724 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 725 u32 addr, u32 mask) 726 { 727 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 728 729 if (rf_path >= rtwdev->chip->rf_path_num) { 730 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 731 return INV_RF_DATA; 732 } 733 734 if (ad_sel) 735 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 736 else 737 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 738 } 739 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 740 741 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 742 u32 addr, u32 mask, u32 data) 743 { 744 const struct rtw89_chip_info *chip = rtwdev->chip; 745 const u32 *base_addr = chip->rf_base_addr; 746 u32 direct_addr; 747 748 if (rf_path >= rtwdev->chip->rf_path_num) { 749 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 750 return false; 751 } 752 753 addr &= 0xff; 754 direct_addr = base_addr[rf_path] + (addr << 2); 755 mask &= RFREG_MASK; 756 757 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 758 759 /* delay to ensure writing properly */ 760 udelay(1); 761 762 return true; 763 } 764 EXPORT_SYMBOL(rtw89_phy_write_rf); 765 766 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 767 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 768 u32 data) 769 { 770 u8 bit_shift; 771 u32 val; 772 bool busy, b_msk_en = false; 773 int ret; 774 775 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 776 1, 30, false, rtwdev); 777 if (ret) { 778 rtw89_err(rtwdev, "write rf busy swsi\n"); 779 return false; 780 } 781 782 data &= RFREG_MASK; 783 mask &= RFREG_MASK; 784 785 if (mask != RFREG_MASK) { 786 b_msk_en = true; 787 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 788 mask); 789 bit_shift = __ffs(mask); 790 data = (data << bit_shift) & RFREG_MASK; 791 } 792 793 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 794 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 795 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 796 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 797 798 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 799 800 return true; 801 } 802 803 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 804 u32 addr, u32 mask, u32 data) 805 { 806 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 807 808 if (rf_path >= rtwdev->chip->rf_path_num) { 809 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 810 return false; 811 } 812 813 if (ad_sel) 814 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 815 else 816 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 817 } 818 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 819 820 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 821 { 822 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 823 } 824 825 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 826 enum rtw89_phy_idx phy_idx) 827 { 828 const struct rtw89_chip_info *chip = rtwdev->chip; 829 830 chip->ops->bb_reset(rtwdev, phy_idx); 831 } 832 833 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 834 const struct rtw89_reg2_def *reg, 835 enum rtw89_rf_path rf_path, 836 void *extra_data) 837 { 838 if (reg->addr == 0xfe) 839 mdelay(50); 840 else if (reg->addr == 0xfd) 841 mdelay(5); 842 else if (reg->addr == 0xfc) 843 mdelay(1); 844 else if (reg->addr == 0xfb) 845 udelay(50); 846 else if (reg->addr == 0xfa) 847 udelay(5); 848 else if (reg->addr == 0xf9) 849 udelay(1); 850 else 851 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 852 } 853 854 union rtw89_phy_bb_gain_arg { 855 u32 addr; 856 struct { 857 union { 858 u8 type; 859 struct { 860 u8 rxsc_start:4; 861 u8 bw:4; 862 }; 863 }; 864 u8 path; 865 u8 gain_band; 866 u8 cfg_type; 867 }; 868 } __packed; 869 870 static void 871 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 872 union rtw89_phy_bb_gain_arg arg, u32 data) 873 { 874 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 875 u8 type = arg.type; 876 u8 path = arg.path; 877 u8 gband = arg.gain_band; 878 int i; 879 880 switch (type) { 881 case 0: 882 for (i = 0; i < 4; i++, data >>= 8) 883 gain->lna_gain[gband][path][i] = data & 0xff; 884 break; 885 case 1: 886 for (i = 4; i < 7; i++, data >>= 8) 887 gain->lna_gain[gband][path][i] = data & 0xff; 888 break; 889 case 2: 890 for (i = 0; i < 2; i++, data >>= 8) 891 gain->tia_gain[gband][path][i] = data & 0xff; 892 break; 893 default: 894 rtw89_warn(rtwdev, 895 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 896 arg.addr, data, type); 897 break; 898 } 899 } 900 901 enum rtw89_phy_bb_rxsc_start_idx { 902 RTW89_BB_RXSC_START_IDX_FULL = 0, 903 RTW89_BB_RXSC_START_IDX_20 = 1, 904 RTW89_BB_RXSC_START_IDX_20_1 = 5, 905 RTW89_BB_RXSC_START_IDX_40 = 9, 906 RTW89_BB_RXSC_START_IDX_80 = 13, 907 }; 908 909 static void 910 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 911 union rtw89_phy_bb_gain_arg arg, u32 data) 912 { 913 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 914 u8 rxsc_start = arg.rxsc_start; 915 u8 bw = arg.bw; 916 u8 path = arg.path; 917 u8 gband = arg.gain_band; 918 u8 rxsc; 919 s8 ofst; 920 int i; 921 922 switch (bw) { 923 case RTW89_CHANNEL_WIDTH_20: 924 gain->rpl_ofst_20[gband][path] = (s8)data; 925 break; 926 case RTW89_CHANNEL_WIDTH_40: 927 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 928 gain->rpl_ofst_40[gband][path][0] = (s8)data; 929 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 930 for (i = 0; i < 2; i++, data >>= 8) { 931 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 932 ofst = (s8)(data & 0xff); 933 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 934 } 935 } 936 break; 937 case RTW89_CHANNEL_WIDTH_80: 938 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 939 gain->rpl_ofst_80[gband][path][0] = (s8)data; 940 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 941 for (i = 0; i < 4; i++, data >>= 8) { 942 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 943 ofst = (s8)(data & 0xff); 944 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 945 } 946 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 947 for (i = 0; i < 2; i++, data >>= 8) { 948 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 949 ofst = (s8)(data & 0xff); 950 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 951 } 952 } 953 break; 954 case RTW89_CHANNEL_WIDTH_160: 955 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 956 gain->rpl_ofst_160[gband][path][0] = (s8)data; 957 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 958 for (i = 0; i < 4; i++, data >>= 8) { 959 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 960 ofst = (s8)(data & 0xff); 961 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 962 } 963 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 964 for (i = 0; i < 4; i++, data >>= 8) { 965 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 966 ofst = (s8)(data & 0xff); 967 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 968 } 969 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 970 for (i = 0; i < 4; i++, data >>= 8) { 971 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 972 ofst = (s8)(data & 0xff); 973 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 974 } 975 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 976 for (i = 0; i < 2; i++, data >>= 8) { 977 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 978 ofst = (s8)(data & 0xff); 979 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 980 } 981 } 982 break; 983 default: 984 rtw89_warn(rtwdev, 985 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 986 arg.addr, data, bw); 987 break; 988 } 989 } 990 991 static void 992 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 993 union rtw89_phy_bb_gain_arg arg, u32 data) 994 { 995 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 996 u8 type = arg.type; 997 u8 path = arg.path; 998 u8 gband = arg.gain_band; 999 int i; 1000 1001 switch (type) { 1002 case 0: 1003 for (i = 0; i < 4; i++, data >>= 8) 1004 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1005 break; 1006 case 1: 1007 for (i = 4; i < 7; i++, data >>= 8) 1008 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1009 break; 1010 default: 1011 rtw89_warn(rtwdev, 1012 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 1013 arg.addr, data, type); 1014 break; 1015 } 1016 } 1017 1018 static void 1019 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1020 union rtw89_phy_bb_gain_arg arg, u32 data) 1021 { 1022 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 1023 u8 type = arg.type; 1024 u8 path = arg.path; 1025 u8 gband = arg.gain_band; 1026 int i; 1027 1028 switch (type) { 1029 case 0: 1030 for (i = 0; i < 4; i++, data >>= 8) 1031 gain->lna_op1db[gband][path][i] = data & 0xff; 1032 break; 1033 case 1: 1034 for (i = 4; i < 7; i++, data >>= 8) 1035 gain->lna_op1db[gband][path][i] = data & 0xff; 1036 break; 1037 case 2: 1038 for (i = 0; i < 4; i++, data >>= 8) 1039 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1040 break; 1041 case 3: 1042 for (i = 4; i < 8; i++, data >>= 8) 1043 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1044 break; 1045 default: 1046 rtw89_warn(rtwdev, 1047 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1048 arg.addr, data, type); 1049 break; 1050 } 1051 } 1052 1053 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 1054 const struct rtw89_reg2_def *reg, 1055 enum rtw89_rf_path rf_path, 1056 void *extra_data) 1057 { 1058 const struct rtw89_chip_info *chip = rtwdev->chip; 1059 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1060 struct rtw89_efuse *efuse = &rtwdev->efuse; 1061 1062 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1063 return; 1064 1065 if (arg.path >= chip->rf_path_num) 1066 return; 1067 1068 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1069 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1070 return; 1071 } 1072 1073 switch (arg.cfg_type) { 1074 case 0: 1075 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1076 break; 1077 case 1: 1078 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1079 break; 1080 case 2: 1081 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1082 break; 1083 case 3: 1084 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1085 break; 1086 case 4: 1087 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1088 if (efuse->rfe_type < 50) 1089 break; 1090 fallthrough; 1091 default: 1092 rtw89_warn(rtwdev, 1093 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1094 arg.addr, reg->data, arg.cfg_type); 1095 break; 1096 } 1097 } 1098 1099 static void 1100 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1101 const struct rtw89_reg2_def *reg, 1102 enum rtw89_rf_path rf_path, 1103 struct rtw89_fw_h2c_rf_reg_info *info) 1104 { 1105 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1106 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1107 1108 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1109 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1110 rf_path, info->curr_idx); 1111 return; 1112 } 1113 1114 info->rtw89_phy_config_rf_h2c[page][idx] = 1115 cpu_to_le32((reg->addr << 20) | reg->data); 1116 info->curr_idx++; 1117 } 1118 1119 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1120 struct rtw89_fw_h2c_rf_reg_info *info) 1121 { 1122 u16 remain = info->curr_idx; 1123 u16 len = 0; 1124 u8 i; 1125 int ret = 0; 1126 1127 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1128 rtw89_warn(rtwdev, 1129 "rf reg h2c total len %d larger than %d\n", 1130 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1131 ret = -EINVAL; 1132 goto out; 1133 } 1134 1135 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1136 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1137 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1138 if (ret) 1139 goto out; 1140 } 1141 out: 1142 info->curr_idx = 0; 1143 1144 return ret; 1145 } 1146 1147 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1148 const struct rtw89_reg2_def *reg, 1149 enum rtw89_rf_path rf_path, 1150 void *extra_data) 1151 { 1152 u32 addr = reg->addr; 1153 1154 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1155 addr == 0xfa || addr == 0xf9) 1156 return; 1157 1158 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1159 return; 1160 1161 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1162 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1163 } 1164 1165 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1166 const struct rtw89_reg2_def *reg, 1167 enum rtw89_rf_path rf_path, 1168 void *extra_data) 1169 { 1170 if (reg->addr == 0xfe) { 1171 mdelay(50); 1172 } else if (reg->addr == 0xfd) { 1173 mdelay(5); 1174 } else if (reg->addr == 0xfc) { 1175 mdelay(1); 1176 } else if (reg->addr == 0xfb) { 1177 udelay(50); 1178 } else if (reg->addr == 0xfa) { 1179 udelay(5); 1180 } else if (reg->addr == 0xf9) { 1181 udelay(1); 1182 } else { 1183 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1184 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1185 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1186 } 1187 } 1188 1189 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1190 const struct rtw89_reg2_def *reg, 1191 enum rtw89_rf_path rf_path, 1192 void *extra_data) 1193 { 1194 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1195 1196 if (reg->addr < 0x100) 1197 return; 1198 1199 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1200 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1201 } 1202 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1203 1204 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1205 const struct rtw89_phy_table *table, 1206 u32 *headline_size, u32 *headline_idx, 1207 u8 rfe, u8 cv) 1208 { 1209 const struct rtw89_reg2_def *reg; 1210 u32 headline; 1211 u32 compare, target; 1212 u8 rfe_para, cv_para; 1213 u8 cv_max = 0; 1214 bool case_matched = false; 1215 u32 i; 1216 1217 for (i = 0; i < table->n_regs; i++) { 1218 reg = &table->regs[i]; 1219 headline = get_phy_headline(reg->addr); 1220 if (headline != PHY_HEADLINE_VALID) 1221 break; 1222 } 1223 *headline_size = i; 1224 if (*headline_size == 0) 1225 return 0; 1226 1227 /* case 1: RFE match, CV match */ 1228 compare = get_phy_compare(rfe, cv); 1229 for (i = 0; i < *headline_size; i++) { 1230 reg = &table->regs[i]; 1231 target = get_phy_target(reg->addr); 1232 if (target == compare) { 1233 *headline_idx = i; 1234 return 0; 1235 } 1236 } 1237 1238 /* case 2: RFE match, CV don't care */ 1239 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1240 for (i = 0; i < *headline_size; i++) { 1241 reg = &table->regs[i]; 1242 target = get_phy_target(reg->addr); 1243 if (target == compare) { 1244 *headline_idx = i; 1245 return 0; 1246 } 1247 } 1248 1249 /* case 3: RFE match, CV max in table */ 1250 for (i = 0; i < *headline_size; i++) { 1251 reg = &table->regs[i]; 1252 rfe_para = get_phy_cond_rfe(reg->addr); 1253 cv_para = get_phy_cond_cv(reg->addr); 1254 if (rfe_para == rfe) { 1255 if (cv_para >= cv_max) { 1256 cv_max = cv_para; 1257 *headline_idx = i; 1258 case_matched = true; 1259 } 1260 } 1261 } 1262 1263 if (case_matched) 1264 return 0; 1265 1266 /* case 4: RFE don't care, CV max in table */ 1267 for (i = 0; i < *headline_size; i++) { 1268 reg = &table->regs[i]; 1269 rfe_para = get_phy_cond_rfe(reg->addr); 1270 cv_para = get_phy_cond_cv(reg->addr); 1271 if (rfe_para == PHY_COND_DONT_CARE) { 1272 if (cv_para >= cv_max) { 1273 cv_max = cv_para; 1274 *headline_idx = i; 1275 case_matched = true; 1276 } 1277 } 1278 } 1279 1280 if (case_matched) 1281 return 0; 1282 1283 return -EINVAL; 1284 } 1285 1286 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1287 const struct rtw89_phy_table *table, 1288 void (*config)(struct rtw89_dev *rtwdev, 1289 const struct rtw89_reg2_def *reg, 1290 enum rtw89_rf_path rf_path, 1291 void *data), 1292 void *extra_data) 1293 { 1294 const struct rtw89_reg2_def *reg; 1295 enum rtw89_rf_path rf_path = table->rf_path; 1296 u8 rfe = rtwdev->efuse.rfe_type; 1297 u8 cv = rtwdev->hal.cv; 1298 u32 i; 1299 u32 headline_size = 0, headline_idx = 0; 1300 u32 target = 0, cfg_target; 1301 u8 cond; 1302 bool is_matched = true; 1303 bool target_found = false; 1304 int ret; 1305 1306 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1307 &headline_idx, rfe, cv); 1308 if (ret) { 1309 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1310 return; 1311 } 1312 1313 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1314 for (i = headline_size; i < table->n_regs; i++) { 1315 reg = &table->regs[i]; 1316 cond = get_phy_cond(reg->addr); 1317 switch (cond) { 1318 case PHY_COND_BRANCH_IF: 1319 case PHY_COND_BRANCH_ELIF: 1320 target = get_phy_target(reg->addr); 1321 break; 1322 case PHY_COND_BRANCH_ELSE: 1323 is_matched = false; 1324 if (!target_found) { 1325 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1326 reg->addr, reg->data); 1327 return; 1328 } 1329 break; 1330 case PHY_COND_BRANCH_END: 1331 is_matched = true; 1332 target_found = false; 1333 break; 1334 case PHY_COND_CHECK: 1335 if (target_found) { 1336 is_matched = false; 1337 break; 1338 } 1339 1340 if (target == cfg_target) { 1341 is_matched = true; 1342 target_found = true; 1343 } else { 1344 is_matched = false; 1345 target_found = false; 1346 } 1347 break; 1348 default: 1349 if (is_matched) 1350 config(rtwdev, reg, rf_path, extra_data); 1351 break; 1352 } 1353 } 1354 } 1355 1356 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1357 { 1358 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1359 const struct rtw89_chip_info *chip = rtwdev->chip; 1360 const struct rtw89_phy_table *bb_table; 1361 const struct rtw89_phy_table *bb_gain_table; 1362 1363 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table; 1364 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1365 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1366 1367 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table; 1368 if (bb_gain_table) 1369 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1370 rtw89_phy_config_bb_gain, NULL); 1371 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1372 } 1373 1374 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1375 { 1376 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1377 udelay(1); 1378 return rtw89_phy_read32(rtwdev, 0x8080); 1379 } 1380 1381 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1382 { 1383 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1384 enum rtw89_rf_path rf_path, void *data); 1385 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1386 const struct rtw89_chip_info *chip = rtwdev->chip; 1387 const struct rtw89_phy_table *rf_table; 1388 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1389 u8 path; 1390 1391 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1392 if (!rf_reg_info) 1393 return; 1394 1395 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1396 rf_table = elm_info->rf_radio[path] ? 1397 elm_info->rf_radio[path] : chip->rf_table[path]; 1398 rf_reg_info->rf_path = rf_table->rf_path; 1399 if (noio) 1400 config = rtw89_phy_config_rf_reg_noio; 1401 else 1402 config = rf_table->config ? rf_table->config : 1403 rtw89_phy_config_rf_reg; 1404 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1405 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1406 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1407 rf_reg_info->rf_path); 1408 } 1409 kfree(rf_reg_info); 1410 } 1411 1412 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1413 { 1414 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1415 const struct rtw89_chip_info *chip = rtwdev->chip; 1416 const struct rtw89_phy_table *nctl_table; 1417 u32 val; 1418 int ret; 1419 1420 /* IQK/DPK clock & reset */ 1421 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1422 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1423 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1424 if (chip->chip_id != RTL8851B) 1425 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1426 if (chip->chip_id == RTL8852B) 1427 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1428 1429 /* check 0x8080 */ 1430 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1431 1432 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1433 1000, false, rtwdev); 1434 if (ret) 1435 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1436 1437 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table; 1438 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1439 1440 if (chip->nctl_post_table) 1441 rtw89_rfk_parser(rtwdev, chip->nctl_post_table); 1442 } 1443 1444 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1445 { 1446 u32 phy_page = addr >> 8; 1447 u32 ofst = 0; 1448 1449 switch (phy_page) { 1450 case 0x6: 1451 case 0x7: 1452 case 0x8: 1453 case 0x9: 1454 case 0xa: 1455 case 0xb: 1456 case 0xc: 1457 case 0xd: 1458 case 0x19: 1459 case 0x1a: 1460 case 0x1b: 1461 ofst = 0x2000; 1462 break; 1463 default: 1464 /* warning case */ 1465 ofst = 0; 1466 break; 1467 } 1468 1469 if (phy_page >= 0x40 && phy_page <= 0x4f) 1470 ofst = 0x2000; 1471 1472 return ofst; 1473 } 1474 1475 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1476 u32 data, enum rtw89_phy_idx phy_idx) 1477 { 1478 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1479 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1480 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1481 } 1482 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1483 1484 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1485 enum rtw89_phy_idx phy_idx) 1486 { 1487 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1488 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1489 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1490 } 1491 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1492 1493 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1494 u32 val) 1495 { 1496 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1497 1498 if (!rtwdev->dbcc_en) 1499 return; 1500 1501 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1502 } 1503 1504 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1505 const struct rtw89_phy_reg3_tbl *tbl) 1506 { 1507 const struct rtw89_reg3_def *reg3; 1508 int i; 1509 1510 for (i = 0; i < tbl->size; i++) { 1511 reg3 = &tbl->reg3[i]; 1512 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1513 } 1514 } 1515 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1516 1517 static const u8 rtw89_rs_idx_num[] = { 1518 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM, 1519 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM, 1520 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM, 1521 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM, 1522 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM, 1523 }; 1524 1525 static const u8 rtw89_rs_nss_num[] = { 1526 [RTW89_RS_CCK] = 1, 1527 [RTW89_RS_OFDM] = 1, 1528 [RTW89_RS_MCS] = RTW89_NSS_NUM, 1529 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM, 1530 [RTW89_RS_OFFSET] = 1, 1531 }; 1532 1533 static const u8 _byr_of_rs[] = { 1534 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1535 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1536 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1537 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1538 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1539 }; 1540 1541 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1542 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_num[rs] + (idx)) 1543 #define _byr_chk(rs, nss, idx) \ 1544 ((nss) < rtw89_rs_nss_num[rs] && (idx) < rtw89_rs_idx_num[rs]) 1545 1546 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1547 const struct rtw89_txpwr_table *tbl) 1548 { 1549 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1550 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1551 s8 *byr; 1552 u32 data; 1553 u8 i, idx; 1554 1555 for (; cfg < end; cfg++) { 1556 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1557 data = cfg->data; 1558 1559 for (i = 0; i < cfg->len; i++, data >>= 8) { 1560 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1561 byr[idx] = (s8)(data & 0xff); 1562 } 1563 } 1564 } 1565 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1566 1567 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1568 ({ \ 1569 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1570 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1571 }) 1572 1573 static 1574 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, 1575 const struct rtw89_rate_desc *rate_desc) 1576 { 1577 s8 *byr; 1578 u8 idx; 1579 1580 if (rate_desc->rs == RTW89_RS_CCK) 1581 band = RTW89_BAND_2G; 1582 1583 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1584 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1585 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1586 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1587 1588 return 0; 1589 } 1590 1591 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1592 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1593 1594 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1595 } 1596 1597 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1598 { 1599 switch (channel_6g) { 1600 case 1 ... 29: 1601 return (channel_6g - 1) / 2; 1602 case 33 ... 61: 1603 return (channel_6g - 3) / 2; 1604 case 65 ... 93: 1605 return (channel_6g - 5) / 2; 1606 case 97 ... 125: 1607 return (channel_6g - 7) / 2; 1608 case 129 ... 157: 1609 return (channel_6g - 9) / 2; 1610 case 161 ... 189: 1611 return (channel_6g - 11) / 2; 1612 case 193 ... 221: 1613 return (channel_6g - 13) / 2; 1614 case 225 ... 253: 1615 return (channel_6g - 15) / 2; 1616 default: 1617 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1618 return 0; 1619 } 1620 } 1621 1622 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1623 { 1624 if (band == RTW89_BAND_6G) 1625 return rtw89_channel_6g_to_idx(rtwdev, channel); 1626 1627 switch (channel) { 1628 case 1 ... 14: 1629 return channel - 1; 1630 case 36 ... 64: 1631 return (channel - 36) / 2; 1632 case 100 ... 144: 1633 return ((channel - 100) / 2) + 15; 1634 case 149 ... 177: 1635 return ((channel - 149) / 2) + 38; 1636 default: 1637 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1638 return 0; 1639 } 1640 } 1641 1642 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1643 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1644 { 1645 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1646 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1647 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1648 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1649 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1650 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1651 u8 regd = rtw89_regd_get(rtwdev, band); 1652 u8 reg6 = regulatory->reg_6ghz_power; 1653 s8 lmt = 0, sar; 1654 1655 switch (band) { 1656 case RTW89_BAND_2G: 1657 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1658 if (lmt) 1659 break; 1660 1661 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1662 break; 1663 case RTW89_BAND_5G: 1664 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1665 if (lmt) 1666 break; 1667 1668 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1669 break; 1670 case RTW89_BAND_6G: 1671 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx]; 1672 if (lmt) 1673 break; 1674 1675 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW] 1676 [RTW89_REG_6GHZ_POWER_DFLT] 1677 [ch_idx]; 1678 break; 1679 default: 1680 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1681 return 0; 1682 } 1683 1684 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1685 sar = rtw89_query_sar(rtwdev); 1686 1687 return min(lmt, sar); 1688 } 1689 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1690 1691 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1692 do { \ 1693 u8 __i; \ 1694 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1695 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1696 band, \ 1697 bw, ntx, \ 1698 rs, __i, \ 1699 (ch)); \ 1700 } while (0) 1701 1702 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1703 struct rtw89_txpwr_limit *lmt, 1704 u8 band, u8 ntx, u8 ch) 1705 { 1706 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1707 ntx, RTW89_RS_CCK, ch); 1708 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1709 ntx, RTW89_RS_CCK, ch); 1710 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1711 ntx, RTW89_RS_OFDM, ch); 1712 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1713 RTW89_CHANNEL_WIDTH_20, 1714 ntx, RTW89_RS_MCS, ch); 1715 } 1716 1717 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1718 struct rtw89_txpwr_limit *lmt, 1719 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1720 { 1721 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1722 ntx, RTW89_RS_CCK, ch - 2); 1723 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1724 ntx, RTW89_RS_CCK, ch); 1725 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1726 ntx, RTW89_RS_OFDM, pri_ch); 1727 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1728 RTW89_CHANNEL_WIDTH_20, 1729 ntx, RTW89_RS_MCS, ch - 2); 1730 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1731 RTW89_CHANNEL_WIDTH_20, 1732 ntx, RTW89_RS_MCS, ch + 2); 1733 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1734 RTW89_CHANNEL_WIDTH_40, 1735 ntx, RTW89_RS_MCS, ch); 1736 } 1737 1738 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1739 struct rtw89_txpwr_limit *lmt, 1740 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1741 { 1742 s8 val_0p5_n[RTW89_BF_NUM]; 1743 s8 val_0p5_p[RTW89_BF_NUM]; 1744 u8 i; 1745 1746 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1747 ntx, RTW89_RS_OFDM, pri_ch); 1748 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1749 RTW89_CHANNEL_WIDTH_20, 1750 ntx, RTW89_RS_MCS, ch - 6); 1751 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1752 RTW89_CHANNEL_WIDTH_20, 1753 ntx, RTW89_RS_MCS, ch - 2); 1754 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1755 RTW89_CHANNEL_WIDTH_20, 1756 ntx, RTW89_RS_MCS, ch + 2); 1757 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1758 RTW89_CHANNEL_WIDTH_20, 1759 ntx, RTW89_RS_MCS, ch + 6); 1760 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1761 RTW89_CHANNEL_WIDTH_40, 1762 ntx, RTW89_RS_MCS, ch - 4); 1763 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1764 RTW89_CHANNEL_WIDTH_40, 1765 ntx, RTW89_RS_MCS, ch + 4); 1766 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1767 RTW89_CHANNEL_WIDTH_80, 1768 ntx, RTW89_RS_MCS, ch); 1769 1770 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1771 ntx, RTW89_RS_MCS, ch - 4); 1772 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1773 ntx, RTW89_RS_MCS, ch + 4); 1774 1775 for (i = 0; i < RTW89_BF_NUM; i++) 1776 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1777 } 1778 1779 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1780 struct rtw89_txpwr_limit *lmt, 1781 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1782 { 1783 s8 val_0p5_n[RTW89_BF_NUM]; 1784 s8 val_0p5_p[RTW89_BF_NUM]; 1785 s8 val_2p5_n[RTW89_BF_NUM]; 1786 s8 val_2p5_p[RTW89_BF_NUM]; 1787 u8 i; 1788 1789 /* fill ofdm section */ 1790 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1791 ntx, RTW89_RS_OFDM, pri_ch); 1792 1793 /* fill mcs 20m section */ 1794 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1795 RTW89_CHANNEL_WIDTH_20, 1796 ntx, RTW89_RS_MCS, ch - 14); 1797 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1798 RTW89_CHANNEL_WIDTH_20, 1799 ntx, RTW89_RS_MCS, ch - 10); 1800 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1801 RTW89_CHANNEL_WIDTH_20, 1802 ntx, RTW89_RS_MCS, ch - 6); 1803 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1804 RTW89_CHANNEL_WIDTH_20, 1805 ntx, RTW89_RS_MCS, ch - 2); 1806 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1807 RTW89_CHANNEL_WIDTH_20, 1808 ntx, RTW89_RS_MCS, ch + 2); 1809 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1810 RTW89_CHANNEL_WIDTH_20, 1811 ntx, RTW89_RS_MCS, ch + 6); 1812 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1813 RTW89_CHANNEL_WIDTH_20, 1814 ntx, RTW89_RS_MCS, ch + 10); 1815 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1816 RTW89_CHANNEL_WIDTH_20, 1817 ntx, RTW89_RS_MCS, ch + 14); 1818 1819 /* fill mcs 40m section */ 1820 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1821 RTW89_CHANNEL_WIDTH_40, 1822 ntx, RTW89_RS_MCS, ch - 12); 1823 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1824 RTW89_CHANNEL_WIDTH_40, 1825 ntx, RTW89_RS_MCS, ch - 4); 1826 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1827 RTW89_CHANNEL_WIDTH_40, 1828 ntx, RTW89_RS_MCS, ch + 4); 1829 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1830 RTW89_CHANNEL_WIDTH_40, 1831 ntx, RTW89_RS_MCS, ch + 12); 1832 1833 /* fill mcs 80m section */ 1834 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1835 RTW89_CHANNEL_WIDTH_80, 1836 ntx, RTW89_RS_MCS, ch - 8); 1837 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1838 RTW89_CHANNEL_WIDTH_80, 1839 ntx, RTW89_RS_MCS, ch + 8); 1840 1841 /* fill mcs 160m section */ 1842 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1843 RTW89_CHANNEL_WIDTH_160, 1844 ntx, RTW89_RS_MCS, ch); 1845 1846 /* fill mcs 40m 0p5 section */ 1847 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1848 ntx, RTW89_RS_MCS, ch - 4); 1849 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1850 ntx, RTW89_RS_MCS, ch + 4); 1851 1852 for (i = 0; i < RTW89_BF_NUM; i++) 1853 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1854 1855 /* fill mcs 40m 2p5 section */ 1856 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1857 ntx, RTW89_RS_MCS, ch - 8); 1858 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1859 ntx, RTW89_RS_MCS, ch + 8); 1860 1861 for (i = 0; i < RTW89_BF_NUM; i++) 1862 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1863 } 1864 1865 static 1866 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1867 const struct rtw89_chan *chan, 1868 struct rtw89_txpwr_limit *lmt, 1869 u8 ntx) 1870 { 1871 u8 band = chan->band_type; 1872 u8 pri_ch = chan->primary_channel; 1873 u8 ch = chan->channel; 1874 u8 bw = chan->band_width; 1875 1876 memset(lmt, 0, sizeof(*lmt)); 1877 1878 switch (bw) { 1879 case RTW89_CHANNEL_WIDTH_20: 1880 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, band, ntx, ch); 1881 break; 1882 case RTW89_CHANNEL_WIDTH_40: 1883 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, band, ntx, ch, 1884 pri_ch); 1885 break; 1886 case RTW89_CHANNEL_WIDTH_80: 1887 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, band, ntx, ch, 1888 pri_ch); 1889 break; 1890 case RTW89_CHANNEL_WIDTH_160: 1891 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, band, ntx, ch, 1892 pri_ch); 1893 break; 1894 } 1895 } 1896 1897 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1898 u8 ru, u8 ntx, u8 ch) 1899 { 1900 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1901 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1902 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1903 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1904 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1905 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1906 u8 regd = rtw89_regd_get(rtwdev, band); 1907 u8 reg6 = regulatory->reg_6ghz_power; 1908 s8 lmt_ru = 0, sar; 1909 1910 switch (band) { 1911 case RTW89_BAND_2G: 1912 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 1913 if (lmt_ru) 1914 break; 1915 1916 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 1917 break; 1918 case RTW89_BAND_5G: 1919 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 1920 if (lmt_ru) 1921 break; 1922 1923 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 1924 break; 1925 case RTW89_BAND_6G: 1926 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx]; 1927 if (lmt_ru) 1928 break; 1929 1930 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW] 1931 [RTW89_REG_6GHZ_POWER_DFLT] 1932 [ch_idx]; 1933 break; 1934 default: 1935 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1936 return 0; 1937 } 1938 1939 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1940 sar = rtw89_query_sar(rtwdev); 1941 1942 return min(lmt_ru, sar); 1943 } 1944 1945 static void 1946 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1947 struct rtw89_txpwr_limit_ru *lmt_ru, 1948 u8 band, u8 ntx, u8 ch) 1949 { 1950 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1951 RTW89_RU26, 1952 ntx, ch); 1953 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1954 RTW89_RU52, 1955 ntx, ch); 1956 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1957 RTW89_RU106, 1958 ntx, ch); 1959 } 1960 1961 static void 1962 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1963 struct rtw89_txpwr_limit_ru *lmt_ru, 1964 u8 band, u8 ntx, u8 ch) 1965 { 1966 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1967 RTW89_RU26, 1968 ntx, ch - 2); 1969 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1970 RTW89_RU26, 1971 ntx, ch + 2); 1972 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1973 RTW89_RU52, 1974 ntx, ch - 2); 1975 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1976 RTW89_RU52, 1977 ntx, ch + 2); 1978 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1979 RTW89_RU106, 1980 ntx, ch - 2); 1981 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1982 RTW89_RU106, 1983 ntx, ch + 2); 1984 } 1985 1986 static void 1987 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1988 struct rtw89_txpwr_limit_ru *lmt_ru, 1989 u8 band, u8 ntx, u8 ch) 1990 { 1991 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1992 RTW89_RU26, 1993 ntx, ch - 6); 1994 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1995 RTW89_RU26, 1996 ntx, ch - 2); 1997 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1998 RTW89_RU26, 1999 ntx, ch + 2); 2000 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2001 RTW89_RU26, 2002 ntx, ch + 6); 2003 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2004 RTW89_RU52, 2005 ntx, ch - 6); 2006 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2007 RTW89_RU52, 2008 ntx, ch - 2); 2009 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2010 RTW89_RU52, 2011 ntx, ch + 2); 2012 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2013 RTW89_RU52, 2014 ntx, ch + 6); 2015 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2016 RTW89_RU106, 2017 ntx, ch - 6); 2018 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2019 RTW89_RU106, 2020 ntx, ch - 2); 2021 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2022 RTW89_RU106, 2023 ntx, ch + 2); 2024 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2025 RTW89_RU106, 2026 ntx, ch + 6); 2027 } 2028 2029 static void 2030 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 2031 struct rtw89_txpwr_limit_ru *lmt_ru, 2032 u8 band, u8 ntx, u8 ch) 2033 { 2034 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 2035 int i; 2036 2037 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 2038 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 2039 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2040 RTW89_RU26, 2041 ntx, 2042 ch + ofst[i]); 2043 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2044 RTW89_RU52, 2045 ntx, 2046 ch + ofst[i]); 2047 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2048 RTW89_RU106, 2049 ntx, 2050 ch + ofst[i]); 2051 } 2052 } 2053 2054 static 2055 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2056 const struct rtw89_chan *chan, 2057 struct rtw89_txpwr_limit_ru *lmt_ru, 2058 u8 ntx) 2059 { 2060 u8 band = chan->band_type; 2061 u8 ch = chan->channel; 2062 u8 bw = chan->band_width; 2063 2064 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2065 2066 switch (bw) { 2067 case RTW89_CHANNEL_WIDTH_20: 2068 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx, 2069 ch); 2070 break; 2071 case RTW89_CHANNEL_WIDTH_40: 2072 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx, 2073 ch); 2074 break; 2075 case RTW89_CHANNEL_WIDTH_80: 2076 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx, 2077 ch); 2078 break; 2079 case RTW89_CHANNEL_WIDTH_160: 2080 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx, 2081 ch); 2082 break; 2083 } 2084 } 2085 2086 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 2087 const struct rtw89_chan *chan, 2088 enum rtw89_phy_idx phy_idx) 2089 { 2090 u8 max_nss_num = rtwdev->chip->rf_path_num; 2091 static const u8 rs[] = { 2092 RTW89_RS_CCK, 2093 RTW89_RS_OFDM, 2094 RTW89_RS_MCS, 2095 RTW89_RS_HEDCM, 2096 }; 2097 struct rtw89_rate_desc cur; 2098 u8 band = chan->band_type; 2099 u8 ch = chan->channel; 2100 u32 addr, val; 2101 s8 v[4] = {}; 2102 u8 i; 2103 2104 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2105 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2106 2107 BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_CCK] % 4); 2108 BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_OFDM] % 4); 2109 BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_MCS] % 4); 2110 BUILD_BUG_ON(rtw89_rs_idx_num[RTW89_RS_HEDCM] % 4); 2111 2112 addr = R_AX_PWR_BY_RATE; 2113 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) { 2114 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2115 if (cur.nss >= rtw89_rs_nss_num[rs[i]]) 2116 continue; 2117 2118 cur.rs = rs[i]; 2119 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num[rs[i]]; 2120 cur.idx++) { 2121 v[cur.idx % 4] = 2122 rtw89_phy_read_txpwr_byrate(rtwdev, 2123 band, 2124 &cur); 2125 2126 if ((cur.idx + 1) % 4) 2127 continue; 2128 2129 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2130 FIELD_PREP(GENMASK(15, 8), v[1]) | 2131 FIELD_PREP(GENMASK(23, 16), v[2]) | 2132 FIELD_PREP(GENMASK(31, 24), v[3]); 2133 2134 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2135 val); 2136 addr += 4; 2137 } 2138 } 2139 } 2140 } 2141 EXPORT_SYMBOL(rtw89_phy_set_txpwr_byrate); 2142 2143 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 2144 const struct rtw89_chan *chan, 2145 enum rtw89_phy_idx phy_idx) 2146 { 2147 struct rtw89_rate_desc desc = { 2148 .nss = RTW89_NSS_1, 2149 .rs = RTW89_RS_OFFSET, 2150 }; 2151 u8 band = chan->band_type; 2152 s8 v[RTW89_RATE_OFFSET_NUM] = {}; 2153 u32 val; 2154 2155 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2156 2157 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM; desc.idx++) 2158 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, &desc); 2159 2160 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM != 5); 2161 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2162 FIELD_PREP(GENMASK(7, 4), v[1]) | 2163 FIELD_PREP(GENMASK(11, 8), v[2]) | 2164 FIELD_PREP(GENMASK(15, 12), v[3]) | 2165 FIELD_PREP(GENMASK(19, 16), v[4]); 2166 2167 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2168 GENMASK(19, 0), val); 2169 } 2170 EXPORT_SYMBOL(rtw89_phy_set_txpwr_offset); 2171 2172 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 2173 const struct rtw89_chan *chan, 2174 enum rtw89_phy_idx phy_idx) 2175 { 2176 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2177 struct rtw89_txpwr_limit lmt; 2178 u8 ch = chan->channel; 2179 u8 bw = chan->band_width; 2180 const s8 *ptr; 2181 u32 addr, val; 2182 u8 i, j; 2183 2184 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2185 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2186 2187 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit) != 2188 RTW89_TXPWR_LMT_PAGE_SIZE); 2189 2190 addr = R_AX_PWR_LMT; 2191 for (i = 0; i < max_ntx_num; i++) { 2192 rtw89_phy_fill_txpwr_limit(rtwdev, chan, &lmt, i); 2193 2194 ptr = (s8 *)&lmt; 2195 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE; 2196 j += 4, addr += 4, ptr += 4) { 2197 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2198 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2199 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2200 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2201 2202 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2203 } 2204 } 2205 } 2206 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit); 2207 2208 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 2209 const struct rtw89_chan *chan, 2210 enum rtw89_phy_idx phy_idx) 2211 { 2212 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2213 struct rtw89_txpwr_limit_ru lmt_ru; 2214 u8 ch = chan->channel; 2215 u8 bw = chan->band_width; 2216 const s8 *ptr; 2217 u32 addr, val; 2218 u8 i, j; 2219 2220 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2221 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2222 2223 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru) != 2224 RTW89_TXPWR_LMT_RU_PAGE_SIZE); 2225 2226 addr = R_AX_PWR_RU_LMT; 2227 for (i = 0; i < max_ntx_num; i++) { 2228 rtw89_phy_fill_txpwr_limit_ru(rtwdev, chan, &lmt_ru, i); 2229 2230 ptr = (s8 *)&lmt_ru; 2231 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE; 2232 j += 4, addr += 4, ptr += 4) { 2233 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2234 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2235 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2236 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2237 2238 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2239 } 2240 } 2241 } 2242 EXPORT_SYMBOL(rtw89_phy_set_txpwr_limit_ru); 2243 2244 struct rtw89_phy_iter_ra_data { 2245 struct rtw89_dev *rtwdev; 2246 struct sk_buff *c2h; 2247 }; 2248 2249 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2250 { 2251 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2252 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2253 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2254 const struct rtw89_c2h_ra_rpt *c2h = 2255 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data; 2256 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2257 const struct rtw89_chip_info *chip = rtwdev->chip; 2258 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE; 2259 u8 mode, rate, bw, giltf, mac_id; 2260 u16 legacy_bitrate; 2261 bool valid; 2262 u8 mcs = 0; 2263 u8 t; 2264 2265 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID); 2266 if (mac_id != rtwsta->mac_id) 2267 return; 2268 2269 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS); 2270 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW); 2271 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF); 2272 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL); 2273 2274 if (format_v1) { 2275 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7); 2276 rate |= u8_encode_bits(t, BIT(7)); 2277 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2); 2278 bw |= u8_encode_bits(t, BIT(2)); 2279 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2); 2280 mode |= u8_encode_bits(t, BIT(2)); 2281 } 2282 2283 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2284 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2285 if (!valid) 2286 return; 2287 } 2288 2289 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2290 2291 switch (mode) { 2292 case RTW89_RA_RPT_MODE_LEGACY: 2293 ra_report->txrate.legacy = legacy_bitrate; 2294 break; 2295 case RTW89_RA_RPT_MODE_HT: 2296 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2297 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2298 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2299 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2300 else 2301 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2302 ra_report->txrate.mcs = rate; 2303 if (giltf) 2304 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2305 mcs = ra_report->txrate.mcs & 0x07; 2306 break; 2307 case RTW89_RA_RPT_MODE_VHT: 2308 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2309 ra_report->txrate.mcs = format_v1 ? 2310 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2311 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2312 ra_report->txrate.nss = format_v1 ? 2313 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2314 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2315 if (giltf) 2316 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2317 mcs = ra_report->txrate.mcs; 2318 break; 2319 case RTW89_RA_RPT_MODE_HE: 2320 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2321 ra_report->txrate.mcs = format_v1 ? 2322 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2323 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2324 ra_report->txrate.nss = format_v1 ? 2325 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2326 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2327 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2328 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2329 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2330 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2331 else 2332 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2333 mcs = ra_report->txrate.mcs; 2334 break; 2335 } 2336 2337 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2338 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2339 ra_report->hw_rate = format_v1 ? 2340 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) | 2341 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) : 2342 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) | 2343 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL); 2344 ra_report->might_fallback_legacy = mcs <= 2; 2345 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2346 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2347 } 2348 2349 static void 2350 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2351 { 2352 struct rtw89_phy_iter_ra_data ra_data; 2353 2354 ra_data.rtwdev = rtwdev; 2355 ra_data.c2h = c2h; 2356 ieee80211_iterate_stations_atomic(rtwdev->hw, 2357 rtw89_phy_c2h_ra_rpt_iter, 2358 &ra_data); 2359 } 2360 2361 static 2362 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2363 struct sk_buff *c2h, u32 len) = { 2364 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2365 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2366 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2367 }; 2368 2369 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2370 u32 len, u8 class, u8 func) 2371 { 2372 void (*handler)(struct rtw89_dev *rtwdev, 2373 struct sk_buff *c2h, u32 len) = NULL; 2374 2375 switch (class) { 2376 case RTW89_PHY_C2H_CLASS_RA: 2377 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2378 handler = rtw89_phy_c2h_ra_handler[func]; 2379 break; 2380 case RTW89_PHY_C2H_CLASS_DM: 2381 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 2382 return; 2383 fallthrough; 2384 default: 2385 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2386 return; 2387 } 2388 if (!handler) { 2389 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2390 func); 2391 return; 2392 } 2393 handler(rtwdev, skb, len); 2394 } 2395 2396 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2397 { 2398 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 2399 u32 reg_mask; 2400 2401 if (sc_xo) 2402 reg_mask = xtal->sc_xo_mask; 2403 else 2404 reg_mask = xtal->sc_xi_mask; 2405 2406 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask); 2407 } 2408 2409 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2410 u8 val) 2411 { 2412 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 2413 u32 reg_mask; 2414 2415 if (sc_xo) 2416 reg_mask = xtal->sc_xo_mask; 2417 else 2418 reg_mask = xtal->sc_xi_mask; 2419 2420 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); 2421 } 2422 2423 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2424 u8 crystal_cap, bool force) 2425 { 2426 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2427 const struct rtw89_chip_info *chip = rtwdev->chip; 2428 u8 sc_xi_val, sc_xo_val; 2429 2430 if (!force && cfo->crystal_cap == crystal_cap) 2431 return; 2432 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2433 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) { 2434 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2435 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2436 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2437 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2438 } else { 2439 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2440 crystal_cap, XTAL_SC_XO_MASK); 2441 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2442 crystal_cap, XTAL_SC_XI_MASK); 2443 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2444 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2445 } 2446 cfo->crystal_cap = sc_xi_val; 2447 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2448 2449 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2450 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2451 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2452 cfo->x_cap_ofst); 2453 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2454 } 2455 2456 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2457 { 2458 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2459 u8 cap; 2460 2461 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2462 cfo->is_adjust = false; 2463 if (cfo->crystal_cap == cfo->def_x_cap) 2464 return; 2465 cap = cfo->crystal_cap; 2466 cap += (cap > cfo->def_x_cap ? -1 : 1); 2467 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2468 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2469 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2470 cfo->def_x_cap); 2471 } 2472 2473 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2474 { 2475 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2476 bool is_linked = rtwdev->total_sta_assoc > 0; 2477 s32 cfo_avg_312; 2478 s32 dcfo_comp_val; 2479 int sign; 2480 2481 if (!is_linked) { 2482 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2483 is_linked); 2484 return; 2485 } 2486 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2487 if (curr_cfo == 0) 2488 return; 2489 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2490 sign = curr_cfo > 0 ? 1 : -1; 2491 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val; 2492 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312); 2493 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2494 cfo_avg_312 = -cfo_avg_312; 2495 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2496 cfo_avg_312); 2497 } 2498 2499 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2500 { 2501 const struct rtw89_chip_info *chip = rtwdev->chip; 2502 2503 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2504 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2505 2506 if (chip->cfo_hw_comp) 2507 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, 2508 B_AX_PWR_UL_CFO_MASK, 0x6); 2509 else 2510 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2511 } 2512 2513 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2514 { 2515 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2516 struct rtw89_efuse *efuse = &rtwdev->efuse; 2517 2518 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2519 cfo->crystal_cap = cfo->crystal_cap_default; 2520 cfo->def_x_cap = cfo->crystal_cap; 2521 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2522 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2523 cfo->is_adjust = false; 2524 cfo->divergence_lock_en = false; 2525 cfo->x_cap_ofst = 0; 2526 cfo->lock_cnt = 0; 2527 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2528 cfo->apply_compensation = false; 2529 cfo->residual_cfo_acc = 0; 2530 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2531 cfo->crystal_cap_default); 2532 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2533 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2534 rtw89_dcfo_comp_init(rtwdev); 2535 cfo->cfo_timer_ms = 2000; 2536 cfo->cfo_trig_by_timer_en = false; 2537 cfo->phy_cfo_trk_cnt = 0; 2538 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2539 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2540 } 2541 2542 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2543 s32 curr_cfo) 2544 { 2545 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2546 s8 crystal_cap = cfo->crystal_cap; 2547 s32 cfo_abs = abs(curr_cfo); 2548 int sign; 2549 2550 if (!cfo->is_adjust) { 2551 if (cfo_abs > CFO_TRK_ENABLE_TH) 2552 cfo->is_adjust = true; 2553 } else { 2554 if (cfo_abs < CFO_TRK_STOP_TH) 2555 cfo->is_adjust = false; 2556 } 2557 if (!cfo->is_adjust) { 2558 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2559 return; 2560 } 2561 sign = curr_cfo > 0 ? 1 : -1; 2562 if (cfo_abs > CFO_TRK_STOP_TH_4) 2563 crystal_cap += 7 * sign; 2564 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2565 crystal_cap += 5 * sign; 2566 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2567 crystal_cap += 3 * sign; 2568 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2569 crystal_cap += 1 * sign; 2570 else 2571 return; 2572 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2573 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2574 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2575 cfo->crystal_cap, cfo->def_x_cap); 2576 } 2577 2578 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2579 { 2580 const struct rtw89_chip_info *chip = rtwdev->chip; 2581 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2582 s32 cfo_khz_all = 0; 2583 s32 cfo_cnt_all = 0; 2584 s32 cfo_all_avg = 0; 2585 u8 i; 2586 2587 if (rtwdev->total_sta_assoc != 1) 2588 return 0; 2589 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2590 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2591 if (cfo->cfo_cnt[i] == 0) 2592 continue; 2593 cfo_khz_all += cfo->cfo_tail[i]; 2594 cfo_cnt_all += cfo->cfo_cnt[i]; 2595 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2596 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2597 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft, 2598 cfo_cnt_all); 2599 } 2600 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2601 "CFO track for macid = %d\n", i); 2602 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2603 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2604 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2605 return cfo_all_avg; 2606 } 2607 2608 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2609 { 2610 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2611 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2612 s32 target_cfo = 0; 2613 s32 cfo_khz_all = 0; 2614 s32 cfo_khz_all_tp_wgt = 0; 2615 s32 cfo_avg = 0; 2616 s32 max_cfo_lb = BIT(31); 2617 s32 min_cfo_ub = GENMASK(30, 0); 2618 u16 cfo_cnt_all = 0; 2619 u8 active_entry_cnt = 0; 2620 u8 sta_cnt = 0; 2621 u32 tp_all = 0; 2622 u8 i; 2623 u8 cfo_tol = 0; 2624 2625 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2626 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2627 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2628 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2629 if (cfo->cfo_cnt[i] == 0) 2630 continue; 2631 cfo_khz_all += cfo->cfo_tail[i]; 2632 cfo_cnt_all += cfo->cfo_cnt[i]; 2633 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2634 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2635 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2636 cfo_khz_all, cfo_cnt_all, cfo_avg); 2637 target_cfo = cfo_avg; 2638 } 2639 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2640 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2641 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2642 if (cfo->cfo_cnt[i] == 0) 2643 continue; 2644 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2645 (s32)cfo->cfo_cnt[i]); 2646 cfo_khz_all += cfo->cfo_avg[i]; 2647 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2648 "Macid=%d, cfo_avg=%d\n", i, 2649 cfo->cfo_avg[i]); 2650 } 2651 sta_cnt = rtwdev->total_sta_assoc; 2652 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2653 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2654 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2655 cfo_khz_all, sta_cnt, cfo_avg); 2656 target_cfo = cfo_avg; 2657 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2658 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2659 cfo_tol = cfo->sta_cfo_tolerance; 2660 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2661 sta_cnt++; 2662 if (cfo->cfo_cnt[i] != 0) { 2663 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2664 (s32)cfo->cfo_cnt[i]); 2665 active_entry_cnt++; 2666 } else { 2667 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2668 } 2669 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2670 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2671 cfo_khz_all += cfo->cfo_avg[i]; 2672 /* need tp for each entry */ 2673 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2674 "[%d] cfo_avg=%d, tp=tbd\n", 2675 i, cfo->cfo_avg[i]); 2676 if (sta_cnt >= rtwdev->total_sta_assoc) 2677 break; 2678 } 2679 tp_all = stats->rx_throughput; /* need tp for each entry */ 2680 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2681 2682 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2683 sta_cnt); 2684 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2685 active_entry_cnt); 2686 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2687 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2688 cfo_khz_all_tp_wgt, cfo_avg); 2689 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2690 max_cfo_lb, min_cfo_ub); 2691 if (max_cfo_lb <= min_cfo_ub) { 2692 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2693 "cfo win_size=%d\n", 2694 min_cfo_ub - max_cfo_lb); 2695 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2696 } else { 2697 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2698 "No intersection of cfo tolerance windows\n"); 2699 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2700 } 2701 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2702 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2703 } 2704 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2705 return target_cfo; 2706 } 2707 2708 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2709 { 2710 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2711 2712 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2713 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2714 cfo->packet_count = 0; 2715 cfo->packet_count_pre = 0; 2716 cfo->cfo_avg_pre = 0; 2717 } 2718 2719 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2720 { 2721 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2722 s32 new_cfo = 0; 2723 bool x_cap_update = false; 2724 u8 pre_x_cap = cfo->crystal_cap; 2725 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2726 2727 cfo->dcfo_avg = 0; 2728 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2729 rtwdev->total_sta_assoc); 2730 if (rtwdev->total_sta_assoc == 0) { 2731 rtw89_phy_cfo_reset(rtwdev); 2732 return; 2733 } 2734 if (cfo->packet_count == 0) { 2735 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2736 return; 2737 } 2738 if (cfo->packet_count == cfo->packet_count_pre) { 2739 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2740 return; 2741 } 2742 if (rtwdev->total_sta_assoc == 1) 2743 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2744 else 2745 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2746 if (new_cfo == 0) { 2747 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2748 return; 2749 } 2750 if (cfo->divergence_lock_en) { 2751 cfo->lock_cnt++; 2752 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2753 cfo->divergence_lock_en = false; 2754 cfo->lock_cnt = 0; 2755 } else { 2756 rtw89_phy_cfo_reset(rtwdev); 2757 } 2758 return; 2759 } 2760 if (cfo->crystal_cap >= cfo->x_cap_ub || 2761 cfo->crystal_cap <= cfo->x_cap_lb) { 2762 cfo->divergence_lock_en = true; 2763 rtw89_phy_cfo_reset(rtwdev); 2764 return; 2765 } 2766 2767 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2768 cfo->cfo_avg_pre = new_cfo; 2769 cfo->dcfo_avg_pre = cfo->dcfo_avg; 2770 x_cap_update = cfo->crystal_cap != pre_x_cap; 2771 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2772 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2773 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2774 cfo->x_cap_ofst); 2775 if (x_cap_update) { 2776 if (cfo->dcfo_avg > 0) 2777 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 2778 else 2779 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 2780 } 2781 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg); 2782 rtw89_phy_cfo_statistics_reset(rtwdev); 2783 } 2784 2785 void rtw89_phy_cfo_track_work(struct work_struct *work) 2786 { 2787 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2788 cfo_track_work.work); 2789 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2790 2791 mutex_lock(&rtwdev->mutex); 2792 if (!cfo->cfo_trig_by_timer_en) 2793 goto out; 2794 rtw89_leave_ps_mode(rtwdev); 2795 rtw89_phy_cfo_dm(rtwdev); 2796 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2797 msecs_to_jiffies(cfo->cfo_timer_ms)); 2798 out: 2799 mutex_unlock(&rtwdev->mutex); 2800 } 2801 2802 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2803 { 2804 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2805 2806 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2807 msecs_to_jiffies(cfo->cfo_timer_ms)); 2808 } 2809 2810 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2811 { 2812 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2813 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2814 bool is_ul_ofdma = false, ofdma_acc_en = false; 2815 2816 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2817 is_ul_ofdma = true; 2818 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2819 is_ul_ofdma) 2820 ofdma_acc_en = true; 2821 2822 switch (cfo->phy_cfo_status) { 2823 case RTW89_PHY_DCFO_STATE_NORMAL: 2824 if (stats->tx_throughput >= CFO_TP_UPPER) { 2825 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2826 cfo->cfo_trig_by_timer_en = true; 2827 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2828 rtw89_phy_cfo_start_work(rtwdev); 2829 } 2830 break; 2831 case RTW89_PHY_DCFO_STATE_ENHANCE: 2832 if (stats->tx_throughput <= CFO_TP_LOWER) 2833 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2834 else if (ofdma_acc_en && 2835 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2836 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2837 else 2838 cfo->phy_cfo_trk_cnt++; 2839 2840 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2841 cfo->phy_cfo_trk_cnt = 0; 2842 cfo->cfo_trig_by_timer_en = false; 2843 } 2844 break; 2845 case RTW89_PHY_DCFO_STATE_HOLD: 2846 if (stats->tx_throughput <= CFO_TP_LOWER) { 2847 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2848 cfo->phy_cfo_trk_cnt = 0; 2849 cfo->cfo_trig_by_timer_en = false; 2850 } else { 2851 cfo->phy_cfo_trk_cnt++; 2852 } 2853 break; 2854 default: 2855 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2856 cfo->phy_cfo_trk_cnt = 0; 2857 break; 2858 } 2859 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2860 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2861 stats->tx_throughput, cfo->phy_cfo_status, 2862 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2863 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2864 if (cfo->cfo_trig_by_timer_en) 2865 return; 2866 rtw89_phy_cfo_dm(rtwdev); 2867 } 2868 2869 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2870 struct rtw89_rx_phy_ppdu *phy_ppdu) 2871 { 2872 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2873 u8 macid = phy_ppdu->mac_id; 2874 2875 if (macid >= CFO_TRACK_MAX_USER) { 2876 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2877 return; 2878 } 2879 2880 cfo->cfo_tail[macid] += cfo_val; 2881 cfo->cfo_cnt[macid]++; 2882 cfo->packet_count++; 2883 } 2884 2885 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2886 { 2887 const struct rtw89_chip_info *chip = rtwdev->chip; 2888 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2889 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2890 2891 if (!chip->support_ul_tb_ctrl) 2892 return; 2893 2894 rtwvif->def_tri_idx = 2895 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 2896 2897 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 2898 rtwvif->dyn_tb_bedge_en = false; 2899 else if (chan->band_type >= RTW89_BAND_5G && 2900 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 2901 rtwvif->dyn_tb_bedge_en = true; 2902 else 2903 rtwvif->dyn_tb_bedge_en = false; 2904 2905 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2906 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 2907 ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx); 2908 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2909 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 2910 rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 2911 } 2912 2913 struct rtw89_phy_ul_tb_check_data { 2914 bool valid; 2915 bool high_tf_client; 2916 bool low_tf_client; 2917 bool dyn_tb_bedge_en; 2918 u8 def_tri_idx; 2919 }; 2920 2921 static 2922 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 2923 struct rtw89_vif *rtwvif, 2924 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 2925 { 2926 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2927 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2928 2929 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 2930 return; 2931 2932 if (!vif->cfg.assoc) 2933 return; 2934 2935 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 2936 ul_tb_data->high_tf_client = true; 2937 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 2938 ul_tb_data->low_tf_client = true; 2939 2940 ul_tb_data->valid = true; 2941 ul_tb_data->def_tri_idx = rtwvif->def_tri_idx; 2942 ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en; 2943 } 2944 2945 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 2946 { 2947 const struct rtw89_chip_info *chip = rtwdev->chip; 2948 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2949 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 2950 struct rtw89_vif *rtwvif; 2951 2952 if (!chip->support_ul_tb_ctrl) 2953 return; 2954 2955 if (rtwdev->total_sta_assoc != 1) 2956 return; 2957 2958 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2959 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data); 2960 2961 if (!ul_tb_data.valid) 2962 return; 2963 2964 if (ul_tb_data.dyn_tb_bedge_en) { 2965 if (ul_tb_data.high_tf_client) { 2966 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 2967 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2968 "[ULTB] Turn off if_bandedge\n"); 2969 } else if (ul_tb_data.low_tf_client) { 2970 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 2971 ul_tb_info->def_if_bandedge); 2972 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2973 "[ULTB] Set to default if_bandedge = %d\n", 2974 ul_tb_info->def_if_bandedge); 2975 } 2976 } 2977 2978 if (ul_tb_info->dyn_tb_tri_en) { 2979 if (ul_tb_data.high_tf_client) { 2980 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 2981 B_TXSHAPE_TRIANGULAR_CFG, 0); 2982 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2983 "[ULTB] Turn off Tx triangle\n"); 2984 } else if (ul_tb_data.low_tf_client) { 2985 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 2986 B_TXSHAPE_TRIANGULAR_CFG, 2987 ul_tb_data.def_tri_idx); 2988 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 2989 "[ULTB] Set to default tx_shap_idx = %d\n", 2990 ul_tb_data.def_tri_idx); 2991 } 2992 } 2993 } 2994 2995 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 2996 { 2997 const struct rtw89_chip_info *chip = rtwdev->chip; 2998 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 2999 3000 if (!chip->support_ul_tb_ctrl) 3001 return; 3002 3003 ul_tb_info->dyn_tb_tri_en = true; 3004 ul_tb_info->def_if_bandedge = 3005 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 3006 } 3007 3008 static 3009 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts) 3010 { 3011 ewma_rssi_init(&antdiv_sts->cck_rssi_avg); 3012 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg); 3013 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg); 3014 antdiv_sts->pkt_cnt_cck = 0; 3015 antdiv_sts->pkt_cnt_ofdm = 0; 3016 antdiv_sts->pkt_cnt_non_legacy = 0; 3017 antdiv_sts->evm = 0; 3018 } 3019 3020 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev, 3021 struct rtw89_rx_phy_ppdu *phy_ppdu, 3022 struct rtw89_antdiv_stats *stats) 3023 { 3024 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) { 3025 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) { 3026 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg); 3027 stats->pkt_cnt_cck++; 3028 } else { 3029 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg); 3030 stats->pkt_cnt_ofdm++; 3031 stats->evm += phy_ppdu->ofdm.evm_min; 3032 } 3033 } else { 3034 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg); 3035 stats->pkt_cnt_non_legacy++; 3036 stats->evm += phy_ppdu->ofdm.evm_min; 3037 } 3038 } 3039 3040 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats) 3041 { 3042 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck && 3043 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm) 3044 return ewma_rssi_read(&stats->non_legacy_rssi_avg); 3045 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck && 3046 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy) 3047 return ewma_rssi_read(&stats->ofdm_rssi_avg); 3048 else 3049 return ewma_rssi_read(&stats->cck_rssi_avg); 3050 } 3051 3052 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats) 3053 { 3054 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm); 3055 } 3056 3057 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 3058 struct rtw89_rx_phy_ppdu *phy_ppdu) 3059 { 3060 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3061 struct rtw89_hal *hal = &rtwdev->hal; 3062 3063 if (!hal->ant_diversity || hal->ant_diversity_fixed) 3064 return; 3065 3066 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats); 3067 3068 if (!antdiv->get_stats) 3069 return; 3070 3071 if (hal->antenna_rx == RF_A) 3072 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats); 3073 else if (hal->antenna_rx == RF_B) 3074 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats); 3075 } 3076 3077 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev) 3078 { 3079 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN, 3080 0x0, RTW89_PHY_0); 3081 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL, 3082 0x0, RTW89_PHY_0); 3083 3084 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND, 3085 0x0, RTW89_PHY_0); 3086 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT, 3087 0x0, RTW89_PHY_0); 3088 3089 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN, 3090 0x0, RTW89_PHY_0); 3091 3092 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING, 3093 0x0100, RTW89_PHY_0); 3094 3095 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX, 3096 0x1, RTW89_PHY_0); 3097 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL, 3098 0x0, RTW89_PHY_0); 3099 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G, 3100 0x0, RTW89_PHY_0); 3101 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G, 3102 0x0, RTW89_PHY_0); 3103 } 3104 3105 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev) 3106 { 3107 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3108 3109 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 3110 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats); 3111 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats); 3112 } 3113 3114 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev) 3115 { 3116 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 3117 struct rtw89_hal *hal = &rtwdev->hal; 3118 3119 if (!hal->ant_diversity) 3120 return; 3121 3122 antdiv->get_stats = false; 3123 antdiv->rssi_pre = 0; 3124 rtw89_phy_antdiv_sts_reset(rtwdev); 3125 rtw89_phy_antdiv_reg_init(rtwdev); 3126 } 3127 3128 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 3129 { 3130 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3131 int i; 3132 u8 th; 3133 3134 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 3135 th = rtw89_chip_get_thermal(rtwdev, i); 3136 if (th) 3137 ewma_thermal_add(&phystat->avg_thermal[i], th); 3138 3139 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 3140 "path(%d) thermal cur=%u avg=%ld", i, th, 3141 ewma_thermal_read(&phystat->avg_thermal[i])); 3142 } 3143 } 3144 3145 struct rtw89_phy_iter_rssi_data { 3146 struct rtw89_dev *rtwdev; 3147 struct rtw89_phy_ch_info *ch_info; 3148 bool rssi_changed; 3149 }; 3150 3151 static void rtw89_phy_stat_rssi_update_iter(void *data, 3152 struct ieee80211_sta *sta) 3153 { 3154 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3155 struct rtw89_phy_iter_rssi_data *rssi_data = 3156 (struct rtw89_phy_iter_rssi_data *)data; 3157 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 3158 unsigned long rssi_curr; 3159 3160 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 3161 3162 if (rssi_curr < ch_info->rssi_min) { 3163 ch_info->rssi_min = rssi_curr; 3164 ch_info->rssi_min_macid = rtwsta->mac_id; 3165 } 3166 3167 if (rtwsta->prev_rssi == 0) { 3168 rtwsta->prev_rssi = rssi_curr; 3169 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 3170 rtwsta->prev_rssi = rssi_curr; 3171 rssi_data->rssi_changed = true; 3172 } 3173 } 3174 3175 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 3176 { 3177 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 3178 3179 rssi_data.rtwdev = rtwdev; 3180 rssi_data.ch_info = &rtwdev->ch_info; 3181 rssi_data.ch_info->rssi_min = U8_MAX; 3182 ieee80211_iterate_stations_atomic(rtwdev->hw, 3183 rtw89_phy_stat_rssi_update_iter, 3184 &rssi_data); 3185 if (rssi_data.rssi_changed) 3186 rtw89_btc_ntfy_wl_sta(rtwdev); 3187 } 3188 3189 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 3190 { 3191 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3192 int i; 3193 3194 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 3195 ewma_thermal_init(&phystat->avg_thermal[i]); 3196 3197 rtw89_phy_stat_thermal_update(rtwdev); 3198 3199 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3200 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 3201 } 3202 3203 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 3204 { 3205 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 3206 3207 rtw89_phy_stat_thermal_update(rtwdev); 3208 rtw89_phy_stat_rssi_update(rtwdev); 3209 3210 phystat->last_pkt_stat = phystat->cur_pkt_stat; 3211 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 3212 } 3213 3214 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 3215 { 3216 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3217 3218 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3219 } 3220 3221 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 3222 { 3223 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3224 3225 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 3226 } 3227 3228 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 3229 { 3230 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3231 3232 env->ccx_manual_ctrl = false; 3233 env->ccx_ongoing = false; 3234 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3235 env->ccx_period = 0; 3236 env->ccx_unit_idx = RTW89_CCX_32_US; 3237 3238 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 3239 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 3240 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3241 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 3242 RTW89_CCX_EDCCA_BW20_0); 3243 } 3244 3245 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 3246 u16 score) 3247 { 3248 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3249 u32 numer = 0; 3250 u16 ret = 0; 3251 3252 numer = report * score + (env->ccx_period >> 1); 3253 if (env->ccx_period) 3254 ret = numer / env->ccx_period; 3255 3256 return ret >= score ? score - 1 : ret; 3257 } 3258 3259 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 3260 u16 time_ms, u32 *period, 3261 u32 *unit_idx) 3262 { 3263 u32 idx; 3264 u8 quotient; 3265 3266 if (time_ms >= CCX_MAX_PERIOD) 3267 time_ms = CCX_MAX_PERIOD; 3268 3269 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 3270 3271 if (quotient < 4) 3272 idx = RTW89_CCX_4_US; 3273 else if (quotient < 8) 3274 idx = RTW89_CCX_8_US; 3275 else if (quotient < 16) 3276 idx = RTW89_CCX_16_US; 3277 else 3278 idx = RTW89_CCX_32_US; 3279 3280 *unit_idx = idx; 3281 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 3282 3283 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3284 "[Trigger Time] period:%d, unit_idx:%d\n", 3285 *period, *unit_idx); 3286 } 3287 3288 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 3289 { 3290 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3291 3292 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3293 "lv:(%d)->(0)\n", env->ccx_rac_lv); 3294 3295 env->ccx_ongoing = false; 3296 env->ccx_rac_lv = RTW89_RAC_RELEASE; 3297 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3298 } 3299 3300 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 3301 struct rtw89_ccx_para_info *para) 3302 { 3303 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3304 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 3305 u8 i = 0; 3306 u16 *ifs_th_l = env->ifs_clm_th_l; 3307 u16 *ifs_th_h = env->ifs_clm_th_h; 3308 u32 ifs_th0_us = 0, ifs_th_times = 0; 3309 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 3310 3311 if (!is_update) 3312 goto ifs_update_finished; 3313 3314 switch (para->ifs_clm_app) { 3315 case RTW89_IFS_CLM_INIT: 3316 case RTW89_IFS_CLM_BACKGROUND: 3317 case RTW89_IFS_CLM_ACS: 3318 case RTW89_IFS_CLM_DBG: 3319 case RTW89_IFS_CLM_DIG: 3320 case RTW89_IFS_CLM_TDMA_DIG: 3321 ifs_th0_us = IFS_CLM_TH0_UPPER; 3322 ifs_th_times = IFS_CLM_TH_MUL; 3323 break; 3324 case RTW89_IFS_CLM_DBG_MANUAL: 3325 ifs_th0_us = para->ifs_clm_manual_th0; 3326 ifs_th_times = para->ifs_clm_manual_th_times; 3327 break; 3328 default: 3329 break; 3330 } 3331 3332 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 3333 * low[i] = high[i-1] + 1 3334 * high[i] = high[i-1] * ifs_th_times 3335 */ 3336 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 3337 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 3338 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 3339 ifs_th0_us); 3340 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 3341 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 3342 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 3343 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 3344 } 3345 3346 ifs_update_finished: 3347 if (!is_update) 3348 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3349 "No need to update IFS_TH\n"); 3350 3351 return is_update; 3352 } 3353 3354 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 3355 { 3356 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3357 u8 i = 0; 3358 3359 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 3360 env->ifs_clm_th_l[0]); 3361 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 3362 env->ifs_clm_th_l[1]); 3363 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 3364 env->ifs_clm_th_l[2]); 3365 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 3366 env->ifs_clm_th_l[3]); 3367 3368 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 3369 env->ifs_clm_th_h[0]); 3370 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 3371 env->ifs_clm_th_h[1]); 3372 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 3373 env->ifs_clm_th_h[2]); 3374 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 3375 env->ifs_clm_th_h[3]); 3376 3377 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3378 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3379 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 3380 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 3381 } 3382 3383 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 3384 { 3385 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3386 struct rtw89_ccx_para_info para = {0}; 3387 3388 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3389 env->ifs_clm_mntr_time = 0; 3390 3391 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 3392 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 3393 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3394 3395 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 3396 true); 3397 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 3398 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 3399 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 3400 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 3401 } 3402 3403 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 3404 enum rtw89_env_racing_lv level) 3405 { 3406 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3407 int ret = 0; 3408 3409 if (level >= RTW89_RAC_MAX_NUM) { 3410 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3411 "[WARNING] Wrong LV=%d\n", level); 3412 return -EINVAL; 3413 } 3414 3415 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3416 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 3417 env->ccx_rac_lv, level); 3418 3419 if (env->ccx_ongoing) { 3420 if (level <= env->ccx_rac_lv) 3421 ret = -EINVAL; 3422 else 3423 env->ccx_ongoing = false; 3424 } 3425 3426 if (ret == 0) 3427 env->ccx_rac_lv = level; 3428 3429 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 3430 !ret); 3431 3432 return ret; 3433 } 3434 3435 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 3436 { 3437 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3438 3439 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 3440 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 3441 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 3442 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 3443 3444 env->ccx_ongoing = true; 3445 } 3446 3447 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 3448 { 3449 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3450 u8 i = 0; 3451 u32 res = 0; 3452 3453 env->ifs_clm_tx_ratio = 3454 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 3455 env->ifs_clm_edcca_excl_cca_ratio = 3456 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 3457 PERCENT); 3458 env->ifs_clm_cck_fa_ratio = 3459 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 3460 env->ifs_clm_ofdm_fa_ratio = 3461 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 3462 env->ifs_clm_cck_cca_excl_fa_ratio = 3463 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 3464 PERCENT); 3465 env->ifs_clm_ofdm_cca_excl_fa_ratio = 3466 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 3467 PERCENT); 3468 env->ifs_clm_cck_fa_permil = 3469 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 3470 env->ifs_clm_ofdm_fa_permil = 3471 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 3472 3473 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 3474 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 3475 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 3476 } else { 3477 env->ifs_clm_ifs_avg[i] = 3478 rtw89_phy_ccx_idx_to_us(rtwdev, 3479 env->ifs_clm_avg[i]); 3480 } 3481 3482 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 3483 res += env->ifs_clm_his[i] >> 1; 3484 if (env->ifs_clm_his[i]) 3485 res /= env->ifs_clm_his[i]; 3486 else 3487 res = 0; 3488 env->ifs_clm_cca_avg[i] = res; 3489 } 3490 3491 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3492 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3493 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 3494 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3495 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 3496 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 3497 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3498 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 3499 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 3500 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3501 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 3502 env->ifs_clm_cck_cca_excl_fa_ratio, 3503 env->ifs_clm_ofdm_cca_excl_fa_ratio); 3504 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3505 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 3506 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3507 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 3508 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 3509 env->ifs_clm_cca_avg[i]); 3510 } 3511 3512 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 3513 { 3514 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3515 u8 i = 0; 3516 3517 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 3518 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3519 "Get IFS_CLM report Fail\n"); 3520 return false; 3521 } 3522 3523 env->ifs_clm_tx = 3524 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3525 B_IFS_CLM_TX_CNT_MSK); 3526 env->ifs_clm_edcca_excl_cca = 3527 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 3528 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 3529 env->ifs_clm_cckcca_excl_fa = 3530 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3531 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 3532 env->ifs_clm_ofdmcca_excl_fa = 3533 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 3534 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 3535 env->ifs_clm_cckfa = 3536 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3537 B_IFS_CLM_CCK_FA_MSK); 3538 env->ifs_clm_ofdmfa = 3539 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 3540 B_IFS_CLM_OFDM_FA_MSK); 3541 3542 env->ifs_clm_his[0] = 3543 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 3544 env->ifs_clm_his[1] = 3545 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 3546 env->ifs_clm_his[2] = 3547 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 3548 env->ifs_clm_his[3] = 3549 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 3550 3551 env->ifs_clm_avg[0] = 3552 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 3553 env->ifs_clm_avg[1] = 3554 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 3555 env->ifs_clm_avg[2] = 3556 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 3557 env->ifs_clm_avg[3] = 3558 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 3559 3560 env->ifs_clm_cca[0] = 3561 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 3562 env->ifs_clm_cca[1] = 3563 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 3564 env->ifs_clm_cca[2] = 3565 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 3566 env->ifs_clm_cca[3] = 3567 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 3568 3569 env->ifs_clm_total_ifs = 3570 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 3571 3572 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 3573 env->ifs_clm_total_ifs); 3574 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3575 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3576 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 3577 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3578 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 3579 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 3580 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3581 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 3582 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 3583 3584 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 3585 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3586 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3587 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 3588 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 3589 3590 rtw89_phy_ifs_clm_get_utility(rtwdev); 3591 3592 return true; 3593 } 3594 3595 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 3596 struct rtw89_ccx_para_info *para) 3597 { 3598 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3599 u32 period = 0; 3600 u32 unit_idx = 0; 3601 3602 if (para->mntr_time == 0) { 3603 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3604 "[WARN] MNTR_TIME is 0\n"); 3605 return -EINVAL; 3606 } 3607 3608 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 3609 return -EINVAL; 3610 3611 if (para->mntr_time != env->ifs_clm_mntr_time) { 3612 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 3613 &period, &unit_idx); 3614 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3615 B_IFS_CLM_PERIOD_MSK, period); 3616 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3617 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 3618 3619 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3620 "Update IFS-CLM time ((%d)) -> ((%d))\n", 3621 env->ifs_clm_mntr_time, para->mntr_time); 3622 3623 env->ifs_clm_mntr_time = para->mntr_time; 3624 env->ccx_period = (u16)period; 3625 env->ccx_unit_idx = (u8)unit_idx; 3626 } 3627 3628 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3629 env->ifs_clm_app = para->ifs_clm_app; 3630 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3631 } 3632 3633 return 0; 3634 } 3635 3636 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3637 { 3638 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3639 struct rtw89_ccx_para_info para = {0}; 3640 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3641 3642 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3643 if (env->ccx_manual_ctrl) { 3644 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3645 "CCX in manual ctrl\n"); 3646 return; 3647 } 3648 3649 /* only ifs_clm for now */ 3650 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3651 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3652 3653 rtw89_phy_ccx_racing_release(rtwdev); 3654 para.mntr_time = 1900; 3655 para.rac_lv = RTW89_RAC_LV_1; 3656 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3657 3658 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3659 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3660 if (chk_result) 3661 rtw89_phy_ccx_trigger(rtwdev); 3662 3663 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3664 "get_result=0x%x, chk_result:0x%x\n", 3665 env->ccx_watchdog_result, chk_result); 3666 } 3667 3668 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3669 { 3670 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 3671 *ie_page == RTW89_RSVD_9) 3672 return false; 3673 else if (*ie_page > RTW89_RSVD_9) 3674 *ie_page -= 1; 3675 3676 return true; 3677 } 3678 3679 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3680 { 3681 static const u8 ie_page_shift = 2; 3682 3683 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3684 } 3685 3686 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3687 enum rtw89_phy_status_bitmap ie_page) 3688 { 3689 u32 addr; 3690 3691 if (!rtw89_physts_ie_page_valid(&ie_page)) 3692 return 0; 3693 3694 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3695 3696 return rtw89_phy_read32(rtwdev, addr); 3697 } 3698 3699 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3700 enum rtw89_phy_status_bitmap ie_page, 3701 u32 val) 3702 { 3703 const struct rtw89_chip_info *chip = rtwdev->chip; 3704 u32 addr; 3705 3706 if (!rtw89_physts_ie_page_valid(&ie_page)) 3707 return; 3708 3709 if (chip->chip_id == RTL8852A) 3710 val &= B_PHY_STS_BITMAP_MSK_52A; 3711 3712 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3713 rtw89_phy_write32(rtwdev, addr, val); 3714 } 3715 3716 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3717 enum rtw89_phy_status_bitmap bitmap, 3718 enum rtw89_phy_status_ie_type ie, 3719 bool enable) 3720 { 3721 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3722 3723 if (enable) 3724 val |= BIT(ie); 3725 else 3726 val &= ~BIT(ie); 3727 3728 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3729 } 3730 3731 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3732 bool enable, 3733 enum rtw89_phy_idx phy_idx) 3734 { 3735 if (enable) { 3736 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3737 B_STS_DIS_TRIG_BY_FAIL); 3738 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3739 B_STS_DIS_TRIG_BY_BRK); 3740 } else { 3741 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3742 B_STS_DIS_TRIG_BY_FAIL); 3743 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3744 B_STS_DIS_TRIG_BY_BRK); 3745 } 3746 } 3747 3748 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3749 { 3750 u8 i; 3751 3752 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3753 3754 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3755 if (i >= RTW89_CCK_PKT) 3756 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3757 RTW89_PHYSTS_IE09_FTR_0, 3758 true); 3759 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3760 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3761 continue; 3762 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3763 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3764 true); 3765 } 3766 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3767 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3768 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3769 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3770 3771 /* force IE01 for channel index, only channel field is valid */ 3772 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3773 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3774 } 3775 3776 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3777 { 3778 const struct rtw89_chip_info *chip = rtwdev->chip; 3779 struct rtw89_dig_info *dig = &rtwdev->dig; 3780 const struct rtw89_phy_dig_gain_cfg *cfg; 3781 const char *msg; 3782 u8 i; 3783 s8 gain_base; 3784 s8 *gain_arr; 3785 u32 tmp; 3786 3787 switch (type) { 3788 case RTW89_DIG_GAIN_LNA_G: 3789 gain_arr = dig->lna_gain_g; 3790 gain_base = LNA0_GAIN; 3791 cfg = chip->dig_table->cfg_lna_g; 3792 msg = "lna_gain_g"; 3793 break; 3794 case RTW89_DIG_GAIN_TIA_G: 3795 gain_arr = dig->tia_gain_g; 3796 gain_base = TIA0_GAIN_G; 3797 cfg = chip->dig_table->cfg_tia_g; 3798 msg = "tia_gain_g"; 3799 break; 3800 case RTW89_DIG_GAIN_LNA_A: 3801 gain_arr = dig->lna_gain_a; 3802 gain_base = LNA0_GAIN; 3803 cfg = chip->dig_table->cfg_lna_a; 3804 msg = "lna_gain_a"; 3805 break; 3806 case RTW89_DIG_GAIN_TIA_A: 3807 gain_arr = dig->tia_gain_a; 3808 gain_base = TIA0_GAIN_A; 3809 cfg = chip->dig_table->cfg_tia_a; 3810 msg = "tia_gain_a"; 3811 break; 3812 default: 3813 return; 3814 } 3815 3816 for (i = 0; i < cfg->size; i++) { 3817 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3818 cfg->table[i].mask); 3819 tmp >>= DIG_GAIN_SHIFT; 3820 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3821 gain_base += DIG_GAIN; 3822 3823 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3824 msg, i, gain_arr[i]); 3825 } 3826 } 3827 3828 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3829 { 3830 struct rtw89_dig_info *dig = &rtwdev->dig; 3831 u32 tmp; 3832 u8 i; 3833 3834 if (!rtwdev->hal.support_igi) 3835 return; 3836 3837 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3838 B_PATH0_IB_PKPW_MSK); 3839 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3840 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3841 B_PATH0_IB_PBK_MSK); 3842 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3843 dig->ib_pkpwr, dig->ib_pbk); 3844 3845 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3846 rtw89_phy_dig_read_gain_table(rtwdev, i); 3847 } 3848 3849 static const u8 rssi_nolink = 22; 3850 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3851 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3852 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3853 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3854 3855 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3856 { 3857 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3858 struct rtw89_dig_info *dig = &rtwdev->dig; 3859 bool is_linked = rtwdev->total_sta_assoc > 0; 3860 3861 if (is_linked) { 3862 dig->igi_rssi = ch_info->rssi_min >> 1; 3863 } else { 3864 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3865 dig->igi_rssi = rssi_nolink; 3866 } 3867 } 3868 3869 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3870 { 3871 struct rtw89_dig_info *dig = &rtwdev->dig; 3872 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3873 bool is_linked = rtwdev->total_sta_assoc > 0; 3874 const u16 *fa_th_src = NULL; 3875 3876 switch (chan->band_type) { 3877 case RTW89_BAND_2G: 3878 dig->lna_gain = dig->lna_gain_g; 3879 dig->tia_gain = dig->tia_gain_g; 3880 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3881 dig->force_gaincode_idx_en = false; 3882 dig->dyn_pd_th_en = true; 3883 break; 3884 case RTW89_BAND_5G: 3885 default: 3886 dig->lna_gain = dig->lna_gain_a; 3887 dig->tia_gain = dig->tia_gain_a; 3888 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3889 dig->force_gaincode_idx_en = true; 3890 dig->dyn_pd_th_en = true; 3891 break; 3892 } 3893 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3894 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3895 } 3896 3897 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3898 static const u8 igi_max_performance_mode = 0x5a; 3899 static const u8 dynamic_pd_threshold_max; 3900 3901 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3902 { 3903 struct rtw89_dig_info *dig = &rtwdev->dig; 3904 3905 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3906 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3907 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3908 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3909 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3910 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3911 3912 dig->dyn_igi_max = igi_max_performance_mode; 3913 dig->dyn_igi_min = dynamic_igi_min; 3914 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3915 dig->pd_low_th_ofst = pd_low_th_offset; 3916 dig->is_linked_pre = false; 3917 } 3918 3919 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3920 { 3921 rtw89_phy_dig_update_gain_para(rtwdev); 3922 rtw89_phy_dig_reset(rtwdev); 3923 } 3924 3925 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3926 { 3927 struct rtw89_dig_info *dig = &rtwdev->dig; 3928 u8 lna_idx; 3929 3930 if (rssi < dig->igi_rssi_th[0]) 3931 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3932 else if (rssi < dig->igi_rssi_th[1]) 3933 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3934 else if (rssi < dig->igi_rssi_th[2]) 3935 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3936 else if (rssi < dig->igi_rssi_th[3]) 3937 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3938 else if (rssi < dig->igi_rssi_th[4]) 3939 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3940 else 3941 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3942 3943 return lna_idx; 3944 } 3945 3946 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3947 { 3948 struct rtw89_dig_info *dig = &rtwdev->dig; 3949 u8 tia_idx; 3950 3951 if (rssi < dig->igi_rssi_th[0]) 3952 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3953 else 3954 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3955 3956 return tia_idx; 3957 } 3958 3959 #define IB_PBK_BASE 110 3960 #define WB_RSSI_BASE 10 3961 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3962 struct rtw89_agc_gaincode_set *set) 3963 { 3964 struct rtw89_dig_info *dig = &rtwdev->dig; 3965 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3966 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3967 s32 wb_rssi = rssi + lna_gain + tia_gain; 3968 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3969 u8 rxb_idx; 3970 3971 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3972 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3973 3974 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3975 wb_rssi, rxb_idx_tmp); 3976 3977 return rxb_idx; 3978 } 3979 3980 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3981 struct rtw89_agc_gaincode_set *set) 3982 { 3983 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3984 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3985 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3986 3987 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3988 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3989 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3990 } 3991 3992 #define IGI_OFFSET_MAX 25 3993 #define IGI_OFFSET_MUL 2 3994 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3995 { 3996 struct rtw89_dig_info *dig = &rtwdev->dig; 3997 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3998 enum rtw89_dig_noisy_level noisy_lv; 3999 u8 igi_offset = dig->fa_rssi_ofst; 4000 u16 fa_ratio = 0; 4001 4002 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 4003 4004 if (fa_ratio < dig->fa_th[0]) 4005 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 4006 else if (fa_ratio < dig->fa_th[1]) 4007 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 4008 else if (fa_ratio < dig->fa_th[2]) 4009 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 4010 else if (fa_ratio < dig->fa_th[3]) 4011 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 4012 else 4013 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 4014 4015 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 4016 igi_offset = 0; 4017 else 4018 igi_offset += noisy_lv * IGI_OFFSET_MUL; 4019 4020 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 4021 dig->fa_rssi_ofst = igi_offset; 4022 4023 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4024 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 4025 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 4026 4027 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4028 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 4029 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 4030 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 4031 noisy_lv, igi_offset); 4032 } 4033 4034 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 4035 { 4036 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4037 4038 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 4039 dig_regs->p0_lna_init.mask, lna_idx); 4040 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 4041 dig_regs->p1_lna_init.mask, lna_idx); 4042 } 4043 4044 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 4045 { 4046 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4047 4048 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 4049 dig_regs->p0_tia_init.mask, tia_idx); 4050 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 4051 dig_regs->p1_tia_init.mask, tia_idx); 4052 } 4053 4054 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 4055 { 4056 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4057 4058 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 4059 dig_regs->p0_rxb_init.mask, rxb_idx); 4060 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 4061 dig_regs->p1_rxb_init.mask, rxb_idx); 4062 } 4063 4064 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 4065 const struct rtw89_agc_gaincode_set set) 4066 { 4067 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 4068 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 4069 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 4070 4071 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 4072 set.lna_idx, set.tia_idx, set.rxb_idx); 4073 } 4074 4075 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 4076 bool enable) 4077 { 4078 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4079 4080 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 4081 dig_regs->p0_p20_pagcugc_en.mask, enable); 4082 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 4083 dig_regs->p0_s20_pagcugc_en.mask, enable); 4084 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 4085 dig_regs->p1_p20_pagcugc_en.mask, enable); 4086 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 4087 dig_regs->p1_s20_pagcugc_en.mask, enable); 4088 4089 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 4090 } 4091 4092 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 4093 { 4094 struct rtw89_dig_info *dig = &rtwdev->dig; 4095 4096 if (!rtwdev->hal.support_igi) 4097 return; 4098 4099 if (dig->force_gaincode_idx_en) { 4100 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 4101 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4102 "Force gaincode index enabled.\n"); 4103 } else { 4104 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 4105 &dig->cur_gaincode); 4106 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 4107 } 4108 } 4109 4110 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 4111 bool enable) 4112 { 4113 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 4114 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 4115 enum rtw89_bandwidth cbw = chan->band_width; 4116 struct rtw89_dig_info *dig = &rtwdev->dig; 4117 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 4118 u8 ofdm_cca_th; 4119 s8 cck_cca_th; 4120 u32 pd_val = 0; 4121 4122 under_region += PD_TH_SB_FLTR_CMP_VAL; 4123 4124 switch (cbw) { 4125 case RTW89_CHANNEL_WIDTH_40: 4126 under_region += PD_TH_BW40_CMP_VAL; 4127 break; 4128 case RTW89_CHANNEL_WIDTH_80: 4129 under_region += PD_TH_BW80_CMP_VAL; 4130 break; 4131 case RTW89_CHANNEL_WIDTH_160: 4132 under_region += PD_TH_BW160_CMP_VAL; 4133 break; 4134 case RTW89_CHANNEL_WIDTH_20: 4135 fallthrough; 4136 default: 4137 under_region += PD_TH_BW20_CMP_VAL; 4138 break; 4139 } 4140 4141 dig->dyn_pd_th_max = dig->igi_rssi; 4142 4143 final_rssi = min_t(u8, rssi, dig->igi_rssi); 4144 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 4145 PD_TH_MAX_RSSI + under_region); 4146 4147 if (enable) { 4148 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 4149 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4150 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 4151 final_rssi, ofdm_cca_th, under_region, pd_val); 4152 } else { 4153 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4154 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 4155 } 4156 4157 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 4158 dig_regs->pd_lower_bound_mask, pd_val); 4159 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 4160 dig_regs->pd_spatial_reuse_en, enable); 4161 4162 if (!rtwdev->hal.support_cckpd) 4163 return; 4164 4165 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 4166 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 4167 4168 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4169 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 4170 final_rssi, cck_cca_th, under_region, pd_val); 4171 4172 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 4173 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 4174 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 4175 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 4176 } 4177 4178 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 4179 { 4180 struct rtw89_dig_info *dig = &rtwdev->dig; 4181 4182 dig->bypass_dig = false; 4183 rtw89_phy_dig_para_reset(rtwdev); 4184 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 4185 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 4186 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4187 rtw89_phy_dig_update_para(rtwdev); 4188 } 4189 4190 #define IGI_RSSI_MIN 10 4191 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 4192 { 4193 struct rtw89_dig_info *dig = &rtwdev->dig; 4194 bool is_linked = rtwdev->total_sta_assoc > 0; 4195 4196 if (unlikely(dig->bypass_dig)) { 4197 dig->bypass_dig = false; 4198 return; 4199 } 4200 4201 if (!dig->is_linked_pre && is_linked) { 4202 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 4203 rtw89_phy_dig_update_para(rtwdev); 4204 } else if (dig->is_linked_pre && !is_linked) { 4205 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 4206 rtw89_phy_dig_update_para(rtwdev); 4207 } 4208 dig->is_linked_pre = is_linked; 4209 4210 rtw89_phy_dig_igi_offset_by_env(rtwdev); 4211 rtw89_phy_dig_update_rssi_info(rtwdev); 4212 4213 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 4214 dig->igi_rssi - IGI_RSSI_MIN : 0; 4215 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 4216 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 4217 4218 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 4219 dig->dyn_igi_max); 4220 4221 rtw89_debug(rtwdev, RTW89_DBG_DIG, 4222 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 4223 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 4224 dig->igi_fa_rssi); 4225 4226 rtw89_phy_dig_config_igi(rtwdev); 4227 4228 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 4229 4230 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 4231 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 4232 else 4233 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 4234 } 4235 4236 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 4237 { 4238 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4239 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4240 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4241 struct rtw89_hal *hal = &rtwdev->hal; 4242 bool *done = data; 4243 u8 rssi_a, rssi_b; 4244 u32 candidate; 4245 4246 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 4247 return; 4248 4249 if (*done) 4250 return; 4251 4252 *done = true; 4253 4254 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 4255 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 4256 4257 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 4258 candidate = RF_A; 4259 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 4260 candidate = RF_B; 4261 else 4262 return; 4263 4264 if (hal->antenna_tx == candidate) 4265 return; 4266 4267 hal->antenna_tx = candidate; 4268 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 4269 4270 if (hal->antenna_tx == RF_A) { 4271 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 4272 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 4273 } else if (hal->antenna_tx == RF_B) { 4274 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 4275 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 4276 } 4277 } 4278 4279 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 4280 { 4281 struct rtw89_hal *hal = &rtwdev->hal; 4282 bool done = false; 4283 4284 if (!hal->tx_path_diversity) 4285 return; 4286 4287 ieee80211_iterate_stations_atomic(rtwdev->hw, 4288 rtw89_phy_tx_path_div_sta_iter, 4289 &done); 4290 } 4291 4292 #define ANTDIV_MAIN 0 4293 #define ANTDIV_AUX 1 4294 4295 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev) 4296 { 4297 struct rtw89_hal *hal = &rtwdev->hal; 4298 u8 default_ant, optional_ant; 4299 4300 if (!hal->ant_diversity || hal->antenna_tx == 0) 4301 return; 4302 4303 if (hal->antenna_tx == RF_B) { 4304 default_ant = ANTDIV_AUX; 4305 optional_ant = ANTDIV_MAIN; 4306 } else { 4307 default_ant = ANTDIV_MAIN; 4308 optional_ant = ANTDIV_AUX; 4309 } 4310 4311 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL, 4312 default_ant, RTW89_PHY_0); 4313 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI, 4314 default_ant, RTW89_PHY_0); 4315 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT, 4316 optional_ant, RTW89_PHY_0); 4317 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI, 4318 default_ant, RTW89_PHY_0); 4319 } 4320 4321 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev) 4322 { 4323 struct rtw89_hal *hal = &rtwdev->hal; 4324 4325 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A; 4326 hal->antenna_tx = hal->antenna_rx; 4327 } 4328 4329 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev) 4330 { 4331 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4332 struct rtw89_hal *hal = &rtwdev->hal; 4333 bool no_change = false; 4334 u8 main_rssi, aux_rssi; 4335 u8 main_evm, aux_evm; 4336 u32 candidate; 4337 4338 antdiv->get_stats = false; 4339 antdiv->training_count = 0; 4340 4341 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats); 4342 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats); 4343 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats); 4344 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats); 4345 4346 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH) 4347 candidate = RF_A; 4348 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH) 4349 candidate = RF_B; 4350 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 4351 candidate = RF_A; 4352 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 4353 candidate = RF_B; 4354 else 4355 no_change = true; 4356 4357 if (no_change) { 4358 /* swap back from training antenna to original */ 4359 rtw89_phy_swap_hal_antenna(rtwdev); 4360 return; 4361 } 4362 4363 hal->antenna_tx = candidate; 4364 hal->antenna_rx = candidate; 4365 } 4366 4367 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev) 4368 { 4369 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4370 u64 state_period; 4371 4372 if (antdiv->training_count % 2 == 0) { 4373 if (antdiv->training_count == 0) 4374 rtw89_phy_antdiv_sts_reset(rtwdev); 4375 4376 antdiv->get_stats = true; 4377 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL); 4378 } else { 4379 antdiv->get_stats = false; 4380 state_period = msecs_to_jiffies(ANTDIV_DELAY); 4381 4382 rtw89_phy_swap_hal_antenna(rtwdev); 4383 rtw89_phy_antdiv_set_ant(rtwdev); 4384 } 4385 4386 antdiv->training_count++; 4387 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 4388 state_period); 4389 } 4390 4391 void rtw89_phy_antdiv_work(struct work_struct *work) 4392 { 4393 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4394 antdiv_work.work); 4395 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4396 4397 mutex_lock(&rtwdev->mutex); 4398 4399 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) { 4400 rtw89_phy_antdiv_training_state(rtwdev); 4401 } else { 4402 rtw89_phy_antdiv_decision_state(rtwdev); 4403 rtw89_phy_antdiv_set_ant(rtwdev); 4404 } 4405 4406 mutex_unlock(&rtwdev->mutex); 4407 } 4408 4409 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev) 4410 { 4411 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4412 struct rtw89_hal *hal = &rtwdev->hal; 4413 u8 rssi, rssi_pre; 4414 4415 if (!hal->ant_diversity || hal->ant_diversity_fixed) 4416 return; 4417 4418 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats); 4419 rssi_pre = antdiv->rssi_pre; 4420 antdiv->rssi_pre = rssi; 4421 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 4422 4423 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH) 4424 return; 4425 4426 antdiv->training_count = 0; 4427 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0); 4428 } 4429 4430 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 4431 { 4432 rtw89_phy_ccx_top_setting_init(rtwdev); 4433 rtw89_phy_ifs_clm_setting_init(rtwdev); 4434 } 4435 4436 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 4437 { 4438 const struct rtw89_chip_info *chip = rtwdev->chip; 4439 4440 rtw89_phy_stat_init(rtwdev); 4441 4442 rtw89_chip_bb_sethw(rtwdev); 4443 4444 rtw89_phy_env_monitor_init(rtwdev); 4445 rtw89_physts_parsing_init(rtwdev); 4446 rtw89_phy_dig_init(rtwdev); 4447 rtw89_phy_cfo_init(rtwdev); 4448 rtw89_phy_ul_tb_info_init(rtwdev); 4449 rtw89_phy_antdiv_init(rtwdev); 4450 rtw89_chip_rfe_gpio(rtwdev); 4451 rtw89_phy_antdiv_set_ant(rtwdev); 4452 4453 rtw89_phy_init_rf_nctl(rtwdev); 4454 rtw89_chip_rfk_init(rtwdev); 4455 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 4456 rtw89_chip_set_txpwr_ctrl(rtwdev); 4457 rtw89_chip_power_trim(rtwdev); 4458 rtw89_chip_cfg_txrx_path(rtwdev); 4459 } 4460 4461 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 4462 { 4463 const struct rtw89_chip_info *chip = rtwdev->chip; 4464 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 4465 u8 bss_color; 4466 4467 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4468 return; 4469 4470 bss_color = vif->bss_conf.he_bss_color.color; 4471 4472 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_VLD0, 0x1, 4473 phy_idx); 4474 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 4475 bss_color, phy_idx); 4476 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 4477 vif->cfg.aid, phy_idx); 4478 } 4479 4480 static void 4481 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4482 { 4483 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 4484 } 4485 4486 static void 4487 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4488 { 4489 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 4490 } 4491 4492 static void 4493 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4494 { 4495 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 4496 } 4497 4498 static void 4499 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4500 { 4501 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 4502 } 4503 4504 static void 4505 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 4506 { 4507 udelay(def->data); 4508 } 4509 4510 static void 4511 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 4512 [RTW89_RFK_F_WRF] = _rfk_write_rf, 4513 [RTW89_RFK_F_WM] = _rfk_write32_mask, 4514 [RTW89_RFK_F_WS] = _rfk_write32_set, 4515 [RTW89_RFK_F_WC] = _rfk_write32_clr, 4516 [RTW89_RFK_F_DELAY] = _rfk_delay, 4517 }; 4518 4519 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 4520 4521 void 4522 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 4523 { 4524 const struct rtw89_reg5_def *p = tbl->defs; 4525 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 4526 4527 for (; p < end; p++) 4528 _rfk_handler[p->flag](rtwdev, p); 4529 } 4530 EXPORT_SYMBOL(rtw89_rfk_parser); 4531 4532 #define RTW89_TSSI_FAST_MODE_NUM 4 4533 4534 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 4535 {0xD934, 0xff0000}, 4536 {0xD934, 0xff000000}, 4537 {0xD938, 0xff}, 4538 {0xD934, 0xff00}, 4539 }; 4540 4541 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 4542 {0xD930, 0xff0000}, 4543 {0xD930, 0xff000000}, 4544 {0xD934, 0xff}, 4545 {0xD930, 0xff00}, 4546 }; 4547 4548 static 4549 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 4550 enum rtw89_mac_idx mac_idx, 4551 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 4552 u32 val) 4553 { 4554 const struct rtw89_reg_def *regs; 4555 u32 reg; 4556 int i; 4557 4558 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4559 regs = rtw89_tssi_fastmode_regs_flat; 4560 else 4561 regs = rtw89_tssi_fastmode_regs_level; 4562 4563 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 4564 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4565 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 4566 } 4567 } 4568 4569 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 4570 {0xD91C, 0xff000000}, 4571 {0xD920, 0xff}, 4572 {0xD920, 0xff00}, 4573 {0xD920, 0xff0000}, 4574 {0xD920, 0xff000000}, 4575 {0xD924, 0xff}, 4576 {0xD924, 0xff00}, 4577 {0xD914, 0xff000000}, 4578 {0xD918, 0xff}, 4579 {0xD918, 0xff00}, 4580 {0xD918, 0xff0000}, 4581 {0xD918, 0xff000000}, 4582 {0xD91C, 0xff}, 4583 {0xD91C, 0xff00}, 4584 {0xD91C, 0xff0000}, 4585 }; 4586 4587 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 4588 {0xD910, 0xff}, 4589 {0xD910, 0xff00}, 4590 {0xD910, 0xff0000}, 4591 {0xD910, 0xff000000}, 4592 {0xD914, 0xff}, 4593 {0xD914, 0xff00}, 4594 {0xD914, 0xff0000}, 4595 {0xD908, 0xff}, 4596 {0xD908, 0xff00}, 4597 {0xD908, 0xff0000}, 4598 {0xD908, 0xff000000}, 4599 {0xD90C, 0xff}, 4600 {0xD90C, 0xff00}, 4601 {0xD90C, 0xff0000}, 4602 {0xD90C, 0xff000000}, 4603 }; 4604 4605 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 4606 enum rtw89_mac_idx mac_idx, 4607 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 4608 { 4609 const struct rtw89_chip_info *chip = rtwdev->chip; 4610 const struct rtw89_reg_def *regs; 4611 const u32 *data; 4612 u32 reg; 4613 int i; 4614 4615 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 4616 return; 4617 4618 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 4619 regs = rtw89_tssi_bandedge_regs_flat; 4620 else 4621 regs = rtw89_tssi_bandedge_regs_level; 4622 4623 data = chip->tssi_dbw_table->data[bandedge_cfg]; 4624 4625 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 4626 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 4627 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 4628 } 4629 4630 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 4631 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 4632 4633 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 4634 data[RTW89_TSSI_SBW20]); 4635 } 4636 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 4637 4638 static 4639 const u8 rtw89_ch_base_table[16] = {1, 0xff, 4640 36, 100, 132, 149, 0xff, 4641 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 4642 #define RTW89_CH_BASE_IDX_2G 0 4643 #define RTW89_CH_BASE_IDX_5G_FIRST 2 4644 #define RTW89_CH_BASE_IDX_5G_LAST 5 4645 #define RTW89_CH_BASE_IDX_6G_FIRST 7 4646 #define RTW89_CH_BASE_IDX_6G_LAST 14 4647 4648 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4) 4649 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0) 4650 4651 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 4652 { 4653 u8 chan_idx; 4654 u8 last, first; 4655 u8 idx; 4656 4657 switch (band) { 4658 case RTW89_BAND_2G: 4659 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) | 4660 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch); 4661 return chan_idx; 4662 case RTW89_BAND_5G: 4663 first = RTW89_CH_BASE_IDX_5G_FIRST; 4664 last = RTW89_CH_BASE_IDX_5G_LAST; 4665 break; 4666 case RTW89_BAND_6G: 4667 first = RTW89_CH_BASE_IDX_6G_FIRST; 4668 last = RTW89_CH_BASE_IDX_6G_LAST; 4669 break; 4670 default: 4671 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 4672 return 0; 4673 } 4674 4675 for (idx = last; idx >= first; idx--) 4676 if (central_ch >= rtw89_ch_base_table[idx]) 4677 break; 4678 4679 if (idx < first) { 4680 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 4681 return 0; 4682 } 4683 4684 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) | 4685 FIELD_PREP(RTW89_CH_OFFSET_MASK, 4686 (central_ch - rtw89_ch_base_table[idx]) >> 1); 4687 return chan_idx; 4688 } 4689 EXPORT_SYMBOL(rtw89_encode_chan_idx); 4690 4691 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 4692 u8 *ch, enum nl80211_band *band) 4693 { 4694 u8 idx, offset; 4695 4696 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx); 4697 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx); 4698 4699 if (idx == RTW89_CH_BASE_IDX_2G) { 4700 *band = NL80211_BAND_2GHZ; 4701 *ch = offset; 4702 return; 4703 } 4704 4705 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 4706 *ch = rtw89_ch_base_table[idx] + (offset << 1); 4707 } 4708 EXPORT_SYMBOL(rtw89_decode_chan_idx); 4709 4710 #define EDCCA_DEFAULT 249 4711 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan) 4712 { 4713 u32 reg = rtwdev->chip->edcca_lvl_reg; 4714 struct rtw89_hal *hal = &rtwdev->hal; 4715 u32 val; 4716 4717 if (scan) { 4718 hal->edcca_bak = rtw89_phy_read32(rtwdev, reg); 4719 val = hal->edcca_bak; 4720 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_EDCCA_LVL_A_MSK); 4721 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_EDCCA_LVL_P_MSK); 4722 u32p_replace_bits(&val, EDCCA_DEFAULT, B_SEG0R_PPDU_LVL_MSK); 4723 rtw89_phy_write32(rtwdev, reg, val); 4724 } else { 4725 rtw89_phy_write32(rtwdev, reg, hal->edcca_bak); 4726 } 4727 } 4728