1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "sar.h" 12 #include "coex.h" 13 14 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 15 const struct rtw89_ra_report *report) 16 { 17 const struct rate_info *txrate = &report->txrate; 18 u32 bit_rate = report->bit_rate; 19 u8 mcs; 20 21 /* lower than ofdm, do not aggregate */ 22 if (bit_rate < 550) 23 return 1; 24 25 /* prevent hardware rate fallback to G mode rate */ 26 if (txrate->flags & RATE_INFO_FLAGS_MCS) 27 mcs = txrate->mcs & 0x07; 28 else if (txrate->flags & (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_HE_MCS)) 29 mcs = txrate->mcs; 30 else 31 mcs = 0; 32 33 if (mcs <= 2) 34 return 1; 35 36 /* lower than 20M vht 2ss mcs8, make it small */ 37 if (bit_rate < 1800) 38 return 1200; 39 40 /* lower than 40M vht 2ss mcs9, make it medium */ 41 if (bit_rate < 4000) 42 return 2600; 43 44 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 45 if (bit_rate < 7000) 46 return 3500; 47 48 return rtwdev->chip->max_amsdu_limit; 49 } 50 51 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 52 { 53 u64 ra_mask = 0; 54 u8 mcs_cap; 55 int i, nss; 56 57 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 58 mcs_cap = mcs_map & 0x3; 59 switch (mcs_cap) { 60 case 2: 61 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 62 break; 63 case 1: 64 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 65 break; 66 case 0: 67 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 68 break; 69 default: 70 break; 71 } 72 } 73 74 return ra_mask; 75 } 76 77 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 78 { 79 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 80 u16 mcs_map; 81 82 switch (sta->deflink.bandwidth) { 83 case IEEE80211_STA_RX_BW_160: 84 if (cap.he_cap_elem.phy_cap_info[0] & 85 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 86 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 87 else 88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 89 break; 90 default: 91 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 92 } 93 94 /* MCS11, MCS9, MCS7 */ 95 return get_mcs_ra_mask(mcs_map, 11, 2); 96 } 97 98 #define RA_FLOOR_TABLE_SIZE 7 99 #define RA_FLOOR_UP_GAP 3 100 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 101 u8 ratr_state) 102 { 103 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 104 u8 rssi_lv = 0; 105 u8 i; 106 107 rssi >>= 1; 108 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 109 if (i >= ratr_state) 110 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 111 if (rssi < rssi_lv_t[i]) { 112 rssi_lv = i; 113 break; 114 } 115 } 116 if (rssi_lv == 0) 117 return 0xffffffffffffffffULL; 118 else if (rssi_lv == 1) 119 return 0xfffffffffffffff0ULL; 120 else if (rssi_lv == 2) 121 return 0xffffffffffffefe0ULL; 122 else if (rssi_lv == 3) 123 return 0xffffffffffffcfc0ULL; 124 else if (rssi_lv == 4) 125 return 0xffffffffffff8f80ULL; 126 else if (rssi_lv >= 5) 127 return 0xffffffffffff0f00ULL; 128 129 return 0xffffffffffffffffULL; 130 } 131 132 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 133 { 134 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 135 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 136 137 if (ra_mask == 0) 138 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 139 140 return ra_mask; 141 } 142 143 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 144 { 145 struct rtw89_hal *hal = &rtwdev->hal; 146 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 147 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 148 enum nl80211_band band; 149 u64 cfg_mask; 150 151 if (!rtwsta->use_cfg_mask) 152 return -1; 153 154 switch (hal->current_band_type) { 155 case RTW89_BAND_2G: 156 band = NL80211_BAND_2GHZ; 157 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 158 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 159 break; 160 case RTW89_BAND_5G: 161 band = NL80211_BAND_5GHZ; 162 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 163 RA_MASK_OFDM_RATES); 164 break; 165 case RTW89_BAND_6G: 166 band = NL80211_BAND_6GHZ; 167 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 168 RA_MASK_OFDM_RATES); 169 break; 170 default: 171 rtw89_warn(rtwdev, "unhandled band type %d\n", hal->current_band_type); 172 return -1; 173 } 174 175 if (sta->deflink.he_cap.has_he) { 176 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 177 RA_MASK_HE_1SS_RATES); 178 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 179 RA_MASK_HE_2SS_RATES); 180 } else if (sta->deflink.vht_cap.vht_supported) { 181 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 182 RA_MASK_VHT_1SS_RATES); 183 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 184 RA_MASK_VHT_2SS_RATES); 185 } else if (sta->deflink.ht_cap.ht_supported) { 186 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 187 RA_MASK_HT_1SS_RATES); 188 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 189 RA_MASK_HT_2SS_RATES); 190 } 191 192 return cfg_mask; 193 } 194 195 static const u64 196 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 197 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 198 static const u64 199 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 200 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 201 static const u64 202 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 203 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 204 205 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 206 struct ieee80211_sta *sta, bool csi) 207 { 208 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 209 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 210 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 211 struct rtw89_ra_info *ra = &rtwsta->ra; 212 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 213 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 214 u64 ra_mask = 0; 215 u64 ra_mask_bak; 216 u8 mode = 0; 217 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 218 u8 bw_mode = 0; 219 u8 stbc_en = 0; 220 u8 ldpc_en = 0; 221 u8 i; 222 bool sgi = false; 223 224 memset(ra, 0, sizeof(*ra)); 225 /* Set the ra mask from sta's capability */ 226 if (sta->deflink.he_cap.has_he) { 227 mode |= RTW89_RA_MODE_HE; 228 csi_mode = RTW89_RA_RPT_MODE_HE; 229 ra_mask |= get_he_ra_mask(sta); 230 high_rate_masks = rtw89_ra_mask_he_rates; 231 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 232 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 233 stbc_en = 1; 234 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 235 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 236 ldpc_en = 1; 237 } else if (sta->deflink.vht_cap.vht_supported) { 238 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 239 240 mode |= RTW89_RA_MODE_VHT; 241 csi_mode = RTW89_RA_RPT_MODE_VHT; 242 /* MCS9, MCS8, MCS7 */ 243 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 244 high_rate_masks = rtw89_ra_mask_vht_rates; 245 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 246 stbc_en = 1; 247 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 248 ldpc_en = 1; 249 } else if (sta->deflink.ht_cap.ht_supported) { 250 mode |= RTW89_RA_MODE_HT; 251 csi_mode = RTW89_RA_RPT_MODE_HT; 252 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 253 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 254 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 255 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 256 high_rate_masks = rtw89_ra_mask_ht_rates; 257 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 258 stbc_en = 1; 259 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 260 ldpc_en = 1; 261 } 262 263 switch (rtwdev->hal.current_band_type) { 264 case RTW89_BAND_2G: 265 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 266 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] <= 0xf) 267 mode |= RTW89_RA_MODE_CCK; 268 else 269 mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM; 270 break; 271 case RTW89_BAND_5G: 272 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 273 mode |= RTW89_RA_MODE_OFDM; 274 break; 275 case RTW89_BAND_6G: 276 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 277 mode |= RTW89_RA_MODE_OFDM; 278 break; 279 default: 280 rtw89_err(rtwdev, "Unknown band type\n"); 281 break; 282 } 283 284 ra_mask_bak = ra_mask; 285 286 if (mode >= RTW89_RA_MODE_HT) { 287 u64 mask = 0; 288 for (i = 0; i < rtwdev->hal.tx_nss; i++) 289 mask |= high_rate_masks[i]; 290 if (mode & RTW89_RA_MODE_OFDM) 291 mask |= RA_MASK_SUBOFDM_RATES; 292 if (mode & RTW89_RA_MODE_CCK) 293 mask |= RA_MASK_SUBCCK_RATES; 294 ra_mask &= mask; 295 } else if (mode & RTW89_RA_MODE_OFDM) { 296 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 297 } 298 299 if (mode != RTW89_RA_MODE_CCK) 300 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 301 302 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 303 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 304 305 switch (sta->deflink.bandwidth) { 306 case IEEE80211_STA_RX_BW_160: 307 bw_mode = RTW89_CHANNEL_WIDTH_160; 308 sgi = sta->deflink.vht_cap.vht_supported && 309 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 310 break; 311 case IEEE80211_STA_RX_BW_80: 312 bw_mode = RTW89_CHANNEL_WIDTH_80; 313 sgi = sta->deflink.vht_cap.vht_supported && 314 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 315 break; 316 case IEEE80211_STA_RX_BW_40: 317 bw_mode = RTW89_CHANNEL_WIDTH_40; 318 sgi = sta->deflink.ht_cap.ht_supported && 319 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 320 break; 321 default: 322 bw_mode = RTW89_CHANNEL_WIDTH_20; 323 sgi = sta->deflink.ht_cap.ht_supported && 324 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 325 break; 326 } 327 328 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 329 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 330 ra->dcm_cap = 1; 331 332 if (rate_pattern->enable) { 333 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 334 ra_mask &= rate_pattern->ra_mask; 335 mode = rate_pattern->ra_mode; 336 } 337 338 ra->bw_cap = bw_mode; 339 ra->mode_ctrl = mode; 340 ra->macid = rtwsta->mac_id; 341 ra->stbc_cap = stbc_en; 342 ra->ldpc_cap = ldpc_en; 343 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 344 ra->en_sgi = sgi; 345 ra->ra_mask = ra_mask; 346 347 if (!csi) 348 return; 349 350 ra->fixed_csi_rate_en = false; 351 ra->ra_csi_rate_en = true; 352 ra->cr_tbl_sel = false; 353 ra->band_num = rtwvif->phy_idx; 354 ra->csi_bw = bw_mode; 355 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 356 ra->csi_mcs_ss_idx = 5; 357 ra->csi_mode = csi_mode; 358 } 359 360 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 361 u32 changed) 362 { 363 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 364 struct rtw89_ra_info *ra = &rtwsta->ra; 365 366 rtw89_phy_ra_sta_update(rtwdev, sta, false); 367 368 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 369 ra->upd_mask = 1; 370 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 371 ra->upd_bw_nss_mask = 1; 372 373 rtw89_debug(rtwdev, RTW89_DBG_RA, 374 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 375 ra->macid, 376 ra->bw_cap, 377 ra->ss_num, 378 ra->en_sgi, 379 ra->giltf); 380 381 rtw89_fw_h2c_ra(rtwdev, ra, false); 382 } 383 384 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 385 u16 rate_base, u64 ra_mask, u8 ra_mode, 386 u32 rate_ctrl, u32 ctrl_skip, bool force) 387 { 388 u8 n, c; 389 390 if (rate_ctrl == ctrl_skip) 391 return true; 392 393 n = hweight32(rate_ctrl); 394 if (n == 0) 395 return true; 396 397 if (force && n != 1) 398 return false; 399 400 if (next->enable) 401 return false; 402 403 c = __fls(rate_ctrl); 404 next->rate = rate_base + c; 405 next->ra_mode = ra_mode; 406 next->ra_mask = ra_mask; 407 next->enable = true; 408 409 return true; 410 } 411 412 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 413 struct ieee80211_vif *vif, 414 const struct cfg80211_bitrate_mask *mask) 415 { 416 struct ieee80211_supported_band *sband; 417 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 418 struct rtw89_phy_rate_pattern next_pattern = {0}; 419 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 420 RTW89_HW_RATE_HE_NSS2_MCS0, 421 RTW89_HW_RATE_HE_NSS3_MCS0, 422 RTW89_HW_RATE_HE_NSS4_MCS0}; 423 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 424 RTW89_HW_RATE_VHT_NSS2_MCS0, 425 RTW89_HW_RATE_VHT_NSS3_MCS0, 426 RTW89_HW_RATE_VHT_NSS4_MCS0}; 427 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 428 RTW89_HW_RATE_MCS8, 429 RTW89_HW_RATE_MCS16, 430 RTW89_HW_RATE_MCS24}; 431 u8 band = rtwdev->hal.current_band_type; 432 u8 tx_nss = rtwdev->hal.tx_nss; 433 u8 i; 434 435 for (i = 0; i < tx_nss; i++) 436 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 437 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 438 mask->control[band].he_mcs[i], 439 0, true)) 440 goto out; 441 442 for (i = 0; i < tx_nss; i++) 443 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 444 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 445 mask->control[band].vht_mcs[i], 446 0, true)) 447 goto out; 448 449 for (i = 0; i < tx_nss; i++) 450 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 451 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 452 mask->control[band].ht_mcs[i], 453 0, true)) 454 goto out; 455 456 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 457 * require at least one basic rate for ieee80211_set_bitrate_mask, 458 * so the decision just depends on if all bitrates are set or not. 459 */ 460 sband = rtwdev->hw->wiphy->bands[band]; 461 if (band == RTW89_BAND_2G) { 462 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 463 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 464 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 465 mask->control[band].legacy, 466 BIT(sband->n_bitrates) - 1, false)) 467 goto out; 468 } else { 469 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 470 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 471 mask->control[band].legacy, 472 BIT(sband->n_bitrates) - 1, false)) 473 goto out; 474 } 475 476 if (!next_pattern.enable) 477 goto out; 478 479 rtwvif->rate_pattern = next_pattern; 480 rtw89_debug(rtwdev, RTW89_DBG_RA, 481 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 482 next_pattern.rate, 483 next_pattern.ra_mask, 484 next_pattern.ra_mode); 485 return; 486 487 out: 488 rtwvif->rate_pattern.enable = false; 489 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 490 } 491 492 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 493 { 494 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 495 496 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 497 } 498 499 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 500 { 501 ieee80211_iterate_stations_atomic(rtwdev->hw, 502 rtw89_phy_ra_updata_sta_iter, 503 rtwdev); 504 } 505 506 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 507 { 508 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 509 struct rtw89_ra_info *ra = &rtwsta->ra; 510 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 511 bool csi = rtw89_sta_has_beamformer_cap(sta); 512 513 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 514 515 if (rssi > 40) 516 ra->init_rate_lv = 1; 517 else if (rssi > 20) 518 ra->init_rate_lv = 2; 519 else if (rssi > 1) 520 ra->init_rate_lv = 3; 521 else 522 ra->init_rate_lv = 0; 523 ra->upd_all = 1; 524 rtw89_debug(rtwdev, RTW89_DBG_RA, 525 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 526 ra->macid, 527 ra->mode_ctrl, 528 ra->bw_cap, 529 ra->ss_num, 530 ra->init_rate_lv); 531 rtw89_debug(rtwdev, RTW89_DBG_RA, 532 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 533 ra->dcm_cap, 534 ra->er_cap, 535 ra->ldpc_cap, 536 ra->stbc_cap, 537 ra->en_sgi, 538 ra->giltf); 539 540 rtw89_fw_h2c_ra(rtwdev, ra, csi); 541 } 542 543 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 544 struct rtw89_channel_params *param, 545 enum rtw89_bandwidth dbw) 546 { 547 enum rtw89_bandwidth cbw = param->bandwidth; 548 u8 pri_ch = param->primary_chan; 549 u8 central_ch = param->center_chan; 550 u8 txsc_idx = 0; 551 u8 tmp = 0; 552 553 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 554 return txsc_idx; 555 556 switch (cbw) { 557 case RTW89_CHANNEL_WIDTH_40: 558 txsc_idx = pri_ch > central_ch ? 1 : 2; 559 break; 560 case RTW89_CHANNEL_WIDTH_80: 561 if (dbw == RTW89_CHANNEL_WIDTH_20) { 562 if (pri_ch > central_ch) 563 txsc_idx = (pri_ch - central_ch) >> 1; 564 else 565 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 566 } else { 567 txsc_idx = pri_ch > central_ch ? 9 : 10; 568 } 569 break; 570 case RTW89_CHANNEL_WIDTH_160: 571 if (pri_ch > central_ch) 572 tmp = (pri_ch - central_ch) >> 1; 573 else 574 tmp = ((central_ch - pri_ch) >> 1) + 1; 575 576 if (dbw == RTW89_CHANNEL_WIDTH_20) { 577 txsc_idx = tmp; 578 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 579 if (tmp == 1 || tmp == 3) 580 txsc_idx = 9; 581 else if (tmp == 5 || tmp == 7) 582 txsc_idx = 11; 583 else if (tmp == 2 || tmp == 4) 584 txsc_idx = 10; 585 else if (tmp == 6 || tmp == 8) 586 txsc_idx = 12; 587 else 588 return 0xff; 589 } else { 590 txsc_idx = pri_ch > central_ch ? 13 : 14; 591 } 592 break; 593 case RTW89_CHANNEL_WIDTH_80_80: 594 if (dbw == RTW89_CHANNEL_WIDTH_20) { 595 if (pri_ch > central_ch) 596 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 597 else 598 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 599 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 600 txsc_idx = pri_ch > central_ch ? 10 : 12; 601 } else { 602 txsc_idx = 14; 603 } 604 break; 605 default: 606 break; 607 } 608 609 return txsc_idx; 610 } 611 EXPORT_SYMBOL(rtw89_phy_get_txsc); 612 613 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 614 { 615 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 616 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 617 } 618 619 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 620 u32 addr, u32 mask) 621 { 622 const struct rtw89_chip_info *chip = rtwdev->chip; 623 const u32 *base_addr = chip->rf_base_addr; 624 u32 val, direct_addr; 625 626 if (rf_path >= rtwdev->chip->rf_path_num) { 627 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 628 return INV_RF_DATA; 629 } 630 631 addr &= 0xff; 632 direct_addr = base_addr[rf_path] + (addr << 2); 633 mask &= RFREG_MASK; 634 635 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 636 637 return val; 638 } 639 EXPORT_SYMBOL(rtw89_phy_read_rf); 640 641 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 642 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 643 { 644 bool busy; 645 bool done; 646 u32 val; 647 int ret; 648 649 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 650 1, 30, false, rtwdev); 651 if (ret) { 652 rtw89_err(rtwdev, "read rf busy swsi\n"); 653 return INV_RF_DATA; 654 } 655 656 mask &= RFREG_MASK; 657 658 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 659 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 660 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 661 udelay(2); 662 663 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 664 30, false, rtwdev, R_SWSI_V1, 665 B_SWSI_R_DATA_DONE_V1); 666 if (ret) { 667 rtw89_err(rtwdev, "read swsi busy\n"); 668 return INV_RF_DATA; 669 } 670 671 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 672 } 673 674 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 675 u32 addr, u32 mask) 676 { 677 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 678 679 if (rf_path >= rtwdev->chip->rf_path_num) { 680 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 681 return INV_RF_DATA; 682 } 683 684 if (ad_sel) 685 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 686 else 687 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 688 } 689 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 690 691 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 692 u32 addr, u32 mask, u32 data) 693 { 694 const struct rtw89_chip_info *chip = rtwdev->chip; 695 const u32 *base_addr = chip->rf_base_addr; 696 u32 direct_addr; 697 698 if (rf_path >= rtwdev->chip->rf_path_num) { 699 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 700 return false; 701 } 702 703 addr &= 0xff; 704 direct_addr = base_addr[rf_path] + (addr << 2); 705 mask &= RFREG_MASK; 706 707 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 708 709 /* delay to ensure writing properly */ 710 udelay(1); 711 712 return true; 713 } 714 EXPORT_SYMBOL(rtw89_phy_write_rf); 715 716 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 717 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 718 u32 data) 719 { 720 u8 bit_shift; 721 u32 val; 722 bool busy, b_msk_en = false; 723 int ret; 724 725 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 726 1, 30, false, rtwdev); 727 if (ret) { 728 rtw89_err(rtwdev, "write rf busy swsi\n"); 729 return false; 730 } 731 732 data &= RFREG_MASK; 733 mask &= RFREG_MASK; 734 735 if (mask != RFREG_MASK) { 736 b_msk_en = true; 737 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 738 mask); 739 bit_shift = __ffs(mask); 740 data = (data << bit_shift) & RFREG_MASK; 741 } 742 743 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 744 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 745 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 746 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 747 748 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 749 750 return true; 751 } 752 753 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 754 u32 addr, u32 mask, u32 data) 755 { 756 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 757 758 if (rf_path >= rtwdev->chip->rf_path_num) { 759 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 760 return false; 761 } 762 763 if (ad_sel) 764 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 765 else 766 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 767 } 768 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 769 770 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 771 enum rtw89_phy_idx phy_idx) 772 { 773 const struct rtw89_chip_info *chip = rtwdev->chip; 774 775 chip->ops->bb_reset(rtwdev, phy_idx); 776 } 777 778 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 779 const struct rtw89_reg2_def *reg, 780 enum rtw89_rf_path rf_path, 781 void *extra_data) 782 { 783 if (reg->addr == 0xfe) 784 mdelay(50); 785 else if (reg->addr == 0xfd) 786 mdelay(5); 787 else if (reg->addr == 0xfc) 788 mdelay(1); 789 else if (reg->addr == 0xfb) 790 udelay(50); 791 else if (reg->addr == 0xfa) 792 udelay(5); 793 else if (reg->addr == 0xf9) 794 udelay(1); 795 else 796 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 797 } 798 799 union rtw89_phy_bb_gain_arg { 800 u32 addr; 801 struct { 802 union { 803 u8 type; 804 struct { 805 u8 rxsc_start:4; 806 u8 bw:4; 807 }; 808 }; 809 u8 path; 810 u8 gain_band; 811 u8 cfg_type; 812 }; 813 } __packed; 814 815 static void 816 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 817 union rtw89_phy_bb_gain_arg arg, u32 data) 818 { 819 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 820 u8 type = arg.type; 821 u8 path = arg.path; 822 u8 gband = arg.gain_band; 823 int i; 824 825 switch (type) { 826 case 0: 827 for (i = 0; i < 4; i++, data >>= 8) 828 gain->lna_gain[gband][path][i] = data & 0xff; 829 break; 830 case 1: 831 for (i = 4; i < 7; i++, data >>= 8) 832 gain->lna_gain[gband][path][i] = data & 0xff; 833 break; 834 case 2: 835 for (i = 0; i < 2; i++, data >>= 8) 836 gain->tia_gain[gband][path][i] = data & 0xff; 837 break; 838 default: 839 rtw89_warn(rtwdev, 840 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 841 arg.addr, data, type); 842 break; 843 } 844 } 845 846 enum rtw89_phy_bb_rxsc_start_idx { 847 RTW89_BB_RXSC_START_IDX_FULL = 0, 848 RTW89_BB_RXSC_START_IDX_20 = 1, 849 RTW89_BB_RXSC_START_IDX_20_1 = 5, 850 RTW89_BB_RXSC_START_IDX_40 = 9, 851 RTW89_BB_RXSC_START_IDX_80 = 13, 852 }; 853 854 static void 855 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 856 union rtw89_phy_bb_gain_arg arg, u32 data) 857 { 858 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 859 u8 rxsc_start = arg.rxsc_start; 860 u8 bw = arg.bw; 861 u8 path = arg.path; 862 u8 gband = arg.gain_band; 863 u8 rxsc; 864 s8 ofst; 865 int i; 866 867 switch (bw) { 868 case RTW89_CHANNEL_WIDTH_20: 869 gain->rpl_ofst_20[gband][path] = (s8)data; 870 break; 871 case RTW89_CHANNEL_WIDTH_40: 872 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 873 gain->rpl_ofst_40[gband][path][0] = (s8)data; 874 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 875 for (i = 0; i < 2; i++, data >>= 8) { 876 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 877 ofst = (s8)(data & 0xff); 878 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 879 } 880 } 881 break; 882 case RTW89_CHANNEL_WIDTH_80: 883 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 884 gain->rpl_ofst_80[gband][path][0] = (s8)data; 885 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 886 for (i = 0; i < 4; i++, data >>= 8) { 887 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 888 ofst = (s8)(data & 0xff); 889 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 890 } 891 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 892 for (i = 0; i < 2; i++, data >>= 8) { 893 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 894 ofst = (s8)(data & 0xff); 895 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 896 } 897 } 898 break; 899 case RTW89_CHANNEL_WIDTH_160: 900 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 901 gain->rpl_ofst_160[gband][path][0] = (s8)data; 902 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 903 for (i = 0; i < 4; i++, data >>= 8) { 904 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 905 ofst = (s8)(data & 0xff); 906 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 907 } 908 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 909 for (i = 0; i < 4; i++, data >>= 8) { 910 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 911 ofst = (s8)(data & 0xff); 912 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 913 } 914 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 915 for (i = 0; i < 4; i++, data >>= 8) { 916 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 917 ofst = (s8)(data & 0xff); 918 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 919 } 920 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 921 for (i = 0; i < 2; i++, data >>= 8) { 922 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 923 ofst = (s8)(data & 0xff); 924 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 925 } 926 } 927 break; 928 default: 929 rtw89_warn(rtwdev, 930 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 931 arg.addr, data, bw); 932 break; 933 } 934 } 935 936 static void 937 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 938 union rtw89_phy_bb_gain_arg arg, u32 data) 939 { 940 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 941 u8 type = arg.type; 942 u8 path = arg.path; 943 u8 gband = arg.gain_band; 944 int i; 945 946 switch (type) { 947 case 0: 948 for (i = 0; i < 4; i++, data >>= 8) 949 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 950 break; 951 case 1: 952 for (i = 4; i < 7; i++, data >>= 8) 953 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 954 break; 955 default: 956 rtw89_warn(rtwdev, 957 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 958 arg.addr, data, type); 959 break; 960 } 961 } 962 963 static void 964 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 965 union rtw89_phy_bb_gain_arg arg, u32 data) 966 { 967 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 968 u8 type = arg.type; 969 u8 path = arg.path; 970 u8 gband = arg.gain_band; 971 int i; 972 973 switch (type) { 974 case 0: 975 for (i = 0; i < 4; i++, data >>= 8) 976 gain->lna_op1db[gband][path][i] = data & 0xff; 977 break; 978 case 1: 979 for (i = 4; i < 7; i++, data >>= 8) 980 gain->lna_op1db[gband][path][i] = data & 0xff; 981 break; 982 case 2: 983 for (i = 0; i < 4; i++, data >>= 8) 984 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 985 break; 986 case 3: 987 for (i = 4; i < 8; i++, data >>= 8) 988 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 989 break; 990 default: 991 rtw89_warn(rtwdev, 992 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 993 arg.addr, data, type); 994 break; 995 } 996 } 997 998 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 999 const struct rtw89_reg2_def *reg, 1000 enum rtw89_rf_path rf_path, 1001 void *extra_data) 1002 { 1003 const struct rtw89_chip_info *chip = rtwdev->chip; 1004 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1005 1006 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1007 return; 1008 1009 if (arg.path >= chip->rf_path_num) 1010 return; 1011 1012 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1013 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1014 return; 1015 } 1016 1017 switch (arg.cfg_type) { 1018 case 0: 1019 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1020 break; 1021 case 1: 1022 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1023 break; 1024 case 2: 1025 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1026 break; 1027 case 3: 1028 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1029 break; 1030 default: 1031 rtw89_warn(rtwdev, 1032 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1033 arg.addr, reg->data, arg.cfg_type); 1034 break; 1035 } 1036 } 1037 1038 static void 1039 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1040 const struct rtw89_reg2_def *reg, 1041 enum rtw89_rf_path rf_path, 1042 struct rtw89_fw_h2c_rf_reg_info *info) 1043 { 1044 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1045 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1046 1047 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1048 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1049 rf_path, info->curr_idx); 1050 return; 1051 } 1052 1053 info->rtw89_phy_config_rf_h2c[page][idx] = 1054 cpu_to_le32((reg->addr << 20) | reg->data); 1055 info->curr_idx++; 1056 } 1057 1058 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1059 struct rtw89_fw_h2c_rf_reg_info *info) 1060 { 1061 u16 remain = info->curr_idx; 1062 u16 len = 0; 1063 u8 i; 1064 int ret = 0; 1065 1066 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1067 rtw89_warn(rtwdev, 1068 "rf reg h2c total len %d larger than %d\n", 1069 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1070 ret = -EINVAL; 1071 goto out; 1072 } 1073 1074 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1075 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1076 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1077 if (ret) 1078 goto out; 1079 } 1080 out: 1081 info->curr_idx = 0; 1082 1083 return ret; 1084 } 1085 1086 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1087 const struct rtw89_reg2_def *reg, 1088 enum rtw89_rf_path rf_path, 1089 void *extra_data) 1090 { 1091 if (reg->addr == 0xfe) { 1092 mdelay(50); 1093 } else if (reg->addr == 0xfd) { 1094 mdelay(5); 1095 } else if (reg->addr == 0xfc) { 1096 mdelay(1); 1097 } else if (reg->addr == 0xfb) { 1098 udelay(50); 1099 } else if (reg->addr == 0xfa) { 1100 udelay(5); 1101 } else if (reg->addr == 0xf9) { 1102 udelay(1); 1103 } else { 1104 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1105 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1106 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1107 } 1108 } 1109 1110 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1111 const struct rtw89_reg2_def *reg, 1112 enum rtw89_rf_path rf_path, 1113 void *extra_data) 1114 { 1115 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1116 1117 if (reg->addr < 0x100) 1118 return; 1119 1120 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1121 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1122 } 1123 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1124 1125 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1126 const struct rtw89_phy_table *table, 1127 u32 *headline_size, u32 *headline_idx, 1128 u8 rfe, u8 cv) 1129 { 1130 const struct rtw89_reg2_def *reg; 1131 u32 headline; 1132 u32 compare, target; 1133 u8 rfe_para, cv_para; 1134 u8 cv_max = 0; 1135 bool case_matched = false; 1136 u32 i; 1137 1138 for (i = 0; i < table->n_regs; i++) { 1139 reg = &table->regs[i]; 1140 headline = get_phy_headline(reg->addr); 1141 if (headline != PHY_HEADLINE_VALID) 1142 break; 1143 } 1144 *headline_size = i; 1145 if (*headline_size == 0) 1146 return 0; 1147 1148 /* case 1: RFE match, CV match */ 1149 compare = get_phy_compare(rfe, cv); 1150 for (i = 0; i < *headline_size; i++) { 1151 reg = &table->regs[i]; 1152 target = get_phy_target(reg->addr); 1153 if (target == compare) { 1154 *headline_idx = i; 1155 return 0; 1156 } 1157 } 1158 1159 /* case 2: RFE match, CV don't care */ 1160 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1161 for (i = 0; i < *headline_size; i++) { 1162 reg = &table->regs[i]; 1163 target = get_phy_target(reg->addr); 1164 if (target == compare) { 1165 *headline_idx = i; 1166 return 0; 1167 } 1168 } 1169 1170 /* case 3: RFE match, CV max in table */ 1171 for (i = 0; i < *headline_size; i++) { 1172 reg = &table->regs[i]; 1173 rfe_para = get_phy_cond_rfe(reg->addr); 1174 cv_para = get_phy_cond_cv(reg->addr); 1175 if (rfe_para == rfe) { 1176 if (cv_para >= cv_max) { 1177 cv_max = cv_para; 1178 *headline_idx = i; 1179 case_matched = true; 1180 } 1181 } 1182 } 1183 1184 if (case_matched) 1185 return 0; 1186 1187 /* case 4: RFE don't care, CV max in table */ 1188 for (i = 0; i < *headline_size; i++) { 1189 reg = &table->regs[i]; 1190 rfe_para = get_phy_cond_rfe(reg->addr); 1191 cv_para = get_phy_cond_cv(reg->addr); 1192 if (rfe_para == PHY_COND_DONT_CARE) { 1193 if (cv_para >= cv_max) { 1194 cv_max = cv_para; 1195 *headline_idx = i; 1196 case_matched = true; 1197 } 1198 } 1199 } 1200 1201 if (case_matched) 1202 return 0; 1203 1204 return -EINVAL; 1205 } 1206 1207 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1208 const struct rtw89_phy_table *table, 1209 void (*config)(struct rtw89_dev *rtwdev, 1210 const struct rtw89_reg2_def *reg, 1211 enum rtw89_rf_path rf_path, 1212 void *data), 1213 void *extra_data) 1214 { 1215 const struct rtw89_reg2_def *reg; 1216 enum rtw89_rf_path rf_path = table->rf_path; 1217 u8 rfe = rtwdev->efuse.rfe_type; 1218 u8 cv = rtwdev->hal.cv; 1219 u32 i; 1220 u32 headline_size = 0, headline_idx = 0; 1221 u32 target = 0, cfg_target; 1222 u8 cond; 1223 bool is_matched = true; 1224 bool target_found = false; 1225 int ret; 1226 1227 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1228 &headline_idx, rfe, cv); 1229 if (ret) { 1230 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1231 return; 1232 } 1233 1234 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1235 for (i = headline_size; i < table->n_regs; i++) { 1236 reg = &table->regs[i]; 1237 cond = get_phy_cond(reg->addr); 1238 switch (cond) { 1239 case PHY_COND_BRANCH_IF: 1240 case PHY_COND_BRANCH_ELIF: 1241 target = get_phy_target(reg->addr); 1242 break; 1243 case PHY_COND_BRANCH_ELSE: 1244 is_matched = false; 1245 if (!target_found) { 1246 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1247 reg->addr, reg->data); 1248 return; 1249 } 1250 break; 1251 case PHY_COND_BRANCH_END: 1252 is_matched = true; 1253 target_found = false; 1254 break; 1255 case PHY_COND_CHECK: 1256 if (target_found) { 1257 is_matched = false; 1258 break; 1259 } 1260 1261 if (target == cfg_target) { 1262 is_matched = true; 1263 target_found = true; 1264 } else { 1265 is_matched = false; 1266 target_found = false; 1267 } 1268 break; 1269 default: 1270 if (is_matched) 1271 config(rtwdev, reg, rf_path, extra_data); 1272 break; 1273 } 1274 } 1275 } 1276 1277 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1278 { 1279 const struct rtw89_chip_info *chip = rtwdev->chip; 1280 const struct rtw89_phy_table *bb_table = chip->bb_table; 1281 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table; 1282 1283 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1284 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1285 if (bb_gain_table) 1286 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1287 rtw89_phy_config_bb_gain, NULL); 1288 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1289 } 1290 1291 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1292 { 1293 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1294 udelay(1); 1295 return rtw89_phy_read32(rtwdev, 0x8080); 1296 } 1297 1298 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev) 1299 { 1300 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1301 enum rtw89_rf_path rf_path, void *data); 1302 const struct rtw89_chip_info *chip = rtwdev->chip; 1303 const struct rtw89_phy_table *rf_table; 1304 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1305 u8 path; 1306 1307 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1308 if (!rf_reg_info) 1309 return; 1310 1311 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1312 rf_table = chip->rf_table[path]; 1313 rf_reg_info->rf_path = rf_table->rf_path; 1314 config = rf_table->config ? rf_table->config : rtw89_phy_config_rf_reg; 1315 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1316 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1317 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1318 rf_reg_info->rf_path); 1319 } 1320 kfree(rf_reg_info); 1321 } 1322 1323 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1324 { 1325 const struct rtw89_chip_info *chip = rtwdev->chip; 1326 const struct rtw89_phy_table *nctl_table; 1327 u32 val; 1328 int ret; 1329 1330 /* IQK/DPK clock & reset */ 1331 rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3); 1332 rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1); 1333 rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000); 1334 rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000); 1335 1336 /* check 0x8080 */ 1337 rtw89_phy_write32(rtwdev, 0x8000, 0x8); 1338 1339 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1340 1000, false, rtwdev); 1341 if (ret) 1342 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1343 1344 nctl_table = chip->nctl_table; 1345 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1346 } 1347 1348 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1349 { 1350 u32 phy_page = addr >> 8; 1351 u32 ofst = 0; 1352 1353 switch (phy_page) { 1354 case 0x6: 1355 case 0x7: 1356 case 0x8: 1357 case 0x9: 1358 case 0xa: 1359 case 0xb: 1360 case 0xc: 1361 case 0xd: 1362 case 0x19: 1363 case 0x1a: 1364 case 0x1b: 1365 ofst = 0x2000; 1366 break; 1367 default: 1368 /* warning case */ 1369 ofst = 0; 1370 break; 1371 } 1372 1373 if (phy_page >= 0x40 && phy_page <= 0x4f) 1374 ofst = 0x2000; 1375 1376 return ofst; 1377 } 1378 1379 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1380 u32 data, enum rtw89_phy_idx phy_idx) 1381 { 1382 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1383 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1384 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1385 } 1386 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1387 1388 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1389 u32 val) 1390 { 1391 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1392 1393 if (!rtwdev->dbcc_en) 1394 return; 1395 1396 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1397 } 1398 1399 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1400 const struct rtw89_phy_reg3_tbl *tbl) 1401 { 1402 const struct rtw89_reg3_def *reg3; 1403 int i; 1404 1405 for (i = 0; i < tbl->size; i++) { 1406 reg3 = &tbl->reg3[i]; 1407 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1408 } 1409 } 1410 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1411 1412 const u8 rtw89_rs_idx_max[] = { 1413 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1414 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1415 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1416 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1417 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1418 }; 1419 EXPORT_SYMBOL(rtw89_rs_idx_max); 1420 1421 const u8 rtw89_rs_nss_max[] = { 1422 [RTW89_RS_CCK] = 1, 1423 [RTW89_RS_OFDM] = 1, 1424 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1425 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1426 [RTW89_RS_OFFSET] = 1, 1427 }; 1428 EXPORT_SYMBOL(rtw89_rs_nss_max); 1429 1430 static const u8 _byr_of_rs[] = { 1431 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1432 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1433 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1434 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1435 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1436 }; 1437 1438 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1439 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1440 #define _byr_chk(rs, nss, idx) \ 1441 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1442 1443 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1444 const struct rtw89_txpwr_table *tbl) 1445 { 1446 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1447 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1448 s8 *byr; 1449 u32 data; 1450 u8 i, idx; 1451 1452 for (; cfg < end; cfg++) { 1453 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1454 data = cfg->data; 1455 1456 for (i = 0; i < cfg->len; i++, data >>= 8) { 1457 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1458 byr[idx] = (s8)(data & 0xff); 1459 } 1460 } 1461 } 1462 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1463 1464 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1465 ({ \ 1466 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1467 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1468 }) 1469 1470 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, 1471 const struct rtw89_rate_desc *rate_desc) 1472 { 1473 enum rtw89_band band = rtwdev->hal.current_band_type; 1474 s8 *byr; 1475 u8 idx; 1476 1477 if (rate_desc->rs == RTW89_RS_CCK) 1478 band = RTW89_BAND_2G; 1479 1480 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1481 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1482 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1483 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1484 1485 return 0; 1486 } 1487 1488 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1489 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1490 1491 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1492 } 1493 EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate); 1494 1495 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1496 { 1497 switch (channel_6g) { 1498 case 1 ... 29: 1499 return (channel_6g - 1) / 2; 1500 case 33 ... 61: 1501 return (channel_6g - 3) / 2; 1502 case 65 ... 93: 1503 return (channel_6g - 5) / 2; 1504 case 97 ... 125: 1505 return (channel_6g - 7) / 2; 1506 case 129 ... 157: 1507 return (channel_6g - 9) / 2; 1508 case 161 ... 189: 1509 return (channel_6g - 11) / 2; 1510 case 193 ... 221: 1511 return (channel_6g - 13) / 2; 1512 case 225 ... 253: 1513 return (channel_6g - 15) / 2; 1514 default: 1515 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1516 return 0; 1517 } 1518 } 1519 1520 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1521 { 1522 if (band == RTW89_BAND_6G) 1523 return rtw89_channel_6g_to_idx(rtwdev, channel); 1524 1525 switch (channel) { 1526 case 1 ... 14: 1527 return channel - 1; 1528 case 36 ... 64: 1529 return (channel - 36) / 2; 1530 case 100 ... 144: 1531 return ((channel - 100) / 2) + 15; 1532 case 149 ... 177: 1533 return ((channel - 149) / 2) + 38; 1534 default: 1535 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1536 return 0; 1537 } 1538 } 1539 1540 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, 1541 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1542 { 1543 const struct rtw89_chip_info *chip = rtwdev->chip; 1544 u8 band = rtwdev->hal.current_band_type; 1545 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1546 u8 regd = rtw89_regd_get(rtwdev, band); 1547 s8 lmt = 0, sar; 1548 1549 switch (band) { 1550 case RTW89_BAND_2G: 1551 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; 1552 if (!lmt) 1553 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf] 1554 [RTW89_WW][ch_idx]; 1555 break; 1556 case RTW89_BAND_5G: 1557 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; 1558 if (!lmt) 1559 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf] 1560 [RTW89_WW][ch_idx]; 1561 break; 1562 case RTW89_BAND_6G: 1563 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx]; 1564 if (!lmt) 1565 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf] 1566 [RTW89_WW][ch_idx]; 1567 break; 1568 default: 1569 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1570 return 0; 1571 } 1572 1573 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1574 sar = rtw89_query_sar(rtwdev); 1575 1576 return min(lmt, sar); 1577 } 1578 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1579 1580 #define __fill_txpwr_limit_nonbf_bf(ptr, bw, ntx, rs, ch) \ 1581 do { \ 1582 u8 __i; \ 1583 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1584 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1585 bw, ntx, \ 1586 rs, __i, \ 1587 (ch)); \ 1588 } while (0) 1589 1590 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1591 struct rtw89_txpwr_limit *lmt, 1592 u8 ntx, u8 ch) 1593 { 1594 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, 1595 ntx, RTW89_RS_CCK, ch); 1596 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, 1597 ntx, RTW89_RS_CCK, ch); 1598 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1599 ntx, RTW89_RS_OFDM, ch); 1600 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1601 ntx, RTW89_RS_MCS, ch); 1602 } 1603 1604 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1605 struct rtw89_txpwr_limit *lmt, 1606 u8 ntx, u8 ch, u8 pri_ch) 1607 { 1608 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, RTW89_CHANNEL_WIDTH_20, 1609 ntx, RTW89_RS_CCK, ch - 2); 1610 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, RTW89_CHANNEL_WIDTH_40, 1611 ntx, RTW89_RS_CCK, ch); 1612 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1613 ntx, RTW89_RS_OFDM, pri_ch); 1614 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1615 ntx, RTW89_RS_MCS, ch - 2); 1616 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1617 ntx, RTW89_RS_MCS, ch + 2); 1618 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1619 ntx, RTW89_RS_MCS, ch); 1620 } 1621 1622 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1623 struct rtw89_txpwr_limit *lmt, 1624 u8 ntx, u8 ch, u8 pri_ch) 1625 { 1626 s8 val_0p5_n[RTW89_BF_NUM]; 1627 s8 val_0p5_p[RTW89_BF_NUM]; 1628 u8 i; 1629 1630 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1631 ntx, RTW89_RS_OFDM, pri_ch); 1632 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1633 ntx, RTW89_RS_MCS, ch - 6); 1634 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1635 ntx, RTW89_RS_MCS, ch - 2); 1636 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20, 1637 ntx, RTW89_RS_MCS, ch + 2); 1638 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20, 1639 ntx, RTW89_RS_MCS, ch + 6); 1640 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1641 ntx, RTW89_RS_MCS, ch - 4); 1642 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40, 1643 ntx, RTW89_RS_MCS, ch + 4); 1644 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80, 1645 ntx, RTW89_RS_MCS, ch); 1646 1647 __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40, 1648 ntx, RTW89_RS_MCS, ch - 4); 1649 __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40, 1650 ntx, RTW89_RS_MCS, ch + 4); 1651 1652 for (i = 0; i < RTW89_BF_NUM; i++) 1653 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1654 } 1655 1656 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1657 struct rtw89_txpwr_limit *lmt, 1658 u8 ntx, u8 ch, u8 pri_ch) 1659 { 1660 s8 val_0p5_n[RTW89_BF_NUM]; 1661 s8 val_0p5_p[RTW89_BF_NUM]; 1662 s8 val_2p5_n[RTW89_BF_NUM]; 1663 s8 val_2p5_p[RTW89_BF_NUM]; 1664 u8 i; 1665 1666 /* fill ofdm section */ 1667 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, RTW89_CHANNEL_WIDTH_20, 1668 ntx, RTW89_RS_OFDM, pri_ch); 1669 1670 /* fill mcs 20m section */ 1671 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], RTW89_CHANNEL_WIDTH_20, 1672 ntx, RTW89_RS_MCS, ch - 14); 1673 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], RTW89_CHANNEL_WIDTH_20, 1674 ntx, RTW89_RS_MCS, ch - 10); 1675 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], RTW89_CHANNEL_WIDTH_20, 1676 ntx, RTW89_RS_MCS, ch - 6); 1677 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], RTW89_CHANNEL_WIDTH_20, 1678 ntx, RTW89_RS_MCS, ch - 2); 1679 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], RTW89_CHANNEL_WIDTH_20, 1680 ntx, RTW89_RS_MCS, ch + 2); 1681 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], RTW89_CHANNEL_WIDTH_20, 1682 ntx, RTW89_RS_MCS, ch + 6); 1683 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], RTW89_CHANNEL_WIDTH_20, 1684 ntx, RTW89_RS_MCS, ch + 10); 1685 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], RTW89_CHANNEL_WIDTH_20, 1686 ntx, RTW89_RS_MCS, ch + 14); 1687 1688 /* fill mcs 40m section */ 1689 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], RTW89_CHANNEL_WIDTH_40, 1690 ntx, RTW89_RS_MCS, ch - 12); 1691 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], RTW89_CHANNEL_WIDTH_40, 1692 ntx, RTW89_RS_MCS, ch - 4); 1693 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], RTW89_CHANNEL_WIDTH_40, 1694 ntx, RTW89_RS_MCS, ch + 4); 1695 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], RTW89_CHANNEL_WIDTH_40, 1696 ntx, RTW89_RS_MCS, ch + 12); 1697 1698 /* fill mcs 80m section */ 1699 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], RTW89_CHANNEL_WIDTH_80, 1700 ntx, RTW89_RS_MCS, ch - 8); 1701 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], RTW89_CHANNEL_WIDTH_80, 1702 ntx, RTW89_RS_MCS, ch + 8); 1703 1704 /* fill mcs 160m section */ 1705 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, RTW89_CHANNEL_WIDTH_160, 1706 ntx, RTW89_RS_MCS, ch); 1707 1708 /* fill mcs 40m 0p5 section */ 1709 __fill_txpwr_limit_nonbf_bf(val_0p5_n, RTW89_CHANNEL_WIDTH_40, 1710 ntx, RTW89_RS_MCS, ch - 4); 1711 __fill_txpwr_limit_nonbf_bf(val_0p5_p, RTW89_CHANNEL_WIDTH_40, 1712 ntx, RTW89_RS_MCS, ch + 4); 1713 1714 for (i = 0; i < RTW89_BF_NUM; i++) 1715 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1716 1717 /* fill mcs 40m 2p5 section */ 1718 __fill_txpwr_limit_nonbf_bf(val_2p5_n, RTW89_CHANNEL_WIDTH_40, 1719 ntx, RTW89_RS_MCS, ch - 8); 1720 __fill_txpwr_limit_nonbf_bf(val_2p5_p, RTW89_CHANNEL_WIDTH_40, 1721 ntx, RTW89_RS_MCS, ch + 8); 1722 1723 for (i = 0; i < RTW89_BF_NUM; i++) 1724 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1725 } 1726 1727 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1728 struct rtw89_txpwr_limit *lmt, 1729 u8 ntx) 1730 { 1731 u8 pri_ch = rtwdev->hal.current_primary_channel; 1732 u8 ch = rtwdev->hal.current_channel; 1733 u8 bw = rtwdev->hal.current_band_width; 1734 1735 memset(lmt, 0, sizeof(*lmt)); 1736 1737 switch (bw) { 1738 case RTW89_CHANNEL_WIDTH_20: 1739 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, ntx, ch); 1740 break; 1741 case RTW89_CHANNEL_WIDTH_40: 1742 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, ntx, ch, pri_ch); 1743 break; 1744 case RTW89_CHANNEL_WIDTH_80: 1745 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, ntx, ch, pri_ch); 1746 break; 1747 case RTW89_CHANNEL_WIDTH_160: 1748 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, ntx, ch, pri_ch); 1749 break; 1750 } 1751 } 1752 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit); 1753 1754 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1755 u8 ru, u8 ntx, u8 ch) 1756 { 1757 const struct rtw89_chip_info *chip = rtwdev->chip; 1758 u8 band = rtwdev->hal.current_band_type; 1759 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1760 u8 regd = rtw89_regd_get(rtwdev, band); 1761 s8 lmt_ru = 0, sar; 1762 1763 switch (band) { 1764 case RTW89_BAND_2G: 1765 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; 1766 if (!lmt_ru) 1767 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx] 1768 [RTW89_WW][ch_idx]; 1769 break; 1770 case RTW89_BAND_5G: 1771 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; 1772 if (!lmt_ru) 1773 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx] 1774 [RTW89_WW][ch_idx]; 1775 break; 1776 case RTW89_BAND_6G: 1777 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx]; 1778 if (!lmt_ru) 1779 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx] 1780 [RTW89_WW][ch_idx]; 1781 break; 1782 default: 1783 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1784 return 0; 1785 } 1786 1787 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1788 sar = rtw89_query_sar(rtwdev); 1789 1790 return min(lmt_ru, sar); 1791 } 1792 1793 static void 1794 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1795 struct rtw89_txpwr_limit_ru *lmt_ru, 1796 u8 ntx, u8 ch) 1797 { 1798 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1799 ntx, ch); 1800 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1801 ntx, ch); 1802 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1803 ntx, ch); 1804 } 1805 1806 static void 1807 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1808 struct rtw89_txpwr_limit_ru *lmt_ru, 1809 u8 ntx, u8 ch) 1810 { 1811 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1812 ntx, ch - 2); 1813 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1814 ntx, ch + 2); 1815 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1816 ntx, ch - 2); 1817 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1818 ntx, ch + 2); 1819 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1820 ntx, ch - 2); 1821 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1822 ntx, ch + 2); 1823 } 1824 1825 static void 1826 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1827 struct rtw89_txpwr_limit_ru *lmt_ru, 1828 u8 ntx, u8 ch) 1829 { 1830 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1831 ntx, ch - 6); 1832 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1833 ntx, ch - 2); 1834 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1835 ntx, ch + 2); 1836 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU26, 1837 ntx, ch + 6); 1838 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1839 ntx, ch - 6); 1840 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1841 ntx, ch - 2); 1842 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1843 ntx, ch + 2); 1844 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU52, 1845 ntx, ch + 6); 1846 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1847 ntx, ch - 6); 1848 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1849 ntx, ch - 2); 1850 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1851 ntx, ch + 2); 1852 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, RTW89_RU106, 1853 ntx, ch + 6); 1854 } 1855 1856 static void 1857 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 1858 struct rtw89_txpwr_limit_ru *lmt_ru, 1859 u8 ntx, u8 ch) 1860 { 1861 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 1862 int i; 1863 1864 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 1865 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 1866 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, 1867 RTW89_RU26, 1868 ntx, 1869 ch + ofst[i]); 1870 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, 1871 RTW89_RU52, 1872 ntx, 1873 ch + ofst[i]); 1874 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, 1875 RTW89_RU106, 1876 ntx, 1877 ch + ofst[i]); 1878 } 1879 } 1880 1881 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1882 struct rtw89_txpwr_limit_ru *lmt_ru, 1883 u8 ntx) 1884 { 1885 u8 ch = rtwdev->hal.current_channel; 1886 u8 bw = rtwdev->hal.current_band_width; 1887 1888 memset(lmt_ru, 0, sizeof(*lmt_ru)); 1889 1890 switch (bw) { 1891 case RTW89_CHANNEL_WIDTH_20: 1892 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, ntx, ch); 1893 break; 1894 case RTW89_CHANNEL_WIDTH_40: 1895 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, ntx, ch); 1896 break; 1897 case RTW89_CHANNEL_WIDTH_80: 1898 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, ntx, ch); 1899 break; 1900 case RTW89_CHANNEL_WIDTH_160: 1901 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, ntx, ch); 1902 break; 1903 } 1904 } 1905 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru); 1906 1907 struct rtw89_phy_iter_ra_data { 1908 struct rtw89_dev *rtwdev; 1909 struct sk_buff *c2h; 1910 }; 1911 1912 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 1913 { 1914 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 1915 struct rtw89_dev *rtwdev = ra_data->rtwdev; 1916 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1917 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 1918 struct sk_buff *c2h = ra_data->c2h; 1919 u8 mode, rate, bw, giltf, mac_id; 1920 1921 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 1922 if (mac_id != rtwsta->mac_id) 1923 return; 1924 1925 memset(ra_report, 0, sizeof(*ra_report)); 1926 1927 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 1928 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 1929 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 1930 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 1931 1932 switch (mode) { 1933 case RTW89_RA_RPT_MODE_LEGACY: 1934 ra_report->txrate.legacy = rtw89_ra_report_to_bitrate(rtwdev, rate); 1935 break; 1936 case RTW89_RA_RPT_MODE_HT: 1937 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 1938 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 1939 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 1940 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 1941 else 1942 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 1943 ra_report->txrate.mcs = rate; 1944 if (giltf) 1945 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1946 break; 1947 case RTW89_RA_RPT_MODE_VHT: 1948 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 1949 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 1950 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 1951 if (giltf) 1952 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1953 break; 1954 case RTW89_RA_RPT_MODE_HE: 1955 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 1956 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 1957 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 1958 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 1959 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 1960 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 1961 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 1962 else 1963 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 1964 break; 1965 } 1966 1967 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 1968 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 1969 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 1970 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 1971 sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 1972 rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1; 1973 } 1974 1975 static void 1976 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 1977 { 1978 struct rtw89_phy_iter_ra_data ra_data; 1979 1980 ra_data.rtwdev = rtwdev; 1981 ra_data.c2h = c2h; 1982 ieee80211_iterate_stations_atomic(rtwdev->hw, 1983 rtw89_phy_c2h_ra_rpt_iter, 1984 &ra_data); 1985 } 1986 1987 static 1988 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 1989 struct sk_buff *c2h, u32 len) = { 1990 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 1991 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 1992 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 1993 }; 1994 1995 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1996 u32 len, u8 class, u8 func) 1997 { 1998 void (*handler)(struct rtw89_dev *rtwdev, 1999 struct sk_buff *c2h, u32 len) = NULL; 2000 2001 switch (class) { 2002 case RTW89_PHY_C2H_CLASS_RA: 2003 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2004 handler = rtw89_phy_c2h_ra_handler[func]; 2005 break; 2006 default: 2007 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2008 return; 2009 } 2010 if (!handler) { 2011 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2012 func); 2013 return; 2014 } 2015 handler(rtwdev, skb, len); 2016 } 2017 2018 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2019 { 2020 u32 reg_mask; 2021 2022 if (sc_xo) 2023 reg_mask = B_AX_XTAL_SC_XO_MASK; 2024 else 2025 reg_mask = B_AX_XTAL_SC_XI_MASK; 2026 2027 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 2028 } 2029 2030 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2031 u8 val) 2032 { 2033 u32 reg_mask; 2034 2035 if (sc_xo) 2036 reg_mask = B_AX_XTAL_SC_XO_MASK; 2037 else 2038 reg_mask = B_AX_XTAL_SC_XI_MASK; 2039 2040 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 2041 } 2042 2043 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2044 u8 crystal_cap, bool force) 2045 { 2046 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2047 const struct rtw89_chip_info *chip = rtwdev->chip; 2048 u8 sc_xi_val, sc_xo_val; 2049 2050 if (!force && cfo->crystal_cap == crystal_cap) 2051 return; 2052 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2053 if (chip->chip_id == RTL8852A) { 2054 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2055 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2056 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2057 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2058 } else { 2059 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2060 crystal_cap, XTAL_SC_XO_MASK); 2061 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2062 crystal_cap, XTAL_SC_XI_MASK); 2063 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2064 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2065 } 2066 cfo->crystal_cap = sc_xi_val; 2067 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2068 2069 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2070 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2071 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2072 cfo->x_cap_ofst); 2073 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2074 } 2075 2076 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2077 { 2078 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2079 u8 cap; 2080 2081 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2082 cfo->is_adjust = false; 2083 if (cfo->crystal_cap == cfo->def_x_cap) 2084 return; 2085 cap = cfo->crystal_cap; 2086 cap += (cap > cfo->def_x_cap ? -1 : 1); 2087 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2088 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2089 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2090 cfo->def_x_cap); 2091 } 2092 2093 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2094 { 2095 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2096 bool is_linked = rtwdev->total_sta_assoc > 0; 2097 s32 cfo_avg_312; 2098 s32 dcfo_comp_val; 2099 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2100 int sign; 2101 2102 if (!is_linked) { 2103 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2104 is_linked); 2105 return; 2106 } 2107 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2108 if (curr_cfo == 0) 2109 return; 2110 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2111 sign = curr_cfo > 0 ? 1 : -1; 2112 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val; 2113 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); 2114 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2115 cfo_avg_312 = -cfo_avg_312; 2116 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2117 cfo_avg_312); 2118 } 2119 2120 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2121 { 2122 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2123 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2124 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2125 } 2126 2127 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2128 { 2129 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2130 struct rtw89_efuse *efuse = &rtwdev->efuse; 2131 2132 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2133 cfo->crystal_cap = cfo->crystal_cap_default; 2134 cfo->def_x_cap = cfo->crystal_cap; 2135 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2136 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2137 cfo->is_adjust = false; 2138 cfo->divergence_lock_en = false; 2139 cfo->x_cap_ofst = 0; 2140 cfo->lock_cnt = 0; 2141 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2142 cfo->apply_compensation = false; 2143 cfo->residual_cfo_acc = 0; 2144 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2145 cfo->crystal_cap_default); 2146 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2147 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2148 rtw89_dcfo_comp_init(rtwdev); 2149 cfo->cfo_timer_ms = 2000; 2150 cfo->cfo_trig_by_timer_en = false; 2151 cfo->phy_cfo_trk_cnt = 0; 2152 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2153 } 2154 2155 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2156 s32 curr_cfo) 2157 { 2158 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2159 s8 crystal_cap = cfo->crystal_cap; 2160 s32 cfo_abs = abs(curr_cfo); 2161 int sign; 2162 2163 if (!cfo->is_adjust) { 2164 if (cfo_abs > CFO_TRK_ENABLE_TH) 2165 cfo->is_adjust = true; 2166 } else { 2167 if (cfo_abs < CFO_TRK_STOP_TH) 2168 cfo->is_adjust = false; 2169 } 2170 if (!cfo->is_adjust) { 2171 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2172 return; 2173 } 2174 sign = curr_cfo > 0 ? 1 : -1; 2175 if (cfo_abs > CFO_TRK_STOP_TH_4) 2176 crystal_cap += 7 * sign; 2177 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2178 crystal_cap += 5 * sign; 2179 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2180 crystal_cap += 3 * sign; 2181 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2182 crystal_cap += 1 * sign; 2183 else 2184 return; 2185 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2186 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2187 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2188 cfo->crystal_cap, cfo->def_x_cap); 2189 } 2190 2191 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2192 { 2193 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2194 s32 cfo_khz_all = 0; 2195 s32 cfo_cnt_all = 0; 2196 s32 cfo_all_avg = 0; 2197 u8 i; 2198 2199 if (rtwdev->total_sta_assoc != 1) 2200 return 0; 2201 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2202 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2203 if (cfo->cfo_cnt[i] == 0) 2204 continue; 2205 cfo_khz_all += cfo->cfo_tail[i]; 2206 cfo_cnt_all += cfo->cfo_cnt[i]; 2207 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2208 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2209 } 2210 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2211 "CFO track for macid = %d\n", i); 2212 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2213 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2214 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2215 return cfo_all_avg; 2216 } 2217 2218 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2219 { 2220 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2221 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2222 s32 target_cfo = 0; 2223 s32 cfo_khz_all = 0; 2224 s32 cfo_khz_all_tp_wgt = 0; 2225 s32 cfo_avg = 0; 2226 s32 max_cfo_lb = BIT(31); 2227 s32 min_cfo_ub = GENMASK(30, 0); 2228 u16 cfo_cnt_all = 0; 2229 u8 active_entry_cnt = 0; 2230 u8 sta_cnt = 0; 2231 u32 tp_all = 0; 2232 u8 i; 2233 u8 cfo_tol = 0; 2234 2235 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2236 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2237 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2238 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2239 if (cfo->cfo_cnt[i] == 0) 2240 continue; 2241 cfo_khz_all += cfo->cfo_tail[i]; 2242 cfo_cnt_all += cfo->cfo_cnt[i]; 2243 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2244 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2245 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2246 cfo_khz_all, cfo_cnt_all, cfo_avg); 2247 target_cfo = cfo_avg; 2248 } 2249 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2250 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2251 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2252 if (cfo->cfo_cnt[i] == 0) 2253 continue; 2254 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2255 (s32)cfo->cfo_cnt[i]); 2256 cfo_khz_all += cfo->cfo_avg[i]; 2257 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2258 "Macid=%d, cfo_avg=%d\n", i, 2259 cfo->cfo_avg[i]); 2260 } 2261 sta_cnt = rtwdev->total_sta_assoc; 2262 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2263 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2264 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2265 cfo_khz_all, sta_cnt, cfo_avg); 2266 target_cfo = cfo_avg; 2267 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2268 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2269 cfo_tol = cfo->sta_cfo_tolerance; 2270 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2271 sta_cnt++; 2272 if (cfo->cfo_cnt[i] != 0) { 2273 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2274 (s32)cfo->cfo_cnt[i]); 2275 active_entry_cnt++; 2276 } else { 2277 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2278 } 2279 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2280 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2281 cfo_khz_all += cfo->cfo_avg[i]; 2282 /* need tp for each entry */ 2283 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2284 "[%d] cfo_avg=%d, tp=tbd\n", 2285 i, cfo->cfo_avg[i]); 2286 if (sta_cnt >= rtwdev->total_sta_assoc) 2287 break; 2288 } 2289 tp_all = stats->rx_throughput; /* need tp for each entry */ 2290 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2291 2292 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2293 sta_cnt); 2294 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2295 active_entry_cnt); 2296 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2297 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2298 cfo_khz_all_tp_wgt, cfo_avg); 2299 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2300 max_cfo_lb, min_cfo_ub); 2301 if (max_cfo_lb <= min_cfo_ub) { 2302 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2303 "cfo win_size=%d\n", 2304 min_cfo_ub - max_cfo_lb); 2305 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2306 } else { 2307 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2308 "No intersection of cfo tolerance windows\n"); 2309 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2310 } 2311 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2312 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2313 } 2314 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2315 return target_cfo; 2316 } 2317 2318 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2319 { 2320 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2321 2322 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2323 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2324 cfo->packet_count = 0; 2325 cfo->packet_count_pre = 0; 2326 cfo->cfo_avg_pre = 0; 2327 } 2328 2329 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2330 { 2331 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2332 s32 new_cfo = 0; 2333 bool x_cap_update = false; 2334 u8 pre_x_cap = cfo->crystal_cap; 2335 2336 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2337 rtwdev->total_sta_assoc); 2338 if (rtwdev->total_sta_assoc == 0) { 2339 rtw89_phy_cfo_reset(rtwdev); 2340 return; 2341 } 2342 if (cfo->packet_count == 0) { 2343 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2344 return; 2345 } 2346 if (cfo->packet_count == cfo->packet_count_pre) { 2347 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2348 return; 2349 } 2350 if (rtwdev->total_sta_assoc == 1) 2351 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2352 else 2353 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2354 if (new_cfo == 0) { 2355 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2356 return; 2357 } 2358 if (cfo->divergence_lock_en) { 2359 cfo->lock_cnt++; 2360 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2361 cfo->divergence_lock_en = false; 2362 cfo->lock_cnt = 0; 2363 } else { 2364 rtw89_phy_cfo_reset(rtwdev); 2365 } 2366 return; 2367 } 2368 if (cfo->crystal_cap >= cfo->x_cap_ub || 2369 cfo->crystal_cap <= cfo->x_cap_lb) { 2370 cfo->divergence_lock_en = true; 2371 rtw89_phy_cfo_reset(rtwdev); 2372 return; 2373 } 2374 2375 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2376 cfo->cfo_avg_pre = new_cfo; 2377 x_cap_update = cfo->crystal_cap != pre_x_cap; 2378 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2379 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2380 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2381 cfo->x_cap_ofst); 2382 if (x_cap_update) { 2383 if (new_cfo > 0) 2384 new_cfo -= CFO_SW_COMP_FINE_TUNE; 2385 else 2386 new_cfo += CFO_SW_COMP_FINE_TUNE; 2387 } 2388 rtw89_dcfo_comp(rtwdev, new_cfo); 2389 rtw89_phy_cfo_statistics_reset(rtwdev); 2390 } 2391 2392 void rtw89_phy_cfo_track_work(struct work_struct *work) 2393 { 2394 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2395 cfo_track_work.work); 2396 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2397 2398 mutex_lock(&rtwdev->mutex); 2399 if (!cfo->cfo_trig_by_timer_en) 2400 goto out; 2401 rtw89_leave_ps_mode(rtwdev); 2402 rtw89_phy_cfo_dm(rtwdev); 2403 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2404 msecs_to_jiffies(cfo->cfo_timer_ms)); 2405 out: 2406 mutex_unlock(&rtwdev->mutex); 2407 } 2408 2409 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2410 { 2411 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2412 2413 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2414 msecs_to_jiffies(cfo->cfo_timer_ms)); 2415 } 2416 2417 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2418 { 2419 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2420 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2421 2422 switch (cfo->phy_cfo_status) { 2423 case RTW89_PHY_DCFO_STATE_NORMAL: 2424 if (stats->tx_throughput >= CFO_TP_UPPER) { 2425 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2426 cfo->cfo_trig_by_timer_en = true; 2427 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2428 rtw89_phy_cfo_start_work(rtwdev); 2429 } 2430 break; 2431 case RTW89_PHY_DCFO_STATE_ENHANCE: 2432 if (cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) { 2433 cfo->phy_cfo_trk_cnt = 0; 2434 cfo->cfo_trig_by_timer_en = false; 2435 } 2436 if (cfo->cfo_trig_by_timer_en == 1) 2437 cfo->phy_cfo_trk_cnt++; 2438 if (stats->tx_throughput <= CFO_TP_LOWER) { 2439 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2440 cfo->phy_cfo_trk_cnt = 0; 2441 cfo->cfo_trig_by_timer_en = false; 2442 } 2443 break; 2444 default: 2445 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2446 cfo->phy_cfo_trk_cnt = 0; 2447 break; 2448 } 2449 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2450 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2451 stats->tx_throughput, cfo->phy_cfo_status, 2452 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2453 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2454 if (cfo->cfo_trig_by_timer_en) 2455 return; 2456 rtw89_phy_cfo_dm(rtwdev); 2457 } 2458 2459 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2460 struct rtw89_rx_phy_ppdu *phy_ppdu) 2461 { 2462 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2463 u8 macid = phy_ppdu->mac_id; 2464 2465 cfo->cfo_tail[macid] += cfo_val; 2466 cfo->cfo_cnt[macid]++; 2467 cfo->packet_count++; 2468 } 2469 2470 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 2471 { 2472 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2473 int i; 2474 u8 th; 2475 2476 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 2477 th = rtw89_chip_get_thermal(rtwdev, i); 2478 if (th) 2479 ewma_thermal_add(&phystat->avg_thermal[i], th); 2480 2481 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2482 "path(%d) thermal cur=%u avg=%ld", i, th, 2483 ewma_thermal_read(&phystat->avg_thermal[i])); 2484 } 2485 } 2486 2487 struct rtw89_phy_iter_rssi_data { 2488 struct rtw89_dev *rtwdev; 2489 struct rtw89_phy_ch_info *ch_info; 2490 bool rssi_changed; 2491 }; 2492 2493 static void rtw89_phy_stat_rssi_update_iter(void *data, 2494 struct ieee80211_sta *sta) 2495 { 2496 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2497 struct rtw89_phy_iter_rssi_data *rssi_data = 2498 (struct rtw89_phy_iter_rssi_data *)data; 2499 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 2500 unsigned long rssi_curr; 2501 2502 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 2503 2504 if (rssi_curr < ch_info->rssi_min) { 2505 ch_info->rssi_min = rssi_curr; 2506 ch_info->rssi_min_macid = rtwsta->mac_id; 2507 } 2508 2509 if (rtwsta->prev_rssi == 0) { 2510 rtwsta->prev_rssi = rssi_curr; 2511 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 2512 rtwsta->prev_rssi = rssi_curr; 2513 rssi_data->rssi_changed = true; 2514 } 2515 } 2516 2517 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 2518 { 2519 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 2520 2521 rssi_data.rtwdev = rtwdev; 2522 rssi_data.ch_info = &rtwdev->ch_info; 2523 rssi_data.ch_info->rssi_min = U8_MAX; 2524 ieee80211_iterate_stations_atomic(rtwdev->hw, 2525 rtw89_phy_stat_rssi_update_iter, 2526 &rssi_data); 2527 if (rssi_data.rssi_changed) 2528 rtw89_btc_ntfy_wl_sta(rtwdev); 2529 } 2530 2531 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 2532 { 2533 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2534 int i; 2535 2536 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2537 ewma_thermal_init(&phystat->avg_thermal[i]); 2538 2539 rtw89_phy_stat_thermal_update(rtwdev); 2540 2541 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2542 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 2543 } 2544 2545 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 2546 { 2547 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2548 2549 rtw89_phy_stat_thermal_update(rtwdev); 2550 rtw89_phy_stat_rssi_update(rtwdev); 2551 2552 phystat->last_pkt_stat = phystat->cur_pkt_stat; 2553 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2554 } 2555 2556 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 2557 { 2558 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2559 2560 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2561 } 2562 2563 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 2564 { 2565 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2566 2567 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2568 } 2569 2570 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 2571 { 2572 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2573 2574 env->ccx_manual_ctrl = false; 2575 env->ccx_ongoing = false; 2576 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2577 env->ccx_rpt_stamp = 0; 2578 env->ccx_period = 0; 2579 env->ccx_unit_idx = RTW89_CCX_32_US; 2580 env->ccx_trigger_time = 0; 2581 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 2582 2583 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 2584 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 2585 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2586 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 2587 RTW89_CCX_EDCCA_BW20_0); 2588 } 2589 2590 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 2591 u16 score) 2592 { 2593 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2594 u32 numer = 0; 2595 u16 ret = 0; 2596 2597 numer = report * score + (env->ccx_period >> 1); 2598 if (env->ccx_period) 2599 ret = numer / env->ccx_period; 2600 2601 return ret >= score ? score - 1 : ret; 2602 } 2603 2604 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 2605 u16 time_ms, u32 *period, 2606 u32 *unit_idx) 2607 { 2608 u32 idx; 2609 u8 quotient; 2610 2611 if (time_ms >= CCX_MAX_PERIOD) 2612 time_ms = CCX_MAX_PERIOD; 2613 2614 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 2615 2616 if (quotient < 4) 2617 idx = RTW89_CCX_4_US; 2618 else if (quotient < 8) 2619 idx = RTW89_CCX_8_US; 2620 else if (quotient < 16) 2621 idx = RTW89_CCX_16_US; 2622 else 2623 idx = RTW89_CCX_32_US; 2624 2625 *unit_idx = idx; 2626 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 2627 2628 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2629 "[Trigger Time] period:%d, unit_idx:%d\n", 2630 *period, *unit_idx); 2631 } 2632 2633 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 2634 { 2635 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2636 2637 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2638 "lv:(%d)->(0)\n", env->ccx_rac_lv); 2639 2640 env->ccx_ongoing = false; 2641 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2642 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2643 } 2644 2645 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 2646 struct rtw89_ccx_para_info *para) 2647 { 2648 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2649 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 2650 u8 i = 0; 2651 u16 *ifs_th_l = env->ifs_clm_th_l; 2652 u16 *ifs_th_h = env->ifs_clm_th_h; 2653 u32 ifs_th0_us = 0, ifs_th_times = 0; 2654 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 2655 2656 if (!is_update) 2657 goto ifs_update_finished; 2658 2659 switch (para->ifs_clm_app) { 2660 case RTW89_IFS_CLM_INIT: 2661 case RTW89_IFS_CLM_BACKGROUND: 2662 case RTW89_IFS_CLM_ACS: 2663 case RTW89_IFS_CLM_DBG: 2664 case RTW89_IFS_CLM_DIG: 2665 case RTW89_IFS_CLM_TDMA_DIG: 2666 ifs_th0_us = IFS_CLM_TH0_UPPER; 2667 ifs_th_times = IFS_CLM_TH_MUL; 2668 break; 2669 case RTW89_IFS_CLM_DBG_MANUAL: 2670 ifs_th0_us = para->ifs_clm_manual_th0; 2671 ifs_th_times = para->ifs_clm_manual_th_times; 2672 break; 2673 default: 2674 break; 2675 } 2676 2677 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 2678 * low[i] = high[i-1] + 1 2679 * high[i] = high[i-1] * ifs_th_times 2680 */ 2681 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 2682 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 2683 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 2684 ifs_th0_us); 2685 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 2686 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 2687 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 2688 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 2689 } 2690 2691 ifs_update_finished: 2692 if (!is_update) 2693 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2694 "No need to update IFS_TH\n"); 2695 2696 return is_update; 2697 } 2698 2699 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 2700 { 2701 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2702 u8 i = 0; 2703 2704 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 2705 env->ifs_clm_th_l[0]); 2706 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 2707 env->ifs_clm_th_l[1]); 2708 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 2709 env->ifs_clm_th_l[2]); 2710 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 2711 env->ifs_clm_th_l[3]); 2712 2713 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 2714 env->ifs_clm_th_h[0]); 2715 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 2716 env->ifs_clm_th_h[1]); 2717 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 2718 env->ifs_clm_th_h[2]); 2719 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 2720 env->ifs_clm_th_h[3]); 2721 2722 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2723 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2724 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 2725 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 2726 } 2727 2728 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 2729 { 2730 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2731 struct rtw89_ccx_para_info para = {0}; 2732 2733 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2734 env->ifs_clm_mntr_time = 0; 2735 2736 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 2737 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 2738 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 2739 2740 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 2741 true); 2742 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 2743 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 2744 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 2745 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 2746 } 2747 2748 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 2749 enum rtw89_env_racing_lv level) 2750 { 2751 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2752 int ret = 0; 2753 2754 if (level >= RTW89_RAC_MAX_NUM) { 2755 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2756 "[WARNING] Wrong LV=%d\n", level); 2757 return -EINVAL; 2758 } 2759 2760 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2761 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 2762 env->ccx_rac_lv, level); 2763 2764 if (env->ccx_ongoing) { 2765 if (level <= env->ccx_rac_lv) 2766 ret = -EINVAL; 2767 else 2768 env->ccx_ongoing = false; 2769 } 2770 2771 if (ret == 0) 2772 env->ccx_rac_lv = level; 2773 2774 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 2775 !ret); 2776 2777 return ret; 2778 } 2779 2780 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 2781 { 2782 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2783 2784 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 2785 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 2786 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 2787 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2788 2789 env->ccx_rpt_stamp++; 2790 env->ccx_ongoing = true; 2791 } 2792 2793 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 2794 { 2795 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2796 u8 i = 0; 2797 u32 res = 0; 2798 2799 env->ifs_clm_tx_ratio = 2800 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 2801 env->ifs_clm_edcca_excl_cca_ratio = 2802 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 2803 PERCENT); 2804 env->ifs_clm_cck_fa_ratio = 2805 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 2806 env->ifs_clm_ofdm_fa_ratio = 2807 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 2808 env->ifs_clm_cck_cca_excl_fa_ratio = 2809 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 2810 PERCENT); 2811 env->ifs_clm_ofdm_cca_excl_fa_ratio = 2812 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 2813 PERCENT); 2814 env->ifs_clm_cck_fa_permil = 2815 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 2816 env->ifs_clm_ofdm_fa_permil = 2817 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 2818 2819 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 2820 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 2821 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 2822 } else { 2823 env->ifs_clm_ifs_avg[i] = 2824 rtw89_phy_ccx_idx_to_us(rtwdev, 2825 env->ifs_clm_avg[i]); 2826 } 2827 2828 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 2829 res += env->ifs_clm_his[i] >> 1; 2830 if (env->ifs_clm_his[i]) 2831 res /= env->ifs_clm_his[i]; 2832 else 2833 res = 0; 2834 env->ifs_clm_cca_avg[i] = res; 2835 } 2836 2837 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2838 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2839 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 2840 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2841 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 2842 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 2843 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2844 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 2845 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 2846 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2847 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 2848 env->ifs_clm_cck_cca_excl_fa_ratio, 2849 env->ifs_clm_ofdm_cca_excl_fa_ratio); 2850 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2851 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 2852 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2853 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 2854 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 2855 env->ifs_clm_cca_avg[i]); 2856 } 2857 2858 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 2859 { 2860 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2861 u8 i = 0; 2862 2863 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 2864 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2865 "Get IFS_CLM report Fail\n"); 2866 return false; 2867 } 2868 2869 env->ifs_clm_tx = 2870 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2871 B_IFS_CLM_TX_CNT_MSK); 2872 env->ifs_clm_edcca_excl_cca = 2873 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2874 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 2875 env->ifs_clm_cckcca_excl_fa = 2876 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2877 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 2878 env->ifs_clm_ofdmcca_excl_fa = 2879 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2880 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 2881 env->ifs_clm_cckfa = 2882 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2883 B_IFS_CLM_CCK_FA_MSK); 2884 env->ifs_clm_ofdmfa = 2885 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2886 B_IFS_CLM_OFDM_FA_MSK); 2887 2888 env->ifs_clm_his[0] = 2889 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 2890 env->ifs_clm_his[1] = 2891 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 2892 env->ifs_clm_his[2] = 2893 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 2894 env->ifs_clm_his[3] = 2895 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 2896 2897 env->ifs_clm_avg[0] = 2898 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 2899 env->ifs_clm_avg[1] = 2900 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 2901 env->ifs_clm_avg[2] = 2902 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 2903 env->ifs_clm_avg[3] = 2904 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 2905 2906 env->ifs_clm_cca[0] = 2907 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 2908 env->ifs_clm_cca[1] = 2909 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 2910 env->ifs_clm_cca[2] = 2911 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 2912 env->ifs_clm_cca[3] = 2913 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 2914 2915 env->ifs_clm_total_ifs = 2916 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 2917 2918 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 2919 env->ifs_clm_total_ifs); 2920 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2921 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2922 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 2923 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2924 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 2925 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 2926 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2927 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 2928 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 2929 2930 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 2931 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2932 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2933 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 2934 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 2935 2936 rtw89_phy_ifs_clm_get_utility(rtwdev); 2937 2938 return true; 2939 } 2940 2941 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 2942 struct rtw89_ccx_para_info *para) 2943 { 2944 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2945 u32 period = 0; 2946 u32 unit_idx = 0; 2947 2948 if (para->mntr_time == 0) { 2949 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2950 "[WARN] MNTR_TIME is 0\n"); 2951 return -EINVAL; 2952 } 2953 2954 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 2955 return -EINVAL; 2956 2957 if (para->mntr_time != env->ifs_clm_mntr_time) { 2958 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 2959 &period, &unit_idx); 2960 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 2961 B_IFS_CLM_PERIOD_MSK, period); 2962 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 2963 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 2964 2965 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2966 "Update IFS-CLM time ((%d)) -> ((%d))\n", 2967 env->ifs_clm_mntr_time, para->mntr_time); 2968 2969 env->ifs_clm_mntr_time = para->mntr_time; 2970 env->ccx_period = (u16)period; 2971 env->ccx_unit_idx = (u8)unit_idx; 2972 } 2973 2974 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 2975 env->ifs_clm_app = para->ifs_clm_app; 2976 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 2977 } 2978 2979 return 0; 2980 } 2981 2982 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 2983 { 2984 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2985 struct rtw89_ccx_para_info para = {0}; 2986 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 2987 2988 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 2989 if (env->ccx_manual_ctrl) { 2990 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2991 "CCX in manual ctrl\n"); 2992 return; 2993 } 2994 2995 /* only ifs_clm for now */ 2996 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 2997 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 2998 2999 rtw89_phy_ccx_racing_release(rtwdev); 3000 para.mntr_time = 1900; 3001 para.rac_lv = RTW89_RAC_LV_1; 3002 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3003 3004 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3005 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3006 if (chk_result) 3007 rtw89_phy_ccx_trigger(rtwdev); 3008 3009 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3010 "get_result=0x%x, chk_result:0x%x\n", 3011 env->ccx_watchdog_result, chk_result); 3012 } 3013 3014 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3015 { 3016 if (*ie_page > RTW89_PHYSTS_BITMAP_NUM || 3017 *ie_page == RTW89_RSVD_9) 3018 return false; 3019 else if (*ie_page > RTW89_RSVD_9) 3020 *ie_page -= 1; 3021 3022 return true; 3023 } 3024 3025 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3026 { 3027 static const u8 ie_page_shift = 2; 3028 3029 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3030 } 3031 3032 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3033 enum rtw89_phy_status_bitmap ie_page) 3034 { 3035 u32 addr; 3036 3037 if (!rtw89_physts_ie_page_valid(&ie_page)) 3038 return 0; 3039 3040 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3041 3042 return rtw89_phy_read32(rtwdev, addr); 3043 } 3044 3045 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3046 enum rtw89_phy_status_bitmap ie_page, 3047 u32 val) 3048 { 3049 const struct rtw89_chip_info *chip = rtwdev->chip; 3050 u32 addr; 3051 3052 if (!rtw89_physts_ie_page_valid(&ie_page)) 3053 return; 3054 3055 if (chip->chip_id == RTL8852A) 3056 val &= B_PHY_STS_BITMAP_MSK_52A; 3057 3058 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3059 rtw89_phy_write32(rtwdev, addr, val); 3060 } 3061 3062 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3063 enum rtw89_phy_status_bitmap bitmap, 3064 enum rtw89_phy_status_ie_type ie, 3065 bool enable) 3066 { 3067 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3068 3069 if (enable) 3070 val |= BIT(ie); 3071 else 3072 val &= ~BIT(ie); 3073 3074 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3075 } 3076 3077 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3078 bool enable, 3079 enum rtw89_phy_idx phy_idx) 3080 { 3081 if (enable) { 3082 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3083 B_STS_DIS_TRIG_BY_FAIL); 3084 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3085 B_STS_DIS_TRIG_BY_BRK); 3086 } else { 3087 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3088 B_STS_DIS_TRIG_BY_FAIL); 3089 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3090 B_STS_DIS_TRIG_BY_BRK); 3091 } 3092 } 3093 3094 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3095 { 3096 const struct rtw89_chip_info *chip = rtwdev->chip; 3097 u8 i; 3098 3099 if (chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 3100 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3101 3102 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3103 if (i >= RTW89_CCK_PKT) 3104 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3105 RTW89_PHYSTS_IE09_FTR_0, 3106 true); 3107 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3108 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3109 continue; 3110 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3111 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3112 true); 3113 } 3114 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3115 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3116 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3117 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3118 3119 /* force IE01 for channel index, only channel field is valid */ 3120 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3121 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3122 } 3123 3124 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3125 { 3126 const struct rtw89_chip_info *chip = rtwdev->chip; 3127 struct rtw89_dig_info *dig = &rtwdev->dig; 3128 const struct rtw89_phy_dig_gain_cfg *cfg; 3129 const char *msg; 3130 u8 i; 3131 s8 gain_base; 3132 s8 *gain_arr; 3133 u32 tmp; 3134 3135 switch (type) { 3136 case RTW89_DIG_GAIN_LNA_G: 3137 gain_arr = dig->lna_gain_g; 3138 gain_base = LNA0_GAIN; 3139 cfg = chip->dig_table->cfg_lna_g; 3140 msg = "lna_gain_g"; 3141 break; 3142 case RTW89_DIG_GAIN_TIA_G: 3143 gain_arr = dig->tia_gain_g; 3144 gain_base = TIA0_GAIN_G; 3145 cfg = chip->dig_table->cfg_tia_g; 3146 msg = "tia_gain_g"; 3147 break; 3148 case RTW89_DIG_GAIN_LNA_A: 3149 gain_arr = dig->lna_gain_a; 3150 gain_base = LNA0_GAIN; 3151 cfg = chip->dig_table->cfg_lna_a; 3152 msg = "lna_gain_a"; 3153 break; 3154 case RTW89_DIG_GAIN_TIA_A: 3155 gain_arr = dig->tia_gain_a; 3156 gain_base = TIA0_GAIN_A; 3157 cfg = chip->dig_table->cfg_tia_a; 3158 msg = "tia_gain_a"; 3159 break; 3160 default: 3161 return; 3162 } 3163 3164 for (i = 0; i < cfg->size; i++) { 3165 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3166 cfg->table[i].mask); 3167 tmp >>= DIG_GAIN_SHIFT; 3168 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3169 gain_base += DIG_GAIN; 3170 3171 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3172 msg, i, gain_arr[i]); 3173 } 3174 } 3175 3176 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3177 { 3178 struct rtw89_dig_info *dig = &rtwdev->dig; 3179 u32 tmp; 3180 u8 i; 3181 3182 if (!rtwdev->hal.support_igi) 3183 return; 3184 3185 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3186 B_PATH0_IB_PKPW_MSK); 3187 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3188 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3189 B_PATH0_IB_PBK_MSK); 3190 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3191 dig->ib_pkpwr, dig->ib_pbk); 3192 3193 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3194 rtw89_phy_dig_read_gain_table(rtwdev, i); 3195 } 3196 3197 static const u8 rssi_nolink = 22; 3198 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3199 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3200 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3201 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3202 3203 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3204 { 3205 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3206 struct rtw89_dig_info *dig = &rtwdev->dig; 3207 bool is_linked = rtwdev->total_sta_assoc > 0; 3208 3209 if (is_linked) { 3210 dig->igi_rssi = ch_info->rssi_min >> 1; 3211 } else { 3212 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3213 dig->igi_rssi = rssi_nolink; 3214 } 3215 } 3216 3217 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3218 { 3219 struct rtw89_dig_info *dig = &rtwdev->dig; 3220 bool is_linked = rtwdev->total_sta_assoc > 0; 3221 const u16 *fa_th_src = NULL; 3222 3223 switch (rtwdev->hal.current_band_type) { 3224 case RTW89_BAND_2G: 3225 dig->lna_gain = dig->lna_gain_g; 3226 dig->tia_gain = dig->tia_gain_g; 3227 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3228 dig->force_gaincode_idx_en = false; 3229 dig->dyn_pd_th_en = true; 3230 break; 3231 case RTW89_BAND_5G: 3232 default: 3233 dig->lna_gain = dig->lna_gain_a; 3234 dig->tia_gain = dig->tia_gain_a; 3235 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3236 dig->force_gaincode_idx_en = true; 3237 dig->dyn_pd_th_en = true; 3238 break; 3239 } 3240 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3241 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3242 } 3243 3244 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3245 static const u8 igi_max_performance_mode = 0x5a; 3246 static const u8 dynamic_pd_threshold_max; 3247 3248 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3249 { 3250 struct rtw89_dig_info *dig = &rtwdev->dig; 3251 3252 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3253 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3254 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3255 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3256 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3257 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3258 3259 dig->dyn_igi_max = igi_max_performance_mode; 3260 dig->dyn_igi_min = dynamic_igi_min; 3261 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3262 dig->pd_low_th_ofst = pd_low_th_offset; 3263 dig->is_linked_pre = false; 3264 } 3265 3266 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3267 { 3268 rtw89_phy_dig_update_gain_para(rtwdev); 3269 rtw89_phy_dig_reset(rtwdev); 3270 } 3271 3272 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3273 { 3274 struct rtw89_dig_info *dig = &rtwdev->dig; 3275 u8 lna_idx; 3276 3277 if (rssi < dig->igi_rssi_th[0]) 3278 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3279 else if (rssi < dig->igi_rssi_th[1]) 3280 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3281 else if (rssi < dig->igi_rssi_th[2]) 3282 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3283 else if (rssi < dig->igi_rssi_th[3]) 3284 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3285 else if (rssi < dig->igi_rssi_th[4]) 3286 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3287 else 3288 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3289 3290 return lna_idx; 3291 } 3292 3293 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3294 { 3295 struct rtw89_dig_info *dig = &rtwdev->dig; 3296 u8 tia_idx; 3297 3298 if (rssi < dig->igi_rssi_th[0]) 3299 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3300 else 3301 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3302 3303 return tia_idx; 3304 } 3305 3306 #define IB_PBK_BASE 110 3307 #define WB_RSSI_BASE 10 3308 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3309 struct rtw89_agc_gaincode_set *set) 3310 { 3311 struct rtw89_dig_info *dig = &rtwdev->dig; 3312 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3313 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3314 s32 wb_rssi = rssi + lna_gain + tia_gain; 3315 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3316 u8 rxb_idx; 3317 3318 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3319 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3320 3321 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3322 wb_rssi, rxb_idx_tmp); 3323 3324 return rxb_idx; 3325 } 3326 3327 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3328 struct rtw89_agc_gaincode_set *set) 3329 { 3330 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3331 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3332 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3333 3334 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3335 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3336 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3337 } 3338 3339 #define IGI_OFFSET_MAX 25 3340 #define IGI_OFFSET_MUL 2 3341 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3342 { 3343 struct rtw89_dig_info *dig = &rtwdev->dig; 3344 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3345 enum rtw89_dig_noisy_level noisy_lv; 3346 u8 igi_offset = dig->fa_rssi_ofst; 3347 u16 fa_ratio = 0; 3348 3349 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3350 3351 if (fa_ratio < dig->fa_th[0]) 3352 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3353 else if (fa_ratio < dig->fa_th[1]) 3354 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3355 else if (fa_ratio < dig->fa_th[2]) 3356 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3357 else if (fa_ratio < dig->fa_th[3]) 3358 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3359 else 3360 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3361 3362 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3363 igi_offset = 0; 3364 else 3365 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3366 3367 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3368 dig->fa_rssi_ofst = igi_offset; 3369 3370 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3371 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3372 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3373 3374 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3375 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3376 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3377 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3378 noisy_lv, igi_offset); 3379 } 3380 3381 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3382 { 3383 rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT, 3384 B_PATH0_LNA_INIT_IDX_MSK, lna_idx); 3385 rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT, 3386 B_PATH1_LNA_INIT_IDX_MSK, lna_idx); 3387 } 3388 3389 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 3390 { 3391 rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT, 3392 B_PATH0_TIA_INIT_IDX_MSK, tia_idx); 3393 rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT, 3394 B_PATH1_TIA_INIT_IDX_MSK, tia_idx); 3395 } 3396 3397 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 3398 { 3399 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT, 3400 B_PATH0_RXB_INIT_IDX_MSK, rxb_idx); 3401 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT, 3402 B_PATH1_RXB_INIT_IDX_MSK, rxb_idx); 3403 } 3404 3405 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 3406 const struct rtw89_agc_gaincode_set set) 3407 { 3408 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 3409 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 3410 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 3411 3412 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 3413 set.lna_idx, set.tia_idx, set.rxb_idx); 3414 } 3415 3416 static const struct rtw89_reg_def sdagc_config[4] = { 3417 {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3418 {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3419 {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3420 {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3421 }; 3422 3423 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 3424 bool enable) 3425 { 3426 u8 i = 0; 3427 3428 for (i = 0; i < ARRAY_SIZE(sdagc_config); i++) 3429 rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr, 3430 sdagc_config[i].mask, enable); 3431 3432 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 3433 } 3434 3435 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 3436 { 3437 struct rtw89_dig_info *dig = &rtwdev->dig; 3438 3439 if (!rtwdev->hal.support_igi) 3440 return; 3441 3442 if (dig->force_gaincode_idx_en) { 3443 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3444 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3445 "Force gaincode index enabled.\n"); 3446 } else { 3447 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 3448 &dig->cur_gaincode); 3449 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 3450 } 3451 } 3452 3453 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 3454 bool enable) 3455 { 3456 enum rtw89_bandwidth cbw = rtwdev->hal.current_band_width; 3457 struct rtw89_dig_info *dig = &rtwdev->dig; 3458 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 3459 u8 ofdm_cca_th; 3460 s8 cck_cca_th; 3461 u32 pd_val = 0; 3462 3463 under_region += PD_TH_SB_FLTR_CMP_VAL; 3464 3465 switch (cbw) { 3466 case RTW89_CHANNEL_WIDTH_40: 3467 under_region += PD_TH_BW40_CMP_VAL; 3468 break; 3469 case RTW89_CHANNEL_WIDTH_80: 3470 under_region += PD_TH_BW80_CMP_VAL; 3471 break; 3472 case RTW89_CHANNEL_WIDTH_160: 3473 under_region += PD_TH_BW160_CMP_VAL; 3474 break; 3475 case RTW89_CHANNEL_WIDTH_20: 3476 fallthrough; 3477 default: 3478 under_region += PD_TH_BW20_CMP_VAL; 3479 break; 3480 } 3481 3482 dig->dyn_pd_th_max = dig->igi_rssi; 3483 3484 final_rssi = min_t(u8, rssi, dig->igi_rssi); 3485 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 3486 PD_TH_MAX_RSSI + under_region); 3487 3488 if (enable) { 3489 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 3490 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3491 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 3492 final_rssi, ofdm_cca_th, under_region, pd_val); 3493 } else { 3494 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3495 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 3496 } 3497 3498 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK, 3499 pd_val); 3500 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, 3501 B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable); 3502 3503 if (!rtwdev->hal.support_cckpd) 3504 return; 3505 3506 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 3507 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 3508 3509 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3510 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 3511 final_rssi, cck_cca_th, under_region, pd_val); 3512 3513 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 3514 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 3515 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 3516 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 3517 } 3518 3519 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 3520 { 3521 struct rtw89_dig_info *dig = &rtwdev->dig; 3522 3523 dig->bypass_dig = false; 3524 rtw89_phy_dig_para_reset(rtwdev); 3525 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3526 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 3527 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3528 rtw89_phy_dig_update_para(rtwdev); 3529 } 3530 3531 #define IGI_RSSI_MIN 10 3532 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 3533 { 3534 struct rtw89_dig_info *dig = &rtwdev->dig; 3535 bool is_linked = rtwdev->total_sta_assoc > 0; 3536 3537 if (unlikely(dig->bypass_dig)) { 3538 dig->bypass_dig = false; 3539 return; 3540 } 3541 3542 if (!dig->is_linked_pre && is_linked) { 3543 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 3544 rtw89_phy_dig_update_para(rtwdev); 3545 } else if (dig->is_linked_pre && !is_linked) { 3546 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 3547 rtw89_phy_dig_update_para(rtwdev); 3548 } 3549 dig->is_linked_pre = is_linked; 3550 3551 rtw89_phy_dig_igi_offset_by_env(rtwdev); 3552 rtw89_phy_dig_update_rssi_info(rtwdev); 3553 3554 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 3555 dig->igi_rssi - IGI_RSSI_MIN : 0; 3556 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 3557 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 3558 3559 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 3560 dig->dyn_igi_max); 3561 3562 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3563 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 3564 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 3565 dig->igi_fa_rssi); 3566 3567 rtw89_phy_dig_config_igi(rtwdev); 3568 3569 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 3570 3571 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 3572 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 3573 else 3574 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3575 } 3576 3577 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 3578 { 3579 rtw89_phy_ccx_top_setting_init(rtwdev); 3580 rtw89_phy_ifs_clm_setting_init(rtwdev); 3581 } 3582 3583 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 3584 { 3585 const struct rtw89_chip_info *chip = rtwdev->chip; 3586 3587 rtw89_phy_stat_init(rtwdev); 3588 3589 rtw89_chip_bb_sethw(rtwdev); 3590 3591 rtw89_phy_env_monitor_init(rtwdev); 3592 rtw89_physts_parsing_init(rtwdev); 3593 rtw89_phy_dig_init(rtwdev); 3594 rtw89_phy_cfo_init(rtwdev); 3595 3596 rtw89_phy_init_rf_nctl(rtwdev); 3597 rtw89_chip_rfk_init(rtwdev); 3598 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 3599 rtw89_chip_set_txpwr_ctrl(rtwdev); 3600 rtw89_chip_power_trim(rtwdev); 3601 rtw89_chip_cfg_txrx_path(rtwdev); 3602 } 3603 3604 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3605 { 3606 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 3607 u8 bss_color; 3608 3609 if (!vif->bss_conf.he_support || !vif->bss_conf.assoc) 3610 return; 3611 3612 bss_color = vif->bss_conf.he_bss_color.color; 3613 3614 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, 3615 phy_idx); 3616 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, 3617 phy_idx); 3618 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, 3619 vif->bss_conf.aid, phy_idx); 3620 } 3621 3622 static void 3623 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3624 { 3625 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 3626 } 3627 3628 static void 3629 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3630 { 3631 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 3632 } 3633 3634 static void 3635 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3636 { 3637 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 3638 } 3639 3640 static void 3641 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3642 { 3643 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 3644 } 3645 3646 static void 3647 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3648 { 3649 udelay(def->data); 3650 } 3651 3652 static void 3653 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 3654 [RTW89_RFK_F_WRF] = _rfk_write_rf, 3655 [RTW89_RFK_F_WM] = _rfk_write32_mask, 3656 [RTW89_RFK_F_WS] = _rfk_write32_set, 3657 [RTW89_RFK_F_WC] = _rfk_write32_clr, 3658 [RTW89_RFK_F_DELAY] = _rfk_delay, 3659 }; 3660 3661 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 3662 3663 void 3664 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 3665 { 3666 const struct rtw89_reg5_def *p = tbl->defs; 3667 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 3668 3669 for (; p < end; p++) 3670 _rfk_handler[p->flag](rtwdev, p); 3671 } 3672 EXPORT_SYMBOL(rtw89_rfk_parser); 3673 3674 #define RTW89_TSSI_FAST_MODE_NUM 4 3675 3676 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 3677 {0xD934, 0xff0000}, 3678 {0xD934, 0xff000000}, 3679 {0xD938, 0xff}, 3680 {0xD934, 0xff00}, 3681 }; 3682 3683 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 3684 {0xD930, 0xff0000}, 3685 {0xD930, 0xff000000}, 3686 {0xD934, 0xff}, 3687 {0xD930, 0xff00}, 3688 }; 3689 3690 static 3691 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 3692 enum rtw89_mac_idx mac_idx, 3693 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 3694 u32 val) 3695 { 3696 const struct rtw89_reg_def *regs; 3697 u32 reg; 3698 int i; 3699 3700 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 3701 regs = rtw89_tssi_fastmode_regs_flat; 3702 else 3703 regs = rtw89_tssi_fastmode_regs_level; 3704 3705 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 3706 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 3707 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 3708 } 3709 } 3710 3711 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 3712 {0xD91C, 0xff000000}, 3713 {0xD920, 0xff}, 3714 {0xD920, 0xff00}, 3715 {0xD920, 0xff0000}, 3716 {0xD920, 0xff000000}, 3717 {0xD924, 0xff}, 3718 {0xD924, 0xff00}, 3719 {0xD914, 0xff000000}, 3720 {0xD918, 0xff}, 3721 {0xD918, 0xff00}, 3722 {0xD918, 0xff0000}, 3723 {0xD918, 0xff000000}, 3724 {0xD91C, 0xff}, 3725 {0xD91C, 0xff00}, 3726 {0xD91C, 0xff0000}, 3727 }; 3728 3729 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 3730 {0xD910, 0xff}, 3731 {0xD910, 0xff00}, 3732 {0xD910, 0xff0000}, 3733 {0xD910, 0xff000000}, 3734 {0xD914, 0xff}, 3735 {0xD914, 0xff00}, 3736 {0xD914, 0xff0000}, 3737 {0xD908, 0xff}, 3738 {0xD908, 0xff00}, 3739 {0xD908, 0xff0000}, 3740 {0xD908, 0xff000000}, 3741 {0xD90C, 0xff}, 3742 {0xD90C, 0xff00}, 3743 {0xD90C, 0xff0000}, 3744 {0xD90C, 0xff000000}, 3745 }; 3746 3747 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 3748 enum rtw89_mac_idx mac_idx, 3749 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 3750 { 3751 const struct rtw89_chip_info *chip = rtwdev->chip; 3752 const struct rtw89_reg_def *regs; 3753 const u32 *data; 3754 u32 reg; 3755 int i; 3756 3757 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 3758 return; 3759 3760 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 3761 regs = rtw89_tssi_bandedge_regs_flat; 3762 else 3763 regs = rtw89_tssi_bandedge_regs_level; 3764 3765 data = chip->tssi_dbw_table->data[bandedge_cfg]; 3766 3767 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 3768 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 3769 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 3770 } 3771 3772 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 3773 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 3774 3775 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 3776 data[RTW89_TSSI_SBW20]); 3777 } 3778 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 3779