1e3037485SYan-Hsuan Chuang /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2e3037485SYan-Hsuan Chuang /* Copyright(c) 2018-2019 Realtek Corporation
3e3037485SYan-Hsuan Chuang */
4e3037485SYan-Hsuan Chuang
5e3037485SYan-Hsuan Chuang #ifndef __RTW8822B_H__
6e3037485SYan-Hsuan Chuang #define __RTW8822B_H__
7e3037485SYan-Hsuan Chuang
8e3037485SYan-Hsuan Chuang #include <asm/byteorder.h>
9e3037485SYan-Hsuan Chuang
10e3037485SYan-Hsuan Chuang #define RCR_VHT_ACK BIT(26)
11e3037485SYan-Hsuan Chuang
12e3037485SYan-Hsuan Chuang struct rtw8822bu_efuse {
13e3037485SYan-Hsuan Chuang u8 res4[4]; /* 0xd0 */
14e3037485SYan-Hsuan Chuang u8 usb_optional_function;
15e3037485SYan-Hsuan Chuang u8 res5[0x1e];
16e3037485SYan-Hsuan Chuang u8 res6[2];
17e3037485SYan-Hsuan Chuang u8 serial[0x0b]; /* 0xf5 */
18e3037485SYan-Hsuan Chuang u8 vid; /* 0x100 */
19e3037485SYan-Hsuan Chuang u8 res7;
20e3037485SYan-Hsuan Chuang u8 pid;
21e3037485SYan-Hsuan Chuang u8 res8[4];
22e3037485SYan-Hsuan Chuang u8 mac_addr[ETH_ALEN]; /* 0x107 */
23e3037485SYan-Hsuan Chuang u8 res9[2];
24e3037485SYan-Hsuan Chuang u8 vendor_name[0x07];
25e3037485SYan-Hsuan Chuang u8 res10[2];
26e3037485SYan-Hsuan Chuang u8 device_name[0x14];
27e3037485SYan-Hsuan Chuang u8 res11[0xcf];
28e3037485SYan-Hsuan Chuang u8 package_type; /* 0x1fb */
29e3037485SYan-Hsuan Chuang u8 res12[0x4];
30e3037485SYan-Hsuan Chuang };
31e3037485SYan-Hsuan Chuang
32e3037485SYan-Hsuan Chuang struct rtw8822be_efuse {
33e3037485SYan-Hsuan Chuang u8 mac_addr[ETH_ALEN]; /* 0xd0 */
34e3037485SYan-Hsuan Chuang u8 vender_id[2];
35e3037485SYan-Hsuan Chuang u8 device_id[2];
36e3037485SYan-Hsuan Chuang u8 sub_vender_id[2];
37e3037485SYan-Hsuan Chuang u8 sub_device_id[2];
38e3037485SYan-Hsuan Chuang u8 pmc[2];
39e3037485SYan-Hsuan Chuang u8 exp_device_cap[2];
40e3037485SYan-Hsuan Chuang u8 msi_cap;
41e3037485SYan-Hsuan Chuang u8 ltr_cap; /* 0xe3 */
42e3037485SYan-Hsuan Chuang u8 exp_link_control[2];
43e3037485SYan-Hsuan Chuang u8 link_cap[4];
44e3037485SYan-Hsuan Chuang u8 link_control[2];
45e3037485SYan-Hsuan Chuang u8 serial_number[8];
46e3037485SYan-Hsuan Chuang u8 res0:2; /* 0xf4 */
47e3037485SYan-Hsuan Chuang u8 ltr_en:1;
48e3037485SYan-Hsuan Chuang u8 res1:2;
49e3037485SYan-Hsuan Chuang u8 obff:2;
50e3037485SYan-Hsuan Chuang u8 res2:3;
51e3037485SYan-Hsuan Chuang u8 obff_cap:2;
52e3037485SYan-Hsuan Chuang u8 res3:4;
53e3037485SYan-Hsuan Chuang u8 res4[3];
54e3037485SYan-Hsuan Chuang u8 class_code[3];
55e3037485SYan-Hsuan Chuang u8 pci_pm_L1_2_supp:1;
56e3037485SYan-Hsuan Chuang u8 pci_pm_L1_1_supp:1;
57e3037485SYan-Hsuan Chuang u8 aspm_pm_L1_2_supp:1;
58e3037485SYan-Hsuan Chuang u8 aspm_pm_L1_1_supp:1;
59e3037485SYan-Hsuan Chuang u8 L1_pm_substates_supp:1;
60e3037485SYan-Hsuan Chuang u8 res5:3;
61e3037485SYan-Hsuan Chuang u8 port_common_mode_restore_time;
62e3037485SYan-Hsuan Chuang u8 port_t_power_on_scale:2;
63e3037485SYan-Hsuan Chuang u8 res6:1;
64e3037485SYan-Hsuan Chuang u8 port_t_power_on_value:5;
65e3037485SYan-Hsuan Chuang u8 res7;
66e3037485SYan-Hsuan Chuang };
67e3037485SYan-Hsuan Chuang
68*9e688784SMartin Blumenstingl struct rtw8822bs_efuse {
69*9e688784SMartin Blumenstingl u8 res4[0x4a]; /* 0xd0 */
70*9e688784SMartin Blumenstingl u8 mac_addr[ETH_ALEN]; /* 0x11a */
71*9e688784SMartin Blumenstingl } __packed;
72*9e688784SMartin Blumenstingl
73e3037485SYan-Hsuan Chuang struct rtw8822b_efuse {
74e3037485SYan-Hsuan Chuang __le16 rtl_id;
75e3037485SYan-Hsuan Chuang u8 res0[0x0e];
76e3037485SYan-Hsuan Chuang
77e3037485SYan-Hsuan Chuang /* power index for four RF paths */
78e3037485SYan-Hsuan Chuang struct rtw_txpwr_idx txpwr_idx_table[4];
79e3037485SYan-Hsuan Chuang
80e3037485SYan-Hsuan Chuang u8 channel_plan; /* 0xb8 */
81e3037485SYan-Hsuan Chuang u8 xtal_k;
82e3037485SYan-Hsuan Chuang u8 thermal_meter;
83e3037485SYan-Hsuan Chuang u8 iqk_lck;
84e3037485SYan-Hsuan Chuang u8 pa_type; /* 0xbc */
85e3037485SYan-Hsuan Chuang u8 lna_type_2g[2]; /* 0xbd */
86e3037485SYan-Hsuan Chuang u8 lna_type_5g[2];
87e3037485SYan-Hsuan Chuang u8 rf_board_option;
88e3037485SYan-Hsuan Chuang u8 rf_feature_option;
89e3037485SYan-Hsuan Chuang u8 rf_bt_setting;
90e3037485SYan-Hsuan Chuang u8 eeprom_version;
91e3037485SYan-Hsuan Chuang u8 eeprom_customer_id;
92e3037485SYan-Hsuan Chuang u8 tx_bb_swing_setting_2g;
93e3037485SYan-Hsuan Chuang u8 tx_bb_swing_setting_5g;
94e3037485SYan-Hsuan Chuang u8 tx_pwr_calibrate_rate;
95e3037485SYan-Hsuan Chuang u8 rf_antenna_option; /* 0xc9 */
96e3037485SYan-Hsuan Chuang u8 rfe_option;
97e3037485SYan-Hsuan Chuang u8 country_code[2];
98e3037485SYan-Hsuan Chuang u8 res[3];
99e3037485SYan-Hsuan Chuang union {
100e3037485SYan-Hsuan Chuang struct rtw8822be_efuse e;
101*9e688784SMartin Blumenstingl struct rtw8822bu_efuse u;
102*9e688784SMartin Blumenstingl struct rtw8822bs_efuse s;
103e3037485SYan-Hsuan Chuang };
104e3037485SYan-Hsuan Chuang };
105e3037485SYan-Hsuan Chuang
106e3037485SYan-Hsuan Chuang static inline void
_rtw_write32s_mask(struct rtw_dev * rtwdev,u32 addr,u32 mask,u32 data)107e3037485SYan-Hsuan Chuang _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
108e3037485SYan-Hsuan Chuang {
109e3037485SYan-Hsuan Chuang /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
110e3037485SYan-Hsuan Chuang rtw_write32_mask(rtwdev, addr, mask, data);
111e3037485SYan-Hsuan Chuang rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
112e3037485SYan-Hsuan Chuang }
113e3037485SYan-Hsuan Chuang
114e3037485SYan-Hsuan Chuang #define rtw_write32s_mask(rtwdev, addr, mask, data) \
115e3037485SYan-Hsuan Chuang do { \
116e3037485SYan-Hsuan Chuang BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \
117e3037485SYan-Hsuan Chuang \
118e3037485SYan-Hsuan Chuang _rtw_write32s_mask(rtwdev, addr, mask, data); \
119e3037485SYan-Hsuan Chuang } while (0)
120e3037485SYan-Hsuan Chuang
121e3037485SYan-Hsuan Chuang /* phy status page0 */
122e3037485SYan-Hsuan Chuang #define GET_PHY_STAT_P0_PWDB(phy_stat) \
123e3037485SYan-Hsuan Chuang le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
124e3037485SYan-Hsuan Chuang
125e3037485SYan-Hsuan Chuang /* phy status page1 */
126e3037485SYan-Hsuan Chuang #define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
127e3037485SYan-Hsuan Chuang le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
128e3037485SYan-Hsuan Chuang #define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
129e3037485SYan-Hsuan Chuang le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
130e3037485SYan-Hsuan Chuang #define GET_PHY_STAT_P1_RF_MODE(phy_stat) \
131e3037485SYan-Hsuan Chuang le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
132e3037485SYan-Hsuan Chuang #define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
133e3037485SYan-Hsuan Chuang le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
134e3037485SYan-Hsuan Chuang #define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
135e3037485SYan-Hsuan Chuang le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
136082a36dcSTsang-Shian Lin #define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \
137082a36dcSTsang-Shian Lin le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
138082a36dcSTsang-Shian Lin #define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \
139082a36dcSTsang-Shian Lin le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
140082a36dcSTsang-Shian Lin #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \
141082a36dcSTsang-Shian Lin le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
142082a36dcSTsang-Shian Lin #define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \
143082a36dcSTsang-Shian Lin le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
144082a36dcSTsang-Shian Lin #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
145082a36dcSTsang-Shian Lin le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
146082a36dcSTsang-Shian Lin #define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \
147082a36dcSTsang-Shian Lin le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
148e3037485SYan-Hsuan Chuang
1497285eb96SZong-Zhe Yang #define RTW8822B_EDCCA_MAX 0x7f
1507285eb96SZong-Zhe Yang #define RTW8822B_EDCCA_SRC_DEF 1
151e3037485SYan-Hsuan Chuang #define REG_HTSTFWT 0x800
152e3037485SYan-Hsuan Chuang #define REG_RXPSEL 0x808
153e3037485SYan-Hsuan Chuang #define BIT_RX_PSEL_RST (BIT(28) | BIT(29))
154e3037485SYan-Hsuan Chuang #define REG_TXPSEL 0x80c
155e3037485SYan-Hsuan Chuang #define REG_RXCCAMSK 0x814
156e3037485SYan-Hsuan Chuang #define REG_CCASEL 0x82c
157e3037485SYan-Hsuan Chuang #define REG_PDMFTH 0x830
158e3037485SYan-Hsuan Chuang #define REG_CCA2ND 0x838
159e3037485SYan-Hsuan Chuang #define REG_L1WT 0x83c
160e3037485SYan-Hsuan Chuang #define REG_L1PKWT 0x840
161e3037485SYan-Hsuan Chuang #define REG_MRC 0x850
162e3037485SYan-Hsuan Chuang #define REG_CLKTRK 0x860
1637285eb96SZong-Zhe Yang #define REG_EDCCA_POW_MA 0x8a0
1647285eb96SZong-Zhe Yang #define BIT_MA_LEVEL GENMASK(1, 0)
165e3037485SYan-Hsuan Chuang #define REG_ADCCLK 0x8ac
166e3037485SYan-Hsuan Chuang #define REG_ADC160 0x8c4
167e3037485SYan-Hsuan Chuang #define REG_ADC40 0x8c8
1687285eb96SZong-Zhe Yang #define REG_EDCCA_DECISION 0x8dc
1697285eb96SZong-Zhe Yang #define BIT_EDCCA_OPTION BIT(5)
170e3037485SYan-Hsuan Chuang #define REG_CDDTXP 0x93c
171e3037485SYan-Hsuan Chuang #define REG_TXPSEL1 0x940
1727285eb96SZong-Zhe Yang #define REG_EDCCA_SOURCE 0x944
1737285eb96SZong-Zhe Yang #define BIT_SOURCE_OPTION GENMASK(29, 28)
174e3037485SYan-Hsuan Chuang #define REG_ACBB0 0x948
175e3037485SYan-Hsuan Chuang #define REG_ACBBRXFIR 0x94c
176e3037485SYan-Hsuan Chuang #define REG_ACGG2TBL 0x958
177e3037485SYan-Hsuan Chuang #define REG_RXSB 0xa00
178e3037485SYan-Hsuan Chuang #define REG_ADCINI 0xa04
179e3037485SYan-Hsuan Chuang #define REG_TXSF2 0xa24
180e3037485SYan-Hsuan Chuang #define REG_TXSF6 0xa28
181e3037485SYan-Hsuan Chuang #define REG_RXDESC 0xa2c
182e3037485SYan-Hsuan Chuang #define REG_ENTXCCK 0xa80
183e3037485SYan-Hsuan Chuang #define REG_AGCTR_A 0xc08
184e3037485SYan-Hsuan Chuang #define REG_TXDFIR 0xc20
185e3037485SYan-Hsuan Chuang #define REG_RXIGI_A 0xc50
186e3037485SYan-Hsuan Chuang #define REG_TRSW 0xca0
187e3037485SYan-Hsuan Chuang #define REG_RFESEL0 0xcb0
188e3037485SYan-Hsuan Chuang #define REG_RFESEL8 0xcb4
189e3037485SYan-Hsuan Chuang #define REG_RFECTL 0xcb8
190e3037485SYan-Hsuan Chuang #define REG_RFEINV 0xcbc
191e3037485SYan-Hsuan Chuang #define REG_AGCTR_B 0xe08
192e3037485SYan-Hsuan Chuang #define REG_RXIGI_B 0xe50
193e3037485SYan-Hsuan Chuang #define REG_ANTWT 0x1904
194e3037485SYan-Hsuan Chuang #define REG_IQKFAILMSK 0x1bf0
195e3037485SYan-Hsuan Chuang
196f429298dSLarry Finger extern const struct rtw_chip_info rtw8822b_hw_spec;
197f429298dSLarry Finger
198e3037485SYan-Hsuan Chuang #endif
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