1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/bcd.h> 6 7 #include "main.h" 8 #include "reg.h" 9 #include "fw.h" 10 #include "phy.h" 11 #include "debug.h" 12 13 struct phy_cfg_pair { 14 u32 addr; 15 u32 data; 16 }; 17 18 union phy_table_tile { 19 struct rtw_phy_cond cond; 20 struct phy_cfg_pair cfg; 21 }; 22 23 static const u32 db_invert_table[12][8] = { 24 {10, 13, 16, 20, 25 25, 32, 40, 50}, 26 {64, 80, 101, 128, 27 160, 201, 256, 318}, 28 {401, 505, 635, 800, 29 1007, 1268, 1596, 2010}, 30 {316, 398, 501, 631, 31 794, 1000, 1259, 1585}, 32 {1995, 2512, 3162, 3981, 33 5012, 6310, 7943, 10000}, 34 {12589, 15849, 19953, 25119, 35 31623, 39811, 50119, 63098}, 36 {79433, 100000, 125893, 158489, 37 199526, 251189, 316228, 398107}, 38 {501187, 630957, 794328, 1000000, 39 1258925, 1584893, 1995262, 2511886}, 40 {3162278, 3981072, 5011872, 6309573, 41 7943282, 1000000, 12589254, 15848932}, 42 {19952623, 25118864, 31622777, 39810717, 43 50118723, 63095734, 79432823, 100000000}, 44 {125892541, 158489319, 199526232, 251188643, 45 316227766, 398107171, 501187234, 630957345}, 46 {794328235, 1000000000, 1258925412, 1584893192, 47 1995262315, 2511886432U, 3162277660U, 3981071706U} 48 }; 49 50 u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M }; 51 u8 rtw_ofdm_rates[] = { 52 DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, 53 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M, 54 DESC_RATE48M, DESC_RATE54M 55 }; 56 u8 rtw_ht_1s_rates[] = { 57 DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, 58 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5, 59 DESC_RATEMCS6, DESC_RATEMCS7 60 }; 61 u8 rtw_ht_2s_rates[] = { 62 DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10, 63 DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13, 64 DESC_RATEMCS14, DESC_RATEMCS15 65 }; 66 u8 rtw_vht_1s_rates[] = { 67 DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, 68 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3, 69 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5, 70 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7, 71 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9 72 }; 73 u8 rtw_vht_2s_rates[] = { 74 DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, 75 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3, 76 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5, 77 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7, 78 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9 79 }; 80 u8 *rtw_rate_section[RTW_RATE_SECTION_MAX] = { 81 rtw_cck_rates, rtw_ofdm_rates, 82 rtw_ht_1s_rates, rtw_ht_2s_rates, 83 rtw_vht_1s_rates, rtw_vht_2s_rates 84 }; 85 EXPORT_SYMBOL(rtw_rate_section); 86 87 u8 rtw_rate_size[RTW_RATE_SECTION_MAX] = { 88 ARRAY_SIZE(rtw_cck_rates), 89 ARRAY_SIZE(rtw_ofdm_rates), 90 ARRAY_SIZE(rtw_ht_1s_rates), 91 ARRAY_SIZE(rtw_ht_2s_rates), 92 ARRAY_SIZE(rtw_vht_1s_rates), 93 ARRAY_SIZE(rtw_vht_2s_rates) 94 }; 95 EXPORT_SYMBOL(rtw_rate_size); 96 97 static const u8 rtw_cck_size = ARRAY_SIZE(rtw_cck_rates); 98 static const u8 rtw_ofdm_size = ARRAY_SIZE(rtw_ofdm_rates); 99 static const u8 rtw_ht_1s_size = ARRAY_SIZE(rtw_ht_1s_rates); 100 static const u8 rtw_ht_2s_size = ARRAY_SIZE(rtw_ht_2s_rates); 101 static const u8 rtw_vht_1s_size = ARRAY_SIZE(rtw_vht_1s_rates); 102 static const u8 rtw_vht_2s_size = ARRAY_SIZE(rtw_vht_2s_rates); 103 104 enum rtw_phy_band_type { 105 PHY_BAND_2G = 0, 106 PHY_BAND_5G = 1, 107 }; 108 109 static void rtw_phy_cck_pd_init(struct rtw_dev *rtwdev) 110 { 111 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 112 u8 i, j; 113 114 for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) { 115 for (j = 0; j < RTW_RF_PATH_MAX; j++) 116 dm_info->cck_pd_lv[i][j] = CCK_PD_LV0; 117 } 118 119 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 120 } 121 122 void rtw_phy_init(struct rtw_dev *rtwdev) 123 { 124 struct rtw_chip_info *chip = rtwdev->chip; 125 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 126 u32 addr, mask; 127 128 dm_info->fa_history[3] = 0; 129 dm_info->fa_history[2] = 0; 130 dm_info->fa_history[1] = 0; 131 dm_info->fa_history[0] = 0; 132 dm_info->igi_bitmap = 0; 133 dm_info->igi_history[3] = 0; 134 dm_info->igi_history[2] = 0; 135 dm_info->igi_history[1] = 0; 136 137 addr = chip->dig[0].addr; 138 mask = chip->dig[0].mask; 139 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask); 140 rtw_phy_cck_pd_init(rtwdev); 141 142 dm_info->iqk.done = false; 143 } 144 EXPORT_SYMBOL(rtw_phy_init); 145 146 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi) 147 { 148 struct rtw_chip_info *chip = rtwdev->chip; 149 struct rtw_hal *hal = &rtwdev->hal; 150 u32 addr, mask; 151 u8 path; 152 153 if (chip->dig_cck) { 154 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0]; 155 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1); 156 } 157 158 for (path = 0; path < hal->rf_path_num; path++) { 159 addr = chip->dig[path].addr; 160 mask = chip->dig[path].mask; 161 rtw_write32_mask(rtwdev, addr, mask, igi); 162 } 163 } 164 165 static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev) 166 { 167 struct rtw_chip_info *chip = rtwdev->chip; 168 169 chip->ops->false_alarm_statistics(rtwdev); 170 } 171 172 #define RA_FLOOR_TABLE_SIZE 7 173 #define RA_FLOOR_UP_GAP 3 174 175 static u8 rtw_phy_get_rssi_level(u8 old_level, u8 rssi) 176 { 177 u8 table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; 178 u8 new_level = 0; 179 int i; 180 181 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) 182 if (i >= old_level) 183 table[i] += RA_FLOOR_UP_GAP; 184 185 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 186 if (rssi < table[i]) { 187 new_level = i; 188 break; 189 } 190 } 191 192 return new_level; 193 } 194 195 struct rtw_phy_stat_iter_data { 196 struct rtw_dev *rtwdev; 197 u8 min_rssi; 198 }; 199 200 static void rtw_phy_stat_rssi_iter(void *data, struct ieee80211_sta *sta) 201 { 202 struct rtw_phy_stat_iter_data *iter_data = data; 203 struct rtw_dev *rtwdev = iter_data->rtwdev; 204 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 205 u8 rssi; 206 207 rssi = ewma_rssi_read(&si->avg_rssi); 208 si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi); 209 210 rtw_fw_send_rssi_info(rtwdev, si); 211 212 iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi); 213 } 214 215 static void rtw_phy_stat_rssi(struct rtw_dev *rtwdev) 216 { 217 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 218 struct rtw_phy_stat_iter_data data = {}; 219 220 data.rtwdev = rtwdev; 221 data.min_rssi = U8_MAX; 222 rtw_iterate_stas_atomic(rtwdev, rtw_phy_stat_rssi_iter, &data); 223 224 dm_info->pre_min_rssi = dm_info->min_rssi; 225 dm_info->min_rssi = data.min_rssi; 226 } 227 228 static void rtw_phy_stat_rate_cnt(struct rtw_dev *rtwdev) 229 { 230 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 231 232 dm_info->last_pkt_count = dm_info->cur_pkt_count; 233 memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count)); 234 } 235 236 static void rtw_phy_statistics(struct rtw_dev *rtwdev) 237 { 238 rtw_phy_stat_rssi(rtwdev); 239 rtw_phy_stat_false_alarm(rtwdev); 240 rtw_phy_stat_rate_cnt(rtwdev); 241 } 242 243 #define DIG_PERF_FA_TH_LOW 250 244 #define DIG_PERF_FA_TH_HIGH 500 245 #define DIG_PERF_FA_TH_EXTRA_HIGH 750 246 #define DIG_PERF_MAX 0x5a 247 #define DIG_PERF_MID 0x40 248 #define DIG_CVRG_FA_TH_LOW 2000 249 #define DIG_CVRG_FA_TH_HIGH 4000 250 #define DIG_CVRG_FA_TH_EXTRA_HIGH 5000 251 #define DIG_CVRG_MAX 0x2a 252 #define DIG_CVRG_MID 0x26 253 #define DIG_CVRG_MIN 0x1c 254 #define DIG_RSSI_GAIN_OFFSET 15 255 256 static bool 257 rtw_phy_dig_check_damping(struct rtw_dm_info *dm_info) 258 { 259 u16 fa_lo = DIG_PERF_FA_TH_LOW; 260 u16 fa_hi = DIG_PERF_FA_TH_HIGH; 261 u16 *fa_history; 262 u8 *igi_history; 263 u8 damping_rssi; 264 u8 min_rssi; 265 u8 diff; 266 u8 igi_bitmap; 267 bool damping = false; 268 269 min_rssi = dm_info->min_rssi; 270 if (dm_info->damping) { 271 damping_rssi = dm_info->damping_rssi; 272 diff = min_rssi > damping_rssi ? min_rssi - damping_rssi : 273 damping_rssi - min_rssi; 274 if (diff > 3 || dm_info->damping_cnt++ > 20) { 275 dm_info->damping = false; 276 return false; 277 } 278 279 return true; 280 } 281 282 igi_history = dm_info->igi_history; 283 fa_history = dm_info->fa_history; 284 igi_bitmap = dm_info->igi_bitmap & 0xf; 285 switch (igi_bitmap) { 286 case 5: 287 /* down -> up -> down -> up */ 288 if (igi_history[0] > igi_history[1] && 289 igi_history[2] > igi_history[3] && 290 igi_history[0] - igi_history[1] >= 2 && 291 igi_history[2] - igi_history[3] >= 2 && 292 fa_history[0] > fa_hi && fa_history[1] < fa_lo && 293 fa_history[2] > fa_hi && fa_history[3] < fa_lo) 294 damping = true; 295 break; 296 case 9: 297 /* up -> down -> down -> up */ 298 if (igi_history[0] > igi_history[1] && 299 igi_history[3] > igi_history[2] && 300 igi_history[0] - igi_history[1] >= 4 && 301 igi_history[3] - igi_history[2] >= 2 && 302 fa_history[0] > fa_hi && fa_history[1] < fa_lo && 303 fa_history[2] < fa_lo && fa_history[3] > fa_hi) 304 damping = true; 305 break; 306 default: 307 return false; 308 } 309 310 if (damping) { 311 dm_info->damping = true; 312 dm_info->damping_cnt = 0; 313 dm_info->damping_rssi = min_rssi; 314 } 315 316 return damping; 317 } 318 319 static void rtw_phy_dig_get_boundary(struct rtw_dm_info *dm_info, 320 u8 *upper, u8 *lower, bool linked) 321 { 322 u8 dig_max, dig_min, dig_mid; 323 u8 min_rssi; 324 325 if (linked) { 326 dig_max = DIG_PERF_MAX; 327 dig_mid = DIG_PERF_MID; 328 /* 22B=0x1c, 22C=0x20 */ 329 dig_min = 0x1c; 330 min_rssi = max_t(u8, dm_info->min_rssi, dig_min); 331 } else { 332 dig_max = DIG_CVRG_MAX; 333 dig_mid = DIG_CVRG_MID; 334 dig_min = DIG_CVRG_MIN; 335 min_rssi = dig_min; 336 } 337 338 /* DIG MAX should be bounded by minimum RSSI with offset +15 */ 339 dig_max = min_t(u8, dig_max, min_rssi + DIG_RSSI_GAIN_OFFSET); 340 341 *lower = clamp_t(u8, min_rssi, dig_min, dig_mid); 342 *upper = clamp_t(u8, *lower + DIG_RSSI_GAIN_OFFSET, dig_min, dig_max); 343 } 344 345 static void rtw_phy_dig_get_threshold(struct rtw_dm_info *dm_info, 346 u16 *fa_th, u8 *step, bool linked) 347 { 348 u8 min_rssi, pre_min_rssi; 349 350 min_rssi = dm_info->min_rssi; 351 pre_min_rssi = dm_info->pre_min_rssi; 352 step[0] = 4; 353 step[1] = 3; 354 step[2] = 2; 355 356 if (linked) { 357 fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH; 358 fa_th[1] = DIG_PERF_FA_TH_HIGH; 359 fa_th[2] = DIG_PERF_FA_TH_LOW; 360 if (pre_min_rssi > min_rssi) { 361 step[0] = 6; 362 step[1] = 4; 363 step[2] = 2; 364 } 365 } else { 366 fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH; 367 fa_th[1] = DIG_CVRG_FA_TH_HIGH; 368 fa_th[2] = DIG_CVRG_FA_TH_LOW; 369 } 370 } 371 372 static void rtw_phy_dig_recorder(struct rtw_dm_info *dm_info, u8 igi, u16 fa) 373 { 374 u8 *igi_history; 375 u16 *fa_history; 376 u8 igi_bitmap; 377 bool up; 378 379 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe; 380 igi_history = dm_info->igi_history; 381 fa_history = dm_info->fa_history; 382 383 up = igi > igi_history[0]; 384 igi_bitmap |= up; 385 386 igi_history[3] = igi_history[2]; 387 igi_history[2] = igi_history[1]; 388 igi_history[1] = igi_history[0]; 389 igi_history[0] = igi; 390 391 fa_history[3] = fa_history[2]; 392 fa_history[2] = fa_history[1]; 393 fa_history[1] = fa_history[0]; 394 fa_history[0] = fa; 395 396 dm_info->igi_bitmap = igi_bitmap; 397 } 398 399 static void rtw_phy_dig(struct rtw_dev *rtwdev) 400 { 401 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 402 u8 upper_bound, lower_bound; 403 u8 pre_igi, cur_igi; 404 u16 fa_th[3], fa_cnt; 405 u8 level; 406 u8 step[3]; 407 bool linked; 408 409 if (test_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags)) 410 return; 411 412 if (rtw_phy_dig_check_damping(dm_info)) 413 return; 414 415 linked = !!rtwdev->sta_cnt; 416 417 fa_cnt = dm_info->total_fa_cnt; 418 pre_igi = dm_info->igi_history[0]; 419 420 rtw_phy_dig_get_threshold(dm_info, fa_th, step, linked); 421 422 /* test the false alarm count from the highest threshold level first, 423 * and increase it by corresponding step size 424 * 425 * note that the step size is offset by -2, compensate it afterall 426 */ 427 cur_igi = pre_igi; 428 for (level = 0; level < 3; level++) { 429 if (fa_cnt > fa_th[level]) { 430 cur_igi += step[level]; 431 break; 432 } 433 } 434 cur_igi -= 2; 435 436 /* calculate the upper/lower bound by the minimum rssi we have among 437 * the peers connected with us, meanwhile make sure the igi value does 438 * not beyond the hardware limitation 439 */ 440 rtw_phy_dig_get_boundary(dm_info, &upper_bound, &lower_bound, linked); 441 cur_igi = clamp_t(u8, cur_igi, lower_bound, upper_bound); 442 443 /* record current igi value and false alarm statistics for further 444 * damping checks, and record the trend of igi values 445 */ 446 rtw_phy_dig_recorder(dm_info, cur_igi, fa_cnt); 447 448 if (cur_igi != pre_igi) 449 rtw_phy_dig_write(rtwdev, cur_igi); 450 } 451 452 static void rtw_phy_ra_info_update_iter(void *data, struct ieee80211_sta *sta) 453 { 454 struct rtw_dev *rtwdev = data; 455 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 456 457 rtw_update_sta_info(rtwdev, si); 458 } 459 460 static void rtw_phy_ra_info_update(struct rtw_dev *rtwdev) 461 { 462 if (rtwdev->watch_dog_cnt & 0x3) 463 return; 464 465 rtw_iterate_stas_atomic(rtwdev, rtw_phy_ra_info_update_iter, rtwdev); 466 } 467 468 static u32 rtw_phy_get_rrsr_mask(struct rtw_dev *rtwdev, u8 rate_idx) 469 { 470 u8 rate_order; 471 472 rate_order = rate_idx; 473 474 if (rate_idx >= DESC_RATEVHT4SS_MCS0) 475 rate_order -= DESC_RATEVHT4SS_MCS0; 476 else if (rate_idx >= DESC_RATEVHT3SS_MCS0) 477 rate_order -= DESC_RATEVHT3SS_MCS0; 478 else if (rate_idx >= DESC_RATEVHT2SS_MCS0) 479 rate_order -= DESC_RATEVHT2SS_MCS0; 480 else if (rate_idx >= DESC_RATEVHT1SS_MCS0) 481 rate_order -= DESC_RATEVHT1SS_MCS0; 482 else if (rate_idx >= DESC_RATEMCS24) 483 rate_order -= DESC_RATEMCS24; 484 else if (rate_idx >= DESC_RATEMCS16) 485 rate_order -= DESC_RATEMCS16; 486 else if (rate_idx >= DESC_RATEMCS8) 487 rate_order -= DESC_RATEMCS8; 488 else if (rate_idx >= DESC_RATEMCS0) 489 rate_order -= DESC_RATEMCS0; 490 else if (rate_idx >= DESC_RATE6M) 491 rate_order -= DESC_RATE6M; 492 else 493 rate_order -= DESC_RATE1M; 494 495 if (rate_idx >= DESC_RATEMCS0 || rate_order == 0) 496 rate_order++; 497 498 return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0); 499 } 500 501 static void rtw_phy_rrsr_mask_min_iter(void *data, struct ieee80211_sta *sta) 502 { 503 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 504 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 505 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 506 u32 mask = 0; 507 508 mask = rtw_phy_get_rrsr_mask(rtwdev, si->ra_report.desc_rate); 509 if (mask < dm_info->rrsr_mask_min) 510 dm_info->rrsr_mask_min = mask; 511 } 512 513 static void rtw_phy_rrsr_update(struct rtw_dev *rtwdev) 514 { 515 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 516 517 dm_info->rrsr_mask_min = RRSR_RATE_ORDER_MAX; 518 rtw_iterate_stas_atomic(rtwdev, rtw_phy_rrsr_mask_min_iter, rtwdev); 519 rtw_write32(rtwdev, REG_RRSR, dm_info->rrsr_val_init & dm_info->rrsr_mask_min); 520 } 521 522 static void rtw_phy_dpk_track(struct rtw_dev *rtwdev) 523 { 524 struct rtw_chip_info *chip = rtwdev->chip; 525 526 if (chip->ops->dpk_track) 527 chip->ops->dpk_track(rtwdev); 528 } 529 530 #define CCK_PD_FA_LV1_MIN 1000 531 #define CCK_PD_FA_LV0_MAX 500 532 533 static u8 rtw_phy_cck_pd_lv_unlink(struct rtw_dev *rtwdev) 534 { 535 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 536 u32 cck_fa_avg = dm_info->cck_fa_avg; 537 538 if (cck_fa_avg > CCK_PD_FA_LV1_MIN) 539 return CCK_PD_LV1; 540 541 if (cck_fa_avg < CCK_PD_FA_LV0_MAX) 542 return CCK_PD_LV0; 543 544 return CCK_PD_LV_MAX; 545 } 546 547 #define CCK_PD_IGI_LV4_VAL 0x38 548 #define CCK_PD_IGI_LV3_VAL 0x2a 549 #define CCK_PD_IGI_LV2_VAL 0x24 550 #define CCK_PD_RSSI_LV4_VAL 32 551 #define CCK_PD_RSSI_LV3_VAL 32 552 #define CCK_PD_RSSI_LV2_VAL 24 553 554 static u8 rtw_phy_cck_pd_lv_link(struct rtw_dev *rtwdev) 555 { 556 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 557 u8 igi = dm_info->igi_history[0]; 558 u8 rssi = dm_info->min_rssi; 559 u32 cck_fa_avg = dm_info->cck_fa_avg; 560 561 if (igi > CCK_PD_IGI_LV4_VAL && rssi > CCK_PD_RSSI_LV4_VAL) 562 return CCK_PD_LV4; 563 if (igi > CCK_PD_IGI_LV3_VAL && rssi > CCK_PD_RSSI_LV3_VAL) 564 return CCK_PD_LV3; 565 if (igi > CCK_PD_IGI_LV2_VAL || rssi > CCK_PD_RSSI_LV2_VAL) 566 return CCK_PD_LV2; 567 if (cck_fa_avg > CCK_PD_FA_LV1_MIN) 568 return CCK_PD_LV1; 569 if (cck_fa_avg < CCK_PD_FA_LV0_MAX) 570 return CCK_PD_LV0; 571 572 return CCK_PD_LV_MAX; 573 } 574 575 static u8 rtw_phy_cck_pd_lv(struct rtw_dev *rtwdev) 576 { 577 if (!rtw_is_assoc(rtwdev)) 578 return rtw_phy_cck_pd_lv_unlink(rtwdev); 579 else 580 return rtw_phy_cck_pd_lv_link(rtwdev); 581 } 582 583 static void rtw_phy_cck_pd(struct rtw_dev *rtwdev) 584 { 585 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 586 struct rtw_chip_info *chip = rtwdev->chip; 587 u32 cck_fa = dm_info->cck_fa_cnt; 588 u8 level; 589 590 if (rtwdev->hal.current_band_type != RTW_BAND_2G) 591 return; 592 593 if (dm_info->cck_fa_avg == CCK_FA_AVG_RESET) 594 dm_info->cck_fa_avg = cck_fa; 595 else 596 dm_info->cck_fa_avg = (dm_info->cck_fa_avg * 3 + cck_fa) >> 2; 597 598 rtw_dbg(rtwdev, RTW_DBG_PHY, "IGI=0x%x, rssi_min=%d, cck_fa=%d\n", 599 dm_info->igi_history[0], dm_info->min_rssi, 600 dm_info->fa_history[0]); 601 rtw_dbg(rtwdev, RTW_DBG_PHY, "cck_fa_avg=%d, cck_pd_default=%d\n", 602 dm_info->cck_fa_avg, dm_info->cck_pd_default); 603 604 level = rtw_phy_cck_pd_lv(rtwdev); 605 606 if (level >= CCK_PD_LV_MAX) 607 return; 608 609 if (chip->ops->cck_pd_set) 610 chip->ops->cck_pd_set(rtwdev, level); 611 } 612 613 static void rtw_phy_pwr_track(struct rtw_dev *rtwdev) 614 { 615 rtwdev->chip->ops->pwr_track(rtwdev); 616 } 617 618 static void rtw_phy_ra_track(struct rtw_dev *rtwdev) 619 { 620 rtw_phy_ra_info_update(rtwdev); 621 rtw_phy_rrsr_update(rtwdev); 622 } 623 624 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev) 625 { 626 /* for further calculation */ 627 rtw_phy_statistics(rtwdev); 628 rtw_phy_dig(rtwdev); 629 rtw_phy_cck_pd(rtwdev); 630 rtw_phy_ra_track(rtwdev); 631 rtw_phy_dpk_track(rtwdev); 632 rtw_phy_pwr_track(rtwdev); 633 } 634 635 #define FRAC_BITS 3 636 637 static u8 rtw_phy_power_2_db(s8 power) 638 { 639 if (power <= -100 || power >= 20) 640 return 0; 641 else if (power >= 0) 642 return 100; 643 else 644 return 100 + power; 645 } 646 647 static u64 rtw_phy_db_2_linear(u8 power_db) 648 { 649 u8 i, j; 650 u64 linear; 651 652 if (power_db > 96) 653 power_db = 96; 654 else if (power_db < 1) 655 return 1; 656 657 /* 1dB ~ 96dB */ 658 i = (power_db - 1) >> 3; 659 j = (power_db - 1) - (i << 3); 660 661 linear = db_invert_table[i][j]; 662 linear = i > 2 ? linear << FRAC_BITS : linear; 663 664 return linear; 665 } 666 667 static u8 rtw_phy_linear_2_db(u64 linear) 668 { 669 u8 i; 670 u8 j; 671 u32 dB; 672 673 if (linear >= db_invert_table[11][7]) 674 return 96; /* maximum 96 dB */ 675 676 for (i = 0; i < 12; i++) { 677 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][7]) 678 break; 679 else if (i > 2 && linear <= db_invert_table[i][7]) 680 break; 681 } 682 683 for (j = 0; j < 8; j++) { 684 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j]) 685 break; 686 else if (i > 2 && linear <= db_invert_table[i][j]) 687 break; 688 } 689 690 if (j == 0 && i == 0) 691 goto end; 692 693 if (j == 0) { 694 if (i != 3) { 695 if (db_invert_table[i][0] - linear > 696 linear - db_invert_table[i - 1][7]) { 697 i = i - 1; 698 j = 7; 699 } 700 } else { 701 if (db_invert_table[3][0] - linear > 702 linear - db_invert_table[2][7]) { 703 i = 2; 704 j = 7; 705 } 706 } 707 } else { 708 if (db_invert_table[i][j] - linear > 709 linear - db_invert_table[i][j - 1]) { 710 j = j - 1; 711 } 712 } 713 end: 714 dB = (i << 3) + j + 1; 715 716 return dB; 717 } 718 719 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num) 720 { 721 s8 power; 722 u8 power_db; 723 u64 linear; 724 u64 sum = 0; 725 u8 path; 726 727 for (path = 0; path < path_num; path++) { 728 power = rf_power[path]; 729 power_db = rtw_phy_power_2_db(power); 730 linear = rtw_phy_db_2_linear(power_db); 731 sum += linear; 732 } 733 734 sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS; 735 switch (path_num) { 736 case 2: 737 sum >>= 1; 738 break; 739 case 3: 740 sum = ((sum) + ((sum) << 1) + ((sum) << 3)) >> 5; 741 break; 742 case 4: 743 sum >>= 2; 744 break; 745 default: 746 break; 747 } 748 749 return rtw_phy_linear_2_db(sum); 750 } 751 EXPORT_SYMBOL(rtw_phy_rf_power_2_rssi); 752 753 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 754 u32 addr, u32 mask) 755 { 756 struct rtw_hal *hal = &rtwdev->hal; 757 struct rtw_chip_info *chip = rtwdev->chip; 758 const u32 *base_addr = chip->rf_base_addr; 759 u32 val, direct_addr; 760 761 if (rf_path >= hal->rf_phy_num) { 762 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 763 return INV_RF_DATA; 764 } 765 766 addr &= 0xff; 767 direct_addr = base_addr[rf_path] + (addr << 2); 768 mask &= RFREG_MASK; 769 770 val = rtw_read32_mask(rtwdev, direct_addr, mask); 771 772 return val; 773 } 774 EXPORT_SYMBOL(rtw_phy_read_rf); 775 776 u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 777 u32 addr, u32 mask) 778 { 779 struct rtw_hal *hal = &rtwdev->hal; 780 struct rtw_chip_info *chip = rtwdev->chip; 781 const struct rtw_rf_sipi_addr *rf_sipi_addr; 782 const struct rtw_rf_sipi_addr *rf_sipi_addr_a; 783 u32 val32; 784 u32 en_pi; 785 u32 r_addr; 786 u32 shift; 787 788 if (rf_path >= hal->rf_phy_num) { 789 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 790 return INV_RF_DATA; 791 } 792 793 if (!chip->rf_sipi_read_addr) { 794 rtw_err(rtwdev, "rf_sipi_read_addr isn't defined\n"); 795 return INV_RF_DATA; 796 } 797 798 rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path]; 799 rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A]; 800 801 addr &= 0xff; 802 803 val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2); 804 val32 = (val32 & ~LSSI_READ_ADDR_MASK) | (addr << 23); 805 rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32); 806 807 /* toggle read edge of path A */ 808 val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2); 809 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK); 810 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK); 811 812 udelay(120); 813 814 en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8)); 815 r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read; 816 817 val32 = rtw_read32_mask(rtwdev, r_addr, LSSI_READ_DATA_MASK); 818 819 shift = __ffs(mask); 820 821 return (val32 & mask) >> shift; 822 } 823 EXPORT_SYMBOL(rtw_phy_read_rf_sipi); 824 825 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 826 u32 addr, u32 mask, u32 data) 827 { 828 struct rtw_hal *hal = &rtwdev->hal; 829 struct rtw_chip_info *chip = rtwdev->chip; 830 u32 *sipi_addr = chip->rf_sipi_addr; 831 u32 data_and_addr; 832 u32 old_data = 0; 833 u32 shift; 834 835 if (rf_path >= hal->rf_phy_num) { 836 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 837 return false; 838 } 839 840 addr &= 0xff; 841 mask &= RFREG_MASK; 842 843 if (mask != RFREG_MASK) { 844 old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK); 845 846 if (old_data == INV_RF_DATA) { 847 rtw_err(rtwdev, "Write fail, rf is disabled\n"); 848 return false; 849 } 850 851 shift = __ffs(mask); 852 data = ((old_data) & (~mask)) | (data << shift); 853 } 854 855 data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff; 856 857 rtw_write32(rtwdev, sipi_addr[rf_path], data_and_addr); 858 859 udelay(13); 860 861 return true; 862 } 863 EXPORT_SYMBOL(rtw_phy_write_rf_reg_sipi); 864 865 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 866 u32 addr, u32 mask, u32 data) 867 { 868 struct rtw_hal *hal = &rtwdev->hal; 869 struct rtw_chip_info *chip = rtwdev->chip; 870 const u32 *base_addr = chip->rf_base_addr; 871 u32 direct_addr; 872 873 if (rf_path >= hal->rf_phy_num) { 874 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 875 return false; 876 } 877 878 addr &= 0xff; 879 direct_addr = base_addr[rf_path] + (addr << 2); 880 mask &= RFREG_MASK; 881 882 rtw_write32_mask(rtwdev, direct_addr, mask, data); 883 884 udelay(1); 885 886 return true; 887 } 888 889 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 890 u32 addr, u32 mask, u32 data) 891 { 892 if (addr != 0x00) 893 return rtw_phy_write_rf_reg(rtwdev, rf_path, addr, mask, data); 894 895 return rtw_phy_write_rf_reg_sipi(rtwdev, rf_path, addr, mask, data); 896 } 897 EXPORT_SYMBOL(rtw_phy_write_rf_reg_mix); 898 899 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg) 900 { 901 struct rtw_hal *hal = &rtwdev->hal; 902 struct rtw_efuse *efuse = &rtwdev->efuse; 903 struct rtw_phy_cond cond = {0}; 904 905 cond.cut = hal->cut_version ? hal->cut_version : 15; 906 cond.pkg = pkg ? pkg : 15; 907 cond.plat = 0x04; 908 cond.rfe = efuse->rfe_option; 909 910 switch (rtw_hci_type(rtwdev)) { 911 case RTW_HCI_TYPE_USB: 912 cond.intf = INTF_USB; 913 break; 914 case RTW_HCI_TYPE_SDIO: 915 cond.intf = INTF_SDIO; 916 break; 917 case RTW_HCI_TYPE_PCIE: 918 default: 919 cond.intf = INTF_PCIE; 920 break; 921 } 922 923 hal->phy_cond = cond; 924 925 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x\n", *((u32 *)&hal->phy_cond)); 926 } 927 928 static bool check_positive(struct rtw_dev *rtwdev, struct rtw_phy_cond cond) 929 { 930 struct rtw_hal *hal = &rtwdev->hal; 931 struct rtw_phy_cond drv_cond = hal->phy_cond; 932 933 if (cond.cut && cond.cut != drv_cond.cut) 934 return false; 935 936 if (cond.pkg && cond.pkg != drv_cond.pkg) 937 return false; 938 939 if (cond.intf && cond.intf != drv_cond.intf) 940 return false; 941 942 if (cond.rfe != drv_cond.rfe) 943 return false; 944 945 return true; 946 } 947 948 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl) 949 { 950 const union phy_table_tile *p = tbl->data; 951 const union phy_table_tile *end = p + tbl->size / 2; 952 struct rtw_phy_cond pos_cond = {0}; 953 bool is_matched = true, is_skipped = false; 954 955 BUILD_BUG_ON(sizeof(union phy_table_tile) != sizeof(struct phy_cfg_pair)); 956 957 for (; p < end; p++) { 958 if (p->cond.pos) { 959 switch (p->cond.branch) { 960 case BRANCH_ENDIF: 961 is_matched = true; 962 is_skipped = false; 963 break; 964 case BRANCH_ELSE: 965 is_matched = is_skipped ? false : true; 966 break; 967 case BRANCH_IF: 968 case BRANCH_ELIF: 969 default: 970 pos_cond = p->cond; 971 break; 972 } 973 } else if (p->cond.neg) { 974 if (!is_skipped) { 975 if (check_positive(rtwdev, pos_cond)) { 976 is_matched = true; 977 is_skipped = true; 978 } else { 979 is_matched = false; 980 is_skipped = false; 981 } 982 } else { 983 is_matched = false; 984 } 985 } else if (is_matched) { 986 (*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data); 987 } 988 } 989 } 990 EXPORT_SYMBOL(rtw_parse_tbl_phy_cond); 991 992 #define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8)) 993 994 static u8 tbl_to_dec_pwr_by_rate(struct rtw_dev *rtwdev, u32 hex, u8 i) 995 { 996 if (rtwdev->chip->is_pwr_by_rate_dec) 997 return bcd_to_dec_pwr_by_rate(hex, i); 998 999 return (hex >> (i * 8)) & 0xFF; 1000 } 1001 1002 static void 1003 rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev *rtwdev, 1004 u32 addr, u32 mask, u32 val, u8 *rate, 1005 u8 *pwr_by_rate, u8 *rate_num) 1006 { 1007 int i; 1008 1009 switch (addr) { 1010 case 0xE00: 1011 case 0x830: 1012 rate[0] = DESC_RATE6M; 1013 rate[1] = DESC_RATE9M; 1014 rate[2] = DESC_RATE12M; 1015 rate[3] = DESC_RATE18M; 1016 for (i = 0; i < 4; ++i) 1017 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1018 *rate_num = 4; 1019 break; 1020 case 0xE04: 1021 case 0x834: 1022 rate[0] = DESC_RATE24M; 1023 rate[1] = DESC_RATE36M; 1024 rate[2] = DESC_RATE48M; 1025 rate[3] = DESC_RATE54M; 1026 for (i = 0; i < 4; ++i) 1027 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1028 *rate_num = 4; 1029 break; 1030 case 0xE08: 1031 rate[0] = DESC_RATE1M; 1032 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1); 1033 *rate_num = 1; 1034 break; 1035 case 0x86C: 1036 if (mask == 0xffffff00) { 1037 rate[0] = DESC_RATE2M; 1038 rate[1] = DESC_RATE5_5M; 1039 rate[2] = DESC_RATE11M; 1040 for (i = 1; i < 4; ++i) 1041 pwr_by_rate[i - 1] = 1042 tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1043 *rate_num = 3; 1044 } else if (mask == 0x000000ff) { 1045 rate[0] = DESC_RATE11M; 1046 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0); 1047 *rate_num = 1; 1048 } 1049 break; 1050 case 0xE10: 1051 case 0x83C: 1052 rate[0] = DESC_RATEMCS0; 1053 rate[1] = DESC_RATEMCS1; 1054 rate[2] = DESC_RATEMCS2; 1055 rate[3] = DESC_RATEMCS3; 1056 for (i = 0; i < 4; ++i) 1057 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1058 *rate_num = 4; 1059 break; 1060 case 0xE14: 1061 case 0x848: 1062 rate[0] = DESC_RATEMCS4; 1063 rate[1] = DESC_RATEMCS5; 1064 rate[2] = DESC_RATEMCS6; 1065 rate[3] = DESC_RATEMCS7; 1066 for (i = 0; i < 4; ++i) 1067 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1068 *rate_num = 4; 1069 break; 1070 case 0xE18: 1071 case 0x84C: 1072 rate[0] = DESC_RATEMCS8; 1073 rate[1] = DESC_RATEMCS9; 1074 rate[2] = DESC_RATEMCS10; 1075 rate[3] = DESC_RATEMCS11; 1076 for (i = 0; i < 4; ++i) 1077 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1078 *rate_num = 4; 1079 break; 1080 case 0xE1C: 1081 case 0x868: 1082 rate[0] = DESC_RATEMCS12; 1083 rate[1] = DESC_RATEMCS13; 1084 rate[2] = DESC_RATEMCS14; 1085 rate[3] = DESC_RATEMCS15; 1086 for (i = 0; i < 4; ++i) 1087 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1088 *rate_num = 4; 1089 break; 1090 case 0x838: 1091 rate[0] = DESC_RATE1M; 1092 rate[1] = DESC_RATE2M; 1093 rate[2] = DESC_RATE5_5M; 1094 for (i = 1; i < 4; ++i) 1095 pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev, 1096 val, i); 1097 *rate_num = 3; 1098 break; 1099 case 0xC20: 1100 case 0xE20: 1101 case 0x1820: 1102 case 0x1A20: 1103 rate[0] = DESC_RATE1M; 1104 rate[1] = DESC_RATE2M; 1105 rate[2] = DESC_RATE5_5M; 1106 rate[3] = DESC_RATE11M; 1107 for (i = 0; i < 4; ++i) 1108 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1109 *rate_num = 4; 1110 break; 1111 case 0xC24: 1112 case 0xE24: 1113 case 0x1824: 1114 case 0x1A24: 1115 rate[0] = DESC_RATE6M; 1116 rate[1] = DESC_RATE9M; 1117 rate[2] = DESC_RATE12M; 1118 rate[3] = DESC_RATE18M; 1119 for (i = 0; i < 4; ++i) 1120 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1121 *rate_num = 4; 1122 break; 1123 case 0xC28: 1124 case 0xE28: 1125 case 0x1828: 1126 case 0x1A28: 1127 rate[0] = DESC_RATE24M; 1128 rate[1] = DESC_RATE36M; 1129 rate[2] = DESC_RATE48M; 1130 rate[3] = DESC_RATE54M; 1131 for (i = 0; i < 4; ++i) 1132 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1133 *rate_num = 4; 1134 break; 1135 case 0xC2C: 1136 case 0xE2C: 1137 case 0x182C: 1138 case 0x1A2C: 1139 rate[0] = DESC_RATEMCS0; 1140 rate[1] = DESC_RATEMCS1; 1141 rate[2] = DESC_RATEMCS2; 1142 rate[3] = DESC_RATEMCS3; 1143 for (i = 0; i < 4; ++i) 1144 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1145 *rate_num = 4; 1146 break; 1147 case 0xC30: 1148 case 0xE30: 1149 case 0x1830: 1150 case 0x1A30: 1151 rate[0] = DESC_RATEMCS4; 1152 rate[1] = DESC_RATEMCS5; 1153 rate[2] = DESC_RATEMCS6; 1154 rate[3] = DESC_RATEMCS7; 1155 for (i = 0; i < 4; ++i) 1156 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1157 *rate_num = 4; 1158 break; 1159 case 0xC34: 1160 case 0xE34: 1161 case 0x1834: 1162 case 0x1A34: 1163 rate[0] = DESC_RATEMCS8; 1164 rate[1] = DESC_RATEMCS9; 1165 rate[2] = DESC_RATEMCS10; 1166 rate[3] = DESC_RATEMCS11; 1167 for (i = 0; i < 4; ++i) 1168 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1169 *rate_num = 4; 1170 break; 1171 case 0xC38: 1172 case 0xE38: 1173 case 0x1838: 1174 case 0x1A38: 1175 rate[0] = DESC_RATEMCS12; 1176 rate[1] = DESC_RATEMCS13; 1177 rate[2] = DESC_RATEMCS14; 1178 rate[3] = DESC_RATEMCS15; 1179 for (i = 0; i < 4; ++i) 1180 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1181 *rate_num = 4; 1182 break; 1183 case 0xC3C: 1184 case 0xE3C: 1185 case 0x183C: 1186 case 0x1A3C: 1187 rate[0] = DESC_RATEVHT1SS_MCS0; 1188 rate[1] = DESC_RATEVHT1SS_MCS1; 1189 rate[2] = DESC_RATEVHT1SS_MCS2; 1190 rate[3] = DESC_RATEVHT1SS_MCS3; 1191 for (i = 0; i < 4; ++i) 1192 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1193 *rate_num = 4; 1194 break; 1195 case 0xC40: 1196 case 0xE40: 1197 case 0x1840: 1198 case 0x1A40: 1199 rate[0] = DESC_RATEVHT1SS_MCS4; 1200 rate[1] = DESC_RATEVHT1SS_MCS5; 1201 rate[2] = DESC_RATEVHT1SS_MCS6; 1202 rate[3] = DESC_RATEVHT1SS_MCS7; 1203 for (i = 0; i < 4; ++i) 1204 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1205 *rate_num = 4; 1206 break; 1207 case 0xC44: 1208 case 0xE44: 1209 case 0x1844: 1210 case 0x1A44: 1211 rate[0] = DESC_RATEVHT1SS_MCS8; 1212 rate[1] = DESC_RATEVHT1SS_MCS9; 1213 rate[2] = DESC_RATEVHT2SS_MCS0; 1214 rate[3] = DESC_RATEVHT2SS_MCS1; 1215 for (i = 0; i < 4; ++i) 1216 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1217 *rate_num = 4; 1218 break; 1219 case 0xC48: 1220 case 0xE48: 1221 case 0x1848: 1222 case 0x1A48: 1223 rate[0] = DESC_RATEVHT2SS_MCS2; 1224 rate[1] = DESC_RATEVHT2SS_MCS3; 1225 rate[2] = DESC_RATEVHT2SS_MCS4; 1226 rate[3] = DESC_RATEVHT2SS_MCS5; 1227 for (i = 0; i < 4; ++i) 1228 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1229 *rate_num = 4; 1230 break; 1231 case 0xC4C: 1232 case 0xE4C: 1233 case 0x184C: 1234 case 0x1A4C: 1235 rate[0] = DESC_RATEVHT2SS_MCS6; 1236 rate[1] = DESC_RATEVHT2SS_MCS7; 1237 rate[2] = DESC_RATEVHT2SS_MCS8; 1238 rate[3] = DESC_RATEVHT2SS_MCS9; 1239 for (i = 0; i < 4; ++i) 1240 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1241 *rate_num = 4; 1242 break; 1243 case 0xCD8: 1244 case 0xED8: 1245 case 0x18D8: 1246 case 0x1AD8: 1247 rate[0] = DESC_RATEMCS16; 1248 rate[1] = DESC_RATEMCS17; 1249 rate[2] = DESC_RATEMCS18; 1250 rate[3] = DESC_RATEMCS19; 1251 for (i = 0; i < 4; ++i) 1252 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1253 *rate_num = 4; 1254 break; 1255 case 0xCDC: 1256 case 0xEDC: 1257 case 0x18DC: 1258 case 0x1ADC: 1259 rate[0] = DESC_RATEMCS20; 1260 rate[1] = DESC_RATEMCS21; 1261 rate[2] = DESC_RATEMCS22; 1262 rate[3] = DESC_RATEMCS23; 1263 for (i = 0; i < 4; ++i) 1264 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1265 *rate_num = 4; 1266 break; 1267 case 0xCE0: 1268 case 0xEE0: 1269 case 0x18E0: 1270 case 0x1AE0: 1271 rate[0] = DESC_RATEVHT3SS_MCS0; 1272 rate[1] = DESC_RATEVHT3SS_MCS1; 1273 rate[2] = DESC_RATEVHT3SS_MCS2; 1274 rate[3] = DESC_RATEVHT3SS_MCS3; 1275 for (i = 0; i < 4; ++i) 1276 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1277 *rate_num = 4; 1278 break; 1279 case 0xCE4: 1280 case 0xEE4: 1281 case 0x18E4: 1282 case 0x1AE4: 1283 rate[0] = DESC_RATEVHT3SS_MCS4; 1284 rate[1] = DESC_RATEVHT3SS_MCS5; 1285 rate[2] = DESC_RATEVHT3SS_MCS6; 1286 rate[3] = DESC_RATEVHT3SS_MCS7; 1287 for (i = 0; i < 4; ++i) 1288 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1289 *rate_num = 4; 1290 break; 1291 case 0xCE8: 1292 case 0xEE8: 1293 case 0x18E8: 1294 case 0x1AE8: 1295 rate[0] = DESC_RATEVHT3SS_MCS8; 1296 rate[1] = DESC_RATEVHT3SS_MCS9; 1297 for (i = 0; i < 2; ++i) 1298 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1299 *rate_num = 2; 1300 break; 1301 default: 1302 rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr); 1303 break; 1304 } 1305 } 1306 1307 static void rtw_phy_store_tx_power_by_rate(struct rtw_dev *rtwdev, 1308 u32 band, u32 rfpath, u32 txnum, 1309 u32 regaddr, u32 bitmask, u32 data) 1310 { 1311 struct rtw_hal *hal = &rtwdev->hal; 1312 u8 rate_num = 0; 1313 u8 rate; 1314 u8 rates[RTW_RF_PATH_MAX] = {0}; 1315 s8 offset; 1316 s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0}; 1317 int i; 1318 1319 rtw_phy_get_rate_values_of_txpwr_by_rate(rtwdev, regaddr, bitmask, data, 1320 rates, pwr_by_rate, &rate_num); 1321 1322 if (WARN_ON(rfpath >= RTW_RF_PATH_MAX || 1323 (band != PHY_BAND_2G && band != PHY_BAND_5G) || 1324 rate_num > RTW_RF_PATH_MAX)) 1325 return; 1326 1327 for (i = 0; i < rate_num; i++) { 1328 offset = pwr_by_rate[i]; 1329 rate = rates[i]; 1330 if (band == PHY_BAND_2G) 1331 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset; 1332 else if (band == PHY_BAND_5G) 1333 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset; 1334 else 1335 continue; 1336 } 1337 } 1338 1339 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl) 1340 { 1341 const struct rtw_phy_pg_cfg_pair *p = tbl->data; 1342 const struct rtw_phy_pg_cfg_pair *end = p + tbl->size; 1343 1344 for (; p < end; p++) { 1345 if (p->addr == 0xfe || p->addr == 0xffe) { 1346 msleep(50); 1347 continue; 1348 } 1349 rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path, 1350 p->tx_num, p->addr, p->bitmask, 1351 p->data); 1352 } 1353 } 1354 EXPORT_SYMBOL(rtw_parse_tbl_bb_pg); 1355 1356 static const u8 rtw_channel_idx_5g[RTW_MAX_CHANNEL_NUM_5G] = { 1357 36, 38, 40, 42, 44, 46, 48, /* Band 1 */ 1358 52, 54, 56, 58, 60, 62, 64, /* Band 2 */ 1359 100, 102, 104, 106, 108, 110, 112, /* Band 3 */ 1360 116, 118, 120, 122, 124, 126, 128, /* Band 3 */ 1361 132, 134, 136, 138, 140, 142, 144, /* Band 3 */ 1362 149, 151, 153, 155, 157, 159, 161, /* Band 4 */ 1363 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */ 1364 1365 static int rtw_channel_to_idx(u8 band, u8 channel) 1366 { 1367 int ch_idx; 1368 u8 n_channel; 1369 1370 if (band == PHY_BAND_2G) { 1371 ch_idx = channel - 1; 1372 n_channel = RTW_MAX_CHANNEL_NUM_2G; 1373 } else if (band == PHY_BAND_5G) { 1374 n_channel = RTW_MAX_CHANNEL_NUM_5G; 1375 for (ch_idx = 0; ch_idx < n_channel; ch_idx++) 1376 if (rtw_channel_idx_5g[ch_idx] == channel) 1377 break; 1378 } else { 1379 return -1; 1380 } 1381 1382 if (ch_idx >= n_channel) 1383 return -1; 1384 1385 return ch_idx; 1386 } 1387 1388 static void rtw_phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band, 1389 u8 bw, u8 rs, u8 ch, s8 pwr_limit) 1390 { 1391 struct rtw_hal *hal = &rtwdev->hal; 1392 u8 max_power_index = rtwdev->chip->max_power_index; 1393 s8 ww; 1394 int ch_idx; 1395 1396 pwr_limit = clamp_t(s8, pwr_limit, 1397 -max_power_index, max_power_index); 1398 ch_idx = rtw_channel_to_idx(band, ch); 1399 1400 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX || 1401 rs >= RTW_RATE_SECTION_MAX || ch_idx < 0) { 1402 WARN(1, 1403 "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n", 1404 regd, band, bw, rs, ch_idx, pwr_limit); 1405 return; 1406 } 1407 1408 if (band == PHY_BAND_2G) { 1409 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit; 1410 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx]; 1411 ww = min_t(s8, ww, pwr_limit); 1412 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww; 1413 } else if (band == PHY_BAND_5G) { 1414 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit; 1415 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx]; 1416 ww = min_t(s8, ww, pwr_limit); 1417 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww; 1418 } 1419 } 1420 1421 /* cross-reference 5G power limits if values are not assigned */ 1422 static void 1423 rtw_xref_5g_txpwr_lmt(struct rtw_dev *rtwdev, u8 regd, 1424 u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht) 1425 { 1426 struct rtw_hal *hal = &rtwdev->hal; 1427 u8 max_power_index = rtwdev->chip->max_power_index; 1428 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx]; 1429 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx]; 1430 1431 if (lmt_ht == lmt_vht) 1432 return; 1433 1434 if (lmt_ht == max_power_index) 1435 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht; 1436 1437 else if (lmt_vht == max_power_index) 1438 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht; 1439 } 1440 1441 /* cross-reference power limits for ht and vht */ 1442 static void 1443 rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx) 1444 { 1445 u8 rs_idx, rs_ht, rs_vht; 1446 u8 rs_cmp[2][2] = {{RTW_RATE_SECTION_HT_1S, RTW_RATE_SECTION_VHT_1S}, 1447 {RTW_RATE_SECTION_HT_2S, RTW_RATE_SECTION_VHT_2S} }; 1448 1449 for (rs_idx = 0; rs_idx < 2; rs_idx++) { 1450 rs_ht = rs_cmp[rs_idx][0]; 1451 rs_vht = rs_cmp[rs_idx][1]; 1452 1453 rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht); 1454 } 1455 } 1456 1457 /* cross-reference power limits for 5G channels */ 1458 static void 1459 rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw) 1460 { 1461 u8 ch_idx; 1462 1463 for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++) 1464 rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx); 1465 } 1466 1467 /* cross-reference power limits for 20/40M bandwidth */ 1468 static void 1469 rtw_xref_txpwr_lmt_by_bw(struct rtw_dev *rtwdev, u8 regd) 1470 { 1471 u8 bw; 1472 1473 for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++) 1474 rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw); 1475 } 1476 1477 /* cross-reference power limits */ 1478 static void rtw_xref_txpwr_lmt(struct rtw_dev *rtwdev) 1479 { 1480 u8 regd; 1481 1482 for (regd = 0; regd < RTW_REGD_MAX; regd++) 1483 rtw_xref_txpwr_lmt_by_bw(rtwdev, regd); 1484 } 1485 1486 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, 1487 const struct rtw_table *tbl) 1488 { 1489 const struct rtw_txpwr_lmt_cfg_pair *p = tbl->data; 1490 const struct rtw_txpwr_lmt_cfg_pair *end = p + tbl->size; 1491 1492 for (; p < end; p++) { 1493 rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band, 1494 p->bw, p->rs, p->ch, p->txpwr_lmt); 1495 } 1496 1497 rtw_xref_txpwr_lmt(rtwdev); 1498 } 1499 EXPORT_SYMBOL(rtw_parse_tbl_txpwr_lmt); 1500 1501 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1502 u32 addr, u32 data) 1503 { 1504 rtw_write8(rtwdev, addr, data); 1505 } 1506 EXPORT_SYMBOL(rtw_phy_cfg_mac); 1507 1508 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1509 u32 addr, u32 data) 1510 { 1511 rtw_write32(rtwdev, addr, data); 1512 } 1513 EXPORT_SYMBOL(rtw_phy_cfg_agc); 1514 1515 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1516 u32 addr, u32 data) 1517 { 1518 if (addr == 0xfe) 1519 msleep(50); 1520 else if (addr == 0xfd) 1521 mdelay(5); 1522 else if (addr == 0xfc) 1523 mdelay(1); 1524 else if (addr == 0xfb) 1525 usleep_range(50, 60); 1526 else if (addr == 0xfa) 1527 udelay(5); 1528 else if (addr == 0xf9) 1529 udelay(1); 1530 else 1531 rtw_write32(rtwdev, addr, data); 1532 } 1533 EXPORT_SYMBOL(rtw_phy_cfg_bb); 1534 1535 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1536 u32 addr, u32 data) 1537 { 1538 if (addr == 0xffe) { 1539 msleep(50); 1540 } else if (addr == 0xfe) { 1541 usleep_range(100, 110); 1542 } else { 1543 rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data); 1544 udelay(1); 1545 } 1546 } 1547 EXPORT_SYMBOL(rtw_phy_cfg_rf); 1548 1549 static void rtw_load_rfk_table(struct rtw_dev *rtwdev) 1550 { 1551 struct rtw_chip_info *chip = rtwdev->chip; 1552 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 1553 1554 if (!chip->rfk_init_tbl) 1555 return; 1556 1557 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1); 1558 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1); 1559 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1); 1560 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1); 1561 rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0); 1562 1563 rtw_load_table(rtwdev, chip->rfk_init_tbl); 1564 1565 dpk_info->is_dpk_pwr_on = true; 1566 } 1567 1568 void rtw_phy_load_tables(struct rtw_dev *rtwdev) 1569 { 1570 struct rtw_chip_info *chip = rtwdev->chip; 1571 u8 rf_path; 1572 1573 rtw_load_table(rtwdev, chip->mac_tbl); 1574 rtw_load_table(rtwdev, chip->bb_tbl); 1575 rtw_load_table(rtwdev, chip->agc_tbl); 1576 rtw_load_rfk_table(rtwdev); 1577 1578 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) { 1579 const struct rtw_table *tbl; 1580 1581 tbl = chip->rf_tbl[rf_path]; 1582 rtw_load_table(rtwdev, tbl); 1583 } 1584 } 1585 EXPORT_SYMBOL(rtw_phy_load_tables); 1586 1587 static u8 rtw_get_channel_group(u8 channel) 1588 { 1589 switch (channel) { 1590 default: 1591 WARN_ON(1); 1592 fallthrough; 1593 case 1: 1594 case 2: 1595 case 36: 1596 case 38: 1597 case 40: 1598 case 42: 1599 return 0; 1600 case 3: 1601 case 4: 1602 case 5: 1603 case 44: 1604 case 46: 1605 case 48: 1606 case 50: 1607 return 1; 1608 case 6: 1609 case 7: 1610 case 8: 1611 case 52: 1612 case 54: 1613 case 56: 1614 case 58: 1615 return 2; 1616 case 9: 1617 case 10: 1618 case 11: 1619 case 60: 1620 case 62: 1621 case 64: 1622 return 3; 1623 case 12: 1624 case 13: 1625 case 100: 1626 case 102: 1627 case 104: 1628 case 106: 1629 return 4; 1630 case 14: 1631 case 108: 1632 case 110: 1633 case 112: 1634 case 114: 1635 return 5; 1636 case 116: 1637 case 118: 1638 case 120: 1639 case 122: 1640 return 6; 1641 case 124: 1642 case 126: 1643 case 128: 1644 case 130: 1645 return 7; 1646 case 132: 1647 case 134: 1648 case 136: 1649 case 138: 1650 return 8; 1651 case 140: 1652 case 142: 1653 case 144: 1654 return 9; 1655 case 149: 1656 case 151: 1657 case 153: 1658 case 155: 1659 return 10; 1660 case 157: 1661 case 159: 1662 case 161: 1663 return 11; 1664 case 165: 1665 case 167: 1666 case 169: 1667 case 171: 1668 return 12; 1669 case 173: 1670 case 175: 1671 case 177: 1672 return 13; 1673 } 1674 } 1675 1676 static s8 rtw_phy_get_dis_dpd_by_rate_diff(struct rtw_dev *rtwdev, u16 rate) 1677 { 1678 struct rtw_chip_info *chip = rtwdev->chip; 1679 s8 dpd_diff = 0; 1680 1681 if (!chip->en_dis_dpd) 1682 return 0; 1683 1684 #define RTW_DPD_RATE_CHECK(_rate) \ 1685 case DESC_RATE ## _rate: \ 1686 if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask) \ 1687 dpd_diff = -6 * chip->txgi_factor; \ 1688 break 1689 1690 switch (rate) { 1691 RTW_DPD_RATE_CHECK(6M); 1692 RTW_DPD_RATE_CHECK(9M); 1693 RTW_DPD_RATE_CHECK(MCS0); 1694 RTW_DPD_RATE_CHECK(MCS1); 1695 RTW_DPD_RATE_CHECK(MCS8); 1696 RTW_DPD_RATE_CHECK(MCS9); 1697 RTW_DPD_RATE_CHECK(VHT1SS_MCS0); 1698 RTW_DPD_RATE_CHECK(VHT1SS_MCS1); 1699 RTW_DPD_RATE_CHECK(VHT2SS_MCS0); 1700 RTW_DPD_RATE_CHECK(VHT2SS_MCS1); 1701 } 1702 #undef RTW_DPD_RATE_CHECK 1703 1704 return dpd_diff; 1705 } 1706 1707 static u8 rtw_phy_get_2g_tx_power_index(struct rtw_dev *rtwdev, 1708 struct rtw_2g_txpwr_idx *pwr_idx_2g, 1709 enum rtw_bandwidth bandwidth, 1710 u8 rate, u8 group) 1711 { 1712 struct rtw_chip_info *chip = rtwdev->chip; 1713 u8 tx_power; 1714 bool mcs_rate; 1715 bool above_2ss; 1716 u8 factor = chip->txgi_factor; 1717 1718 if (rate <= DESC_RATE11M) 1719 tx_power = pwr_idx_2g->cck_base[group]; 1720 else 1721 tx_power = pwr_idx_2g->bw40_base[group]; 1722 1723 if (rate >= DESC_RATE6M && rate <= DESC_RATE54M) 1724 tx_power += pwr_idx_2g->ht_1s_diff.ofdm * factor; 1725 1726 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) || 1727 (rate >= DESC_RATEVHT1SS_MCS0 && 1728 rate <= DESC_RATEVHT2SS_MCS9); 1729 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) || 1730 (rate >= DESC_RATEVHT2SS_MCS0); 1731 1732 if (!mcs_rate) 1733 return tx_power; 1734 1735 switch (bandwidth) { 1736 default: 1737 WARN_ON(1); 1738 fallthrough; 1739 case RTW_CHANNEL_WIDTH_20: 1740 tx_power += pwr_idx_2g->ht_1s_diff.bw20 * factor; 1741 if (above_2ss) 1742 tx_power += pwr_idx_2g->ht_2s_diff.bw20 * factor; 1743 break; 1744 case RTW_CHANNEL_WIDTH_40: 1745 /* bw40 is the base power */ 1746 if (above_2ss) 1747 tx_power += pwr_idx_2g->ht_2s_diff.bw40 * factor; 1748 break; 1749 } 1750 1751 return tx_power; 1752 } 1753 1754 static u8 rtw_phy_get_5g_tx_power_index(struct rtw_dev *rtwdev, 1755 struct rtw_5g_txpwr_idx *pwr_idx_5g, 1756 enum rtw_bandwidth bandwidth, 1757 u8 rate, u8 group) 1758 { 1759 struct rtw_chip_info *chip = rtwdev->chip; 1760 u8 tx_power; 1761 u8 upper, lower; 1762 bool mcs_rate; 1763 bool above_2ss; 1764 u8 factor = chip->txgi_factor; 1765 1766 tx_power = pwr_idx_5g->bw40_base[group]; 1767 1768 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS15) || 1769 (rate >= DESC_RATEVHT1SS_MCS0 && 1770 rate <= DESC_RATEVHT2SS_MCS9); 1771 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) || 1772 (rate >= DESC_RATEVHT2SS_MCS0); 1773 1774 if (!mcs_rate) { 1775 tx_power += pwr_idx_5g->ht_1s_diff.ofdm * factor; 1776 return tx_power; 1777 } 1778 1779 switch (bandwidth) { 1780 default: 1781 WARN_ON(1); 1782 fallthrough; 1783 case RTW_CHANNEL_WIDTH_20: 1784 tx_power += pwr_idx_5g->ht_1s_diff.bw20 * factor; 1785 if (above_2ss) 1786 tx_power += pwr_idx_5g->ht_2s_diff.bw20 * factor; 1787 break; 1788 case RTW_CHANNEL_WIDTH_40: 1789 /* bw40 is the base power */ 1790 if (above_2ss) 1791 tx_power += pwr_idx_5g->ht_2s_diff.bw40 * factor; 1792 break; 1793 case RTW_CHANNEL_WIDTH_80: 1794 /* the base idx of bw80 is the average of bw40+/bw40- */ 1795 lower = pwr_idx_5g->bw40_base[group]; 1796 upper = pwr_idx_5g->bw40_base[group + 1]; 1797 1798 tx_power = (lower + upper) / 2; 1799 tx_power += pwr_idx_5g->vht_1s_diff.bw80 * factor; 1800 if (above_2ss) 1801 tx_power += pwr_idx_5g->vht_2s_diff.bw80 * factor; 1802 break; 1803 } 1804 1805 return tx_power; 1806 } 1807 1808 static s8 rtw_phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band, 1809 enum rtw_bandwidth bw, u8 rf_path, 1810 u8 rate, u8 channel, u8 regd) 1811 { 1812 struct rtw_hal *hal = &rtwdev->hal; 1813 u8 *cch_by_bw = hal->cch_by_bw; 1814 s8 power_limit = (s8)rtwdev->chip->max_power_index; 1815 u8 rs; 1816 int ch_idx; 1817 u8 cur_bw, cur_ch; 1818 s8 cur_lmt; 1819 1820 if (regd > RTW_REGD_WW) 1821 return power_limit; 1822 1823 if (rate >= DESC_RATE1M && rate <= DESC_RATE11M) 1824 rs = RTW_RATE_SECTION_CCK; 1825 else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M) 1826 rs = RTW_RATE_SECTION_OFDM; 1827 else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7) 1828 rs = RTW_RATE_SECTION_HT_1S; 1829 else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) 1830 rs = RTW_RATE_SECTION_HT_2S; 1831 else if (rate >= DESC_RATEVHT1SS_MCS0 && rate <= DESC_RATEVHT1SS_MCS9) 1832 rs = RTW_RATE_SECTION_VHT_1S; 1833 else if (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9) 1834 rs = RTW_RATE_SECTION_VHT_2S; 1835 else 1836 goto err; 1837 1838 /* only 20M BW with cck and ofdm */ 1839 if (rs == RTW_RATE_SECTION_CCK || rs == RTW_RATE_SECTION_OFDM) 1840 bw = RTW_CHANNEL_WIDTH_20; 1841 1842 /* only 20/40M BW with ht */ 1843 if (rs == RTW_RATE_SECTION_HT_1S || rs == RTW_RATE_SECTION_HT_2S) 1844 bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40); 1845 1846 /* select min power limit among [20M BW ~ current BW] */ 1847 for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) { 1848 cur_ch = cch_by_bw[cur_bw]; 1849 1850 ch_idx = rtw_channel_to_idx(band, cur_ch); 1851 if (ch_idx < 0) 1852 goto err; 1853 1854 cur_lmt = cur_ch <= RTW_MAX_CHANNEL_NUM_2G ? 1855 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] : 1856 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx]; 1857 1858 power_limit = min_t(s8, cur_lmt, power_limit); 1859 } 1860 1861 return power_limit; 1862 1863 err: 1864 WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n", 1865 band, bw, rf_path, rate, channel); 1866 return (s8)rtwdev->chip->max_power_index; 1867 } 1868 1869 void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw, 1870 u8 ch, u8 regd, struct rtw_power_params *pwr_param) 1871 { 1872 struct rtw_hal *hal = &rtwdev->hal; 1873 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1874 struct rtw_txpwr_idx *pwr_idx; 1875 u8 group, band; 1876 u8 *base = &pwr_param->pwr_base; 1877 s8 *offset = &pwr_param->pwr_offset; 1878 s8 *limit = &pwr_param->pwr_limit; 1879 s8 *remnant = &pwr_param->pwr_remnant; 1880 1881 pwr_idx = &rtwdev->efuse.txpwr_idx_table[path]; 1882 group = rtw_get_channel_group(ch); 1883 1884 /* base power index for 2.4G/5G */ 1885 if (IS_CH_2G_BAND(ch)) { 1886 band = PHY_BAND_2G; 1887 *base = rtw_phy_get_2g_tx_power_index(rtwdev, 1888 &pwr_idx->pwr_idx_2g, 1889 bw, rate, group); 1890 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate]; 1891 } else { 1892 band = PHY_BAND_5G; 1893 *base = rtw_phy_get_5g_tx_power_index(rtwdev, 1894 &pwr_idx->pwr_idx_5g, 1895 bw, rate, group); 1896 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate]; 1897 } 1898 1899 *limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path, 1900 rate, ch, regd); 1901 *remnant = (rate <= DESC_RATE11M ? dm_info->txagc_remnant_cck : 1902 dm_info->txagc_remnant_ofdm); 1903 } 1904 1905 u8 1906 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate, 1907 enum rtw_bandwidth bandwidth, u8 channel, u8 regd) 1908 { 1909 struct rtw_power_params pwr_param = {0}; 1910 u8 tx_power; 1911 s8 offset; 1912 1913 rtw_get_tx_power_params(rtwdev, rf_path, rate, bandwidth, 1914 channel, regd, &pwr_param); 1915 1916 tx_power = pwr_param.pwr_base; 1917 offset = min_t(s8, pwr_param.pwr_offset, pwr_param.pwr_limit); 1918 1919 if (rtwdev->chip->en_dis_dpd) 1920 offset += rtw_phy_get_dis_dpd_by_rate_diff(rtwdev, rate); 1921 1922 tx_power += offset + pwr_param.pwr_remnant; 1923 1924 if (tx_power > rtwdev->chip->max_power_index) 1925 tx_power = rtwdev->chip->max_power_index; 1926 1927 return tx_power; 1928 } 1929 EXPORT_SYMBOL(rtw_phy_get_tx_power_index); 1930 1931 static void rtw_phy_set_tx_power_index_by_rs(struct rtw_dev *rtwdev, 1932 u8 ch, u8 path, u8 rs) 1933 { 1934 struct rtw_hal *hal = &rtwdev->hal; 1935 u8 regd = rtwdev->regd.txpwr_regd; 1936 u8 *rates; 1937 u8 size; 1938 u8 rate; 1939 u8 pwr_idx; 1940 u8 bw; 1941 int i; 1942 1943 if (rs >= RTW_RATE_SECTION_MAX) 1944 return; 1945 1946 rates = rtw_rate_section[rs]; 1947 size = rtw_rate_size[rs]; 1948 bw = hal->current_band_width; 1949 for (i = 0; i < size; i++) { 1950 rate = rates[i]; 1951 pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, rate, 1952 bw, ch, regd); 1953 hal->tx_pwr_tbl[path][rate] = pwr_idx; 1954 } 1955 } 1956 1957 /* set tx power level by path for each rates, note that the order of the rates 1958 * are *very* important, bacause 8822B/8821C combines every four bytes of tx 1959 * power index into a four-byte power index register, and calls set_tx_agc to 1960 * write these values into hardware 1961 */ 1962 static void rtw_phy_set_tx_power_level_by_path(struct rtw_dev *rtwdev, 1963 u8 ch, u8 path) 1964 { 1965 struct rtw_hal *hal = &rtwdev->hal; 1966 u8 rs; 1967 1968 /* do not need cck rates if we are not in 2.4G */ 1969 if (hal->current_band_type == RTW_BAND_2G) 1970 rs = RTW_RATE_SECTION_CCK; 1971 else 1972 rs = RTW_RATE_SECTION_OFDM; 1973 1974 for (; rs < RTW_RATE_SECTION_MAX; rs++) 1975 rtw_phy_set_tx_power_index_by_rs(rtwdev, ch, path, rs); 1976 } 1977 1978 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel) 1979 { 1980 struct rtw_chip_info *chip = rtwdev->chip; 1981 struct rtw_hal *hal = &rtwdev->hal; 1982 u8 path; 1983 1984 mutex_lock(&hal->tx_power_mutex); 1985 1986 for (path = 0; path < hal->rf_path_num; path++) 1987 rtw_phy_set_tx_power_level_by_path(rtwdev, channel, path); 1988 1989 chip->ops->set_tx_power_index(rtwdev); 1990 mutex_unlock(&hal->tx_power_mutex); 1991 } 1992 EXPORT_SYMBOL(rtw_phy_set_tx_power_level); 1993 1994 static void 1995 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path, 1996 u8 rs, u8 size, u8 *rates) 1997 { 1998 u8 rate; 1999 u8 base_idx, rate_idx; 2000 s8 base_2g, base_5g; 2001 2002 if (rs >= RTW_RATE_SECTION_VHT_1S) 2003 base_idx = rates[size - 3]; 2004 else 2005 base_idx = rates[size - 1]; 2006 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx]; 2007 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx]; 2008 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g; 2009 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g; 2010 for (rate = 0; rate < size; rate++) { 2011 rate_idx = rates[rate]; 2012 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g; 2013 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g; 2014 } 2015 } 2016 2017 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal) 2018 { 2019 u8 path; 2020 2021 for (path = 0; path < RTW_RF_PATH_MAX; path++) { 2022 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 2023 RTW_RATE_SECTION_CCK, 2024 rtw_cck_size, rtw_cck_rates); 2025 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 2026 RTW_RATE_SECTION_OFDM, 2027 rtw_ofdm_size, rtw_ofdm_rates); 2028 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 2029 RTW_RATE_SECTION_HT_1S, 2030 rtw_ht_1s_size, rtw_ht_1s_rates); 2031 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 2032 RTW_RATE_SECTION_HT_2S, 2033 rtw_ht_2s_size, rtw_ht_2s_rates); 2034 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 2035 RTW_RATE_SECTION_VHT_1S, 2036 rtw_vht_1s_size, rtw_vht_1s_rates); 2037 rtw_phy_tx_power_by_rate_config_by_path(hal, path, 2038 RTW_RATE_SECTION_VHT_2S, 2039 rtw_vht_2s_size, rtw_vht_2s_rates); 2040 } 2041 } 2042 2043 static void 2044 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs) 2045 { 2046 s8 base; 2047 u8 ch; 2048 2049 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) { 2050 base = hal->tx_pwr_by_rate_base_2g[0][rs]; 2051 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base; 2052 } 2053 2054 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) { 2055 base = hal->tx_pwr_by_rate_base_5g[0][rs]; 2056 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base; 2057 } 2058 } 2059 2060 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal) 2061 { 2062 u8 regd, bw, rs; 2063 2064 /* default at channel 1 */ 2065 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1; 2066 2067 for (regd = 0; regd < RTW_REGD_MAX; regd++) 2068 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) 2069 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) 2070 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs); 2071 } 2072 2073 static void rtw_phy_init_tx_power_limit(struct rtw_dev *rtwdev, 2074 u8 regd, u8 bw, u8 rs) 2075 { 2076 struct rtw_hal *hal = &rtwdev->hal; 2077 s8 max_power_index = (s8)rtwdev->chip->max_power_index; 2078 u8 ch; 2079 2080 /* 2.4G channels */ 2081 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) 2082 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index; 2083 2084 /* 5G channels */ 2085 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) 2086 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index; 2087 } 2088 2089 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev) 2090 { 2091 struct rtw_hal *hal = &rtwdev->hal; 2092 u8 regd, path, rate, rs, bw; 2093 2094 /* init tx power by rate offset */ 2095 for (path = 0; path < RTW_RF_PATH_MAX; path++) { 2096 for (rate = 0; rate < DESC_RATE_MAX; rate++) { 2097 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0; 2098 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0; 2099 } 2100 } 2101 2102 /* init tx power limit */ 2103 for (regd = 0; regd < RTW_REGD_MAX; regd++) 2104 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) 2105 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) 2106 rtw_phy_init_tx_power_limit(rtwdev, regd, bw, 2107 rs); 2108 } 2109 2110 void rtw_phy_config_swing_table(struct rtw_dev *rtwdev, 2111 struct rtw_swing_table *swing_table) 2112 { 2113 const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl; 2114 u8 channel = rtwdev->hal.current_channel; 2115 2116 if (IS_CH_2G_BAND(channel)) { 2117 if (rtwdev->dm_info.tx_rate <= DESC_RATE11M) { 2118 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2g_ccka_p; 2119 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2g_ccka_n; 2120 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2g_cckb_p; 2121 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2g_cckb_n; 2122 } else { 2123 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p; 2124 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n; 2125 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p; 2126 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n; 2127 } 2128 } else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 2129 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_1]; 2130 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_1]; 2131 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_1]; 2132 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_1]; 2133 } else if (IS_CH_5G_BAND_3(channel)) { 2134 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_2]; 2135 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_2]; 2136 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_2]; 2137 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_2]; 2138 } else if (IS_CH_5G_BAND_4(channel)) { 2139 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_3]; 2140 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_3]; 2141 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_3]; 2142 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_3]; 2143 } else { 2144 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p; 2145 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n; 2146 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p; 2147 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n; 2148 } 2149 } 2150 EXPORT_SYMBOL(rtw_phy_config_swing_table); 2151 2152 void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path) 2153 { 2154 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2155 2156 ewma_thermal_add(&dm_info->avg_thermal[path], thermal); 2157 dm_info->thermal_avg[path] = 2158 ewma_thermal_read(&dm_info->avg_thermal[path]); 2159 } 2160 EXPORT_SYMBOL(rtw_phy_pwrtrack_avg); 2161 2162 bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal, 2163 u8 path) 2164 { 2165 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2166 u8 avg = ewma_thermal_read(&dm_info->avg_thermal[path]); 2167 2168 if (avg == thermal) 2169 return false; 2170 2171 return true; 2172 } 2173 EXPORT_SYMBOL(rtw_phy_pwrtrack_thermal_changed); 2174 2175 u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path) 2176 { 2177 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2178 u8 therm_avg, therm_efuse, therm_delta; 2179 2180 therm_avg = dm_info->thermal_avg[path]; 2181 therm_efuse = rtwdev->efuse.thermal_meter[path]; 2182 therm_delta = abs(therm_avg - therm_efuse); 2183 2184 return min_t(u8, therm_delta, RTW_PWR_TRK_TBL_SZ - 1); 2185 } 2186 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_delta); 2187 2188 s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev, 2189 struct rtw_swing_table *swing_table, 2190 u8 tbl_path, u8 therm_path, u8 delta) 2191 { 2192 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2193 const u8 *delta_swing_table_idx_pos; 2194 const u8 *delta_swing_table_idx_neg; 2195 2196 if (delta >= RTW_PWR_TRK_TBL_SZ) { 2197 rtw_warn(rtwdev, "power track table overflow\n"); 2198 return 0; 2199 } 2200 2201 if (!swing_table) { 2202 rtw_warn(rtwdev, "swing table not configured\n"); 2203 return 0; 2204 } 2205 2206 delta_swing_table_idx_pos = swing_table->p[tbl_path]; 2207 delta_swing_table_idx_neg = swing_table->n[tbl_path]; 2208 2209 if (!delta_swing_table_idx_pos || !delta_swing_table_idx_neg) { 2210 rtw_warn(rtwdev, "invalid swing table index\n"); 2211 return 0; 2212 } 2213 2214 if (dm_info->thermal_avg[therm_path] > 2215 rtwdev->efuse.thermal_meter[therm_path]) 2216 return delta_swing_table_idx_pos[delta]; 2217 else 2218 return -delta_swing_table_idx_neg[delta]; 2219 } 2220 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_pwridx); 2221 2222 bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev) 2223 { 2224 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2225 u8 delta_iqk; 2226 2227 delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k); 2228 if (delta_iqk >= rtwdev->chip->iqk_threshold) { 2229 dm_info->thermal_meter_k = dm_info->thermal_avg[0]; 2230 return true; 2231 } 2232 return false; 2233 } 2234 EXPORT_SYMBOL(rtw_phy_pwrtrack_need_iqk); 2235