1*93121c03SLarry Finger /* SPDX-License-Identifier: GPL-2.0 */ 2*93121c03SLarry Finger /* Copyright(c) 2009-2014 Realtek Corporation.*/ 3f1d2b4d3SLarry Finger 4f1d2b4d3SLarry Finger #ifndef __RTL8723BE_PHY_H__ 5f1d2b4d3SLarry Finger #define __RTL8723BE_PHY_H__ 6f1d2b4d3SLarry Finger 7f1d2b4d3SLarry Finger /* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence 8f1d2b4d3SLarry Finger * will be wrong. 9f1d2b4d3SLarry Finger */ 10f1d2b4d3SLarry Finger #define MAX_TX_COUNT 4 11f1d2b4d3SLarry Finger #define TX_1S 0 12f1d2b4d3SLarry Finger #define TX_2S 1 13f1d2b4d3SLarry Finger #define TX_3S 2 14f1d2b4d3SLarry Finger #define TX_4S 3 15f1d2b4d3SLarry Finger 16f1d2b4d3SLarry Finger #define MAX_POWER_INDEX 0x3F 17f1d2b4d3SLarry Finger 18f1d2b4d3SLarry Finger #define MAX_PRECMD_CNT 16 19f1d2b4d3SLarry Finger #define MAX_RFDEPENDCMD_CNT 16 20f1d2b4d3SLarry Finger #define MAX_POSTCMD_CNT 16 21f1d2b4d3SLarry Finger 22f1d2b4d3SLarry Finger #define MAX_DOZE_WAITING_TIMES_9x 64 23f1d2b4d3SLarry Finger 24f1d2b4d3SLarry Finger #define RT_CANNOT_IO(hw) false 25f1d2b4d3SLarry Finger #define HIGHPOWER_RADIOA_ARRAYLEN 22 26f1d2b4d3SLarry Finger 27f1d2b4d3SLarry Finger #define TARGET_CHNL_NUM_2G_5G 59 28f1d2b4d3SLarry Finger 29f1d2b4d3SLarry Finger #define IQK_ADDA_REG_NUM 16 30f1d2b4d3SLarry Finger #define IQK_BB_REG_NUM 9 31f1d2b4d3SLarry Finger #define MAX_TOLERANCE 5 32f1d2b4d3SLarry Finger #define IQK_DELAY_TIME 10 33f1d2b4d3SLarry Finger #define index_mapping_NUM 15 34f1d2b4d3SLarry Finger 35f1d2b4d3SLarry Finger #define APK_BB_REG_NUM 5 36f1d2b4d3SLarry Finger #define APK_AFE_REG_NUM 16 37f1d2b4d3SLarry Finger #define APK_CURVE_REG_NUM 4 38f1d2b4d3SLarry Finger #define PATH_NUM 1 39f1d2b4d3SLarry Finger 40f1d2b4d3SLarry Finger #define LOOP_LIMIT 5 41f1d2b4d3SLarry Finger #define MAX_STALL_TIME 50 42f1d2b4d3SLarry Finger #define ANTENNADIVERSITYVALUE 0x80 43f1d2b4d3SLarry Finger #define MAX_TXPWR_IDX_NMODE_92S 63 44f1d2b4d3SLarry Finger #define RESET_CNT_LIMIT 3 45f1d2b4d3SLarry Finger 46f1d2b4d3SLarry Finger #define IQK_ADDA_REG_NUM 16 47f1d2b4d3SLarry Finger #define IQK_MAC_REG_NUM 4 48f1d2b4d3SLarry Finger 49f1d2b4d3SLarry Finger #define RF6052_MAX_PATH 2 50f1d2b4d3SLarry Finger 51f1d2b4d3SLarry Finger #define CT_OFFSET_MAC_ADDR 0X16 52f1d2b4d3SLarry Finger 53f1d2b4d3SLarry Finger #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A 54f1d2b4d3SLarry Finger #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60 55f1d2b4d3SLarry Finger #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66 56f1d2b4d3SLarry Finger #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69 57f1d2b4d3SLarry Finger #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C 58f1d2b4d3SLarry Finger 59f1d2b4d3SLarry Finger #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F 60f1d2b4d3SLarry Finger #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72 61f1d2b4d3SLarry Finger 62f1d2b4d3SLarry Finger #define CT_OFFSET_CHANNEL_PLAH 0x75 63f1d2b4d3SLarry Finger #define CT_OFFSET_THERMAL_METER 0x78 64f1d2b4d3SLarry Finger #define CT_OFFSET_RF_OPTION 0x79 65f1d2b4d3SLarry Finger #define CT_OFFSET_VERSION 0x7E 66f1d2b4d3SLarry Finger #define CT_OFFSET_CUSTOMER_ID 0x7F 67f1d2b4d3SLarry Finger 68f1d2b4d3SLarry Finger #define RTL92C_MAX_PATH_NUM 2 69f1d2b4d3SLarry Finger 70f1d2b4d3SLarry Finger enum baseband_config_type { 71f1d2b4d3SLarry Finger BASEBAND_CONFIG_PHY_REG = 0, 72f1d2b4d3SLarry Finger BASEBAND_CONFIG_AGC_TAB = 1, 73f1d2b4d3SLarry Finger }; 74f1d2b4d3SLarry Finger 75f1d2b4d3SLarry Finger enum ant_div_type { 76f1d2b4d3SLarry Finger NO_ANTDIV = 0xFF, 77f1d2b4d3SLarry Finger CG_TRX_HW_ANTDIV = 0x01, 78f1d2b4d3SLarry Finger CGCS_RX_HW_ANTDIV = 0x02, 79f1d2b4d3SLarry Finger FIXED_HW_ANTDIV = 0x03, 80f1d2b4d3SLarry Finger CG_TRX_SMART_ANTDIV = 0x04, 81f1d2b4d3SLarry Finger CGCS_RX_SW_ANTDIV = 0x05, 82f1d2b4d3SLarry Finger 83f1d2b4d3SLarry Finger }; 84f1d2b4d3SLarry Finger 85f1d2b4d3SLarry Finger u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw, 86f1d2b4d3SLarry Finger enum radio_path rfpath, 87f1d2b4d3SLarry Finger u32 regaddr, u32 bitmask); 88f1d2b4d3SLarry Finger void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw, 89f1d2b4d3SLarry Finger enum radio_path rfpath, 90f1d2b4d3SLarry Finger u32 regaddr, u32 bitmask, u32 data); 91f1d2b4d3SLarry Finger bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw); 92f1d2b4d3SLarry Finger bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw); 93f1d2b4d3SLarry Finger bool rtl8723be_phy_rf_config(struct ieee80211_hw *hw); 94f1d2b4d3SLarry Finger void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); 95f1d2b4d3SLarry Finger void rtl8723be_phy_set_txpower_level(struct ieee80211_hw *hw, 96f1d2b4d3SLarry Finger u8 channel); 97f1d2b4d3SLarry Finger void rtl8723be_phy_scan_operation_backup(struct ieee80211_hw *hw, 98f1d2b4d3SLarry Finger u8 operation); 99f1d2b4d3SLarry Finger void rtl8723be_phy_set_bw_mode_callback(struct ieee80211_hw *hw); 100f1d2b4d3SLarry Finger void rtl8723be_phy_set_bw_mode(struct ieee80211_hw *hw, 101f1d2b4d3SLarry Finger enum nl80211_channel_type ch_type); 102f1d2b4d3SLarry Finger void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw); 103f1d2b4d3SLarry Finger u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw); 104f1d2b4d3SLarry Finger void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw, 105f1d2b4d3SLarry Finger bool b_recovery); 106f1d2b4d3SLarry Finger void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw); 107f1d2b4d3SLarry Finger void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain); 108f1d2b4d3SLarry Finger bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 109f1d2b4d3SLarry Finger enum radio_path rfpath); 110f1d2b4d3SLarry Finger bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); 111f1d2b4d3SLarry Finger bool rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw, 112f1d2b4d3SLarry Finger enum rf_pwrstate rfpwr_state); 113f1d2b4d3SLarry Finger #endif 114