11ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
233aca94dSKalle Valo /*
333aca94dSKalle Valo Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
433aca94dSKalle Valo <http://rt2x00.serialmonkey.com>
533aca94dSKalle Valo
633aca94dSKalle Valo */
733aca94dSKalle Valo
833aca94dSKalle Valo /*
933aca94dSKalle Valo Module: rt2x00
1033aca94dSKalle Valo Abstract: rt2x00 queue datastructures and routines
1133aca94dSKalle Valo */
1233aca94dSKalle Valo
1333aca94dSKalle Valo #ifndef RT2X00QUEUE_H
1433aca94dSKalle Valo #define RT2X00QUEUE_H
1533aca94dSKalle Valo
1633aca94dSKalle Valo #include <linux/prefetch.h>
1733aca94dSKalle Valo
1833aca94dSKalle Valo /**
1933aca94dSKalle Valo * DOC: Entry frame size
2033aca94dSKalle Valo *
2133aca94dSKalle Valo * Ralink PCI devices demand the Frame size to be a multiple of 128 bytes,
2233aca94dSKalle Valo * for USB devices this restriction does not apply, but the value of
2333aca94dSKalle Valo * 2432 makes sense since it is big enough to contain the maximum fragment
2433aca94dSKalle Valo * size according to the ieee802.11 specs.
2533aca94dSKalle Valo * The aggregation size depends on support from the driver, but should
2633aca94dSKalle Valo * be something around 3840 bytes.
2733aca94dSKalle Valo */
2833aca94dSKalle Valo #define DATA_FRAME_SIZE 2432
2933aca94dSKalle Valo #define MGMT_FRAME_SIZE 256
3033aca94dSKalle Valo #define AGGREGATION_SIZE 3840
3133aca94dSKalle Valo
3233aca94dSKalle Valo /**
3333aca94dSKalle Valo * enum data_queue_qid: Queue identification
3433aca94dSKalle Valo *
3533aca94dSKalle Valo * @QID_AC_VO: AC VO queue
3633aca94dSKalle Valo * @QID_AC_VI: AC VI queue
3733aca94dSKalle Valo * @QID_AC_BE: AC BE queue
3833aca94dSKalle Valo * @QID_AC_BK: AC BK queue
3933aca94dSKalle Valo * @QID_HCCA: HCCA queue
4033aca94dSKalle Valo * @QID_MGMT: MGMT queue (prio queue)
4133aca94dSKalle Valo * @QID_RX: RX queue
4233aca94dSKalle Valo * @QID_OTHER: None of the above (don't use, only present for completeness)
4333aca94dSKalle Valo * @QID_BEACON: Beacon queue (value unspecified, don't send it to device)
4433aca94dSKalle Valo * @QID_ATIM: Atim queue (value unspecified, don't send it to device)
4533aca94dSKalle Valo */
4633aca94dSKalle Valo enum data_queue_qid {
4733aca94dSKalle Valo QID_AC_VO = 0,
4833aca94dSKalle Valo QID_AC_VI = 1,
4933aca94dSKalle Valo QID_AC_BE = 2,
5033aca94dSKalle Valo QID_AC_BK = 3,
5133aca94dSKalle Valo QID_HCCA = 4,
5233aca94dSKalle Valo QID_MGMT = 13,
5333aca94dSKalle Valo QID_RX = 14,
5433aca94dSKalle Valo QID_OTHER = 15,
5533aca94dSKalle Valo QID_BEACON,
5633aca94dSKalle Valo QID_ATIM,
5733aca94dSKalle Valo };
5833aca94dSKalle Valo
5933aca94dSKalle Valo /**
6033aca94dSKalle Valo * enum skb_frame_desc_flags: Flags for &struct skb_frame_desc
6133aca94dSKalle Valo *
6233aca94dSKalle Valo * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX
6333aca94dSKalle Valo * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX
6433aca94dSKalle Valo * @SKBDESC_IV_STRIPPED: Frame contained a IV/EIV provided by
6533aca94dSKalle Valo * mac80211 but was stripped for processing by the driver.
6633aca94dSKalle Valo * @SKBDESC_NOT_MAC80211: Frame didn't originate from mac80211,
6733aca94dSKalle Valo * don't try to pass it back.
6833aca94dSKalle Valo * @SKBDESC_DESC_IN_SKB: The descriptor is at the start of the
6933aca94dSKalle Valo * skb, instead of in the desc field.
7033aca94dSKalle Valo */
7133aca94dSKalle Valo enum skb_frame_desc_flags {
7233aca94dSKalle Valo SKBDESC_DMA_MAPPED_RX = 1 << 0,
7333aca94dSKalle Valo SKBDESC_DMA_MAPPED_TX = 1 << 1,
7433aca94dSKalle Valo SKBDESC_IV_STRIPPED = 1 << 2,
7533aca94dSKalle Valo SKBDESC_NOT_MAC80211 = 1 << 3,
7633aca94dSKalle Valo SKBDESC_DESC_IN_SKB = 1 << 4,
7733aca94dSKalle Valo };
7833aca94dSKalle Valo
7933aca94dSKalle Valo /**
8033aca94dSKalle Valo * struct skb_frame_desc: Descriptor information for the skb buffer
8133aca94dSKalle Valo *
8233aca94dSKalle Valo * This structure is placed over the driver_data array, this means that
8333aca94dSKalle Valo * this structure should not exceed the size of that array (40 bytes).
8433aca94dSKalle Valo *
8533aca94dSKalle Valo * @flags: Frame flags, see &enum skb_frame_desc_flags.
8633aca94dSKalle Valo * @desc_len: Length of the frame descriptor.
8733aca94dSKalle Valo * @tx_rate_idx: the index of the TX rate, used for TX status reporting
8833aca94dSKalle Valo * @tx_rate_flags: the TX rate flags, used for TX status reporting
8933aca94dSKalle Valo * @desc: Pointer to descriptor part of the frame.
9033aca94dSKalle Valo * Note that this pointer could point to something outside
9133aca94dSKalle Valo * of the scope of the skb->data pointer.
9233aca94dSKalle Valo * @iv: IV/EIV data used during encryption/decryption.
9333aca94dSKalle Valo * @skb_dma: (PCI-only) the DMA address associated with the sk buffer.
94a13d985fSStanislaw Gruszka * @sta: The station where sk buffer was sent.
9533aca94dSKalle Valo */
9633aca94dSKalle Valo struct skb_frame_desc {
9733aca94dSKalle Valo u8 flags;
9833aca94dSKalle Valo
9933aca94dSKalle Valo u8 desc_len;
10033aca94dSKalle Valo u8 tx_rate_idx;
10133aca94dSKalle Valo u8 tx_rate_flags;
10233aca94dSKalle Valo
10333aca94dSKalle Valo void *desc;
10433aca94dSKalle Valo
10533aca94dSKalle Valo __le32 iv[2];
10633aca94dSKalle Valo
10733aca94dSKalle Valo dma_addr_t skb_dma;
108a13d985fSStanislaw Gruszka struct ieee80211_sta *sta;
10933aca94dSKalle Valo };
11033aca94dSKalle Valo
11133aca94dSKalle Valo /**
11233aca94dSKalle Valo * get_skb_frame_desc - Obtain the rt2x00 frame descriptor from a sk_buff.
11333aca94dSKalle Valo * @skb: &struct sk_buff from where we obtain the &struct skb_frame_desc
11433aca94dSKalle Valo */
get_skb_frame_desc(struct sk_buff * skb)11533aca94dSKalle Valo static inline struct skb_frame_desc* get_skb_frame_desc(struct sk_buff *skb)
11633aca94dSKalle Valo {
11733aca94dSKalle Valo BUILD_BUG_ON(sizeof(struct skb_frame_desc) >
11833aca94dSKalle Valo IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
11933aca94dSKalle Valo return (struct skb_frame_desc *)&IEEE80211_SKB_CB(skb)->driver_data;
12033aca94dSKalle Valo }
12133aca94dSKalle Valo
12233aca94dSKalle Valo /**
12333aca94dSKalle Valo * enum rxdone_entry_desc_flags: Flags for &struct rxdone_entry_desc
12433aca94dSKalle Valo *
12533aca94dSKalle Valo * @RXDONE_SIGNAL_PLCP: Signal field contains the plcp value.
12633aca94dSKalle Valo * @RXDONE_SIGNAL_BITRATE: Signal field contains the bitrate value.
12733aca94dSKalle Valo * @RXDONE_SIGNAL_MCS: Signal field contains the mcs value.
12833aca94dSKalle Valo * @RXDONE_MY_BSS: Does this frame originate from device's BSS.
12933aca94dSKalle Valo * @RXDONE_CRYPTO_IV: Driver provided IV/EIV data.
13033aca94dSKalle Valo * @RXDONE_CRYPTO_ICV: Driver provided ICV data.
13133aca94dSKalle Valo * @RXDONE_L2PAD: 802.11 payload has been padded to 4-byte boundary.
13233aca94dSKalle Valo */
13333aca94dSKalle Valo enum rxdone_entry_desc_flags {
13433aca94dSKalle Valo RXDONE_SIGNAL_PLCP = BIT(0),
13533aca94dSKalle Valo RXDONE_SIGNAL_BITRATE = BIT(1),
13633aca94dSKalle Valo RXDONE_SIGNAL_MCS = BIT(2),
13733aca94dSKalle Valo RXDONE_MY_BSS = BIT(3),
13833aca94dSKalle Valo RXDONE_CRYPTO_IV = BIT(4),
13933aca94dSKalle Valo RXDONE_CRYPTO_ICV = BIT(5),
14033aca94dSKalle Valo RXDONE_L2PAD = BIT(6),
14133aca94dSKalle Valo };
14233aca94dSKalle Valo
14333aca94dSKalle Valo /**
14433aca94dSKalle Valo * RXDONE_SIGNAL_MASK - Define to mask off all &rxdone_entry_desc_flags flags
14533aca94dSKalle Valo * except for the RXDONE_SIGNAL_* flags. This is useful to convert the dev_flags
14633aca94dSKalle Valo * from &rxdone_entry_desc to a signal value type.
14733aca94dSKalle Valo */
14833aca94dSKalle Valo #define RXDONE_SIGNAL_MASK \
14933aca94dSKalle Valo ( RXDONE_SIGNAL_PLCP | RXDONE_SIGNAL_BITRATE | RXDONE_SIGNAL_MCS )
15033aca94dSKalle Valo
15133aca94dSKalle Valo /**
15233aca94dSKalle Valo * struct rxdone_entry_desc: RX Entry descriptor
15333aca94dSKalle Valo *
15433aca94dSKalle Valo * Summary of information that has been read from the RX frame descriptor.
15533aca94dSKalle Valo *
15633aca94dSKalle Valo * @timestamp: RX Timestamp
15733aca94dSKalle Valo * @signal: Signal of the received frame.
15833aca94dSKalle Valo * @rssi: RSSI of the received frame.
15933aca94dSKalle Valo * @size: Data size of the received frame.
16033aca94dSKalle Valo * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags).
16133aca94dSKalle Valo * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags).
16233aca94dSKalle Valo * @rate_mode: Rate mode (See @enum rate_modulation).
16333aca94dSKalle Valo * @cipher: Cipher type used during decryption.
16433aca94dSKalle Valo * @cipher_status: Decryption status.
16533aca94dSKalle Valo * @iv: IV/EIV data used during decryption.
16633aca94dSKalle Valo * @icv: ICV data used during decryption.
16733aca94dSKalle Valo */
16833aca94dSKalle Valo struct rxdone_entry_desc {
16933aca94dSKalle Valo u64 timestamp;
17033aca94dSKalle Valo int signal;
17133aca94dSKalle Valo int rssi;
17233aca94dSKalle Valo int size;
17333aca94dSKalle Valo int flags;
17433aca94dSKalle Valo int dev_flags;
17533aca94dSKalle Valo u16 rate_mode;
1767fdd69c5SJohannes Berg u16 enc_flags;
177da6a4352SJohannes Berg enum mac80211_rx_encoding encoding;
178da6a4352SJohannes Berg enum rate_info_bw bw;
17933aca94dSKalle Valo u8 cipher;
18033aca94dSKalle Valo u8 cipher_status;
18133aca94dSKalle Valo
18233aca94dSKalle Valo __le32 iv[2];
18333aca94dSKalle Valo __le32 icv;
18433aca94dSKalle Valo };
18533aca94dSKalle Valo
18633aca94dSKalle Valo /**
18733aca94dSKalle Valo * enum txdone_entry_desc_flags: Flags for &struct txdone_entry_desc
18833aca94dSKalle Valo *
18933aca94dSKalle Valo * Every txdone report has to contain the basic result of the
19033aca94dSKalle Valo * transmission, either &TXDONE_UNKNOWN, &TXDONE_SUCCESS or
19133aca94dSKalle Valo * &TXDONE_FAILURE. The flag &TXDONE_FALLBACK can be used in
19233aca94dSKalle Valo * conjunction with all of these flags but should only be set
19333aca94dSKalle Valo * if retires > 0. The flag &TXDONE_EXCESSIVE_RETRY can only be used
19433aca94dSKalle Valo * in conjunction with &TXDONE_FAILURE.
19533aca94dSKalle Valo *
19633aca94dSKalle Valo * @TXDONE_UNKNOWN: Hardware could not determine success of transmission.
19733aca94dSKalle Valo * @TXDONE_SUCCESS: Frame was successfully send
19833aca94dSKalle Valo * @TXDONE_FALLBACK: Hardware used fallback rates for retries
19933aca94dSKalle Valo * @TXDONE_FAILURE: Frame was not successfully send
20033aca94dSKalle Valo * @TXDONE_EXCESSIVE_RETRY: In addition to &TXDONE_FAILURE, the
20133aca94dSKalle Valo * frame transmission failed due to excessive retries.
20233aca94dSKalle Valo */
20333aca94dSKalle Valo enum txdone_entry_desc_flags {
20433aca94dSKalle Valo TXDONE_UNKNOWN,
20533aca94dSKalle Valo TXDONE_SUCCESS,
20633aca94dSKalle Valo TXDONE_FALLBACK,
20733aca94dSKalle Valo TXDONE_FAILURE,
20833aca94dSKalle Valo TXDONE_EXCESSIVE_RETRY,
20933aca94dSKalle Valo TXDONE_AMPDU,
210ec80ad70SStanislaw Gruszka TXDONE_NO_ACK_REQ,
21133aca94dSKalle Valo };
21233aca94dSKalle Valo
21333aca94dSKalle Valo /**
21433aca94dSKalle Valo * struct txdone_entry_desc: TX done entry descriptor
21533aca94dSKalle Valo *
21633aca94dSKalle Valo * Summary of information that has been read from the TX frame descriptor
21733aca94dSKalle Valo * after the device is done with transmission.
21833aca94dSKalle Valo *
21933aca94dSKalle Valo * @flags: TX done flags (See &enum txdone_entry_desc_flags).
22033aca94dSKalle Valo * @retry: Retry count.
22133aca94dSKalle Valo */
22233aca94dSKalle Valo struct txdone_entry_desc {
22333aca94dSKalle Valo unsigned long flags;
22433aca94dSKalle Valo int retry;
22533aca94dSKalle Valo };
22633aca94dSKalle Valo
22733aca94dSKalle Valo /**
22833aca94dSKalle Valo * enum txentry_desc_flags: Status flags for TX entry descriptor
22933aca94dSKalle Valo *
23033aca94dSKalle Valo * @ENTRY_TXD_RTS_FRAME: This frame is a RTS frame.
23133aca94dSKalle Valo * @ENTRY_TXD_CTS_FRAME: This frame is a CTS-to-self frame.
23233aca94dSKalle Valo * @ENTRY_TXD_GENERATE_SEQ: This frame requires sequence counter.
23333aca94dSKalle Valo * @ENTRY_TXD_FIRST_FRAGMENT: This is the first frame.
23433aca94dSKalle Valo * @ENTRY_TXD_MORE_FRAG: This frame is followed by another fragment.
23533aca94dSKalle Valo * @ENTRY_TXD_REQ_TIMESTAMP: Require timestamp to be inserted.
23633aca94dSKalle Valo * @ENTRY_TXD_BURST: This frame belongs to the same burst event.
23733aca94dSKalle Valo * @ENTRY_TXD_ACK: An ACK is required for this frame.
23833aca94dSKalle Valo * @ENTRY_TXD_RETRY_MODE: When set, the long retry count is used.
23933aca94dSKalle Valo * @ENTRY_TXD_ENCRYPT: This frame should be encrypted.
24033aca94dSKalle Valo * @ENTRY_TXD_ENCRYPT_PAIRWISE: Use pairwise key table (instead of shared).
24133aca94dSKalle Valo * @ENTRY_TXD_ENCRYPT_IV: Generate IV/EIV in hardware.
24233aca94dSKalle Valo * @ENTRY_TXD_ENCRYPT_MMIC: Generate MIC in hardware.
24333aca94dSKalle Valo * @ENTRY_TXD_HT_AMPDU: This frame is part of an AMPDU.
24433aca94dSKalle Valo * @ENTRY_TXD_HT_BW_40: Use 40MHz Bandwidth.
24533aca94dSKalle Valo * @ENTRY_TXD_HT_SHORT_GI: Use short GI.
24633aca94dSKalle Valo * @ENTRY_TXD_HT_MIMO_PS: The receiving STA is in dynamic SM PS mode.
24733aca94dSKalle Valo */
24833aca94dSKalle Valo enum txentry_desc_flags {
24933aca94dSKalle Valo ENTRY_TXD_RTS_FRAME,
25033aca94dSKalle Valo ENTRY_TXD_CTS_FRAME,
25133aca94dSKalle Valo ENTRY_TXD_GENERATE_SEQ,
25233aca94dSKalle Valo ENTRY_TXD_FIRST_FRAGMENT,
25333aca94dSKalle Valo ENTRY_TXD_MORE_FRAG,
25433aca94dSKalle Valo ENTRY_TXD_REQ_TIMESTAMP,
25533aca94dSKalle Valo ENTRY_TXD_BURST,
25633aca94dSKalle Valo ENTRY_TXD_ACK,
25733aca94dSKalle Valo ENTRY_TXD_RETRY_MODE,
25833aca94dSKalle Valo ENTRY_TXD_ENCRYPT,
25933aca94dSKalle Valo ENTRY_TXD_ENCRYPT_PAIRWISE,
26033aca94dSKalle Valo ENTRY_TXD_ENCRYPT_IV,
26133aca94dSKalle Valo ENTRY_TXD_ENCRYPT_MMIC,
26233aca94dSKalle Valo ENTRY_TXD_HT_AMPDU,
26333aca94dSKalle Valo ENTRY_TXD_HT_BW_40,
26433aca94dSKalle Valo ENTRY_TXD_HT_SHORT_GI,
26533aca94dSKalle Valo ENTRY_TXD_HT_MIMO_PS,
26633aca94dSKalle Valo };
26733aca94dSKalle Valo
26833aca94dSKalle Valo /**
26933aca94dSKalle Valo * struct txentry_desc: TX Entry descriptor
27033aca94dSKalle Valo *
27133aca94dSKalle Valo * Summary of information for the frame descriptor before sending a TX frame.
27233aca94dSKalle Valo *
27333aca94dSKalle Valo * @flags: Descriptor flags (See &enum queue_entry_flags).
27433aca94dSKalle Valo * @length: Length of the entire frame.
27533aca94dSKalle Valo * @header_length: Length of 802.11 header.
27633aca94dSKalle Valo * @length_high: PLCP length high word.
27733aca94dSKalle Valo * @length_low: PLCP length low word.
27833aca94dSKalle Valo * @signal: PLCP signal.
27933aca94dSKalle Valo * @service: PLCP service.
28033aca94dSKalle Valo * @msc: MCS.
28133aca94dSKalle Valo * @stbc: Use Space Time Block Coding (only available for MCS rates < 8).
28233aca94dSKalle Valo * @ba_size: Size of the recepients RX reorder buffer - 1.
28333aca94dSKalle Valo * @rate_mode: Rate mode (See @enum rate_modulation).
28433aca94dSKalle Valo * @mpdu_density: MDPU density.
28533aca94dSKalle Valo * @retry_limit: Max number of retries.
28633aca94dSKalle Valo * @ifs: IFS value.
28733aca94dSKalle Valo * @txop: IFS value for 11n capable chips.
28833aca94dSKalle Valo * @cipher: Cipher type used for encryption.
28933aca94dSKalle Valo * @key_idx: Key index used for encryption.
29033aca94dSKalle Valo * @iv_offset: Position where IV should be inserted by hardware.
29133aca94dSKalle Valo * @iv_len: Length of IV data.
29233aca94dSKalle Valo */
29333aca94dSKalle Valo struct txentry_desc {
29433aca94dSKalle Valo unsigned long flags;
29533aca94dSKalle Valo
29633aca94dSKalle Valo u16 length;
29733aca94dSKalle Valo u16 header_length;
29833aca94dSKalle Valo
29933aca94dSKalle Valo union {
30033aca94dSKalle Valo struct {
30133aca94dSKalle Valo u16 length_high;
30233aca94dSKalle Valo u16 length_low;
30333aca94dSKalle Valo u16 signal;
30433aca94dSKalle Valo u16 service;
30533aca94dSKalle Valo enum ifs ifs;
30633aca94dSKalle Valo } plcp;
30733aca94dSKalle Valo
30833aca94dSKalle Valo struct {
30933aca94dSKalle Valo u16 mcs;
31033aca94dSKalle Valo u8 stbc;
31133aca94dSKalle Valo u8 ba_size;
31233aca94dSKalle Valo u8 mpdu_density;
31333aca94dSKalle Valo enum txop txop;
31433aca94dSKalle Valo int wcid;
31533aca94dSKalle Valo } ht;
31633aca94dSKalle Valo } u;
31733aca94dSKalle Valo
31833aca94dSKalle Valo enum rate_modulation rate_mode;
31933aca94dSKalle Valo
32033aca94dSKalle Valo short retry_limit;
32133aca94dSKalle Valo
32233aca94dSKalle Valo enum cipher cipher;
32333aca94dSKalle Valo u16 key_idx;
32433aca94dSKalle Valo u16 iv_offset;
32533aca94dSKalle Valo u16 iv_len;
32633aca94dSKalle Valo };
32733aca94dSKalle Valo
32833aca94dSKalle Valo /**
32933aca94dSKalle Valo * enum queue_entry_flags: Status flags for queue entry
33033aca94dSKalle Valo *
33133aca94dSKalle Valo * @ENTRY_BCN_ASSIGNED: This entry has been assigned to an interface.
33233aca94dSKalle Valo * As long as this bit is set, this entry may only be touched
33333aca94dSKalle Valo * through the interface structure.
33433aca94dSKalle Valo * @ENTRY_OWNER_DEVICE_DATA: This entry is owned by the device for data
33533aca94dSKalle Valo * transfer (either TX or RX depending on the queue). The entry should
33633aca94dSKalle Valo * only be touched after the device has signaled it is done with it.
33733aca94dSKalle Valo * @ENTRY_DATA_PENDING: This entry contains a valid frame and is waiting
33833aca94dSKalle Valo * for the signal to start sending.
33933aca94dSKalle Valo * @ENTRY_DATA_IO_FAILED: Hardware indicated that an IO error occurred
34033aca94dSKalle Valo * while transferring the data to the hardware. No TX status report will
34133aca94dSKalle Valo * be expected from the hardware.
34233aca94dSKalle Valo * @ENTRY_DATA_STATUS_PENDING: The entry has been send to the device and
34333aca94dSKalle Valo * returned. It is now waiting for the status reporting before the
34433aca94dSKalle Valo * entry can be reused again.
34533aca94dSKalle Valo */
34633aca94dSKalle Valo enum queue_entry_flags {
34733aca94dSKalle Valo ENTRY_BCN_ASSIGNED,
34833aca94dSKalle Valo ENTRY_BCN_ENABLED,
34933aca94dSKalle Valo ENTRY_OWNER_DEVICE_DATA,
35033aca94dSKalle Valo ENTRY_DATA_PENDING,
35133aca94dSKalle Valo ENTRY_DATA_IO_FAILED,
35233aca94dSKalle Valo ENTRY_DATA_STATUS_PENDING,
35333aca94dSKalle Valo };
35433aca94dSKalle Valo
35533aca94dSKalle Valo /**
35633aca94dSKalle Valo * struct queue_entry: Entry inside the &struct data_queue
35733aca94dSKalle Valo *
35833aca94dSKalle Valo * @flags: Entry flags, see &enum queue_entry_flags.
35933aca94dSKalle Valo * @last_action: Timestamp of last change.
36033aca94dSKalle Valo * @queue: The data queue (&struct data_queue) to which this entry belongs.
36133aca94dSKalle Valo * @skb: The buffer which is currently being transmitted (for TX queue),
36233aca94dSKalle Valo * or used to directly receive data in (for RX queue).
36333aca94dSKalle Valo * @entry_idx: The entry index number.
36433aca94dSKalle Valo * @priv_data: Private data belonging to this queue entry. The pointer
36533aca94dSKalle Valo * points to data specific to a particular driver and queue type.
36633aca94dSKalle Valo * @status: Device specific status
36733aca94dSKalle Valo */
36833aca94dSKalle Valo struct queue_entry {
36933aca94dSKalle Valo unsigned long flags;
37033aca94dSKalle Valo unsigned long last_action;
37133aca94dSKalle Valo
37233aca94dSKalle Valo struct data_queue *queue;
37333aca94dSKalle Valo
37433aca94dSKalle Valo struct sk_buff *skb;
37533aca94dSKalle Valo
37633aca94dSKalle Valo unsigned int entry_idx;
37733aca94dSKalle Valo
37833aca94dSKalle Valo void *priv_data;
37933aca94dSKalle Valo };
38033aca94dSKalle Valo
38133aca94dSKalle Valo /**
38233aca94dSKalle Valo * enum queue_index: Queue index type
38333aca94dSKalle Valo *
38433aca94dSKalle Valo * @Q_INDEX: Index pointer to the current entry in the queue, if this entry is
38533aca94dSKalle Valo * owned by the hardware then the queue is considered to be full.
38633aca94dSKalle Valo * @Q_INDEX_DMA_DONE: Index pointer for the next entry which will have been
38733aca94dSKalle Valo * transferred to the hardware.
38833aca94dSKalle Valo * @Q_INDEX_DONE: Index pointer to the next entry which will be completed by
38933aca94dSKalle Valo * the hardware and for which we need to run the txdone handler. If this
39033aca94dSKalle Valo * entry is not owned by the hardware the queue is considered to be empty.
39133aca94dSKalle Valo * @Q_INDEX_MAX: Keep last, used in &struct data_queue to determine the size
39233aca94dSKalle Valo * of the index array.
39333aca94dSKalle Valo */
39433aca94dSKalle Valo enum queue_index {
39533aca94dSKalle Valo Q_INDEX,
39633aca94dSKalle Valo Q_INDEX_DMA_DONE,
39733aca94dSKalle Valo Q_INDEX_DONE,
39833aca94dSKalle Valo Q_INDEX_MAX,
39933aca94dSKalle Valo };
40033aca94dSKalle Valo
40133aca94dSKalle Valo /**
40233aca94dSKalle Valo * enum data_queue_flags: Status flags for data queues
40333aca94dSKalle Valo *
40433aca94dSKalle Valo * @QUEUE_STARTED: The queue has been started. Fox RX queues this means the
40533aca94dSKalle Valo * device might be DMA'ing skbuffers. TX queues will accept skbuffers to
40633aca94dSKalle Valo * be transmitted and beacon queues will start beaconing the configured
40733aca94dSKalle Valo * beacons.
40833aca94dSKalle Valo * @QUEUE_PAUSED: The queue has been started but is currently paused.
40933aca94dSKalle Valo * When this bit is set, the queue has been stopped in mac80211,
41033aca94dSKalle Valo * preventing new frames to be enqueued. However, a few frames
41133aca94dSKalle Valo * might still appear shortly after the pausing...
41233aca94dSKalle Valo */
41333aca94dSKalle Valo enum data_queue_flags {
41433aca94dSKalle Valo QUEUE_STARTED,
41533aca94dSKalle Valo QUEUE_PAUSED,
41633aca94dSKalle Valo };
41733aca94dSKalle Valo
41833aca94dSKalle Valo /**
41933aca94dSKalle Valo * struct data_queue: Data queue
42033aca94dSKalle Valo *
42133aca94dSKalle Valo * @rt2x00dev: Pointer to main &struct rt2x00dev where this queue belongs to.
42233aca94dSKalle Valo * @entries: Base address of the &struct queue_entry which are
42333aca94dSKalle Valo * part of this queue.
42433aca94dSKalle Valo * @qid: The queue identification, see &enum data_queue_qid.
42533aca94dSKalle Valo * @flags: Entry flags, see &enum queue_entry_flags.
42633aca94dSKalle Valo * @status_lock: The mutex for protecting the start/stop/flush
42733aca94dSKalle Valo * handling on this queue.
42833aca94dSKalle Valo * @tx_lock: Spinlock to serialize tx operations on this queue.
42933aca94dSKalle Valo * @index_lock: Spinlock to protect index handling. Whenever @index, @index_done or
43033aca94dSKalle Valo * @index_crypt needs to be changed this lock should be grabbed to prevent
43133aca94dSKalle Valo * index corruption due to concurrency.
43233aca94dSKalle Valo * @count: Number of frames handled in the queue.
43333aca94dSKalle Valo * @limit: Maximum number of entries in the queue.
43433aca94dSKalle Valo * @threshold: Minimum number of free entries before queue is kicked by force.
43533aca94dSKalle Valo * @length: Number of frames in queue.
43633aca94dSKalle Valo * @index: Index pointers to entry positions in the queue,
43733aca94dSKalle Valo * use &enum queue_index to get a specific index field.
438*759c5b59SStanislaw Gruszka * @wd_count: watchdog counter number of times entry does change
439*759c5b59SStanislaw Gruszka * in the queue
440*759c5b59SStanislaw Gruszka * @wd_idx: index of queue entry saved by watchdog
44133aca94dSKalle Valo * @txop: maximum burst time.
44233aca94dSKalle Valo * @aifs: The aifs value for outgoing frames (field ignored in RX queue).
44333aca94dSKalle Valo * @cw_min: The cw min value for outgoing frames (field ignored in RX queue).
44433aca94dSKalle Valo * @cw_max: The cw max value for outgoing frames (field ignored in RX queue).
44533aca94dSKalle Valo * @data_size: Maximum data size for the frames in this queue.
44633aca94dSKalle Valo * @desc_size: Hardware descriptor size for the data in this queue.
44733aca94dSKalle Valo * @priv_size: Size of per-queue_entry private data.
44833aca94dSKalle Valo * @usb_endpoint: Device endpoint used for communication (USB only)
44933aca94dSKalle Valo * @usb_maxpacket: Max packet size for given endpoint (USB only)
45033aca94dSKalle Valo */
45133aca94dSKalle Valo struct data_queue {
45233aca94dSKalle Valo struct rt2x00_dev *rt2x00dev;
45333aca94dSKalle Valo struct queue_entry *entries;
45433aca94dSKalle Valo
45533aca94dSKalle Valo enum data_queue_qid qid;
45633aca94dSKalle Valo unsigned long flags;
45733aca94dSKalle Valo
45833aca94dSKalle Valo struct mutex status_lock;
45933aca94dSKalle Valo spinlock_t tx_lock;
46033aca94dSKalle Valo spinlock_t index_lock;
46133aca94dSKalle Valo
46233aca94dSKalle Valo unsigned int count;
46333aca94dSKalle Valo unsigned short limit;
46433aca94dSKalle Valo unsigned short threshold;
46533aca94dSKalle Valo unsigned short length;
46633aca94dSKalle Valo unsigned short index[Q_INDEX_MAX];
46733aca94dSKalle Valo
468*759c5b59SStanislaw Gruszka unsigned short wd_count;
469*759c5b59SStanislaw Gruszka unsigned int wd_idx;
470*759c5b59SStanislaw Gruszka
47133aca94dSKalle Valo unsigned short txop;
47233aca94dSKalle Valo unsigned short aifs;
47333aca94dSKalle Valo unsigned short cw_min;
47433aca94dSKalle Valo unsigned short cw_max;
47533aca94dSKalle Valo
47633aca94dSKalle Valo unsigned short data_size;
47733aca94dSKalle Valo unsigned char desc_size;
47833aca94dSKalle Valo unsigned char winfo_size;
47933aca94dSKalle Valo unsigned short priv_size;
48033aca94dSKalle Valo
48133aca94dSKalle Valo unsigned short usb_endpoint;
48233aca94dSKalle Valo unsigned short usb_maxpacket;
48333aca94dSKalle Valo };
48433aca94dSKalle Valo
48533aca94dSKalle Valo /**
48633aca94dSKalle Valo * queue_end - Return pointer to the last queue (HELPER MACRO).
48733aca94dSKalle Valo * @__dev: Pointer to &struct rt2x00_dev
48833aca94dSKalle Valo *
48933aca94dSKalle Valo * Using the base rx pointer and the maximum number of available queues,
49033aca94dSKalle Valo * this macro will return the address of 1 position beyond the end of the
49133aca94dSKalle Valo * queues array.
49233aca94dSKalle Valo */
49333aca94dSKalle Valo #define queue_end(__dev) \
49433aca94dSKalle Valo &(__dev)->rx[(__dev)->data_queues]
49533aca94dSKalle Valo
49633aca94dSKalle Valo /**
49733aca94dSKalle Valo * tx_queue_end - Return pointer to the last TX queue (HELPER MACRO).
49833aca94dSKalle Valo * @__dev: Pointer to &struct rt2x00_dev
49933aca94dSKalle Valo *
50033aca94dSKalle Valo * Using the base tx pointer and the maximum number of available TX
50133aca94dSKalle Valo * queues, this macro will return the address of 1 position beyond
50233aca94dSKalle Valo * the end of the TX queue array.
50333aca94dSKalle Valo */
50433aca94dSKalle Valo #define tx_queue_end(__dev) \
50533aca94dSKalle Valo &(__dev)->tx[(__dev)->ops->tx_queues]
50633aca94dSKalle Valo
50733aca94dSKalle Valo /**
50833aca94dSKalle Valo * queue_next - Return pointer to next queue in list (HELPER MACRO).
50933aca94dSKalle Valo * @__queue: Current queue for which we need the next queue
51033aca94dSKalle Valo *
51133aca94dSKalle Valo * Using the current queue address we take the address directly
51233aca94dSKalle Valo * after the queue to take the next queue. Note that this macro
51333aca94dSKalle Valo * should be used carefully since it does not protect against
51433aca94dSKalle Valo * moving past the end of the list. (See macros &queue_end and
51533aca94dSKalle Valo * &tx_queue_end for determining the end of the queue).
51633aca94dSKalle Valo */
51733aca94dSKalle Valo #define queue_next(__queue) \
51833aca94dSKalle Valo &(__queue)[1]
51933aca94dSKalle Valo
52033aca94dSKalle Valo /**
52133aca94dSKalle Valo * queue_loop - Loop through the queues within a specific range (HELPER MACRO).
52233aca94dSKalle Valo * @__entry: Pointer where the current queue entry will be stored in.
52333aca94dSKalle Valo * @__start: Start queue pointer.
52433aca94dSKalle Valo * @__end: End queue pointer.
52533aca94dSKalle Valo *
52633aca94dSKalle Valo * This macro will loop through all queues between &__start and &__end.
52733aca94dSKalle Valo */
52833aca94dSKalle Valo #define queue_loop(__entry, __start, __end) \
52933aca94dSKalle Valo for ((__entry) = (__start); \
53033aca94dSKalle Valo prefetch(queue_next(__entry)), (__entry) != (__end);\
53133aca94dSKalle Valo (__entry) = queue_next(__entry))
53233aca94dSKalle Valo
53333aca94dSKalle Valo /**
53433aca94dSKalle Valo * queue_for_each - Loop through all queues
53533aca94dSKalle Valo * @__dev: Pointer to &struct rt2x00_dev
53633aca94dSKalle Valo * @__entry: Pointer where the current queue entry will be stored in.
53733aca94dSKalle Valo *
53833aca94dSKalle Valo * This macro will loop through all available queues.
53933aca94dSKalle Valo */
54033aca94dSKalle Valo #define queue_for_each(__dev, __entry) \
54133aca94dSKalle Valo queue_loop(__entry, (__dev)->rx, queue_end(__dev))
54233aca94dSKalle Valo
54333aca94dSKalle Valo /**
54433aca94dSKalle Valo * tx_queue_for_each - Loop through the TX queues
54533aca94dSKalle Valo * @__dev: Pointer to &struct rt2x00_dev
54633aca94dSKalle Valo * @__entry: Pointer where the current queue entry will be stored in.
54733aca94dSKalle Valo *
54833aca94dSKalle Valo * This macro will loop through all TX related queues excluding
54933aca94dSKalle Valo * the Beacon and Atim queues.
55033aca94dSKalle Valo */
55133aca94dSKalle Valo #define tx_queue_for_each(__dev, __entry) \
55233aca94dSKalle Valo queue_loop(__entry, (__dev)->tx, tx_queue_end(__dev))
55333aca94dSKalle Valo
55433aca94dSKalle Valo /**
55533aca94dSKalle Valo * txall_queue_for_each - Loop through all TX related queues
55633aca94dSKalle Valo * @__dev: Pointer to &struct rt2x00_dev
55733aca94dSKalle Valo * @__entry: Pointer where the current queue entry will be stored in.
55833aca94dSKalle Valo *
55933aca94dSKalle Valo * This macro will loop through all TX related queues including
56033aca94dSKalle Valo * the Beacon and Atim queues.
56133aca94dSKalle Valo */
56233aca94dSKalle Valo #define txall_queue_for_each(__dev, __entry) \
56333aca94dSKalle Valo queue_loop(__entry, (__dev)->tx, queue_end(__dev))
56433aca94dSKalle Valo
56533aca94dSKalle Valo /**
56633aca94dSKalle Valo * rt2x00queue_for_each_entry - Loop through all entries in the queue
56733aca94dSKalle Valo * @queue: Pointer to @data_queue
56833aca94dSKalle Valo * @start: &enum queue_index Pointer to start index
56933aca94dSKalle Valo * @end: &enum queue_index Pointer to end index
57033aca94dSKalle Valo * @data: Data to pass to the callback function
57133aca94dSKalle Valo * @fn: The function to call for each &struct queue_entry
57233aca94dSKalle Valo *
57333aca94dSKalle Valo * This will walk through all entries in the queue, in chronological
57433aca94dSKalle Valo * order. This means it will start at the current @start pointer
57533aca94dSKalle Valo * and will walk through the queue until it reaches the @end pointer.
57633aca94dSKalle Valo *
57733aca94dSKalle Valo * If fn returns true for an entry rt2x00queue_for_each_entry will stop
57833aca94dSKalle Valo * processing and return true as well.
57933aca94dSKalle Valo */
58033aca94dSKalle Valo bool rt2x00queue_for_each_entry(struct data_queue *queue,
58133aca94dSKalle Valo enum queue_index start,
58233aca94dSKalle Valo enum queue_index end,
58333aca94dSKalle Valo void *data,
58433aca94dSKalle Valo bool (*fn)(struct queue_entry *entry,
58533aca94dSKalle Valo void *data));
58633aca94dSKalle Valo
58733aca94dSKalle Valo /**
58833aca94dSKalle Valo * rt2x00queue_empty - Check if the queue is empty.
58933aca94dSKalle Valo * @queue: Queue to check if empty.
59033aca94dSKalle Valo */
rt2x00queue_empty(struct data_queue * queue)59133aca94dSKalle Valo static inline int rt2x00queue_empty(struct data_queue *queue)
59233aca94dSKalle Valo {
59333aca94dSKalle Valo return queue->length == 0;
59433aca94dSKalle Valo }
59533aca94dSKalle Valo
59633aca94dSKalle Valo /**
59733aca94dSKalle Valo * rt2x00queue_full - Check if the queue is full.
59833aca94dSKalle Valo * @queue: Queue to check if full.
59933aca94dSKalle Valo */
rt2x00queue_full(struct data_queue * queue)60033aca94dSKalle Valo static inline int rt2x00queue_full(struct data_queue *queue)
60133aca94dSKalle Valo {
60233aca94dSKalle Valo return queue->length == queue->limit;
60333aca94dSKalle Valo }
60433aca94dSKalle Valo
60533aca94dSKalle Valo /**
60633aca94dSKalle Valo * rt2x00queue_free - Check the number of available entries in queue.
60733aca94dSKalle Valo * @queue: Queue to check.
60833aca94dSKalle Valo */
rt2x00queue_available(struct data_queue * queue)60933aca94dSKalle Valo static inline int rt2x00queue_available(struct data_queue *queue)
61033aca94dSKalle Valo {
61133aca94dSKalle Valo return queue->limit - queue->length;
61233aca94dSKalle Valo }
61333aca94dSKalle Valo
61433aca94dSKalle Valo /**
61533aca94dSKalle Valo * rt2x00queue_threshold - Check if the queue is below threshold
61633aca94dSKalle Valo * @queue: Queue to check.
61733aca94dSKalle Valo */
rt2x00queue_threshold(struct data_queue * queue)61833aca94dSKalle Valo static inline int rt2x00queue_threshold(struct data_queue *queue)
61933aca94dSKalle Valo {
62033aca94dSKalle Valo return rt2x00queue_available(queue) < queue->threshold;
62133aca94dSKalle Valo }
62233aca94dSKalle Valo /**
62333aca94dSKalle Valo * rt2x00queue_dma_timeout - Check if a timeout occurred for DMA transfers
62433aca94dSKalle Valo * @entry: Queue entry to check.
62533aca94dSKalle Valo */
rt2x00queue_dma_timeout(struct queue_entry * entry)62633aca94dSKalle Valo static inline int rt2x00queue_dma_timeout(struct queue_entry *entry)
62733aca94dSKalle Valo {
62833aca94dSKalle Valo if (!test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
62933aca94dSKalle Valo return false;
63033aca94dSKalle Valo return time_after(jiffies, entry->last_action + msecs_to_jiffies(100));
63133aca94dSKalle Valo }
63233aca94dSKalle Valo
63333aca94dSKalle Valo /**
63433aca94dSKalle Valo * _rt2x00_desc_read - Read a word from the hardware descriptor.
63533aca94dSKalle Valo * @desc: Base descriptor address
63633aca94dSKalle Valo * @word: Word index from where the descriptor should be read.
63733aca94dSKalle Valo */
_rt2x00_desc_read(__le32 * desc,const u8 word)638b9b23872SArnd Bergmann static inline __le32 _rt2x00_desc_read(__le32 *desc, const u8 word)
63933aca94dSKalle Valo {
640b9b23872SArnd Bergmann return desc[word];
64133aca94dSKalle Valo }
64233aca94dSKalle Valo
64333aca94dSKalle Valo /**
64433aca94dSKalle Valo * rt2x00_desc_read - Read a word from the hardware descriptor, this
64533aca94dSKalle Valo * function will take care of the byte ordering.
64633aca94dSKalle Valo * @desc: Base descriptor address
64733aca94dSKalle Valo * @word: Word index from where the descriptor should be read.
64833aca94dSKalle Valo */
rt2x00_desc_read(__le32 * desc,const u8 word)649b9b23872SArnd Bergmann static inline u32 rt2x00_desc_read(__le32 *desc, const u8 word)
65033aca94dSKalle Valo {
651b9b23872SArnd Bergmann return le32_to_cpu(_rt2x00_desc_read(desc, word));
65233aca94dSKalle Valo }
65333aca94dSKalle Valo
65433aca94dSKalle Valo /**
65533aca94dSKalle Valo * rt2x00_desc_write - write a word to the hardware descriptor, this
65633aca94dSKalle Valo * function will take care of the byte ordering.
65733aca94dSKalle Valo * @desc: Base descriptor address
65833aca94dSKalle Valo * @word: Word index from where the descriptor should be written.
65933aca94dSKalle Valo * @value: Value that should be written into the descriptor.
66033aca94dSKalle Valo */
_rt2x00_desc_write(__le32 * desc,const u8 word,__le32 value)66133aca94dSKalle Valo static inline void _rt2x00_desc_write(__le32 *desc, const u8 word, __le32 value)
66233aca94dSKalle Valo {
66333aca94dSKalle Valo desc[word] = value;
66433aca94dSKalle Valo }
66533aca94dSKalle Valo
66633aca94dSKalle Valo /**
66733aca94dSKalle Valo * rt2x00_desc_write - write a word to the hardware descriptor.
66833aca94dSKalle Valo * @desc: Base descriptor address
66933aca94dSKalle Valo * @word: Word index from where the descriptor should be written.
67033aca94dSKalle Valo * @value: Value that should be written into the descriptor.
67133aca94dSKalle Valo */
rt2x00_desc_write(__le32 * desc,const u8 word,u32 value)67233aca94dSKalle Valo static inline void rt2x00_desc_write(__le32 *desc, const u8 word, u32 value)
67333aca94dSKalle Valo {
67433aca94dSKalle Valo _rt2x00_desc_write(desc, word, cpu_to_le32(value));
67533aca94dSKalle Valo }
67633aca94dSKalle Valo
67733aca94dSKalle Valo #endif /* RT2X00QUEUE_H */
678