1*33aca94dSKalle Valo /* 2*33aca94dSKalle Valo Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> 3*33aca94dSKalle Valo Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com> 4*33aca94dSKalle Valo Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com> 5*33aca94dSKalle Valo <http://rt2x00.serialmonkey.com> 6*33aca94dSKalle Valo 7*33aca94dSKalle Valo This program is free software; you can redistribute it and/or modify 8*33aca94dSKalle Valo it under the terms of the GNU General Public License as published by 9*33aca94dSKalle Valo the Free Software Foundation; either version 2 of the License, or 10*33aca94dSKalle Valo (at your option) any later version. 11*33aca94dSKalle Valo 12*33aca94dSKalle Valo This program is distributed in the hope that it will be useful, 13*33aca94dSKalle Valo but WITHOUT ANY WARRANTY; without even the implied warranty of 14*33aca94dSKalle Valo MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*33aca94dSKalle Valo GNU General Public License for more details. 16*33aca94dSKalle Valo 17*33aca94dSKalle Valo You should have received a copy of the GNU General Public License 18*33aca94dSKalle Valo along with this program; if not, see <http://www.gnu.org/licenses/>. 19*33aca94dSKalle Valo */ 20*33aca94dSKalle Valo 21*33aca94dSKalle Valo /* 22*33aca94dSKalle Valo Module: rt2x00 23*33aca94dSKalle Valo Abstract: rt2x00 global information. 24*33aca94dSKalle Valo */ 25*33aca94dSKalle Valo 26*33aca94dSKalle Valo #ifndef RT2X00_H 27*33aca94dSKalle Valo #define RT2X00_H 28*33aca94dSKalle Valo 29*33aca94dSKalle Valo #include <linux/bitops.h> 30*33aca94dSKalle Valo #include <linux/interrupt.h> 31*33aca94dSKalle Valo #include <linux/skbuff.h> 32*33aca94dSKalle Valo #include <linux/workqueue.h> 33*33aca94dSKalle Valo #include <linux/firmware.h> 34*33aca94dSKalle Valo #include <linux/leds.h> 35*33aca94dSKalle Valo #include <linux/mutex.h> 36*33aca94dSKalle Valo #include <linux/etherdevice.h> 37*33aca94dSKalle Valo #include <linux/input-polldev.h> 38*33aca94dSKalle Valo #include <linux/kfifo.h> 39*33aca94dSKalle Valo #include <linux/hrtimer.h> 40*33aca94dSKalle Valo #include <linux/average.h> 41*33aca94dSKalle Valo 42*33aca94dSKalle Valo #include <net/mac80211.h> 43*33aca94dSKalle Valo 44*33aca94dSKalle Valo #include "rt2x00debug.h" 45*33aca94dSKalle Valo #include "rt2x00dump.h" 46*33aca94dSKalle Valo #include "rt2x00leds.h" 47*33aca94dSKalle Valo #include "rt2x00reg.h" 48*33aca94dSKalle Valo #include "rt2x00queue.h" 49*33aca94dSKalle Valo 50*33aca94dSKalle Valo /* 51*33aca94dSKalle Valo * Module information. 52*33aca94dSKalle Valo */ 53*33aca94dSKalle Valo #define DRV_VERSION "2.3.0" 54*33aca94dSKalle Valo #define DRV_PROJECT "http://rt2x00.serialmonkey.com" 55*33aca94dSKalle Valo 56*33aca94dSKalle Valo /* Debug definitions. 57*33aca94dSKalle Valo * Debug output has to be enabled during compile time. 58*33aca94dSKalle Valo */ 59*33aca94dSKalle Valo #ifdef CONFIG_RT2X00_DEBUG 60*33aca94dSKalle Valo #define DEBUG 61*33aca94dSKalle Valo #endif /* CONFIG_RT2X00_DEBUG */ 62*33aca94dSKalle Valo 63*33aca94dSKalle Valo /* Utility printing macros 64*33aca94dSKalle Valo * rt2x00_probe_err is for messages when rt2x00_dev is uninitialized 65*33aca94dSKalle Valo */ 66*33aca94dSKalle Valo #define rt2x00_probe_err(fmt, ...) \ 67*33aca94dSKalle Valo printk(KERN_ERR KBUILD_MODNAME ": %s: Error - " fmt, \ 68*33aca94dSKalle Valo __func__, ##__VA_ARGS__) 69*33aca94dSKalle Valo #define rt2x00_err(dev, fmt, ...) \ 70*33aca94dSKalle Valo wiphy_err((dev)->hw->wiphy, "%s: Error - " fmt, \ 71*33aca94dSKalle Valo __func__, ##__VA_ARGS__) 72*33aca94dSKalle Valo #define rt2x00_warn(dev, fmt, ...) \ 73*33aca94dSKalle Valo wiphy_warn((dev)->hw->wiphy, "%s: Warning - " fmt, \ 74*33aca94dSKalle Valo __func__, ##__VA_ARGS__) 75*33aca94dSKalle Valo #define rt2x00_info(dev, fmt, ...) \ 76*33aca94dSKalle Valo wiphy_info((dev)->hw->wiphy, "%s: Info - " fmt, \ 77*33aca94dSKalle Valo __func__, ##__VA_ARGS__) 78*33aca94dSKalle Valo 79*33aca94dSKalle Valo /* Various debug levels */ 80*33aca94dSKalle Valo #define rt2x00_dbg(dev, fmt, ...) \ 81*33aca94dSKalle Valo wiphy_dbg((dev)->hw->wiphy, "%s: Debug - " fmt, \ 82*33aca94dSKalle Valo __func__, ##__VA_ARGS__) 83*33aca94dSKalle Valo #define rt2x00_eeprom_dbg(dev, fmt, ...) \ 84*33aca94dSKalle Valo wiphy_dbg((dev)->hw->wiphy, "%s: EEPROM recovery - " fmt, \ 85*33aca94dSKalle Valo __func__, ##__VA_ARGS__) 86*33aca94dSKalle Valo 87*33aca94dSKalle Valo /* 88*33aca94dSKalle Valo * Duration calculations 89*33aca94dSKalle Valo * The rate variable passed is: 100kbs. 90*33aca94dSKalle Valo * To convert from bytes to bits we multiply size with 8, 91*33aca94dSKalle Valo * then the size is multiplied with 10 to make the 92*33aca94dSKalle Valo * real rate -> rate argument correction. 93*33aca94dSKalle Valo */ 94*33aca94dSKalle Valo #define GET_DURATION(__size, __rate) (((__size) * 8 * 10) / (__rate)) 95*33aca94dSKalle Valo #define GET_DURATION_RES(__size, __rate)(((__size) * 8 * 10) % (__rate)) 96*33aca94dSKalle Valo 97*33aca94dSKalle Valo /* 98*33aca94dSKalle Valo * Determine the number of L2 padding bytes required between the header and 99*33aca94dSKalle Valo * the payload. 100*33aca94dSKalle Valo */ 101*33aca94dSKalle Valo #define L2PAD_SIZE(__hdrlen) (-(__hdrlen) & 3) 102*33aca94dSKalle Valo 103*33aca94dSKalle Valo /* 104*33aca94dSKalle Valo * Determine the alignment requirement, 105*33aca94dSKalle Valo * to make sure the 802.11 payload is padded to a 4-byte boundrary 106*33aca94dSKalle Valo * we must determine the address of the payload and calculate the 107*33aca94dSKalle Valo * amount of bytes needed to move the data. 108*33aca94dSKalle Valo */ 109*33aca94dSKalle Valo #define ALIGN_SIZE(__skb, __header) \ 110*33aca94dSKalle Valo ( ((unsigned long)((__skb)->data + (__header))) & 3 ) 111*33aca94dSKalle Valo 112*33aca94dSKalle Valo /* 113*33aca94dSKalle Valo * Constants for extra TX headroom for alignment purposes. 114*33aca94dSKalle Valo */ 115*33aca94dSKalle Valo #define RT2X00_ALIGN_SIZE 4 /* Only whole frame needs alignment */ 116*33aca94dSKalle Valo #define RT2X00_L2PAD_SIZE 8 /* Both header & payload need alignment */ 117*33aca94dSKalle Valo 118*33aca94dSKalle Valo /* 119*33aca94dSKalle Valo * Standard timing and size defines. 120*33aca94dSKalle Valo * These values should follow the ieee80211 specifications. 121*33aca94dSKalle Valo */ 122*33aca94dSKalle Valo #define ACK_SIZE 14 123*33aca94dSKalle Valo #define IEEE80211_HEADER 24 124*33aca94dSKalle Valo #define PLCP 48 125*33aca94dSKalle Valo #define BEACON 100 126*33aca94dSKalle Valo #define PREAMBLE 144 127*33aca94dSKalle Valo #define SHORT_PREAMBLE 72 128*33aca94dSKalle Valo #define SLOT_TIME 20 129*33aca94dSKalle Valo #define SHORT_SLOT_TIME 9 130*33aca94dSKalle Valo #define SIFS 10 131*33aca94dSKalle Valo #define PIFS ( SIFS + SLOT_TIME ) 132*33aca94dSKalle Valo #define SHORT_PIFS ( SIFS + SHORT_SLOT_TIME ) 133*33aca94dSKalle Valo #define DIFS ( PIFS + SLOT_TIME ) 134*33aca94dSKalle Valo #define SHORT_DIFS ( SHORT_PIFS + SHORT_SLOT_TIME ) 135*33aca94dSKalle Valo #define EIFS ( SIFS + DIFS + \ 136*33aca94dSKalle Valo GET_DURATION(IEEE80211_HEADER + ACK_SIZE, 10) ) 137*33aca94dSKalle Valo #define SHORT_EIFS ( SIFS + SHORT_DIFS + \ 138*33aca94dSKalle Valo GET_DURATION(IEEE80211_HEADER + ACK_SIZE, 10) ) 139*33aca94dSKalle Valo 140*33aca94dSKalle Valo enum rt2x00_chip_intf { 141*33aca94dSKalle Valo RT2X00_CHIP_INTF_PCI, 142*33aca94dSKalle Valo RT2X00_CHIP_INTF_PCIE, 143*33aca94dSKalle Valo RT2X00_CHIP_INTF_USB, 144*33aca94dSKalle Valo RT2X00_CHIP_INTF_SOC, 145*33aca94dSKalle Valo }; 146*33aca94dSKalle Valo 147*33aca94dSKalle Valo /* 148*33aca94dSKalle Valo * Chipset identification 149*33aca94dSKalle Valo * The chipset on the device is composed of a RT and RF chip. 150*33aca94dSKalle Valo * The chipset combination is important for determining device capabilities. 151*33aca94dSKalle Valo */ 152*33aca94dSKalle Valo struct rt2x00_chip { 153*33aca94dSKalle Valo u16 rt; 154*33aca94dSKalle Valo #define RT2460 0x2460 155*33aca94dSKalle Valo #define RT2560 0x2560 156*33aca94dSKalle Valo #define RT2570 0x2570 157*33aca94dSKalle Valo #define RT2661 0x2661 158*33aca94dSKalle Valo #define RT2573 0x2573 159*33aca94dSKalle Valo #define RT2860 0x2860 /* 2.4GHz */ 160*33aca94dSKalle Valo #define RT2872 0x2872 /* WSOC */ 161*33aca94dSKalle Valo #define RT2883 0x2883 /* WSOC */ 162*33aca94dSKalle Valo #define RT3070 0x3070 163*33aca94dSKalle Valo #define RT3071 0x3071 164*33aca94dSKalle Valo #define RT3090 0x3090 /* 2.4GHz PCIe */ 165*33aca94dSKalle Valo #define RT3290 0x3290 166*33aca94dSKalle Valo #define RT3352 0x3352 /* WSOC */ 167*33aca94dSKalle Valo #define RT3390 0x3390 168*33aca94dSKalle Valo #define RT3572 0x3572 169*33aca94dSKalle Valo #define RT3593 0x3593 170*33aca94dSKalle Valo #define RT3883 0x3883 /* WSOC */ 171*33aca94dSKalle Valo #define RT5390 0x5390 /* 2.4GHz */ 172*33aca94dSKalle Valo #define RT5392 0x5392 /* 2.4GHz */ 173*33aca94dSKalle Valo #define RT5592 0x5592 174*33aca94dSKalle Valo 175*33aca94dSKalle Valo u16 rf; 176*33aca94dSKalle Valo u16 rev; 177*33aca94dSKalle Valo 178*33aca94dSKalle Valo enum rt2x00_chip_intf intf; 179*33aca94dSKalle Valo }; 180*33aca94dSKalle Valo 181*33aca94dSKalle Valo /* 182*33aca94dSKalle Valo * RF register values that belong to a particular channel. 183*33aca94dSKalle Valo */ 184*33aca94dSKalle Valo struct rf_channel { 185*33aca94dSKalle Valo int channel; 186*33aca94dSKalle Valo u32 rf1; 187*33aca94dSKalle Valo u32 rf2; 188*33aca94dSKalle Valo u32 rf3; 189*33aca94dSKalle Valo u32 rf4; 190*33aca94dSKalle Valo }; 191*33aca94dSKalle Valo 192*33aca94dSKalle Valo /* 193*33aca94dSKalle Valo * Channel information structure 194*33aca94dSKalle Valo */ 195*33aca94dSKalle Valo struct channel_info { 196*33aca94dSKalle Valo unsigned int flags; 197*33aca94dSKalle Valo #define GEOGRAPHY_ALLOWED 0x00000001 198*33aca94dSKalle Valo 199*33aca94dSKalle Valo short max_power; 200*33aca94dSKalle Valo short default_power1; 201*33aca94dSKalle Valo short default_power2; 202*33aca94dSKalle Valo short default_power3; 203*33aca94dSKalle Valo }; 204*33aca94dSKalle Valo 205*33aca94dSKalle Valo /* 206*33aca94dSKalle Valo * Antenna setup values. 207*33aca94dSKalle Valo */ 208*33aca94dSKalle Valo struct antenna_setup { 209*33aca94dSKalle Valo enum antenna rx; 210*33aca94dSKalle Valo enum antenna tx; 211*33aca94dSKalle Valo u8 rx_chain_num; 212*33aca94dSKalle Valo u8 tx_chain_num; 213*33aca94dSKalle Valo }; 214*33aca94dSKalle Valo 215*33aca94dSKalle Valo /* 216*33aca94dSKalle Valo * Quality statistics about the currently active link. 217*33aca94dSKalle Valo */ 218*33aca94dSKalle Valo struct link_qual { 219*33aca94dSKalle Valo /* 220*33aca94dSKalle Valo * Statistics required for Link tuning by driver 221*33aca94dSKalle Valo * The rssi value is provided by rt2x00lib during the 222*33aca94dSKalle Valo * link_tuner() callback function. 223*33aca94dSKalle Valo * The false_cca field is filled during the link_stats() 224*33aca94dSKalle Valo * callback function and could be used during the 225*33aca94dSKalle Valo * link_tuner() callback function. 226*33aca94dSKalle Valo */ 227*33aca94dSKalle Valo int rssi; 228*33aca94dSKalle Valo int false_cca; 229*33aca94dSKalle Valo 230*33aca94dSKalle Valo /* 231*33aca94dSKalle Valo * VGC levels 232*33aca94dSKalle Valo * Hardware driver will tune the VGC level during each call 233*33aca94dSKalle Valo * to the link_tuner() callback function. This vgc_level is 234*33aca94dSKalle Valo * is determined based on the link quality statistics like 235*33aca94dSKalle Valo * average RSSI and the false CCA count. 236*33aca94dSKalle Valo * 237*33aca94dSKalle Valo * In some cases the drivers need to differentiate between 238*33aca94dSKalle Valo * the currently "desired" VGC level and the level configured 239*33aca94dSKalle Valo * in the hardware. The latter is important to reduce the 240*33aca94dSKalle Valo * number of BBP register reads to reduce register access 241*33aca94dSKalle Valo * overhead. For this reason we store both values here. 242*33aca94dSKalle Valo */ 243*33aca94dSKalle Valo u8 vgc_level; 244*33aca94dSKalle Valo u8 vgc_level_reg; 245*33aca94dSKalle Valo 246*33aca94dSKalle Valo /* 247*33aca94dSKalle Valo * Statistics required for Signal quality calculation. 248*33aca94dSKalle Valo * These fields might be changed during the link_stats() 249*33aca94dSKalle Valo * callback function. 250*33aca94dSKalle Valo */ 251*33aca94dSKalle Valo int rx_success; 252*33aca94dSKalle Valo int rx_failed; 253*33aca94dSKalle Valo int tx_success; 254*33aca94dSKalle Valo int tx_failed; 255*33aca94dSKalle Valo }; 256*33aca94dSKalle Valo 257*33aca94dSKalle Valo DECLARE_EWMA(rssi, 1024, 8) 258*33aca94dSKalle Valo 259*33aca94dSKalle Valo /* 260*33aca94dSKalle Valo * Antenna settings about the currently active link. 261*33aca94dSKalle Valo */ 262*33aca94dSKalle Valo struct link_ant { 263*33aca94dSKalle Valo /* 264*33aca94dSKalle Valo * Antenna flags 265*33aca94dSKalle Valo */ 266*33aca94dSKalle Valo unsigned int flags; 267*33aca94dSKalle Valo #define ANTENNA_RX_DIVERSITY 0x00000001 268*33aca94dSKalle Valo #define ANTENNA_TX_DIVERSITY 0x00000002 269*33aca94dSKalle Valo #define ANTENNA_MODE_SAMPLE 0x00000004 270*33aca94dSKalle Valo 271*33aca94dSKalle Valo /* 272*33aca94dSKalle Valo * Currently active TX/RX antenna setup. 273*33aca94dSKalle Valo * When software diversity is used, this will indicate 274*33aca94dSKalle Valo * which antenna is actually used at this time. 275*33aca94dSKalle Valo */ 276*33aca94dSKalle Valo struct antenna_setup active; 277*33aca94dSKalle Valo 278*33aca94dSKalle Valo /* 279*33aca94dSKalle Valo * RSSI history information for the antenna. 280*33aca94dSKalle Valo * Used to determine when to switch antenna 281*33aca94dSKalle Valo * when using software diversity. 282*33aca94dSKalle Valo */ 283*33aca94dSKalle Valo int rssi_history; 284*33aca94dSKalle Valo 285*33aca94dSKalle Valo /* 286*33aca94dSKalle Valo * Current RSSI average of the currently active antenna. 287*33aca94dSKalle Valo * Similar to the avg_rssi in the link_qual structure 288*33aca94dSKalle Valo * this value is updated by using the walking average. 289*33aca94dSKalle Valo */ 290*33aca94dSKalle Valo struct ewma_rssi rssi_ant; 291*33aca94dSKalle Valo }; 292*33aca94dSKalle Valo 293*33aca94dSKalle Valo /* 294*33aca94dSKalle Valo * To optimize the quality of the link we need to store 295*33aca94dSKalle Valo * the quality of received frames and periodically 296*33aca94dSKalle Valo * optimize the link. 297*33aca94dSKalle Valo */ 298*33aca94dSKalle Valo struct link { 299*33aca94dSKalle Valo /* 300*33aca94dSKalle Valo * Link tuner counter 301*33aca94dSKalle Valo * The number of times the link has been tuned 302*33aca94dSKalle Valo * since the radio has been switched on. 303*33aca94dSKalle Valo */ 304*33aca94dSKalle Valo u32 count; 305*33aca94dSKalle Valo 306*33aca94dSKalle Valo /* 307*33aca94dSKalle Valo * Quality measurement values. 308*33aca94dSKalle Valo */ 309*33aca94dSKalle Valo struct link_qual qual; 310*33aca94dSKalle Valo 311*33aca94dSKalle Valo /* 312*33aca94dSKalle Valo * TX/RX antenna setup. 313*33aca94dSKalle Valo */ 314*33aca94dSKalle Valo struct link_ant ant; 315*33aca94dSKalle Valo 316*33aca94dSKalle Valo /* 317*33aca94dSKalle Valo * Currently active average RSSI value 318*33aca94dSKalle Valo */ 319*33aca94dSKalle Valo struct ewma_rssi avg_rssi; 320*33aca94dSKalle Valo 321*33aca94dSKalle Valo /* 322*33aca94dSKalle Valo * Work structure for scheduling periodic link tuning. 323*33aca94dSKalle Valo */ 324*33aca94dSKalle Valo struct delayed_work work; 325*33aca94dSKalle Valo 326*33aca94dSKalle Valo /* 327*33aca94dSKalle Valo * Work structure for scheduling periodic watchdog monitoring. 328*33aca94dSKalle Valo * This work must be scheduled on the kernel workqueue, while 329*33aca94dSKalle Valo * all other work structures must be queued on the mac80211 330*33aca94dSKalle Valo * workqueue. This guarantees that the watchdog can schedule 331*33aca94dSKalle Valo * other work structures and wait for their completion in order 332*33aca94dSKalle Valo * to bring the device/driver back into the desired state. 333*33aca94dSKalle Valo */ 334*33aca94dSKalle Valo struct delayed_work watchdog_work; 335*33aca94dSKalle Valo 336*33aca94dSKalle Valo /* 337*33aca94dSKalle Valo * Work structure for scheduling periodic AGC adjustments. 338*33aca94dSKalle Valo */ 339*33aca94dSKalle Valo struct delayed_work agc_work; 340*33aca94dSKalle Valo 341*33aca94dSKalle Valo /* 342*33aca94dSKalle Valo * Work structure for scheduling periodic VCO calibration. 343*33aca94dSKalle Valo */ 344*33aca94dSKalle Valo struct delayed_work vco_work; 345*33aca94dSKalle Valo }; 346*33aca94dSKalle Valo 347*33aca94dSKalle Valo enum rt2x00_delayed_flags { 348*33aca94dSKalle Valo DELAYED_UPDATE_BEACON, 349*33aca94dSKalle Valo }; 350*33aca94dSKalle Valo 351*33aca94dSKalle Valo /* 352*33aca94dSKalle Valo * Interface structure 353*33aca94dSKalle Valo * Per interface configuration details, this structure 354*33aca94dSKalle Valo * is allocated as the private data for ieee80211_vif. 355*33aca94dSKalle Valo */ 356*33aca94dSKalle Valo struct rt2x00_intf { 357*33aca94dSKalle Valo /* 358*33aca94dSKalle Valo * beacon->skb must be protected with the mutex. 359*33aca94dSKalle Valo */ 360*33aca94dSKalle Valo struct mutex beacon_skb_mutex; 361*33aca94dSKalle Valo 362*33aca94dSKalle Valo /* 363*33aca94dSKalle Valo * Entry in the beacon queue which belongs to 364*33aca94dSKalle Valo * this interface. Each interface has its own 365*33aca94dSKalle Valo * dedicated beacon entry. 366*33aca94dSKalle Valo */ 367*33aca94dSKalle Valo struct queue_entry *beacon; 368*33aca94dSKalle Valo bool enable_beacon; 369*33aca94dSKalle Valo 370*33aca94dSKalle Valo /* 371*33aca94dSKalle Valo * Actions that needed rescheduling. 372*33aca94dSKalle Valo */ 373*33aca94dSKalle Valo unsigned long delayed_flags; 374*33aca94dSKalle Valo 375*33aca94dSKalle Valo /* 376*33aca94dSKalle Valo * Software sequence counter, this is only required 377*33aca94dSKalle Valo * for hardware which doesn't support hardware 378*33aca94dSKalle Valo * sequence counting. 379*33aca94dSKalle Valo */ 380*33aca94dSKalle Valo atomic_t seqno; 381*33aca94dSKalle Valo }; 382*33aca94dSKalle Valo 383*33aca94dSKalle Valo static inline struct rt2x00_intf* vif_to_intf(struct ieee80211_vif *vif) 384*33aca94dSKalle Valo { 385*33aca94dSKalle Valo return (struct rt2x00_intf *)vif->drv_priv; 386*33aca94dSKalle Valo } 387*33aca94dSKalle Valo 388*33aca94dSKalle Valo /** 389*33aca94dSKalle Valo * struct hw_mode_spec: Hardware specifications structure 390*33aca94dSKalle Valo * 391*33aca94dSKalle Valo * Details about the supported modes, rates and channels 392*33aca94dSKalle Valo * of a particular chipset. This is used by rt2x00lib 393*33aca94dSKalle Valo * to build the ieee80211_hw_mode array for mac80211. 394*33aca94dSKalle Valo * 395*33aca94dSKalle Valo * @supported_bands: Bitmask contained the supported bands (2.4GHz, 5.2GHz). 396*33aca94dSKalle Valo * @supported_rates: Rate types which are supported (CCK, OFDM). 397*33aca94dSKalle Valo * @num_channels: Number of supported channels. This is used as array size 398*33aca94dSKalle Valo * for @tx_power_a, @tx_power_bg and @channels. 399*33aca94dSKalle Valo * @channels: Device/chipset specific channel values (See &struct rf_channel). 400*33aca94dSKalle Valo * @channels_info: Additional information for channels (See &struct channel_info). 401*33aca94dSKalle Valo * @ht: Driver HT Capabilities (See &ieee80211_sta_ht_cap). 402*33aca94dSKalle Valo */ 403*33aca94dSKalle Valo struct hw_mode_spec { 404*33aca94dSKalle Valo unsigned int supported_bands; 405*33aca94dSKalle Valo #define SUPPORT_BAND_2GHZ 0x00000001 406*33aca94dSKalle Valo #define SUPPORT_BAND_5GHZ 0x00000002 407*33aca94dSKalle Valo 408*33aca94dSKalle Valo unsigned int supported_rates; 409*33aca94dSKalle Valo #define SUPPORT_RATE_CCK 0x00000001 410*33aca94dSKalle Valo #define SUPPORT_RATE_OFDM 0x00000002 411*33aca94dSKalle Valo 412*33aca94dSKalle Valo unsigned int num_channels; 413*33aca94dSKalle Valo const struct rf_channel *channels; 414*33aca94dSKalle Valo const struct channel_info *channels_info; 415*33aca94dSKalle Valo 416*33aca94dSKalle Valo struct ieee80211_sta_ht_cap ht; 417*33aca94dSKalle Valo }; 418*33aca94dSKalle Valo 419*33aca94dSKalle Valo /* 420*33aca94dSKalle Valo * Configuration structure wrapper around the 421*33aca94dSKalle Valo * mac80211 configuration structure. 422*33aca94dSKalle Valo * When mac80211 configures the driver, rt2x00lib 423*33aca94dSKalle Valo * can precalculate values which are equal for all 424*33aca94dSKalle Valo * rt2x00 drivers. Those values can be stored in here. 425*33aca94dSKalle Valo */ 426*33aca94dSKalle Valo struct rt2x00lib_conf { 427*33aca94dSKalle Valo struct ieee80211_conf *conf; 428*33aca94dSKalle Valo 429*33aca94dSKalle Valo struct rf_channel rf; 430*33aca94dSKalle Valo struct channel_info channel; 431*33aca94dSKalle Valo }; 432*33aca94dSKalle Valo 433*33aca94dSKalle Valo /* 434*33aca94dSKalle Valo * Configuration structure for erp settings. 435*33aca94dSKalle Valo */ 436*33aca94dSKalle Valo struct rt2x00lib_erp { 437*33aca94dSKalle Valo int short_preamble; 438*33aca94dSKalle Valo int cts_protection; 439*33aca94dSKalle Valo 440*33aca94dSKalle Valo u32 basic_rates; 441*33aca94dSKalle Valo 442*33aca94dSKalle Valo int slot_time; 443*33aca94dSKalle Valo 444*33aca94dSKalle Valo short sifs; 445*33aca94dSKalle Valo short pifs; 446*33aca94dSKalle Valo short difs; 447*33aca94dSKalle Valo short eifs; 448*33aca94dSKalle Valo 449*33aca94dSKalle Valo u16 beacon_int; 450*33aca94dSKalle Valo u16 ht_opmode; 451*33aca94dSKalle Valo }; 452*33aca94dSKalle Valo 453*33aca94dSKalle Valo /* 454*33aca94dSKalle Valo * Configuration structure for hardware encryption. 455*33aca94dSKalle Valo */ 456*33aca94dSKalle Valo struct rt2x00lib_crypto { 457*33aca94dSKalle Valo enum cipher cipher; 458*33aca94dSKalle Valo 459*33aca94dSKalle Valo enum set_key_cmd cmd; 460*33aca94dSKalle Valo const u8 *address; 461*33aca94dSKalle Valo 462*33aca94dSKalle Valo u32 bssidx; 463*33aca94dSKalle Valo 464*33aca94dSKalle Valo u8 key[16]; 465*33aca94dSKalle Valo u8 tx_mic[8]; 466*33aca94dSKalle Valo u8 rx_mic[8]; 467*33aca94dSKalle Valo 468*33aca94dSKalle Valo int wcid; 469*33aca94dSKalle Valo }; 470*33aca94dSKalle Valo 471*33aca94dSKalle Valo /* 472*33aca94dSKalle Valo * Configuration structure wrapper around the 473*33aca94dSKalle Valo * rt2x00 interface configuration handler. 474*33aca94dSKalle Valo */ 475*33aca94dSKalle Valo struct rt2x00intf_conf { 476*33aca94dSKalle Valo /* 477*33aca94dSKalle Valo * Interface type 478*33aca94dSKalle Valo */ 479*33aca94dSKalle Valo enum nl80211_iftype type; 480*33aca94dSKalle Valo 481*33aca94dSKalle Valo /* 482*33aca94dSKalle Valo * TSF sync value, this is dependent on the operation type. 483*33aca94dSKalle Valo */ 484*33aca94dSKalle Valo enum tsf_sync sync; 485*33aca94dSKalle Valo 486*33aca94dSKalle Valo /* 487*33aca94dSKalle Valo * The MAC and BSSID addresses are simple array of bytes, 488*33aca94dSKalle Valo * these arrays are little endian, so when sending the addresses 489*33aca94dSKalle Valo * to the drivers, copy the it into a endian-signed variable. 490*33aca94dSKalle Valo * 491*33aca94dSKalle Valo * Note that all devices (except rt2500usb) have 32 bits 492*33aca94dSKalle Valo * register word sizes. This means that whatever variable we 493*33aca94dSKalle Valo * pass _must_ be a multiple of 32 bits. Otherwise the device 494*33aca94dSKalle Valo * might not accept what we are sending to it. 495*33aca94dSKalle Valo * This will also make it easier for the driver to write 496*33aca94dSKalle Valo * the data to the device. 497*33aca94dSKalle Valo */ 498*33aca94dSKalle Valo __le32 mac[2]; 499*33aca94dSKalle Valo __le32 bssid[2]; 500*33aca94dSKalle Valo }; 501*33aca94dSKalle Valo 502*33aca94dSKalle Valo /* 503*33aca94dSKalle Valo * Private structure for storing STA details 504*33aca94dSKalle Valo * wcid: Wireless Client ID 505*33aca94dSKalle Valo */ 506*33aca94dSKalle Valo struct rt2x00_sta { 507*33aca94dSKalle Valo int wcid; 508*33aca94dSKalle Valo }; 509*33aca94dSKalle Valo 510*33aca94dSKalle Valo static inline struct rt2x00_sta* sta_to_rt2x00_sta(struct ieee80211_sta *sta) 511*33aca94dSKalle Valo { 512*33aca94dSKalle Valo return (struct rt2x00_sta *)sta->drv_priv; 513*33aca94dSKalle Valo } 514*33aca94dSKalle Valo 515*33aca94dSKalle Valo /* 516*33aca94dSKalle Valo * rt2x00lib callback functions. 517*33aca94dSKalle Valo */ 518*33aca94dSKalle Valo struct rt2x00lib_ops { 519*33aca94dSKalle Valo /* 520*33aca94dSKalle Valo * Interrupt handlers. 521*33aca94dSKalle Valo */ 522*33aca94dSKalle Valo irq_handler_t irq_handler; 523*33aca94dSKalle Valo 524*33aca94dSKalle Valo /* 525*33aca94dSKalle Valo * TX status tasklet handler. 526*33aca94dSKalle Valo */ 527*33aca94dSKalle Valo void (*txstatus_tasklet) (unsigned long data); 528*33aca94dSKalle Valo void (*pretbtt_tasklet) (unsigned long data); 529*33aca94dSKalle Valo void (*tbtt_tasklet) (unsigned long data); 530*33aca94dSKalle Valo void (*rxdone_tasklet) (unsigned long data); 531*33aca94dSKalle Valo void (*autowake_tasklet) (unsigned long data); 532*33aca94dSKalle Valo 533*33aca94dSKalle Valo /* 534*33aca94dSKalle Valo * Device init handlers. 535*33aca94dSKalle Valo */ 536*33aca94dSKalle Valo int (*probe_hw) (struct rt2x00_dev *rt2x00dev); 537*33aca94dSKalle Valo char *(*get_firmware_name) (struct rt2x00_dev *rt2x00dev); 538*33aca94dSKalle Valo int (*check_firmware) (struct rt2x00_dev *rt2x00dev, 539*33aca94dSKalle Valo const u8 *data, const size_t len); 540*33aca94dSKalle Valo int (*load_firmware) (struct rt2x00_dev *rt2x00dev, 541*33aca94dSKalle Valo const u8 *data, const size_t len); 542*33aca94dSKalle Valo 543*33aca94dSKalle Valo /* 544*33aca94dSKalle Valo * Device initialization/deinitialization handlers. 545*33aca94dSKalle Valo */ 546*33aca94dSKalle Valo int (*initialize) (struct rt2x00_dev *rt2x00dev); 547*33aca94dSKalle Valo void (*uninitialize) (struct rt2x00_dev *rt2x00dev); 548*33aca94dSKalle Valo 549*33aca94dSKalle Valo /* 550*33aca94dSKalle Valo * queue initialization handlers 551*33aca94dSKalle Valo */ 552*33aca94dSKalle Valo bool (*get_entry_state) (struct queue_entry *entry); 553*33aca94dSKalle Valo void (*clear_entry) (struct queue_entry *entry); 554*33aca94dSKalle Valo 555*33aca94dSKalle Valo /* 556*33aca94dSKalle Valo * Radio control handlers. 557*33aca94dSKalle Valo */ 558*33aca94dSKalle Valo int (*set_device_state) (struct rt2x00_dev *rt2x00dev, 559*33aca94dSKalle Valo enum dev_state state); 560*33aca94dSKalle Valo int (*rfkill_poll) (struct rt2x00_dev *rt2x00dev); 561*33aca94dSKalle Valo void (*link_stats) (struct rt2x00_dev *rt2x00dev, 562*33aca94dSKalle Valo struct link_qual *qual); 563*33aca94dSKalle Valo void (*reset_tuner) (struct rt2x00_dev *rt2x00dev, 564*33aca94dSKalle Valo struct link_qual *qual); 565*33aca94dSKalle Valo void (*link_tuner) (struct rt2x00_dev *rt2x00dev, 566*33aca94dSKalle Valo struct link_qual *qual, const u32 count); 567*33aca94dSKalle Valo void (*gain_calibration) (struct rt2x00_dev *rt2x00dev); 568*33aca94dSKalle Valo void (*vco_calibration) (struct rt2x00_dev *rt2x00dev); 569*33aca94dSKalle Valo 570*33aca94dSKalle Valo /* 571*33aca94dSKalle Valo * Data queue handlers. 572*33aca94dSKalle Valo */ 573*33aca94dSKalle Valo void (*watchdog) (struct rt2x00_dev *rt2x00dev); 574*33aca94dSKalle Valo void (*start_queue) (struct data_queue *queue); 575*33aca94dSKalle Valo void (*kick_queue) (struct data_queue *queue); 576*33aca94dSKalle Valo void (*stop_queue) (struct data_queue *queue); 577*33aca94dSKalle Valo void (*flush_queue) (struct data_queue *queue, bool drop); 578*33aca94dSKalle Valo void (*tx_dma_done) (struct queue_entry *entry); 579*33aca94dSKalle Valo 580*33aca94dSKalle Valo /* 581*33aca94dSKalle Valo * TX control handlers 582*33aca94dSKalle Valo */ 583*33aca94dSKalle Valo void (*write_tx_desc) (struct queue_entry *entry, 584*33aca94dSKalle Valo struct txentry_desc *txdesc); 585*33aca94dSKalle Valo void (*write_tx_data) (struct queue_entry *entry, 586*33aca94dSKalle Valo struct txentry_desc *txdesc); 587*33aca94dSKalle Valo void (*write_beacon) (struct queue_entry *entry, 588*33aca94dSKalle Valo struct txentry_desc *txdesc); 589*33aca94dSKalle Valo void (*clear_beacon) (struct queue_entry *entry); 590*33aca94dSKalle Valo int (*get_tx_data_len) (struct queue_entry *entry); 591*33aca94dSKalle Valo 592*33aca94dSKalle Valo /* 593*33aca94dSKalle Valo * RX control handlers 594*33aca94dSKalle Valo */ 595*33aca94dSKalle Valo void (*fill_rxdone) (struct queue_entry *entry, 596*33aca94dSKalle Valo struct rxdone_entry_desc *rxdesc); 597*33aca94dSKalle Valo 598*33aca94dSKalle Valo /* 599*33aca94dSKalle Valo * Configuration handlers. 600*33aca94dSKalle Valo */ 601*33aca94dSKalle Valo int (*config_shared_key) (struct rt2x00_dev *rt2x00dev, 602*33aca94dSKalle Valo struct rt2x00lib_crypto *crypto, 603*33aca94dSKalle Valo struct ieee80211_key_conf *key); 604*33aca94dSKalle Valo int (*config_pairwise_key) (struct rt2x00_dev *rt2x00dev, 605*33aca94dSKalle Valo struct rt2x00lib_crypto *crypto, 606*33aca94dSKalle Valo struct ieee80211_key_conf *key); 607*33aca94dSKalle Valo void (*config_filter) (struct rt2x00_dev *rt2x00dev, 608*33aca94dSKalle Valo const unsigned int filter_flags); 609*33aca94dSKalle Valo void (*config_intf) (struct rt2x00_dev *rt2x00dev, 610*33aca94dSKalle Valo struct rt2x00_intf *intf, 611*33aca94dSKalle Valo struct rt2x00intf_conf *conf, 612*33aca94dSKalle Valo const unsigned int flags); 613*33aca94dSKalle Valo #define CONFIG_UPDATE_TYPE ( 1 << 1 ) 614*33aca94dSKalle Valo #define CONFIG_UPDATE_MAC ( 1 << 2 ) 615*33aca94dSKalle Valo #define CONFIG_UPDATE_BSSID ( 1 << 3 ) 616*33aca94dSKalle Valo 617*33aca94dSKalle Valo void (*config_erp) (struct rt2x00_dev *rt2x00dev, 618*33aca94dSKalle Valo struct rt2x00lib_erp *erp, 619*33aca94dSKalle Valo u32 changed); 620*33aca94dSKalle Valo void (*config_ant) (struct rt2x00_dev *rt2x00dev, 621*33aca94dSKalle Valo struct antenna_setup *ant); 622*33aca94dSKalle Valo void (*config) (struct rt2x00_dev *rt2x00dev, 623*33aca94dSKalle Valo struct rt2x00lib_conf *libconf, 624*33aca94dSKalle Valo const unsigned int changed_flags); 625*33aca94dSKalle Valo int (*sta_add) (struct rt2x00_dev *rt2x00dev, 626*33aca94dSKalle Valo struct ieee80211_vif *vif, 627*33aca94dSKalle Valo struct ieee80211_sta *sta); 628*33aca94dSKalle Valo int (*sta_remove) (struct rt2x00_dev *rt2x00dev, 629*33aca94dSKalle Valo int wcid); 630*33aca94dSKalle Valo }; 631*33aca94dSKalle Valo 632*33aca94dSKalle Valo /* 633*33aca94dSKalle Valo * rt2x00 driver callback operation structure. 634*33aca94dSKalle Valo */ 635*33aca94dSKalle Valo struct rt2x00_ops { 636*33aca94dSKalle Valo const char *name; 637*33aca94dSKalle Valo const unsigned int drv_data_size; 638*33aca94dSKalle Valo const unsigned int max_ap_intf; 639*33aca94dSKalle Valo const unsigned int eeprom_size; 640*33aca94dSKalle Valo const unsigned int rf_size; 641*33aca94dSKalle Valo const unsigned int tx_queues; 642*33aca94dSKalle Valo void (*queue_init)(struct data_queue *queue); 643*33aca94dSKalle Valo const struct rt2x00lib_ops *lib; 644*33aca94dSKalle Valo const void *drv; 645*33aca94dSKalle Valo const struct ieee80211_ops *hw; 646*33aca94dSKalle Valo #ifdef CONFIG_RT2X00_LIB_DEBUGFS 647*33aca94dSKalle Valo const struct rt2x00debug *debugfs; 648*33aca94dSKalle Valo #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 649*33aca94dSKalle Valo }; 650*33aca94dSKalle Valo 651*33aca94dSKalle Valo /* 652*33aca94dSKalle Valo * rt2x00 state flags 653*33aca94dSKalle Valo */ 654*33aca94dSKalle Valo enum rt2x00_state_flags { 655*33aca94dSKalle Valo /* 656*33aca94dSKalle Valo * Device flags 657*33aca94dSKalle Valo */ 658*33aca94dSKalle Valo DEVICE_STATE_PRESENT, 659*33aca94dSKalle Valo DEVICE_STATE_REGISTERED_HW, 660*33aca94dSKalle Valo DEVICE_STATE_INITIALIZED, 661*33aca94dSKalle Valo DEVICE_STATE_STARTED, 662*33aca94dSKalle Valo DEVICE_STATE_ENABLED_RADIO, 663*33aca94dSKalle Valo DEVICE_STATE_SCANNING, 664*33aca94dSKalle Valo 665*33aca94dSKalle Valo /* 666*33aca94dSKalle Valo * Driver configuration 667*33aca94dSKalle Valo */ 668*33aca94dSKalle Valo CONFIG_CHANNEL_HT40, 669*33aca94dSKalle Valo CONFIG_POWERSAVING, 670*33aca94dSKalle Valo CONFIG_HT_DISABLED, 671*33aca94dSKalle Valo CONFIG_QOS_DISABLED, 672*33aca94dSKalle Valo 673*33aca94dSKalle Valo /* 674*33aca94dSKalle Valo * Mark we currently are sequentially reading TX_STA_FIFO register 675*33aca94dSKalle Valo * FIXME: this is for only rt2800usb, should go to private data 676*33aca94dSKalle Valo */ 677*33aca94dSKalle Valo TX_STATUS_READING, 678*33aca94dSKalle Valo }; 679*33aca94dSKalle Valo 680*33aca94dSKalle Valo /* 681*33aca94dSKalle Valo * rt2x00 capability flags 682*33aca94dSKalle Valo */ 683*33aca94dSKalle Valo enum rt2x00_capability_flags { 684*33aca94dSKalle Valo /* 685*33aca94dSKalle Valo * Requirements 686*33aca94dSKalle Valo */ 687*33aca94dSKalle Valo REQUIRE_FIRMWARE, 688*33aca94dSKalle Valo REQUIRE_BEACON_GUARD, 689*33aca94dSKalle Valo REQUIRE_ATIM_QUEUE, 690*33aca94dSKalle Valo REQUIRE_DMA, 691*33aca94dSKalle Valo REQUIRE_COPY_IV, 692*33aca94dSKalle Valo REQUIRE_L2PAD, 693*33aca94dSKalle Valo REQUIRE_TXSTATUS_FIFO, 694*33aca94dSKalle Valo REQUIRE_TASKLET_CONTEXT, 695*33aca94dSKalle Valo REQUIRE_SW_SEQNO, 696*33aca94dSKalle Valo REQUIRE_HT_TX_DESC, 697*33aca94dSKalle Valo REQUIRE_PS_AUTOWAKE, 698*33aca94dSKalle Valo REQUIRE_DELAYED_RFKILL, 699*33aca94dSKalle Valo 700*33aca94dSKalle Valo /* 701*33aca94dSKalle Valo * Capabilities 702*33aca94dSKalle Valo */ 703*33aca94dSKalle Valo CAPABILITY_HW_BUTTON, 704*33aca94dSKalle Valo CAPABILITY_HW_CRYPTO, 705*33aca94dSKalle Valo CAPABILITY_POWER_LIMIT, 706*33aca94dSKalle Valo CAPABILITY_CONTROL_FILTERS, 707*33aca94dSKalle Valo CAPABILITY_CONTROL_FILTER_PSPOLL, 708*33aca94dSKalle Valo CAPABILITY_PRE_TBTT_INTERRUPT, 709*33aca94dSKalle Valo CAPABILITY_LINK_TUNING, 710*33aca94dSKalle Valo CAPABILITY_FRAME_TYPE, 711*33aca94dSKalle Valo CAPABILITY_RF_SEQUENCE, 712*33aca94dSKalle Valo CAPABILITY_EXTERNAL_LNA_A, 713*33aca94dSKalle Valo CAPABILITY_EXTERNAL_LNA_BG, 714*33aca94dSKalle Valo CAPABILITY_DOUBLE_ANTENNA, 715*33aca94dSKalle Valo CAPABILITY_BT_COEXIST, 716*33aca94dSKalle Valo CAPABILITY_VCO_RECALIBRATION, 717*33aca94dSKalle Valo }; 718*33aca94dSKalle Valo 719*33aca94dSKalle Valo /* 720*33aca94dSKalle Valo * Interface combinations 721*33aca94dSKalle Valo */ 722*33aca94dSKalle Valo enum { 723*33aca94dSKalle Valo IF_COMB_AP = 0, 724*33aca94dSKalle Valo NUM_IF_COMB, 725*33aca94dSKalle Valo }; 726*33aca94dSKalle Valo 727*33aca94dSKalle Valo /* 728*33aca94dSKalle Valo * rt2x00 device structure. 729*33aca94dSKalle Valo */ 730*33aca94dSKalle Valo struct rt2x00_dev { 731*33aca94dSKalle Valo /* 732*33aca94dSKalle Valo * Device structure. 733*33aca94dSKalle Valo * The structure stored in here depends on the 734*33aca94dSKalle Valo * system bus (PCI or USB). 735*33aca94dSKalle Valo * When accessing this variable, the rt2x00dev_{pci,usb} 736*33aca94dSKalle Valo * macros should be used for correct typecasting. 737*33aca94dSKalle Valo */ 738*33aca94dSKalle Valo struct device *dev; 739*33aca94dSKalle Valo 740*33aca94dSKalle Valo /* 741*33aca94dSKalle Valo * Callback functions. 742*33aca94dSKalle Valo */ 743*33aca94dSKalle Valo const struct rt2x00_ops *ops; 744*33aca94dSKalle Valo 745*33aca94dSKalle Valo /* 746*33aca94dSKalle Valo * Driver data. 747*33aca94dSKalle Valo */ 748*33aca94dSKalle Valo void *drv_data; 749*33aca94dSKalle Valo 750*33aca94dSKalle Valo /* 751*33aca94dSKalle Valo * IEEE80211 control structure. 752*33aca94dSKalle Valo */ 753*33aca94dSKalle Valo struct ieee80211_hw *hw; 754*33aca94dSKalle Valo struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; 755*33aca94dSKalle Valo enum ieee80211_band curr_band; 756*33aca94dSKalle Valo int curr_freq; 757*33aca94dSKalle Valo 758*33aca94dSKalle Valo /* 759*33aca94dSKalle Valo * If enabled, the debugfs interface structures 760*33aca94dSKalle Valo * required for deregistration of debugfs. 761*33aca94dSKalle Valo */ 762*33aca94dSKalle Valo #ifdef CONFIG_RT2X00_LIB_DEBUGFS 763*33aca94dSKalle Valo struct rt2x00debug_intf *debugfs_intf; 764*33aca94dSKalle Valo #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 765*33aca94dSKalle Valo 766*33aca94dSKalle Valo /* 767*33aca94dSKalle Valo * LED structure for changing the LED status 768*33aca94dSKalle Valo * by mac8011 or the kernel. 769*33aca94dSKalle Valo */ 770*33aca94dSKalle Valo #ifdef CONFIG_RT2X00_LIB_LEDS 771*33aca94dSKalle Valo struct rt2x00_led led_radio; 772*33aca94dSKalle Valo struct rt2x00_led led_assoc; 773*33aca94dSKalle Valo struct rt2x00_led led_qual; 774*33aca94dSKalle Valo u16 led_mcu_reg; 775*33aca94dSKalle Valo #endif /* CONFIG_RT2X00_LIB_LEDS */ 776*33aca94dSKalle Valo 777*33aca94dSKalle Valo /* 778*33aca94dSKalle Valo * Device state flags. 779*33aca94dSKalle Valo * In these flags the current status is stored. 780*33aca94dSKalle Valo * Access to these flags should occur atomically. 781*33aca94dSKalle Valo */ 782*33aca94dSKalle Valo unsigned long flags; 783*33aca94dSKalle Valo 784*33aca94dSKalle Valo /* 785*33aca94dSKalle Valo * Device capabiltiy flags. 786*33aca94dSKalle Valo * In these flags the device/driver capabilities are stored. 787*33aca94dSKalle Valo * Access to these flags should occur non-atomically. 788*33aca94dSKalle Valo */ 789*33aca94dSKalle Valo unsigned long cap_flags; 790*33aca94dSKalle Valo 791*33aca94dSKalle Valo /* 792*33aca94dSKalle Valo * Device information, Bus IRQ and name (PCI, SoC) 793*33aca94dSKalle Valo */ 794*33aca94dSKalle Valo int irq; 795*33aca94dSKalle Valo const char *name; 796*33aca94dSKalle Valo 797*33aca94dSKalle Valo /* 798*33aca94dSKalle Valo * Chipset identification. 799*33aca94dSKalle Valo */ 800*33aca94dSKalle Valo struct rt2x00_chip chip; 801*33aca94dSKalle Valo 802*33aca94dSKalle Valo /* 803*33aca94dSKalle Valo * hw capability specifications. 804*33aca94dSKalle Valo */ 805*33aca94dSKalle Valo struct hw_mode_spec spec; 806*33aca94dSKalle Valo 807*33aca94dSKalle Valo /* 808*33aca94dSKalle Valo * This is the default TX/RX antenna setup as indicated 809*33aca94dSKalle Valo * by the device's EEPROM. 810*33aca94dSKalle Valo */ 811*33aca94dSKalle Valo struct antenna_setup default_ant; 812*33aca94dSKalle Valo 813*33aca94dSKalle Valo /* 814*33aca94dSKalle Valo * Register pointers 815*33aca94dSKalle Valo * csr.base: CSR base register address. (PCI) 816*33aca94dSKalle Valo * csr.cache: CSR cache for usb_control_msg. (USB) 817*33aca94dSKalle Valo */ 818*33aca94dSKalle Valo union csr { 819*33aca94dSKalle Valo void __iomem *base; 820*33aca94dSKalle Valo void *cache; 821*33aca94dSKalle Valo } csr; 822*33aca94dSKalle Valo 823*33aca94dSKalle Valo /* 824*33aca94dSKalle Valo * Mutex to protect register accesses. 825*33aca94dSKalle Valo * For PCI and USB devices it protects against concurrent indirect 826*33aca94dSKalle Valo * register access (BBP, RF, MCU) since accessing those 827*33aca94dSKalle Valo * registers require multiple calls to the CSR registers. 828*33aca94dSKalle Valo * For USB devices it also protects the csr_cache since that 829*33aca94dSKalle Valo * field is used for normal CSR access and it cannot support 830*33aca94dSKalle Valo * multiple callers simultaneously. 831*33aca94dSKalle Valo */ 832*33aca94dSKalle Valo struct mutex csr_mutex; 833*33aca94dSKalle Valo 834*33aca94dSKalle Valo /* 835*33aca94dSKalle Valo * Current packet filter configuration for the device. 836*33aca94dSKalle Valo * This contains all currently active FIF_* flags send 837*33aca94dSKalle Valo * to us by mac80211 during configure_filter(). 838*33aca94dSKalle Valo */ 839*33aca94dSKalle Valo unsigned int packet_filter; 840*33aca94dSKalle Valo 841*33aca94dSKalle Valo /* 842*33aca94dSKalle Valo * Interface details: 843*33aca94dSKalle Valo * - Open ap interface count. 844*33aca94dSKalle Valo * - Open sta interface count. 845*33aca94dSKalle Valo * - Association count. 846*33aca94dSKalle Valo * - Beaconing enabled count. 847*33aca94dSKalle Valo */ 848*33aca94dSKalle Valo unsigned int intf_ap_count; 849*33aca94dSKalle Valo unsigned int intf_sta_count; 850*33aca94dSKalle Valo unsigned int intf_associated; 851*33aca94dSKalle Valo unsigned int intf_beaconing; 852*33aca94dSKalle Valo 853*33aca94dSKalle Valo /* 854*33aca94dSKalle Valo * Interface combinations 855*33aca94dSKalle Valo */ 856*33aca94dSKalle Valo struct ieee80211_iface_limit if_limits_ap; 857*33aca94dSKalle Valo struct ieee80211_iface_combination if_combinations[NUM_IF_COMB]; 858*33aca94dSKalle Valo 859*33aca94dSKalle Valo /* 860*33aca94dSKalle Valo * Link quality 861*33aca94dSKalle Valo */ 862*33aca94dSKalle Valo struct link link; 863*33aca94dSKalle Valo 864*33aca94dSKalle Valo /* 865*33aca94dSKalle Valo * EEPROM data. 866*33aca94dSKalle Valo */ 867*33aca94dSKalle Valo __le16 *eeprom; 868*33aca94dSKalle Valo 869*33aca94dSKalle Valo /* 870*33aca94dSKalle Valo * Active RF register values. 871*33aca94dSKalle Valo * These are stored here so we don't need 872*33aca94dSKalle Valo * to read the rf registers and can directly 873*33aca94dSKalle Valo * use this value instead. 874*33aca94dSKalle Valo * This field should be accessed by using 875*33aca94dSKalle Valo * rt2x00_rf_read() and rt2x00_rf_write(). 876*33aca94dSKalle Valo */ 877*33aca94dSKalle Valo u32 *rf; 878*33aca94dSKalle Valo 879*33aca94dSKalle Valo /* 880*33aca94dSKalle Valo * LNA gain 881*33aca94dSKalle Valo */ 882*33aca94dSKalle Valo short lna_gain; 883*33aca94dSKalle Valo 884*33aca94dSKalle Valo /* 885*33aca94dSKalle Valo * Current TX power value. 886*33aca94dSKalle Valo */ 887*33aca94dSKalle Valo u16 tx_power; 888*33aca94dSKalle Valo 889*33aca94dSKalle Valo /* 890*33aca94dSKalle Valo * Current retry values. 891*33aca94dSKalle Valo */ 892*33aca94dSKalle Valo u8 short_retry; 893*33aca94dSKalle Valo u8 long_retry; 894*33aca94dSKalle Valo 895*33aca94dSKalle Valo /* 896*33aca94dSKalle Valo * Rssi <-> Dbm offset 897*33aca94dSKalle Valo */ 898*33aca94dSKalle Valo u8 rssi_offset; 899*33aca94dSKalle Valo 900*33aca94dSKalle Valo /* 901*33aca94dSKalle Valo * Frequency offset. 902*33aca94dSKalle Valo */ 903*33aca94dSKalle Valo u8 freq_offset; 904*33aca94dSKalle Valo 905*33aca94dSKalle Valo /* 906*33aca94dSKalle Valo * Association id. 907*33aca94dSKalle Valo */ 908*33aca94dSKalle Valo u16 aid; 909*33aca94dSKalle Valo 910*33aca94dSKalle Valo /* 911*33aca94dSKalle Valo * Beacon interval. 912*33aca94dSKalle Valo */ 913*33aca94dSKalle Valo u16 beacon_int; 914*33aca94dSKalle Valo 915*33aca94dSKalle Valo /** 916*33aca94dSKalle Valo * Timestamp of last received beacon 917*33aca94dSKalle Valo */ 918*33aca94dSKalle Valo unsigned long last_beacon; 919*33aca94dSKalle Valo 920*33aca94dSKalle Valo /* 921*33aca94dSKalle Valo * Low level statistics which will have 922*33aca94dSKalle Valo * to be kept up to date while device is running. 923*33aca94dSKalle Valo */ 924*33aca94dSKalle Valo struct ieee80211_low_level_stats low_level_stats; 925*33aca94dSKalle Valo 926*33aca94dSKalle Valo /** 927*33aca94dSKalle Valo * Work queue for all work which should not be placed 928*33aca94dSKalle Valo * on the mac80211 workqueue (because of dependencies 929*33aca94dSKalle Valo * between various work structures). 930*33aca94dSKalle Valo */ 931*33aca94dSKalle Valo struct workqueue_struct *workqueue; 932*33aca94dSKalle Valo 933*33aca94dSKalle Valo /* 934*33aca94dSKalle Valo * Scheduled work. 935*33aca94dSKalle Valo * NOTE: intf_work will use ieee80211_iterate_active_interfaces() 936*33aca94dSKalle Valo * which means it cannot be placed on the hw->workqueue 937*33aca94dSKalle Valo * due to RTNL locking requirements. 938*33aca94dSKalle Valo */ 939*33aca94dSKalle Valo struct work_struct intf_work; 940*33aca94dSKalle Valo 941*33aca94dSKalle Valo /** 942*33aca94dSKalle Valo * Scheduled work for TX/RX done handling (USB devices) 943*33aca94dSKalle Valo */ 944*33aca94dSKalle Valo struct work_struct rxdone_work; 945*33aca94dSKalle Valo struct work_struct txdone_work; 946*33aca94dSKalle Valo 947*33aca94dSKalle Valo /* 948*33aca94dSKalle Valo * Powersaving work 949*33aca94dSKalle Valo */ 950*33aca94dSKalle Valo struct delayed_work autowakeup_work; 951*33aca94dSKalle Valo struct work_struct sleep_work; 952*33aca94dSKalle Valo 953*33aca94dSKalle Valo /* 954*33aca94dSKalle Valo * Data queue arrays for RX, TX, Beacon and ATIM. 955*33aca94dSKalle Valo */ 956*33aca94dSKalle Valo unsigned int data_queues; 957*33aca94dSKalle Valo struct data_queue *rx; 958*33aca94dSKalle Valo struct data_queue *tx; 959*33aca94dSKalle Valo struct data_queue *bcn; 960*33aca94dSKalle Valo struct data_queue *atim; 961*33aca94dSKalle Valo 962*33aca94dSKalle Valo /* 963*33aca94dSKalle Valo * Firmware image. 964*33aca94dSKalle Valo */ 965*33aca94dSKalle Valo const struct firmware *fw; 966*33aca94dSKalle Valo 967*33aca94dSKalle Valo /* 968*33aca94dSKalle Valo * FIFO for storing tx status reports between isr and tasklet. 969*33aca94dSKalle Valo */ 970*33aca94dSKalle Valo DECLARE_KFIFO_PTR(txstatus_fifo, u32); 971*33aca94dSKalle Valo 972*33aca94dSKalle Valo /* 973*33aca94dSKalle Valo * Timer to ensure tx status reports are read (rt2800usb). 974*33aca94dSKalle Valo */ 975*33aca94dSKalle Valo struct hrtimer txstatus_timer; 976*33aca94dSKalle Valo 977*33aca94dSKalle Valo /* 978*33aca94dSKalle Valo * Tasklet for processing tx status reports (rt2800pci). 979*33aca94dSKalle Valo */ 980*33aca94dSKalle Valo struct tasklet_struct txstatus_tasklet; 981*33aca94dSKalle Valo struct tasklet_struct pretbtt_tasklet; 982*33aca94dSKalle Valo struct tasklet_struct tbtt_tasklet; 983*33aca94dSKalle Valo struct tasklet_struct rxdone_tasklet; 984*33aca94dSKalle Valo struct tasklet_struct autowake_tasklet; 985*33aca94dSKalle Valo 986*33aca94dSKalle Valo /* 987*33aca94dSKalle Valo * Used for VCO periodic calibration. 988*33aca94dSKalle Valo */ 989*33aca94dSKalle Valo int rf_channel; 990*33aca94dSKalle Valo 991*33aca94dSKalle Valo /* 992*33aca94dSKalle Valo * Protect the interrupt mask register. 993*33aca94dSKalle Valo */ 994*33aca94dSKalle Valo spinlock_t irqmask_lock; 995*33aca94dSKalle Valo 996*33aca94dSKalle Valo /* 997*33aca94dSKalle Valo * List of BlockAckReq TX entries that need driver BlockAck processing. 998*33aca94dSKalle Valo */ 999*33aca94dSKalle Valo struct list_head bar_list; 1000*33aca94dSKalle Valo spinlock_t bar_list_lock; 1001*33aca94dSKalle Valo 1002*33aca94dSKalle Valo /* Extra TX headroom required for alignment purposes. */ 1003*33aca94dSKalle Valo unsigned int extra_tx_headroom; 1004*33aca94dSKalle Valo }; 1005*33aca94dSKalle Valo 1006*33aca94dSKalle Valo struct rt2x00_bar_list_entry { 1007*33aca94dSKalle Valo struct list_head list; 1008*33aca94dSKalle Valo struct rcu_head head; 1009*33aca94dSKalle Valo 1010*33aca94dSKalle Valo struct queue_entry *entry; 1011*33aca94dSKalle Valo int block_acked; 1012*33aca94dSKalle Valo 1013*33aca94dSKalle Valo /* Relevant parts of the IEEE80211 BAR header */ 1014*33aca94dSKalle Valo __u8 ra[6]; 1015*33aca94dSKalle Valo __u8 ta[6]; 1016*33aca94dSKalle Valo __le16 control; 1017*33aca94dSKalle Valo __le16 start_seq_num; 1018*33aca94dSKalle Valo }; 1019*33aca94dSKalle Valo 1020*33aca94dSKalle Valo /* 1021*33aca94dSKalle Valo * Register defines. 1022*33aca94dSKalle Valo * Some registers require multiple attempts before success, 1023*33aca94dSKalle Valo * in those cases REGISTER_BUSY_COUNT attempts should be 1024*33aca94dSKalle Valo * taken with a REGISTER_BUSY_DELAY interval. Due to USB 1025*33aca94dSKalle Valo * bus delays, we do not have to loop so many times to wait 1026*33aca94dSKalle Valo * for valid register value on that bus. 1027*33aca94dSKalle Valo */ 1028*33aca94dSKalle Valo #define REGISTER_BUSY_COUNT 100 1029*33aca94dSKalle Valo #define REGISTER_USB_BUSY_COUNT 20 1030*33aca94dSKalle Valo #define REGISTER_BUSY_DELAY 100 1031*33aca94dSKalle Valo 1032*33aca94dSKalle Valo /* 1033*33aca94dSKalle Valo * Generic RF access. 1034*33aca94dSKalle Valo * The RF is being accessed by word index. 1035*33aca94dSKalle Valo */ 1036*33aca94dSKalle Valo static inline void rt2x00_rf_read(struct rt2x00_dev *rt2x00dev, 1037*33aca94dSKalle Valo const unsigned int word, u32 *data) 1038*33aca94dSKalle Valo { 1039*33aca94dSKalle Valo BUG_ON(word < 1 || word > rt2x00dev->ops->rf_size / sizeof(u32)); 1040*33aca94dSKalle Valo *data = rt2x00dev->rf[word - 1]; 1041*33aca94dSKalle Valo } 1042*33aca94dSKalle Valo 1043*33aca94dSKalle Valo static inline void rt2x00_rf_write(struct rt2x00_dev *rt2x00dev, 1044*33aca94dSKalle Valo const unsigned int word, u32 data) 1045*33aca94dSKalle Valo { 1046*33aca94dSKalle Valo BUG_ON(word < 1 || word > rt2x00dev->ops->rf_size / sizeof(u32)); 1047*33aca94dSKalle Valo rt2x00dev->rf[word - 1] = data; 1048*33aca94dSKalle Valo } 1049*33aca94dSKalle Valo 1050*33aca94dSKalle Valo /* 1051*33aca94dSKalle Valo * Generic EEPROM access. The EEPROM is being accessed by word or byte index. 1052*33aca94dSKalle Valo */ 1053*33aca94dSKalle Valo static inline void *rt2x00_eeprom_addr(struct rt2x00_dev *rt2x00dev, 1054*33aca94dSKalle Valo const unsigned int word) 1055*33aca94dSKalle Valo { 1056*33aca94dSKalle Valo return (void *)&rt2x00dev->eeprom[word]; 1057*33aca94dSKalle Valo } 1058*33aca94dSKalle Valo 1059*33aca94dSKalle Valo static inline void rt2x00_eeprom_read(struct rt2x00_dev *rt2x00dev, 1060*33aca94dSKalle Valo const unsigned int word, u16 *data) 1061*33aca94dSKalle Valo { 1062*33aca94dSKalle Valo *data = le16_to_cpu(rt2x00dev->eeprom[word]); 1063*33aca94dSKalle Valo } 1064*33aca94dSKalle Valo 1065*33aca94dSKalle Valo static inline void rt2x00_eeprom_write(struct rt2x00_dev *rt2x00dev, 1066*33aca94dSKalle Valo const unsigned int word, u16 data) 1067*33aca94dSKalle Valo { 1068*33aca94dSKalle Valo rt2x00dev->eeprom[word] = cpu_to_le16(data); 1069*33aca94dSKalle Valo } 1070*33aca94dSKalle Valo 1071*33aca94dSKalle Valo static inline u8 rt2x00_eeprom_byte(struct rt2x00_dev *rt2x00dev, 1072*33aca94dSKalle Valo const unsigned int byte) 1073*33aca94dSKalle Valo { 1074*33aca94dSKalle Valo return *(((u8 *)rt2x00dev->eeprom) + byte); 1075*33aca94dSKalle Valo } 1076*33aca94dSKalle Valo 1077*33aca94dSKalle Valo /* 1078*33aca94dSKalle Valo * Chipset handlers 1079*33aca94dSKalle Valo */ 1080*33aca94dSKalle Valo static inline void rt2x00_set_chip(struct rt2x00_dev *rt2x00dev, 1081*33aca94dSKalle Valo const u16 rt, const u16 rf, const u16 rev) 1082*33aca94dSKalle Valo { 1083*33aca94dSKalle Valo rt2x00dev->chip.rt = rt; 1084*33aca94dSKalle Valo rt2x00dev->chip.rf = rf; 1085*33aca94dSKalle Valo rt2x00dev->chip.rev = rev; 1086*33aca94dSKalle Valo 1087*33aca94dSKalle Valo rt2x00_info(rt2x00dev, "Chipset detected - rt: %04x, rf: %04x, rev: %04x\n", 1088*33aca94dSKalle Valo rt2x00dev->chip.rt, rt2x00dev->chip.rf, 1089*33aca94dSKalle Valo rt2x00dev->chip.rev); 1090*33aca94dSKalle Valo } 1091*33aca94dSKalle Valo 1092*33aca94dSKalle Valo static inline void rt2x00_set_rt(struct rt2x00_dev *rt2x00dev, 1093*33aca94dSKalle Valo const u16 rt, const u16 rev) 1094*33aca94dSKalle Valo { 1095*33aca94dSKalle Valo rt2x00dev->chip.rt = rt; 1096*33aca94dSKalle Valo rt2x00dev->chip.rev = rev; 1097*33aca94dSKalle Valo 1098*33aca94dSKalle Valo rt2x00_info(rt2x00dev, "RT chipset %04x, rev %04x detected\n", 1099*33aca94dSKalle Valo rt2x00dev->chip.rt, rt2x00dev->chip.rev); 1100*33aca94dSKalle Valo } 1101*33aca94dSKalle Valo 1102*33aca94dSKalle Valo static inline void rt2x00_set_rf(struct rt2x00_dev *rt2x00dev, const u16 rf) 1103*33aca94dSKalle Valo { 1104*33aca94dSKalle Valo rt2x00dev->chip.rf = rf; 1105*33aca94dSKalle Valo 1106*33aca94dSKalle Valo rt2x00_info(rt2x00dev, "RF chipset %04x detected\n", 1107*33aca94dSKalle Valo rt2x00dev->chip.rf); 1108*33aca94dSKalle Valo } 1109*33aca94dSKalle Valo 1110*33aca94dSKalle Valo static inline bool rt2x00_rt(struct rt2x00_dev *rt2x00dev, const u16 rt) 1111*33aca94dSKalle Valo { 1112*33aca94dSKalle Valo return (rt2x00dev->chip.rt == rt); 1113*33aca94dSKalle Valo } 1114*33aca94dSKalle Valo 1115*33aca94dSKalle Valo static inline bool rt2x00_rf(struct rt2x00_dev *rt2x00dev, const u16 rf) 1116*33aca94dSKalle Valo { 1117*33aca94dSKalle Valo return (rt2x00dev->chip.rf == rf); 1118*33aca94dSKalle Valo } 1119*33aca94dSKalle Valo 1120*33aca94dSKalle Valo static inline u16 rt2x00_rev(struct rt2x00_dev *rt2x00dev) 1121*33aca94dSKalle Valo { 1122*33aca94dSKalle Valo return rt2x00dev->chip.rev; 1123*33aca94dSKalle Valo } 1124*33aca94dSKalle Valo 1125*33aca94dSKalle Valo static inline bool rt2x00_rt_rev(struct rt2x00_dev *rt2x00dev, 1126*33aca94dSKalle Valo const u16 rt, const u16 rev) 1127*33aca94dSKalle Valo { 1128*33aca94dSKalle Valo return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) == rev); 1129*33aca94dSKalle Valo } 1130*33aca94dSKalle Valo 1131*33aca94dSKalle Valo static inline bool rt2x00_rt_rev_lt(struct rt2x00_dev *rt2x00dev, 1132*33aca94dSKalle Valo const u16 rt, const u16 rev) 1133*33aca94dSKalle Valo { 1134*33aca94dSKalle Valo return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) < rev); 1135*33aca94dSKalle Valo } 1136*33aca94dSKalle Valo 1137*33aca94dSKalle Valo static inline bool rt2x00_rt_rev_gte(struct rt2x00_dev *rt2x00dev, 1138*33aca94dSKalle Valo const u16 rt, const u16 rev) 1139*33aca94dSKalle Valo { 1140*33aca94dSKalle Valo return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) >= rev); 1141*33aca94dSKalle Valo } 1142*33aca94dSKalle Valo 1143*33aca94dSKalle Valo static inline void rt2x00_set_chip_intf(struct rt2x00_dev *rt2x00dev, 1144*33aca94dSKalle Valo enum rt2x00_chip_intf intf) 1145*33aca94dSKalle Valo { 1146*33aca94dSKalle Valo rt2x00dev->chip.intf = intf; 1147*33aca94dSKalle Valo } 1148*33aca94dSKalle Valo 1149*33aca94dSKalle Valo static inline bool rt2x00_intf(struct rt2x00_dev *rt2x00dev, 1150*33aca94dSKalle Valo enum rt2x00_chip_intf intf) 1151*33aca94dSKalle Valo { 1152*33aca94dSKalle Valo return (rt2x00dev->chip.intf == intf); 1153*33aca94dSKalle Valo } 1154*33aca94dSKalle Valo 1155*33aca94dSKalle Valo static inline bool rt2x00_is_pci(struct rt2x00_dev *rt2x00dev) 1156*33aca94dSKalle Valo { 1157*33aca94dSKalle Valo return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI) || 1158*33aca94dSKalle Valo rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE); 1159*33aca94dSKalle Valo } 1160*33aca94dSKalle Valo 1161*33aca94dSKalle Valo static inline bool rt2x00_is_pcie(struct rt2x00_dev *rt2x00dev) 1162*33aca94dSKalle Valo { 1163*33aca94dSKalle Valo return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE); 1164*33aca94dSKalle Valo } 1165*33aca94dSKalle Valo 1166*33aca94dSKalle Valo static inline bool rt2x00_is_usb(struct rt2x00_dev *rt2x00dev) 1167*33aca94dSKalle Valo { 1168*33aca94dSKalle Valo return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_USB); 1169*33aca94dSKalle Valo } 1170*33aca94dSKalle Valo 1171*33aca94dSKalle Valo static inline bool rt2x00_is_soc(struct rt2x00_dev *rt2x00dev) 1172*33aca94dSKalle Valo { 1173*33aca94dSKalle Valo return rt2x00_intf(rt2x00dev, RT2X00_CHIP_INTF_SOC); 1174*33aca94dSKalle Valo } 1175*33aca94dSKalle Valo 1176*33aca94dSKalle Valo /* Helpers for capability flags */ 1177*33aca94dSKalle Valo 1178*33aca94dSKalle Valo static inline bool 1179*33aca94dSKalle Valo rt2x00_has_cap_flag(struct rt2x00_dev *rt2x00dev, 1180*33aca94dSKalle Valo enum rt2x00_capability_flags cap_flag) 1181*33aca94dSKalle Valo { 1182*33aca94dSKalle Valo return test_bit(cap_flag, &rt2x00dev->cap_flags); 1183*33aca94dSKalle Valo } 1184*33aca94dSKalle Valo 1185*33aca94dSKalle Valo static inline bool 1186*33aca94dSKalle Valo rt2x00_has_cap_hw_crypto(struct rt2x00_dev *rt2x00dev) 1187*33aca94dSKalle Valo { 1188*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_HW_CRYPTO); 1189*33aca94dSKalle Valo } 1190*33aca94dSKalle Valo 1191*33aca94dSKalle Valo static inline bool 1192*33aca94dSKalle Valo rt2x00_has_cap_power_limit(struct rt2x00_dev *rt2x00dev) 1193*33aca94dSKalle Valo { 1194*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_POWER_LIMIT); 1195*33aca94dSKalle Valo } 1196*33aca94dSKalle Valo 1197*33aca94dSKalle Valo static inline bool 1198*33aca94dSKalle Valo rt2x00_has_cap_control_filters(struct rt2x00_dev *rt2x00dev) 1199*33aca94dSKalle Valo { 1200*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_CONTROL_FILTERS); 1201*33aca94dSKalle Valo } 1202*33aca94dSKalle Valo 1203*33aca94dSKalle Valo static inline bool 1204*33aca94dSKalle Valo rt2x00_has_cap_control_filter_pspoll(struct rt2x00_dev *rt2x00dev) 1205*33aca94dSKalle Valo { 1206*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_CONTROL_FILTER_PSPOLL); 1207*33aca94dSKalle Valo } 1208*33aca94dSKalle Valo 1209*33aca94dSKalle Valo static inline bool 1210*33aca94dSKalle Valo rt2x00_has_cap_pre_tbtt_interrupt(struct rt2x00_dev *rt2x00dev) 1211*33aca94dSKalle Valo { 1212*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_PRE_TBTT_INTERRUPT); 1213*33aca94dSKalle Valo } 1214*33aca94dSKalle Valo 1215*33aca94dSKalle Valo static inline bool 1216*33aca94dSKalle Valo rt2x00_has_cap_link_tuning(struct rt2x00_dev *rt2x00dev) 1217*33aca94dSKalle Valo { 1218*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_LINK_TUNING); 1219*33aca94dSKalle Valo } 1220*33aca94dSKalle Valo 1221*33aca94dSKalle Valo static inline bool 1222*33aca94dSKalle Valo rt2x00_has_cap_frame_type(struct rt2x00_dev *rt2x00dev) 1223*33aca94dSKalle Valo { 1224*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_FRAME_TYPE); 1225*33aca94dSKalle Valo } 1226*33aca94dSKalle Valo 1227*33aca94dSKalle Valo static inline bool 1228*33aca94dSKalle Valo rt2x00_has_cap_rf_sequence(struct rt2x00_dev *rt2x00dev) 1229*33aca94dSKalle Valo { 1230*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_RF_SEQUENCE); 1231*33aca94dSKalle Valo } 1232*33aca94dSKalle Valo 1233*33aca94dSKalle Valo static inline bool 1234*33aca94dSKalle Valo rt2x00_has_cap_external_lna_a(struct rt2x00_dev *rt2x00dev) 1235*33aca94dSKalle Valo { 1236*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_LNA_A); 1237*33aca94dSKalle Valo } 1238*33aca94dSKalle Valo 1239*33aca94dSKalle Valo static inline bool 1240*33aca94dSKalle Valo rt2x00_has_cap_external_lna_bg(struct rt2x00_dev *rt2x00dev) 1241*33aca94dSKalle Valo { 1242*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_LNA_BG); 1243*33aca94dSKalle Valo } 1244*33aca94dSKalle Valo 1245*33aca94dSKalle Valo static inline bool 1246*33aca94dSKalle Valo rt2x00_has_cap_double_antenna(struct rt2x00_dev *rt2x00dev) 1247*33aca94dSKalle Valo { 1248*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_DOUBLE_ANTENNA); 1249*33aca94dSKalle Valo } 1250*33aca94dSKalle Valo 1251*33aca94dSKalle Valo static inline bool 1252*33aca94dSKalle Valo rt2x00_has_cap_bt_coexist(struct rt2x00_dev *rt2x00dev) 1253*33aca94dSKalle Valo { 1254*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_BT_COEXIST); 1255*33aca94dSKalle Valo } 1256*33aca94dSKalle Valo 1257*33aca94dSKalle Valo static inline bool 1258*33aca94dSKalle Valo rt2x00_has_cap_vco_recalibration(struct rt2x00_dev *rt2x00dev) 1259*33aca94dSKalle Valo { 1260*33aca94dSKalle Valo return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_VCO_RECALIBRATION); 1261*33aca94dSKalle Valo } 1262*33aca94dSKalle Valo 1263*33aca94dSKalle Valo /** 1264*33aca94dSKalle Valo * rt2x00queue_map_txskb - Map a skb into DMA for TX purposes. 1265*33aca94dSKalle Valo * @entry: Pointer to &struct queue_entry 1266*33aca94dSKalle Valo * 1267*33aca94dSKalle Valo * Returns -ENOMEM if mapping fail, 0 otherwise. 1268*33aca94dSKalle Valo */ 1269*33aca94dSKalle Valo int rt2x00queue_map_txskb(struct queue_entry *entry); 1270*33aca94dSKalle Valo 1271*33aca94dSKalle Valo /** 1272*33aca94dSKalle Valo * rt2x00queue_unmap_skb - Unmap a skb from DMA. 1273*33aca94dSKalle Valo * @entry: Pointer to &struct queue_entry 1274*33aca94dSKalle Valo */ 1275*33aca94dSKalle Valo void rt2x00queue_unmap_skb(struct queue_entry *entry); 1276*33aca94dSKalle Valo 1277*33aca94dSKalle Valo /** 1278*33aca94dSKalle Valo * rt2x00queue_get_tx_queue - Convert tx queue index to queue pointer 1279*33aca94dSKalle Valo * @rt2x00dev: Pointer to &struct rt2x00_dev. 1280*33aca94dSKalle Valo * @queue: rt2x00 queue index (see &enum data_queue_qid). 1281*33aca94dSKalle Valo * 1282*33aca94dSKalle Valo * Returns NULL for non tx queues. 1283*33aca94dSKalle Valo */ 1284*33aca94dSKalle Valo static inline struct data_queue * 1285*33aca94dSKalle Valo rt2x00queue_get_tx_queue(struct rt2x00_dev *rt2x00dev, 1286*33aca94dSKalle Valo const enum data_queue_qid queue) 1287*33aca94dSKalle Valo { 1288*33aca94dSKalle Valo if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx) 1289*33aca94dSKalle Valo return &rt2x00dev->tx[queue]; 1290*33aca94dSKalle Valo 1291*33aca94dSKalle Valo if (queue == QID_ATIM) 1292*33aca94dSKalle Valo return rt2x00dev->atim; 1293*33aca94dSKalle Valo 1294*33aca94dSKalle Valo return NULL; 1295*33aca94dSKalle Valo } 1296*33aca94dSKalle Valo 1297*33aca94dSKalle Valo /** 1298*33aca94dSKalle Valo * rt2x00queue_get_entry - Get queue entry where the given index points to. 1299*33aca94dSKalle Valo * @queue: Pointer to &struct data_queue from where we obtain the entry. 1300*33aca94dSKalle Valo * @index: Index identifier for obtaining the correct index. 1301*33aca94dSKalle Valo */ 1302*33aca94dSKalle Valo struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, 1303*33aca94dSKalle Valo enum queue_index index); 1304*33aca94dSKalle Valo 1305*33aca94dSKalle Valo /** 1306*33aca94dSKalle Valo * rt2x00queue_pause_queue - Pause a data queue 1307*33aca94dSKalle Valo * @queue: Pointer to &struct data_queue. 1308*33aca94dSKalle Valo * 1309*33aca94dSKalle Valo * This function will pause the data queue locally, preventing 1310*33aca94dSKalle Valo * new frames to be added to the queue (while the hardware is 1311*33aca94dSKalle Valo * still allowed to run). 1312*33aca94dSKalle Valo */ 1313*33aca94dSKalle Valo void rt2x00queue_pause_queue(struct data_queue *queue); 1314*33aca94dSKalle Valo 1315*33aca94dSKalle Valo /** 1316*33aca94dSKalle Valo * rt2x00queue_unpause_queue - unpause a data queue 1317*33aca94dSKalle Valo * @queue: Pointer to &struct data_queue. 1318*33aca94dSKalle Valo * 1319*33aca94dSKalle Valo * This function will unpause the data queue locally, allowing 1320*33aca94dSKalle Valo * new frames to be added to the queue again. 1321*33aca94dSKalle Valo */ 1322*33aca94dSKalle Valo void rt2x00queue_unpause_queue(struct data_queue *queue); 1323*33aca94dSKalle Valo 1324*33aca94dSKalle Valo /** 1325*33aca94dSKalle Valo * rt2x00queue_start_queue - Start a data queue 1326*33aca94dSKalle Valo * @queue: Pointer to &struct data_queue. 1327*33aca94dSKalle Valo * 1328*33aca94dSKalle Valo * This function will start handling all pending frames in the queue. 1329*33aca94dSKalle Valo */ 1330*33aca94dSKalle Valo void rt2x00queue_start_queue(struct data_queue *queue); 1331*33aca94dSKalle Valo 1332*33aca94dSKalle Valo /** 1333*33aca94dSKalle Valo * rt2x00queue_stop_queue - Halt a data queue 1334*33aca94dSKalle Valo * @queue: Pointer to &struct data_queue. 1335*33aca94dSKalle Valo * 1336*33aca94dSKalle Valo * This function will stop all pending frames in the queue. 1337*33aca94dSKalle Valo */ 1338*33aca94dSKalle Valo void rt2x00queue_stop_queue(struct data_queue *queue); 1339*33aca94dSKalle Valo 1340*33aca94dSKalle Valo /** 1341*33aca94dSKalle Valo * rt2x00queue_flush_queue - Flush a data queue 1342*33aca94dSKalle Valo * @queue: Pointer to &struct data_queue. 1343*33aca94dSKalle Valo * @drop: True to drop all pending frames. 1344*33aca94dSKalle Valo * 1345*33aca94dSKalle Valo * This function will flush the queue. After this call 1346*33aca94dSKalle Valo * the queue is guaranteed to be empty. 1347*33aca94dSKalle Valo */ 1348*33aca94dSKalle Valo void rt2x00queue_flush_queue(struct data_queue *queue, bool drop); 1349*33aca94dSKalle Valo 1350*33aca94dSKalle Valo /** 1351*33aca94dSKalle Valo * rt2x00queue_start_queues - Start all data queues 1352*33aca94dSKalle Valo * @rt2x00dev: Pointer to &struct rt2x00_dev. 1353*33aca94dSKalle Valo * 1354*33aca94dSKalle Valo * This function will loop through all available queues to start them 1355*33aca94dSKalle Valo */ 1356*33aca94dSKalle Valo void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev); 1357*33aca94dSKalle Valo 1358*33aca94dSKalle Valo /** 1359*33aca94dSKalle Valo * rt2x00queue_stop_queues - Halt all data queues 1360*33aca94dSKalle Valo * @rt2x00dev: Pointer to &struct rt2x00_dev. 1361*33aca94dSKalle Valo * 1362*33aca94dSKalle Valo * This function will loop through all available queues to stop 1363*33aca94dSKalle Valo * any pending frames. 1364*33aca94dSKalle Valo */ 1365*33aca94dSKalle Valo void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev); 1366*33aca94dSKalle Valo 1367*33aca94dSKalle Valo /** 1368*33aca94dSKalle Valo * rt2x00queue_flush_queues - Flush all data queues 1369*33aca94dSKalle Valo * @rt2x00dev: Pointer to &struct rt2x00_dev. 1370*33aca94dSKalle Valo * @drop: True to drop all pending frames. 1371*33aca94dSKalle Valo * 1372*33aca94dSKalle Valo * This function will loop through all available queues to flush 1373*33aca94dSKalle Valo * any pending frames. 1374*33aca94dSKalle Valo */ 1375*33aca94dSKalle Valo void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop); 1376*33aca94dSKalle Valo 1377*33aca94dSKalle Valo /* 1378*33aca94dSKalle Valo * Debugfs handlers. 1379*33aca94dSKalle Valo */ 1380*33aca94dSKalle Valo /** 1381*33aca94dSKalle Valo * rt2x00debug_dump_frame - Dump a frame to userspace through debugfs. 1382*33aca94dSKalle Valo * @rt2x00dev: Pointer to &struct rt2x00_dev. 1383*33aca94dSKalle Valo * @type: The type of frame that is being dumped. 1384*33aca94dSKalle Valo * @skb: The skb containing the frame to be dumped. 1385*33aca94dSKalle Valo */ 1386*33aca94dSKalle Valo #ifdef CONFIG_RT2X00_LIB_DEBUGFS 1387*33aca94dSKalle Valo void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev, 1388*33aca94dSKalle Valo enum rt2x00_dump_type type, struct sk_buff *skb); 1389*33aca94dSKalle Valo #else 1390*33aca94dSKalle Valo static inline void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev, 1391*33aca94dSKalle Valo enum rt2x00_dump_type type, 1392*33aca94dSKalle Valo struct sk_buff *skb) 1393*33aca94dSKalle Valo { 1394*33aca94dSKalle Valo } 1395*33aca94dSKalle Valo #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1396*33aca94dSKalle Valo 1397*33aca94dSKalle Valo /* 1398*33aca94dSKalle Valo * Utility functions. 1399*33aca94dSKalle Valo */ 1400*33aca94dSKalle Valo u32 rt2x00lib_get_bssidx(struct rt2x00_dev *rt2x00dev, 1401*33aca94dSKalle Valo struct ieee80211_vif *vif); 1402*33aca94dSKalle Valo 1403*33aca94dSKalle Valo /* 1404*33aca94dSKalle Valo * Interrupt context handlers. 1405*33aca94dSKalle Valo */ 1406*33aca94dSKalle Valo void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev); 1407*33aca94dSKalle Valo void rt2x00lib_pretbtt(struct rt2x00_dev *rt2x00dev); 1408*33aca94dSKalle Valo void rt2x00lib_dmastart(struct queue_entry *entry); 1409*33aca94dSKalle Valo void rt2x00lib_dmadone(struct queue_entry *entry); 1410*33aca94dSKalle Valo void rt2x00lib_txdone(struct queue_entry *entry, 1411*33aca94dSKalle Valo struct txdone_entry_desc *txdesc); 1412*33aca94dSKalle Valo void rt2x00lib_txdone_noinfo(struct queue_entry *entry, u32 status); 1413*33aca94dSKalle Valo void rt2x00lib_rxdone(struct queue_entry *entry, gfp_t gfp); 1414*33aca94dSKalle Valo 1415*33aca94dSKalle Valo /* 1416*33aca94dSKalle Valo * mac80211 handlers. 1417*33aca94dSKalle Valo */ 1418*33aca94dSKalle Valo void rt2x00mac_tx(struct ieee80211_hw *hw, 1419*33aca94dSKalle Valo struct ieee80211_tx_control *control, 1420*33aca94dSKalle Valo struct sk_buff *skb); 1421*33aca94dSKalle Valo int rt2x00mac_start(struct ieee80211_hw *hw); 1422*33aca94dSKalle Valo void rt2x00mac_stop(struct ieee80211_hw *hw); 1423*33aca94dSKalle Valo int rt2x00mac_add_interface(struct ieee80211_hw *hw, 1424*33aca94dSKalle Valo struct ieee80211_vif *vif); 1425*33aca94dSKalle Valo void rt2x00mac_remove_interface(struct ieee80211_hw *hw, 1426*33aca94dSKalle Valo struct ieee80211_vif *vif); 1427*33aca94dSKalle Valo int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed); 1428*33aca94dSKalle Valo void rt2x00mac_configure_filter(struct ieee80211_hw *hw, 1429*33aca94dSKalle Valo unsigned int changed_flags, 1430*33aca94dSKalle Valo unsigned int *total_flags, 1431*33aca94dSKalle Valo u64 multicast); 1432*33aca94dSKalle Valo int rt2x00mac_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, 1433*33aca94dSKalle Valo bool set); 1434*33aca94dSKalle Valo #ifdef CONFIG_RT2X00_LIB_CRYPTO 1435*33aca94dSKalle Valo int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 1436*33aca94dSKalle Valo struct ieee80211_vif *vif, struct ieee80211_sta *sta, 1437*33aca94dSKalle Valo struct ieee80211_key_conf *key); 1438*33aca94dSKalle Valo #else 1439*33aca94dSKalle Valo #define rt2x00mac_set_key NULL 1440*33aca94dSKalle Valo #endif /* CONFIG_RT2X00_LIB_CRYPTO */ 1441*33aca94dSKalle Valo int rt2x00mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1442*33aca94dSKalle Valo struct ieee80211_sta *sta); 1443*33aca94dSKalle Valo int rt2x00mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1444*33aca94dSKalle Valo struct ieee80211_sta *sta); 1445*33aca94dSKalle Valo void rt2x00mac_sw_scan_start(struct ieee80211_hw *hw, 1446*33aca94dSKalle Valo struct ieee80211_vif *vif, 1447*33aca94dSKalle Valo const u8 *mac_addr); 1448*33aca94dSKalle Valo void rt2x00mac_sw_scan_complete(struct ieee80211_hw *hw, 1449*33aca94dSKalle Valo struct ieee80211_vif *vif); 1450*33aca94dSKalle Valo int rt2x00mac_get_stats(struct ieee80211_hw *hw, 1451*33aca94dSKalle Valo struct ieee80211_low_level_stats *stats); 1452*33aca94dSKalle Valo void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw, 1453*33aca94dSKalle Valo struct ieee80211_vif *vif, 1454*33aca94dSKalle Valo struct ieee80211_bss_conf *bss_conf, 1455*33aca94dSKalle Valo u32 changes); 1456*33aca94dSKalle Valo int rt2x00mac_conf_tx(struct ieee80211_hw *hw, 1457*33aca94dSKalle Valo struct ieee80211_vif *vif, u16 queue, 1458*33aca94dSKalle Valo const struct ieee80211_tx_queue_params *params); 1459*33aca94dSKalle Valo void rt2x00mac_rfkill_poll(struct ieee80211_hw *hw); 1460*33aca94dSKalle Valo void rt2x00mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1461*33aca94dSKalle Valo u32 queues, bool drop); 1462*33aca94dSKalle Valo int rt2x00mac_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant); 1463*33aca94dSKalle Valo int rt2x00mac_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1464*33aca94dSKalle Valo void rt2x00mac_get_ringparam(struct ieee80211_hw *hw, 1465*33aca94dSKalle Valo u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max); 1466*33aca94dSKalle Valo bool rt2x00mac_tx_frames_pending(struct ieee80211_hw *hw); 1467*33aca94dSKalle Valo 1468*33aca94dSKalle Valo /* 1469*33aca94dSKalle Valo * Driver allocation handlers. 1470*33aca94dSKalle Valo */ 1471*33aca94dSKalle Valo int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev); 1472*33aca94dSKalle Valo void rt2x00lib_remove_dev(struct rt2x00_dev *rt2x00dev); 1473*33aca94dSKalle Valo #ifdef CONFIG_PM 1474*33aca94dSKalle Valo int rt2x00lib_suspend(struct rt2x00_dev *rt2x00dev, pm_message_t state); 1475*33aca94dSKalle Valo int rt2x00lib_resume(struct rt2x00_dev *rt2x00dev); 1476*33aca94dSKalle Valo #endif /* CONFIG_PM */ 1477*33aca94dSKalle Valo 1478*33aca94dSKalle Valo #endif /* RT2X00_H */ 1479