11ccea77eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 233aca94dSKalle Valo /* Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com> 333aca94dSKalle Valo * Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com> 433aca94dSKalle Valo * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> 533aca94dSKalle Valo * Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com> 633aca94dSKalle Valo * Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de> 733aca94dSKalle Valo * Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com> 833aca94dSKalle Valo * Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com> 933aca94dSKalle Valo * Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com> 1033aca94dSKalle Valo * <http://rt2x00.serialmonkey.com> 1133aca94dSKalle Valo */ 1233aca94dSKalle Valo 1333aca94dSKalle Valo /* Module: rt2800mmio 1433aca94dSKalle Valo * Abstract: forward declarations for the rt2800mmio module. 1533aca94dSKalle Valo */ 1633aca94dSKalle Valo 1733aca94dSKalle Valo #ifndef RT2800MMIO_H 1833aca94dSKalle Valo #define RT2800MMIO_H 1933aca94dSKalle Valo 2033aca94dSKalle Valo /* 2133aca94dSKalle Valo * Queue register offset macros 2233aca94dSKalle Valo */ 2333aca94dSKalle Valo #define TX_QUEUE_REG_OFFSET 0x10 2433aca94dSKalle Valo #define TX_BASE_PTR(__x) (TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)) 2533aca94dSKalle Valo #define TX_MAX_CNT(__x) (TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)) 2633aca94dSKalle Valo #define TX_CTX_IDX(__x) (TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)) 2733aca94dSKalle Valo #define TX_DTX_IDX(__x) (TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)) 2833aca94dSKalle Valo 2933aca94dSKalle Valo /* 3033aca94dSKalle Valo * DMA descriptor defines. 3133aca94dSKalle Valo */ 3233aca94dSKalle Valo #define TXD_DESC_SIZE (4 * sizeof(__le32)) 3333aca94dSKalle Valo #define RXD_DESC_SIZE (4 * sizeof(__le32)) 3433aca94dSKalle Valo 3533aca94dSKalle Valo /* 3633aca94dSKalle Valo * TX descriptor format for TX, PRIO and Beacon Ring. 3733aca94dSKalle Valo */ 3833aca94dSKalle Valo 3933aca94dSKalle Valo /* 4033aca94dSKalle Valo * Word0 4133aca94dSKalle Valo */ 4233aca94dSKalle Valo #define TXD_W0_SD_PTR0 FIELD32(0xffffffff) 4333aca94dSKalle Valo 4433aca94dSKalle Valo /* 4533aca94dSKalle Valo * Word1 4633aca94dSKalle Valo */ 4733aca94dSKalle Valo #define TXD_W1_SD_LEN1 FIELD32(0x00003fff) 4833aca94dSKalle Valo #define TXD_W1_LAST_SEC1 FIELD32(0x00004000) 4933aca94dSKalle Valo #define TXD_W1_BURST FIELD32(0x00008000) 5033aca94dSKalle Valo #define TXD_W1_SD_LEN0 FIELD32(0x3fff0000) 5133aca94dSKalle Valo #define TXD_W1_LAST_SEC0 FIELD32(0x40000000) 5233aca94dSKalle Valo #define TXD_W1_DMA_DONE FIELD32(0x80000000) 5333aca94dSKalle Valo 5433aca94dSKalle Valo /* 5533aca94dSKalle Valo * Word2 5633aca94dSKalle Valo */ 5733aca94dSKalle Valo #define TXD_W2_SD_PTR1 FIELD32(0xffffffff) 5833aca94dSKalle Valo 5933aca94dSKalle Valo /* 6033aca94dSKalle Valo * Word3 6133aca94dSKalle Valo * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI 6233aca94dSKalle Valo * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler. 6333aca94dSKalle Valo * 0:MGMT, 1:HCCA 2:EDCA 6433aca94dSKalle Valo */ 6533aca94dSKalle Valo #define TXD_W3_WIV FIELD32(0x01000000) 6633aca94dSKalle Valo #define TXD_W3_QSEL FIELD32(0x06000000) 6733aca94dSKalle Valo #define TXD_W3_TCO FIELD32(0x20000000) 6833aca94dSKalle Valo #define TXD_W3_UCO FIELD32(0x40000000) 6933aca94dSKalle Valo #define TXD_W3_ICO FIELD32(0x80000000) 7033aca94dSKalle Valo 7133aca94dSKalle Valo /* 7233aca94dSKalle Valo * RX descriptor format for RX Ring. 7333aca94dSKalle Valo */ 7433aca94dSKalle Valo 7533aca94dSKalle Valo /* 7633aca94dSKalle Valo * Word0 7733aca94dSKalle Valo */ 7833aca94dSKalle Valo #define RXD_W0_SDP0 FIELD32(0xffffffff) 7933aca94dSKalle Valo 8033aca94dSKalle Valo /* 8133aca94dSKalle Valo * Word1 8233aca94dSKalle Valo */ 8333aca94dSKalle Valo #define RXD_W1_SDL1 FIELD32(0x00003fff) 8433aca94dSKalle Valo #define RXD_W1_SDL0 FIELD32(0x3fff0000) 8533aca94dSKalle Valo #define RXD_W1_LS0 FIELD32(0x40000000) 8633aca94dSKalle Valo #define RXD_W1_DMA_DONE FIELD32(0x80000000) 8733aca94dSKalle Valo 8833aca94dSKalle Valo /* 8933aca94dSKalle Valo * Word2 9033aca94dSKalle Valo */ 9133aca94dSKalle Valo #define RXD_W2_SDP1 FIELD32(0xffffffff) 9233aca94dSKalle Valo 9333aca94dSKalle Valo /* 9433aca94dSKalle Valo * Word3 9533aca94dSKalle Valo * AMSDU: RX with 802.3 header, not 802.11 header. 9633aca94dSKalle Valo * DECRYPTED: This frame is being decrypted. 9733aca94dSKalle Valo */ 9833aca94dSKalle Valo #define RXD_W3_BA FIELD32(0x00000001) 9933aca94dSKalle Valo #define RXD_W3_DATA FIELD32(0x00000002) 10033aca94dSKalle Valo #define RXD_W3_NULLDATA FIELD32(0x00000004) 10133aca94dSKalle Valo #define RXD_W3_FRAG FIELD32(0x00000008) 10233aca94dSKalle Valo #define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010) 10333aca94dSKalle Valo #define RXD_W3_MULTICAST FIELD32(0x00000020) 10433aca94dSKalle Valo #define RXD_W3_BROADCAST FIELD32(0x00000040) 10533aca94dSKalle Valo #define RXD_W3_MY_BSS FIELD32(0x00000080) 10633aca94dSKalle Valo #define RXD_W3_CRC_ERROR FIELD32(0x00000100) 10733aca94dSKalle Valo #define RXD_W3_CIPHER_ERROR FIELD32(0x00000600) 10833aca94dSKalle Valo #define RXD_W3_AMSDU FIELD32(0x00000800) 10933aca94dSKalle Valo #define RXD_W3_HTC FIELD32(0x00001000) 11033aca94dSKalle Valo #define RXD_W3_RSSI FIELD32(0x00002000) 11133aca94dSKalle Valo #define RXD_W3_L2PAD FIELD32(0x00004000) 11233aca94dSKalle Valo #define RXD_W3_AMPDU FIELD32(0x00008000) 11333aca94dSKalle Valo #define RXD_W3_DECRYPTED FIELD32(0x00010000) 11433aca94dSKalle Valo #define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000) 11533aca94dSKalle Valo #define RXD_W3_PLCP_RSSI FIELD32(0x00040000) 11633aca94dSKalle Valo 1172034afe4SStanislaw Gruszka unsigned int rt2800mmio_get_dma_done(struct data_queue *queue); 1182034afe4SStanislaw Gruszka 11933aca94dSKalle Valo /* TX descriptor initialization */ 12033aca94dSKalle Valo __le32 *rt2800mmio_get_txwi(struct queue_entry *entry); 12133aca94dSKalle Valo void rt2800mmio_write_tx_desc(struct queue_entry *entry, 12233aca94dSKalle Valo struct txentry_desc *txdesc); 12333aca94dSKalle Valo 12433aca94dSKalle Valo /* RX control handlers */ 12533aca94dSKalle Valo void rt2800mmio_fill_rxdone(struct queue_entry *entry, 12633aca94dSKalle Valo struct rxdone_entry_desc *rxdesc); 12733aca94dSKalle Valo 12833aca94dSKalle Valo /* Interrupt functions */ 129*a0d6ea9bSAllen Pais void rt2800mmio_txstatus_tasklet(struct tasklet_struct *t); 130*a0d6ea9bSAllen Pais void rt2800mmio_pretbtt_tasklet(struct tasklet_struct *t); 131*a0d6ea9bSAllen Pais void rt2800mmio_tbtt_tasklet(struct tasklet_struct *t); 132*a0d6ea9bSAllen Pais void rt2800mmio_rxdone_tasklet(struct tasklet_struct *t); 133*a0d6ea9bSAllen Pais void rt2800mmio_autowake_tasklet(struct tasklet_struct *t); 13433aca94dSKalle Valo irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance); 13533aca94dSKalle Valo void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev, 13633aca94dSKalle Valo enum dev_state state); 13733aca94dSKalle Valo 13833aca94dSKalle Valo /* Queue handlers */ 13933aca94dSKalle Valo void rt2800mmio_start_queue(struct data_queue *queue); 14033aca94dSKalle Valo void rt2800mmio_kick_queue(struct data_queue *queue); 14102405644SStanislaw Gruszka void rt2800mmio_flush_queue(struct data_queue *queue, bool drop); 14233aca94dSKalle Valo void rt2800mmio_stop_queue(struct data_queue *queue); 14333aca94dSKalle Valo void rt2800mmio_queue_init(struct data_queue *queue); 14433aca94dSKalle Valo 14533aca94dSKalle Valo /* Initialization functions */ 146e5ceab9dSStanislaw Gruszka int rt2800mmio_probe_hw(struct rt2x00_dev *rt2x00dev); 14733aca94dSKalle Valo bool rt2800mmio_get_entry_state(struct queue_entry *entry); 14833aca94dSKalle Valo void rt2800mmio_clear_entry(struct queue_entry *entry); 14933aca94dSKalle Valo int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev); 15033aca94dSKalle Valo int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev); 15133aca94dSKalle Valo 15233aca94dSKalle Valo /* Device state switch handlers. */ 15333aca94dSKalle Valo int rt2800mmio_enable_radio(struct rt2x00_dev *rt2x00dev); 15433aca94dSKalle Valo 15533aca94dSKalle Valo #endif /* RT2800MMIO_H */ 156