1*68d57a07SSrinivasan Raju /* SPDX-License-Identifier: GPL-2.0-only */ 2*68d57a07SSrinivasan Raju /* 3*68d57a07SSrinivasan Raju * Copyright (c) 2021 pureLiFi 4*68d57a07SSrinivasan Raju */ 5*68d57a07SSrinivasan Raju 6*68d57a07SSrinivasan Raju #define PURELIFI_BYTE_NUM_ALIGNMENT 4 7*68d57a07SSrinivasan Raju #define ETH_ALEN 6 8*68d57a07SSrinivasan Raju #define AP_USER_LIMIT 8 9*68d57a07SSrinivasan Raju 10*68d57a07SSrinivasan Raju #define PLF_VNDR_FPGA_STATE_REQ 0x30 11*68d57a07SSrinivasan Raju #define PLF_VNDR_FPGA_SET_REQ 0x33 12*68d57a07SSrinivasan Raju #define PLF_VNDR_FPGA_SET_CMD 0x34 13*68d57a07SSrinivasan Raju #define PLF_VNDR_FPGA_STATE_CMD 0x35 14*68d57a07SSrinivasan Raju 15*68d57a07SSrinivasan Raju #define PLF_VNDR_XL_FW_CMD 0x80 16*68d57a07SSrinivasan Raju #define PLF_VNDR_XL_DATA_CMD 0x81 17*68d57a07SSrinivasan Raju #define PLF_VNDR_XL_FILE_CMD 0x82 18*68d57a07SSrinivasan Raju #define PLF_VNDR_XL_EX_CMD 0x83 19*68d57a07SSrinivasan Raju 20*68d57a07SSrinivasan Raju #define PLF_MAC_VENDOR_REQUEST 0x36 21*68d57a07SSrinivasan Raju #define PLF_SERIAL_NUMBER_VENDOR_REQUEST 0x37 22*68d57a07SSrinivasan Raju #define PLF_FIRMWARE_VERSION_VENDOR_REQUEST 0x39 23*68d57a07SSrinivasan Raju #define PLF_SERIAL_LEN 14 24*68d57a07SSrinivasan Raju #define PLF_FW_VER_LEN 8 25*68d57a07SSrinivasan Raju 26*68d57a07SSrinivasan Raju struct rx_status { 27*68d57a07SSrinivasan Raju __be16 rssi; 28*68d57a07SSrinivasan Raju u8 rate_idx; 29*68d57a07SSrinivasan Raju u8 pad; 30*68d57a07SSrinivasan Raju __be64 crc_error_count; 31*68d57a07SSrinivasan Raju } __packed; 32*68d57a07SSrinivasan Raju 33*68d57a07SSrinivasan Raju enum plf_usb_req_enum { 34*68d57a07SSrinivasan Raju USB_REQ_TEST_WR = 0, 35*68d57a07SSrinivasan Raju USB_REQ_MAC_WR = 1, 36*68d57a07SSrinivasan Raju USB_REQ_POWER_WR = 2, 37*68d57a07SSrinivasan Raju USB_REQ_RXTX_WR = 3, 38*68d57a07SSrinivasan Raju USB_REQ_BEACON_WR = 4, 39*68d57a07SSrinivasan Raju USB_REQ_BEACON_INTERVAL_WR = 5, 40*68d57a07SSrinivasan Raju USB_REQ_RTS_CTS_RATE_WR = 6, 41*68d57a07SSrinivasan Raju USB_REQ_HASH_WR = 7, 42*68d57a07SSrinivasan Raju USB_REQ_DATA_TX = 8, 43*68d57a07SSrinivasan Raju USB_REQ_RATE_WR = 9, 44*68d57a07SSrinivasan Raju USB_REQ_SET_FREQ = 15 45*68d57a07SSrinivasan Raju }; 46*68d57a07SSrinivasan Raju 47*68d57a07SSrinivasan Raju struct plf_usb_req { 48*68d57a07SSrinivasan Raju __be32 id; /* should be plf_usb_req_enum */ 49*68d57a07SSrinivasan Raju __be32 len; 50*68d57a07SSrinivasan Raju u8 buf[512]; 51*68d57a07SSrinivasan Raju }; 52*68d57a07SSrinivasan Raju 53