1*1802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2c869f77dSJakub Kicinski /*
3c869f77dSJakub Kicinski * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4c869f77dSJakub Kicinski * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5c869f77dSJakub Kicinski */
6c869f77dSJakub Kicinski
7c869f77dSJakub Kicinski #ifndef __MT7601U_DMA_H
8c869f77dSJakub Kicinski #define __MT7601U_DMA_H
9c869f77dSJakub Kicinski
10c869f77dSJakub Kicinski #include <asm/unaligned.h>
11c869f77dSJakub Kicinski #include <linux/skbuff.h>
12c869f77dSJakub Kicinski
13c869f77dSJakub Kicinski #define MT_DMA_HDR_LEN 4
14c869f77dSJakub Kicinski #define MT_RX_INFO_LEN 4
15c869f77dSJakub Kicinski #define MT_FCE_INFO_LEN 4
16c869f77dSJakub Kicinski #define MT_DMA_HDRS (MT_DMA_HDR_LEN + MT_RX_INFO_LEN)
17c869f77dSJakub Kicinski
18c869f77dSJakub Kicinski /* Common Tx DMA descriptor fields */
19c869f77dSJakub Kicinski #define MT_TXD_INFO_LEN GENMASK(15, 0)
20c869f77dSJakub Kicinski #define MT_TXD_INFO_D_PORT GENMASK(29, 27)
21c869f77dSJakub Kicinski #define MT_TXD_INFO_TYPE GENMASK(31, 30)
22c869f77dSJakub Kicinski
23c869f77dSJakub Kicinski enum mt76_msg_port {
24c869f77dSJakub Kicinski WLAN_PORT,
25c869f77dSJakub Kicinski CPU_RX_PORT,
26c869f77dSJakub Kicinski CPU_TX_PORT,
27c869f77dSJakub Kicinski HOST_PORT,
28c869f77dSJakub Kicinski VIRTUAL_CPU_RX_PORT,
29c869f77dSJakub Kicinski VIRTUAL_CPU_TX_PORT,
30c869f77dSJakub Kicinski DISCARD,
31c869f77dSJakub Kicinski };
32c869f77dSJakub Kicinski
33c869f77dSJakub Kicinski enum mt76_info_type {
34c869f77dSJakub Kicinski DMA_PACKET,
35c869f77dSJakub Kicinski DMA_COMMAND,
36c869f77dSJakub Kicinski };
37c869f77dSJakub Kicinski
38c869f77dSJakub Kicinski /* Tx DMA packet specific flags */
39c869f77dSJakub Kicinski #define MT_TXD_PKT_INFO_NEXT_VLD BIT(16)
40c869f77dSJakub Kicinski #define MT_TXD_PKT_INFO_TX_BURST BIT(17)
41c869f77dSJakub Kicinski #define MT_TXD_PKT_INFO_80211 BIT(19)
42c869f77dSJakub Kicinski #define MT_TXD_PKT_INFO_TSO BIT(20)
43c869f77dSJakub Kicinski #define MT_TXD_PKT_INFO_CSO BIT(21)
44c869f77dSJakub Kicinski #define MT_TXD_PKT_INFO_WIV BIT(24)
45c869f77dSJakub Kicinski #define MT_TXD_PKT_INFO_QSEL GENMASK(26, 25)
46c869f77dSJakub Kicinski
47c869f77dSJakub Kicinski enum mt76_qsel {
48c869f77dSJakub Kicinski MT_QSEL_MGMT,
49c869f77dSJakub Kicinski MT_QSEL_HCCA,
50c869f77dSJakub Kicinski MT_QSEL_EDCA,
51c869f77dSJakub Kicinski MT_QSEL_EDCA_2,
52c869f77dSJakub Kicinski };
53c869f77dSJakub Kicinski
54c869f77dSJakub Kicinski /* Tx DMA MCU command specific flags */
55c869f77dSJakub Kicinski #define MT_TXD_CMD_INFO_SEQ GENMASK(19, 16)
56c869f77dSJakub Kicinski #define MT_TXD_CMD_INFO_TYPE GENMASK(26, 20)
57c869f77dSJakub Kicinski
mt7601u_dma_skb_wrap(struct sk_buff * skb,enum mt76_msg_port d_port,enum mt76_info_type type,u32 flags)58c869f77dSJakub Kicinski static inline int mt7601u_dma_skb_wrap(struct sk_buff *skb,
59c869f77dSJakub Kicinski enum mt76_msg_port d_port,
60c869f77dSJakub Kicinski enum mt76_info_type type, u32 flags)
61c869f77dSJakub Kicinski {
62c869f77dSJakub Kicinski u32 info;
63c869f77dSJakub Kicinski
64c869f77dSJakub Kicinski /* Buffer layout:
65c869f77dSJakub Kicinski * | 4B | xfer len | pad | 4B |
66c869f77dSJakub Kicinski * | TXINFO | pkt/cmd | zero pad to 4B | zero |
67c869f77dSJakub Kicinski *
68c869f77dSJakub Kicinski * length field of TXINFO should be set to 'xfer len'.
69c869f77dSJakub Kicinski */
70c869f77dSJakub Kicinski
71c869f77dSJakub Kicinski info = flags |
72d43af505SJakub Kicinski FIELD_PREP(MT_TXD_INFO_LEN, round_up(skb->len, 4)) |
73d43af505SJakub Kicinski FIELD_PREP(MT_TXD_INFO_D_PORT, d_port) |
74d43af505SJakub Kicinski FIELD_PREP(MT_TXD_INFO_TYPE, type);
75c869f77dSJakub Kicinski
76c869f77dSJakub Kicinski put_unaligned_le32(info, skb_push(skb, sizeof(info)));
77c869f77dSJakub Kicinski return skb_put_padto(skb, round_up(skb->len, 4) + 4);
78c869f77dSJakub Kicinski }
79c869f77dSJakub Kicinski
80c869f77dSJakub Kicinski static inline int
mt7601u_dma_skb_wrap_pkt(struct sk_buff * skb,enum mt76_qsel qsel,u32 flags)81c869f77dSJakub Kicinski mt7601u_dma_skb_wrap_pkt(struct sk_buff *skb, enum mt76_qsel qsel, u32 flags)
82c869f77dSJakub Kicinski {
83d43af505SJakub Kicinski flags |= FIELD_PREP(MT_TXD_PKT_INFO_QSEL, qsel);
84c869f77dSJakub Kicinski return mt7601u_dma_skb_wrap(skb, WLAN_PORT, DMA_PACKET, flags);
85c869f77dSJakub Kicinski }
86c869f77dSJakub Kicinski
87c869f77dSJakub Kicinski /* Common Rx DMA descriptor fields */
88c869f77dSJakub Kicinski #define MT_RXD_INFO_LEN GENMASK(13, 0)
89c869f77dSJakub Kicinski #define MT_RXD_INFO_PCIE_INTR BIT(24)
90c869f77dSJakub Kicinski #define MT_RXD_INFO_QSEL GENMASK(26, 25)
91c869f77dSJakub Kicinski #define MT_RXD_INFO_PORT GENMASK(29, 27)
92c869f77dSJakub Kicinski #define MT_RXD_INFO_TYPE GENMASK(31, 30)
93c869f77dSJakub Kicinski
94c869f77dSJakub Kicinski /* Rx DMA packet specific flags */
95c869f77dSJakub Kicinski #define MT_RXD_PKT_INFO_UDP_ERR BIT(16)
96c869f77dSJakub Kicinski #define MT_RXD_PKT_INFO_TCP_ERR BIT(17)
97c869f77dSJakub Kicinski #define MT_RXD_PKT_INFO_IP_ERR BIT(18)
98c869f77dSJakub Kicinski #define MT_RXD_PKT_INFO_PKT_80211 BIT(19)
99c869f77dSJakub Kicinski #define MT_RXD_PKT_INFO_L3L4_DONE BIT(20)
100c869f77dSJakub Kicinski #define MT_RXD_PKT_INFO_MAC_LEN GENMASK(23, 21)
101c869f77dSJakub Kicinski
102c869f77dSJakub Kicinski /* Rx DMA MCU command specific flags */
103c869f77dSJakub Kicinski #define MT_RXD_CMD_INFO_SELF_GEN BIT(15)
104c869f77dSJakub Kicinski #define MT_RXD_CMD_INFO_CMD_SEQ GENMASK(19, 16)
105c869f77dSJakub Kicinski #define MT_RXD_CMD_INFO_EVT_TYPE GENMASK(23, 20)
106c869f77dSJakub Kicinski
107c869f77dSJakub Kicinski enum mt76_evt_type {
108c869f77dSJakub Kicinski CMD_DONE,
109c869f77dSJakub Kicinski CMD_ERROR,
110c869f77dSJakub Kicinski CMD_RETRY,
111c869f77dSJakub Kicinski EVENT_PWR_RSP,
112c869f77dSJakub Kicinski EVENT_WOW_RSP,
113c869f77dSJakub Kicinski EVENT_CARRIER_DETECT_RSP,
114c869f77dSJakub Kicinski EVENT_DFS_DETECT_RSP,
115c869f77dSJakub Kicinski };
116c869f77dSJakub Kicinski
117c869f77dSJakub Kicinski #endif
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