xref: /openbmc/linux/drivers/net/wireless/marvell/libertas/if_spi.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2f988d640SKalle Valo /*
3f988d640SKalle Valo  *	linux/drivers/net/wireless/libertas/if_spi.c
4f988d640SKalle Valo  *
5f988d640SKalle Valo  *	Driver for Marvell SPI WLAN cards.
6f988d640SKalle Valo  *
7f988d640SKalle Valo  *	Copyright 2008 Analog Devices Inc.
8f988d640SKalle Valo  *
9f988d640SKalle Valo  *	Authors:
10f988d640SKalle Valo  *	Andrey Yurovsky <andrey@cozybit.com>
11f988d640SKalle Valo  *	Colin McCabe <colin@cozybit.com>
12f988d640SKalle Valo  */
13f988d640SKalle Valo 
14f988d640SKalle Valo #ifndef _LBS_IF_SPI_H_
15f988d640SKalle Valo #define _LBS_IF_SPI_H_
16f988d640SKalle Valo 
17f988d640SKalle Valo #define IPFIELD_ALIGN_OFFSET 2
18f988d640SKalle Valo #define IF_SPI_CMD_BUF_SIZE 2400
19f988d640SKalle Valo 
20f988d640SKalle Valo /***************** Firmware *****************/
21f988d640SKalle Valo 
22f988d640SKalle Valo #define IF_SPI_FW_NAME_MAX 30
23f988d640SKalle Valo 
24f988d640SKalle Valo #define MAX_MAIN_FW_LOAD_CRC_ERR 10
25f988d640SKalle Valo 
26f988d640SKalle Valo /* Chunk size when loading the helper firmware */
27f988d640SKalle Valo #define HELPER_FW_LOAD_CHUNK_SZ 64
28f988d640SKalle Valo 
29f988d640SKalle Valo /* Value to write to indicate end of helper firmware dnld */
30f988d640SKalle Valo #define FIRMWARE_DNLD_OK 0x0000
31f988d640SKalle Valo 
32f988d640SKalle Valo /* Value to check once the main firmware is downloaded */
33f988d640SKalle Valo #define SUCCESSFUL_FW_DOWNLOAD_MAGIC 0x88888888
34f988d640SKalle Valo 
35f988d640SKalle Valo /***************** SPI Interface Unit *****************/
36f988d640SKalle Valo /* Masks used in SPI register read/write operations */
37f988d640SKalle Valo #define IF_SPI_READ_OPERATION_MASK 0x0
38f988d640SKalle Valo #define IF_SPI_WRITE_OPERATION_MASK 0x8000
39f988d640SKalle Valo 
40f988d640SKalle Valo /* SPI register offsets. 4-byte aligned. */
41f988d640SKalle Valo #define IF_SPI_DEVICEID_CTRL_REG 0x00	/* DeviceID controller reg */
42f988d640SKalle Valo #define IF_SPI_IO_READBASE_REG 0x04 	/* Read I/O base reg */
43f988d640SKalle Valo #define IF_SPI_IO_WRITEBASE_REG 0x08	/* Write I/O base reg */
44f988d640SKalle Valo #define IF_SPI_IO_RDWRPORT_REG 0x0C	/* Read/Write I/O port reg */
45f988d640SKalle Valo 
46f988d640SKalle Valo #define IF_SPI_CMD_READBASE_REG 0x10	/* Read command base reg */
47f988d640SKalle Valo #define IF_SPI_CMD_WRITEBASE_REG 0x14	/* Write command base reg */
48f988d640SKalle Valo #define IF_SPI_CMD_RDWRPORT_REG 0x18	/* Read/Write command port reg */
49f988d640SKalle Valo 
50f988d640SKalle Valo #define IF_SPI_DATA_READBASE_REG 0x1C	/* Read data base reg */
51f988d640SKalle Valo #define IF_SPI_DATA_WRITEBASE_REG 0x20	/* Write data base reg */
52f988d640SKalle Valo #define IF_SPI_DATA_RDWRPORT_REG 0x24	/* Read/Write data port reg */
53f988d640SKalle Valo 
54f988d640SKalle Valo #define IF_SPI_SCRATCH_1_REG 0x28	/* Scratch reg 1 */
55f988d640SKalle Valo #define IF_SPI_SCRATCH_2_REG 0x2C	/* Scratch reg 2 */
56f988d640SKalle Valo #define IF_SPI_SCRATCH_3_REG 0x30	/* Scratch reg 3 */
57f988d640SKalle Valo #define IF_SPI_SCRATCH_4_REG 0x34	/* Scratch reg 4 */
58f988d640SKalle Valo 
59f988d640SKalle Valo #define IF_SPI_TX_FRAME_SEQ_NUM_REG 0x38 /* Tx frame sequence number reg */
60f988d640SKalle Valo #define IF_SPI_TX_FRAME_STATUS_REG 0x3C	/* Tx frame status reg */
61f988d640SKalle Valo 
62f988d640SKalle Valo #define IF_SPI_HOST_INT_CTRL_REG 0x40	/* Host interrupt controller reg */
63f988d640SKalle Valo 
64f988d640SKalle Valo #define IF_SPI_CARD_INT_CAUSE_REG 0x44	/* Card interrupt cause reg */
65f988d640SKalle Valo #define IF_SPI_CARD_INT_STATUS_REG 0x48 /* Card interrupt status reg */
66f988d640SKalle Valo #define IF_SPI_CARD_INT_EVENT_MASK_REG 0x4C /* Card interrupt event mask */
67f988d640SKalle Valo #define IF_SPI_CARD_INT_STATUS_MASK_REG	0x50 /* Card interrupt status mask */
68f988d640SKalle Valo 
69f988d640SKalle Valo #define IF_SPI_CARD_INT_RESET_SELECT_REG 0x54 /* Card interrupt reset select */
70f988d640SKalle Valo 
71f988d640SKalle Valo #define IF_SPI_HOST_INT_CAUSE_REG 0x58	/* Host interrupt cause reg */
72f988d640SKalle Valo #define IF_SPI_HOST_INT_STATUS_REG 0x5C	/* Host interrupt status reg */
73f988d640SKalle Valo #define IF_SPI_HOST_INT_EVENT_MASK_REG 0x60 /* Host interrupt event mask */
74f988d640SKalle Valo #define IF_SPI_HOST_INT_STATUS_MASK_REG	0x64 /* Host interrupt status mask */
75f988d640SKalle Valo #define IF_SPI_HOST_INT_RESET_SELECT_REG 0x68 /* Host interrupt reset select */
76f988d640SKalle Valo 
77f988d640SKalle Valo #define IF_SPI_DELAY_READ_REG 0x6C	/* Delay read reg */
78f988d640SKalle Valo #define IF_SPI_SPU_BUS_MODE_REG 0x70	/* SPU BUS mode reg */
79f988d640SKalle Valo 
80f988d640SKalle Valo /***************** IF_SPI_DEVICEID_CTRL_REG *****************/
81f988d640SKalle Valo #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16)
82f988d640SKalle Valo #define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff)
83f988d640SKalle Valo 
84f988d640SKalle Valo /***************** IF_SPI_HOST_INT_CTRL_REG *****************/
85f988d640SKalle Valo /* Host Interrupt Control bit : Wake up */
86f988d640SKalle Valo #define IF_SPI_HICT_WAKE_UP				(1<<0)
87f988d640SKalle Valo /* Host Interrupt Control bit : WLAN ready */
88f988d640SKalle Valo #define IF_SPI_HICT_WLAN_READY				(1<<1)
89f988d640SKalle Valo /*#define IF_SPI_HICT_FIFO_FIRST_HALF_EMPTY		(1<<2) */
90f988d640SKalle Valo /*#define IF_SPI_HICT_FIFO_SECOND_HALF_EMPTY		(1<<3) */
91f988d640SKalle Valo /*#define IF_SPI_HICT_IRQSRC_WLAN			(1<<4) */
92f988d640SKalle Valo /* Host Interrupt Control bit : Tx auto download */
93f988d640SKalle Valo #define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO		(1<<5)
94f988d640SKalle Valo /* Host Interrupt Control bit : Rx auto upload */
95f988d640SKalle Valo #define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO			(1<<6)
96f988d640SKalle Valo /* Host Interrupt Control bit : Command auto download */
97f988d640SKalle Valo #define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO		(1<<7)
98f988d640SKalle Valo /* Host Interrupt Control bit : Command auto upload */
99f988d640SKalle Valo #define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO		(1<<8)
100f988d640SKalle Valo 
101f988d640SKalle Valo /***************** IF_SPI_CARD_INT_CAUSE_REG *****************/
102f988d640SKalle Valo /* Card Interrupt Case bit : Tx download over */
103f988d640SKalle Valo #define IF_SPI_CIC_TX_DOWNLOAD_OVER			(1<<0)
104f988d640SKalle Valo /* Card Interrupt Case bit : Rx upload over */
105f988d640SKalle Valo #define IF_SPI_CIC_RX_UPLOAD_OVER			(1<<1)
106f988d640SKalle Valo /* Card Interrupt Case bit : Command download over */
107f988d640SKalle Valo #define IF_SPI_CIC_CMD_DOWNLOAD_OVER			(1<<2)
108f988d640SKalle Valo /* Card Interrupt Case bit : Host event */
109f988d640SKalle Valo #define IF_SPI_CIC_HOST_EVENT				(1<<3)
110f988d640SKalle Valo /* Card Interrupt Case bit : Command upload over */
111f988d640SKalle Valo #define IF_SPI_CIC_CMD_UPLOAD_OVER			(1<<4)
112f988d640SKalle Valo /* Card Interrupt Case bit : Power down */
113f988d640SKalle Valo #define IF_SPI_CIC_POWER_DOWN				(1<<5)
114f988d640SKalle Valo 
115f988d640SKalle Valo /***************** IF_SPI_CARD_INT_STATUS_REG *****************/
116f988d640SKalle Valo #define IF_SPI_CIS_TX_DOWNLOAD_OVER			(1<<0)
117f988d640SKalle Valo #define IF_SPI_CIS_RX_UPLOAD_OVER			(1<<1)
118f988d640SKalle Valo #define IF_SPI_CIS_CMD_DOWNLOAD_OVER			(1<<2)
119f988d640SKalle Valo #define IF_SPI_CIS_HOST_EVENT				(1<<3)
120f988d640SKalle Valo #define IF_SPI_CIS_CMD_UPLOAD_OVER			(1<<4)
121f988d640SKalle Valo #define IF_SPI_CIS_POWER_DOWN				(1<<5)
122f988d640SKalle Valo 
123f988d640SKalle Valo /***************** IF_SPI_HOST_INT_CAUSE_REG *****************/
124f988d640SKalle Valo #define IF_SPI_HICU_TX_DOWNLOAD_RDY			(1<<0)
125f988d640SKalle Valo #define IF_SPI_HICU_RX_UPLOAD_RDY			(1<<1)
126f988d640SKalle Valo #define IF_SPI_HICU_CMD_DOWNLOAD_RDY			(1<<2)
127f988d640SKalle Valo #define IF_SPI_HICU_CARD_EVENT				(1<<3)
128f988d640SKalle Valo #define IF_SPI_HICU_CMD_UPLOAD_RDY			(1<<4)
129f988d640SKalle Valo #define IF_SPI_HICU_IO_WR_FIFO_OVERFLOW			(1<<5)
130f988d640SKalle Valo #define IF_SPI_HICU_IO_RD_FIFO_UNDERFLOW		(1<<6)
131f988d640SKalle Valo #define IF_SPI_HICU_DATA_WR_FIFO_OVERFLOW		(1<<7)
132f988d640SKalle Valo #define IF_SPI_HICU_DATA_RD_FIFO_UNDERFLOW		(1<<8)
133f988d640SKalle Valo #define IF_SPI_HICU_CMD_WR_FIFO_OVERFLOW		(1<<9)
134f988d640SKalle Valo #define IF_SPI_HICU_CMD_RD_FIFO_UNDERFLOW		(1<<10)
135f988d640SKalle Valo 
136f988d640SKalle Valo /***************** IF_SPI_HOST_INT_STATUS_REG *****************/
137f988d640SKalle Valo /* Host Interrupt Status bit : Tx download ready */
138f988d640SKalle Valo #define IF_SPI_HIST_TX_DOWNLOAD_RDY			(1<<0)
139f988d640SKalle Valo /* Host Interrupt Status bit : Rx upload ready */
140f988d640SKalle Valo #define IF_SPI_HIST_RX_UPLOAD_RDY			(1<<1)
141f988d640SKalle Valo /* Host Interrupt Status bit : Command download ready */
142f988d640SKalle Valo #define IF_SPI_HIST_CMD_DOWNLOAD_RDY			(1<<2)
143f988d640SKalle Valo /* Host Interrupt Status bit : Card event */
144f988d640SKalle Valo #define IF_SPI_HIST_CARD_EVENT				(1<<3)
145f988d640SKalle Valo /* Host Interrupt Status bit : Command upload ready */
146f988d640SKalle Valo #define IF_SPI_HIST_CMD_UPLOAD_RDY			(1<<4)
147f988d640SKalle Valo /* Host Interrupt Status bit : I/O write FIFO overflow */
148f988d640SKalle Valo #define IF_SPI_HIST_IO_WR_FIFO_OVERFLOW			(1<<5)
149f988d640SKalle Valo /* Host Interrupt Status bit : I/O read FIFO underflow */
150f988d640SKalle Valo #define IF_SPI_HIST_IO_RD_FIFO_UNDRFLOW			(1<<6)
151f988d640SKalle Valo /* Host Interrupt Status bit : Data write FIFO overflow */
152f988d640SKalle Valo #define IF_SPI_HIST_DATA_WR_FIFO_OVERFLOW		(1<<7)
153f988d640SKalle Valo /* Host Interrupt Status bit : Data read FIFO underflow */
154f988d640SKalle Valo #define IF_SPI_HIST_DATA_RD_FIFO_UNDERFLOW		(1<<8)
155f988d640SKalle Valo /* Host Interrupt Status bit : Command write FIFO overflow */
156f988d640SKalle Valo #define IF_SPI_HIST_CMD_WR_FIFO_OVERFLOW		(1<<9)
157f988d640SKalle Valo /* Host Interrupt Status bit : Command read FIFO underflow */
158f988d640SKalle Valo #define IF_SPI_HIST_CMD_RD_FIFO_UNDERFLOW		(1<<10)
159f988d640SKalle Valo 
160f988d640SKalle Valo /***************** IF_SPI_HOST_INT_STATUS_MASK_REG *****************/
161f988d640SKalle Valo /* Host Interrupt Status Mask bit : Tx download ready */
162f988d640SKalle Valo #define IF_SPI_HISM_TX_DOWNLOAD_RDY			(1<<0)
163f988d640SKalle Valo /* Host Interrupt Status Mask bit : Rx upload ready */
164f988d640SKalle Valo #define IF_SPI_HISM_RX_UPLOAD_RDY			(1<<1)
165f988d640SKalle Valo /* Host Interrupt Status Mask bit : Command download ready */
166f988d640SKalle Valo #define IF_SPI_HISM_CMD_DOWNLOAD_RDY			(1<<2)
167f988d640SKalle Valo /* Host Interrupt Status Mask bit : Card event */
168f988d640SKalle Valo #define IF_SPI_HISM_CARDEVENT				(1<<3)
169f988d640SKalle Valo /* Host Interrupt Status Mask bit : Command upload ready */
170f988d640SKalle Valo #define IF_SPI_HISM_CMD_UPLOAD_RDY			(1<<4)
171f988d640SKalle Valo /* Host Interrupt Status Mask bit : I/O write FIFO overflow */
172f988d640SKalle Valo #define IF_SPI_HISM_IO_WR_FIFO_OVERFLOW			(1<<5)
173f988d640SKalle Valo /* Host Interrupt Status Mask bit : I/O read FIFO underflow */
174f988d640SKalle Valo #define IF_SPI_HISM_IO_RD_FIFO_UNDERFLOW		(1<<6)
175f988d640SKalle Valo /* Host Interrupt Status Mask bit : Data write FIFO overflow */
176f988d640SKalle Valo #define IF_SPI_HISM_DATA_WR_FIFO_OVERFLOW		(1<<7)
177f988d640SKalle Valo /* Host Interrupt Status Mask bit : Data write FIFO underflow */
178f988d640SKalle Valo #define IF_SPI_HISM_DATA_RD_FIFO_UNDERFLOW		(1<<8)
179f988d640SKalle Valo /* Host Interrupt Status Mask bit : Command write FIFO overflow */
180f988d640SKalle Valo #define IF_SPI_HISM_CMD_WR_FIFO_OVERFLOW		(1<<9)
181f988d640SKalle Valo /* Host Interrupt Status Mask bit : Command write FIFO underflow */
182f988d640SKalle Valo #define IF_SPI_HISM_CMD_RD_FIFO_UNDERFLOW		(1<<10)
183f988d640SKalle Valo 
184f988d640SKalle Valo /***************** IF_SPI_SPU_BUS_MODE_REG *****************/
185f988d640SKalle Valo /* SCK edge on which the WLAN module outputs data on MISO */
186f988d640SKalle Valo #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_FALLING 0x8
187f988d640SKalle Valo #define IF_SPI_BUS_MODE_SPI_CLOCK_PHASE_RISING 0x0
188f988d640SKalle Valo 
189f988d640SKalle Valo /* In a SPU read operation, there is a delay between writing the SPU
190f988d640SKalle Valo  * register name and getting back data from the WLAN module.
191f988d640SKalle Valo  * This can be specified in terms of nanoseconds or in terms of dummy
192f988d640SKalle Valo  * clock cycles which the master must output before receiving a response. */
193f988d640SKalle Valo #define IF_SPI_BUS_MODE_DELAY_METHOD_DUMMY_CLOCK 0x4
194f988d640SKalle Valo #define IF_SPI_BUS_MODE_DELAY_METHOD_TIMED 0x0
195f988d640SKalle Valo 
196f988d640SKalle Valo /* Some different modes of SPI operation */
197f988d640SKalle Valo #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_16_BIT_DATA 0x00
198f988d640SKalle Valo #define IF_SPI_BUS_MODE_8_BIT_ADDRESS_32_BIT_DATA 0x01
199f988d640SKalle Valo #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_16_BIT_DATA 0x02
200f988d640SKalle Valo #define IF_SPI_BUS_MODE_16_BIT_ADDRESS_32_BIT_DATA 0x03
201f988d640SKalle Valo 
202f988d640SKalle Valo #endif
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