1*298e50adSKalle Valo /* SPDX-License-Identifier: GPL-2.0 */ 2*298e50adSKalle Valo #ifndef __WL3501_H__ 3*298e50adSKalle Valo #define __WL3501_H__ 4*298e50adSKalle Valo 5*298e50adSKalle Valo #include <linux/spinlock.h> 6*298e50adSKalle Valo #include <linux/ieee80211.h> 7*298e50adSKalle Valo 8*298e50adSKalle Valo /* define for WLA 2.0 */ 9*298e50adSKalle Valo #define WL3501_BLKSZ 256 10*298e50adSKalle Valo /* 11*298e50adSKalle Valo * ID for input Signals of DRIVER block 12*298e50adSKalle Valo * bit[7-5] is block ID: 000 13*298e50adSKalle Valo * bit[4-0] is signal ID 14*298e50adSKalle Valo */ 15*298e50adSKalle Valo enum wl3501_signals { 16*298e50adSKalle Valo WL3501_SIG_ALARM, 17*298e50adSKalle Valo WL3501_SIG_MD_CONFIRM, 18*298e50adSKalle Valo WL3501_SIG_MD_IND, 19*298e50adSKalle Valo WL3501_SIG_ASSOC_CONFIRM, 20*298e50adSKalle Valo WL3501_SIG_ASSOC_IND, 21*298e50adSKalle Valo WL3501_SIG_AUTH_CONFIRM, 22*298e50adSKalle Valo WL3501_SIG_AUTH_IND, 23*298e50adSKalle Valo WL3501_SIG_DEAUTH_CONFIRM, 24*298e50adSKalle Valo WL3501_SIG_DEAUTH_IND, 25*298e50adSKalle Valo WL3501_SIG_DISASSOC_CONFIRM, 26*298e50adSKalle Valo WL3501_SIG_DISASSOC_IND, 27*298e50adSKalle Valo WL3501_SIG_GET_CONFIRM, 28*298e50adSKalle Valo WL3501_SIG_JOIN_CONFIRM, 29*298e50adSKalle Valo WL3501_SIG_PWR_MGMT_CONFIRM, 30*298e50adSKalle Valo WL3501_SIG_REASSOC_CONFIRM, 31*298e50adSKalle Valo WL3501_SIG_REASSOC_IND, 32*298e50adSKalle Valo WL3501_SIG_SCAN_CONFIRM, 33*298e50adSKalle Valo WL3501_SIG_SET_CONFIRM, 34*298e50adSKalle Valo WL3501_SIG_START_CONFIRM, 35*298e50adSKalle Valo WL3501_SIG_RESYNC_CONFIRM, 36*298e50adSKalle Valo WL3501_SIG_SITE_CONFIRM, 37*298e50adSKalle Valo WL3501_SIG_SAVE_CONFIRM, 38*298e50adSKalle Valo WL3501_SIG_RFTEST_CONFIRM, 39*298e50adSKalle Valo /* 40*298e50adSKalle Valo * ID for input Signals of MLME block 41*298e50adSKalle Valo * bit[7-5] is block ID: 010 42*298e50adSKalle Valo * bit[4-0] is signal ID 43*298e50adSKalle Valo */ 44*298e50adSKalle Valo WL3501_SIG_ASSOC_REQ = 0x20, 45*298e50adSKalle Valo WL3501_SIG_AUTH_REQ, 46*298e50adSKalle Valo WL3501_SIG_DEAUTH_REQ, 47*298e50adSKalle Valo WL3501_SIG_DISASSOC_REQ, 48*298e50adSKalle Valo WL3501_SIG_GET_REQ, 49*298e50adSKalle Valo WL3501_SIG_JOIN_REQ, 50*298e50adSKalle Valo WL3501_SIG_PWR_MGMT_REQ, 51*298e50adSKalle Valo WL3501_SIG_REASSOC_REQ, 52*298e50adSKalle Valo WL3501_SIG_SCAN_REQ, 53*298e50adSKalle Valo WL3501_SIG_SET_REQ, 54*298e50adSKalle Valo WL3501_SIG_START_REQ, 55*298e50adSKalle Valo WL3501_SIG_MD_REQ, 56*298e50adSKalle Valo WL3501_SIG_RESYNC_REQ, 57*298e50adSKalle Valo WL3501_SIG_SITE_REQ, 58*298e50adSKalle Valo WL3501_SIG_SAVE_REQ, 59*298e50adSKalle Valo WL3501_SIG_RF_TEST_REQ, 60*298e50adSKalle Valo WL3501_SIG_MM_CONFIRM = 0x60, 61*298e50adSKalle Valo WL3501_SIG_MM_IND, 62*298e50adSKalle Valo }; 63*298e50adSKalle Valo 64*298e50adSKalle Valo enum wl3501_mib_attribs { 65*298e50adSKalle Valo WL3501_MIB_ATTR_STATION_ID, 66*298e50adSKalle Valo WL3501_MIB_ATTR_AUTH_ALGORITHMS, 67*298e50adSKalle Valo WL3501_MIB_ATTR_AUTH_TYPE, 68*298e50adSKalle Valo WL3501_MIB_ATTR_MEDIUM_OCCUPANCY_LIMIT, 69*298e50adSKalle Valo WL3501_MIB_ATTR_CF_POLLABLE, 70*298e50adSKalle Valo WL3501_MIB_ATTR_CFP_PERIOD, 71*298e50adSKalle Valo WL3501_MIB_ATTR_CFPMAX_DURATION, 72*298e50adSKalle Valo WL3501_MIB_ATTR_AUTH_RESP_TMOUT, 73*298e50adSKalle Valo WL3501_MIB_ATTR_RX_DTIMS, 74*298e50adSKalle Valo WL3501_MIB_ATTR_PRIV_OPT_IMPLEMENTED, 75*298e50adSKalle Valo WL3501_MIB_ATTR_PRIV_INVOKED, 76*298e50adSKalle Valo WL3501_MIB_ATTR_WEP_DEFAULT_KEYS, 77*298e50adSKalle Valo WL3501_MIB_ATTR_WEP_DEFAULT_KEY_ID, 78*298e50adSKalle Valo WL3501_MIB_ATTR_WEP_KEY_MAPPINGS, 79*298e50adSKalle Valo WL3501_MIB_ATTR_WEP_KEY_MAPPINGS_LEN, 80*298e50adSKalle Valo WL3501_MIB_ATTR_EXCLUDE_UNENCRYPTED, 81*298e50adSKalle Valo WL3501_MIB_ATTR_WEP_ICV_ERROR_COUNT, 82*298e50adSKalle Valo WL3501_MIB_ATTR_WEP_UNDECRYPTABLE_COUNT, 83*298e50adSKalle Valo WL3501_MIB_ATTR_WEP_EXCLUDED_COUNT, 84*298e50adSKalle Valo WL3501_MIB_ATTR_MAC_ADDR, 85*298e50adSKalle Valo WL3501_MIB_ATTR_GROUP_ADDRS, 86*298e50adSKalle Valo WL3501_MIB_ATTR_RTS_THRESHOLD, 87*298e50adSKalle Valo WL3501_MIB_ATTR_SHORT_RETRY_LIMIT, 88*298e50adSKalle Valo WL3501_MIB_ATTR_LONG_RETRY_LIMIT, 89*298e50adSKalle Valo WL3501_MIB_ATTR_FRAG_THRESHOLD, 90*298e50adSKalle Valo WL3501_MIB_ATTR_MAX_TX_MSDU_LIFETIME, 91*298e50adSKalle Valo WL3501_MIB_ATTR_MAX_RX_LIFETIME, 92*298e50adSKalle Valo WL3501_MIB_ATTR_MANUFACTURER_ID, 93*298e50adSKalle Valo WL3501_MIB_ATTR_PRODUCT_ID, 94*298e50adSKalle Valo WL3501_MIB_ATTR_TX_FRAG_COUNT, 95*298e50adSKalle Valo WL3501_MIB_ATTR_MULTICAST_TX_FRAME_COUNT, 96*298e50adSKalle Valo WL3501_MIB_ATTR_FAILED_COUNT, 97*298e50adSKalle Valo WL3501_MIB_ATTR_RX_FRAG_COUNT, 98*298e50adSKalle Valo WL3501_MIB_ATTR_MULTICAST_RX_COUNT, 99*298e50adSKalle Valo WL3501_MIB_ATTR_FCS_ERROR_COUNT, 100*298e50adSKalle Valo WL3501_MIB_ATTR_RETRY_COUNT, 101*298e50adSKalle Valo WL3501_MIB_ATTR_MULTIPLE_RETRY_COUNT, 102*298e50adSKalle Valo WL3501_MIB_ATTR_RTS_SUCCESS_COUNT, 103*298e50adSKalle Valo WL3501_MIB_ATTR_RTS_FAILURE_COUNT, 104*298e50adSKalle Valo WL3501_MIB_ATTR_ACK_FAILURE_COUNT, 105*298e50adSKalle Valo WL3501_MIB_ATTR_FRAME_DUPLICATE_COUNT, 106*298e50adSKalle Valo WL3501_MIB_ATTR_PHY_TYPE, 107*298e50adSKalle Valo WL3501_MIB_ATTR_REG_DOMAINS_SUPPORT, 108*298e50adSKalle Valo WL3501_MIB_ATTR_CURRENT_REG_DOMAIN, 109*298e50adSKalle Valo WL3501_MIB_ATTR_SLOT_TIME, 110*298e50adSKalle Valo WL3501_MIB_ATTR_CCA_TIME, 111*298e50adSKalle Valo WL3501_MIB_ATTR_RX_TX_TURNAROUND_TIME, 112*298e50adSKalle Valo WL3501_MIB_ATTR_TX_PLCP_DELAY, 113*298e50adSKalle Valo WL3501_MIB_ATTR_RX_TX_SWITCH_TIME, 114*298e50adSKalle Valo WL3501_MIB_ATTR_TX_RAMP_ON_TIME, 115*298e50adSKalle Valo WL3501_MIB_ATTR_TX_RF_DELAY, 116*298e50adSKalle Valo WL3501_MIB_ATTR_SIFS_TIME, 117*298e50adSKalle Valo WL3501_MIB_ATTR_RX_RF_DELAY, 118*298e50adSKalle Valo WL3501_MIB_ATTR_RX_PLCP_DELAY, 119*298e50adSKalle Valo WL3501_MIB_ATTR_MAC_PROCESSING_DELAY, 120*298e50adSKalle Valo WL3501_MIB_ATTR_TX_RAMP_OFF_TIME, 121*298e50adSKalle Valo WL3501_MIB_ATTR_PREAMBLE_LEN, 122*298e50adSKalle Valo WL3501_MIB_ATTR_PLCP_HEADER_LEN, 123*298e50adSKalle Valo WL3501_MIB_ATTR_MPDU_DURATION_FACTOR, 124*298e50adSKalle Valo WL3501_MIB_ATTR_AIR_PROPAGATION_TIME, 125*298e50adSKalle Valo WL3501_MIB_ATTR_TEMP_TYPE, 126*298e50adSKalle Valo WL3501_MIB_ATTR_CW_MIN, 127*298e50adSKalle Valo WL3501_MIB_ATTR_CW_MAX, 128*298e50adSKalle Valo WL3501_MIB_ATTR_SUPPORT_DATA_RATES_TX, 129*298e50adSKalle Valo WL3501_MIB_ATTR_SUPPORT_DATA_RATES_RX, 130*298e50adSKalle Valo WL3501_MIB_ATTR_MPDU_MAX_LEN, 131*298e50adSKalle Valo WL3501_MIB_ATTR_SUPPORT_TX_ANTENNAS, 132*298e50adSKalle Valo WL3501_MIB_ATTR_CURRENT_TX_ANTENNA, 133*298e50adSKalle Valo WL3501_MIB_ATTR_SUPPORT_RX_ANTENNAS, 134*298e50adSKalle Valo WL3501_MIB_ATTR_DIVERSITY_SUPPORT, 135*298e50adSKalle Valo WL3501_MIB_ATTR_DIVERSITY_SELECTION_RS, 136*298e50adSKalle Valo WL3501_MIB_ATTR_NR_SUPPORTED_PWR_LEVELS, 137*298e50adSKalle Valo WL3501_MIB_ATTR_TX_PWR_LEVEL1, 138*298e50adSKalle Valo WL3501_MIB_ATTR_TX_PWR_LEVEL2, 139*298e50adSKalle Valo WL3501_MIB_ATTR_TX_PWR_LEVEL3, 140*298e50adSKalle Valo WL3501_MIB_ATTR_TX_PWR_LEVEL4, 141*298e50adSKalle Valo WL3501_MIB_ATTR_TX_PWR_LEVEL5, 142*298e50adSKalle Valo WL3501_MIB_ATTR_TX_PWR_LEVEL6, 143*298e50adSKalle Valo WL3501_MIB_ATTR_TX_PWR_LEVEL7, 144*298e50adSKalle Valo WL3501_MIB_ATTR_TX_PWR_LEVEL8, 145*298e50adSKalle Valo WL3501_MIB_ATTR_CURRENT_TX_PWR_LEVEL, 146*298e50adSKalle Valo WL3501_MIB_ATTR_CURRENT_CHAN, 147*298e50adSKalle Valo WL3501_MIB_ATTR_CCA_MODE_SUPPORTED, 148*298e50adSKalle Valo WL3501_MIB_ATTR_CURRENT_CCA_MODE, 149*298e50adSKalle Valo WL3501_MIB_ATTR_ED_THRESHOLD, 150*298e50adSKalle Valo WL3501_MIB_ATTR_SINTHESIZER_LOCKED, 151*298e50adSKalle Valo WL3501_MIB_ATTR_CURRENT_PWR_STATE, 152*298e50adSKalle Valo WL3501_MIB_ATTR_DOZE_TURNON_TIME, 153*298e50adSKalle Valo WL3501_MIB_ATTR_RCR33, 154*298e50adSKalle Valo WL3501_MIB_ATTR_DEFAULT_CHAN, 155*298e50adSKalle Valo WL3501_MIB_ATTR_SSID, 156*298e50adSKalle Valo WL3501_MIB_ATTR_PWR_MGMT_ENABLE, 157*298e50adSKalle Valo WL3501_MIB_ATTR_NET_CAPABILITY, 158*298e50adSKalle Valo WL3501_MIB_ATTR_ROUTING, 159*298e50adSKalle Valo }; 160*298e50adSKalle Valo 161*298e50adSKalle Valo enum wl3501_net_type { 162*298e50adSKalle Valo WL3501_NET_TYPE_INFRA, 163*298e50adSKalle Valo WL3501_NET_TYPE_ADHOC, 164*298e50adSKalle Valo WL3501_NET_TYPE_ANY_BSS, 165*298e50adSKalle Valo }; 166*298e50adSKalle Valo 167*298e50adSKalle Valo enum wl3501_scan_type { 168*298e50adSKalle Valo WL3501_SCAN_TYPE_ACTIVE, 169*298e50adSKalle Valo WL3501_SCAN_TYPE_PASSIVE, 170*298e50adSKalle Valo }; 171*298e50adSKalle Valo 172*298e50adSKalle Valo enum wl3501_tx_result { 173*298e50adSKalle Valo WL3501_TX_RESULT_SUCCESS, 174*298e50adSKalle Valo WL3501_TX_RESULT_NO_BSS, 175*298e50adSKalle Valo WL3501_TX_RESULT_RETRY_LIMIT, 176*298e50adSKalle Valo }; 177*298e50adSKalle Valo 178*298e50adSKalle Valo enum wl3501_sys_type { 179*298e50adSKalle Valo WL3501_SYS_TYPE_OPEN, 180*298e50adSKalle Valo WL3501_SYS_TYPE_SHARE_KEY, 181*298e50adSKalle Valo }; 182*298e50adSKalle Valo 183*298e50adSKalle Valo enum wl3501_status { 184*298e50adSKalle Valo WL3501_STATUS_SUCCESS, 185*298e50adSKalle Valo WL3501_STATUS_INVALID, 186*298e50adSKalle Valo WL3501_STATUS_TIMEOUT, 187*298e50adSKalle Valo WL3501_STATUS_REFUSED, 188*298e50adSKalle Valo WL3501_STATUS_MANY_REQ, 189*298e50adSKalle Valo WL3501_STATUS_ALREADY_BSS, 190*298e50adSKalle Valo }; 191*298e50adSKalle Valo 192*298e50adSKalle Valo #define WL3501_MGMT_CAPABILITY_ESS 0x0001 /* see 802.11 p.58 */ 193*298e50adSKalle Valo #define WL3501_MGMT_CAPABILITY_IBSS 0x0002 /* - " - */ 194*298e50adSKalle Valo #define WL3501_MGMT_CAPABILITY_CF_POLLABLE 0x0004 /* - " - */ 195*298e50adSKalle Valo #define WL3501_MGMT_CAPABILITY_CF_POLL_REQUEST 0x0008 /* - " - */ 196*298e50adSKalle Valo #define WL3501_MGMT_CAPABILITY_PRIVACY 0x0010 /* - " - */ 197*298e50adSKalle Valo 198*298e50adSKalle Valo #define IW_REG_DOMAIN_FCC 0x10 /* Channel 1 to 11 USA */ 199*298e50adSKalle Valo #define IW_REG_DOMAIN_DOC 0x20 /* Channel 1 to 11 Canada */ 200*298e50adSKalle Valo #define IW_REG_DOMAIN_ETSI 0x30 /* Channel 1 to 13 Europe */ 201*298e50adSKalle Valo #define IW_REG_DOMAIN_SPAIN 0x31 /* Channel 10 to 11 Spain */ 202*298e50adSKalle Valo #define IW_REG_DOMAIN_FRANCE 0x32 /* Channel 10 to 13 France */ 203*298e50adSKalle Valo #define IW_REG_DOMAIN_MKK 0x40 /* Channel 14 Japan */ 204*298e50adSKalle Valo #define IW_REG_DOMAIN_MKK1 0x41 /* Channel 1-14 Japan */ 205*298e50adSKalle Valo #define IW_REG_DOMAIN_ISRAEL 0x50 /* Channel 3 - 9 Israel */ 206*298e50adSKalle Valo 207*298e50adSKalle Valo #define IW_MGMT_RATE_LABEL_MANDATORY 128 /* MSB */ 208*298e50adSKalle Valo 209*298e50adSKalle Valo enum iw_mgmt_rate_labels { 210*298e50adSKalle Valo IW_MGMT_RATE_LABEL_1MBIT = 2, 211*298e50adSKalle Valo IW_MGMT_RATE_LABEL_2MBIT = 4, 212*298e50adSKalle Valo IW_MGMT_RATE_LABEL_5_5MBIT = 11, 213*298e50adSKalle Valo IW_MGMT_RATE_LABEL_11MBIT = 22, 214*298e50adSKalle Valo }; 215*298e50adSKalle Valo 216*298e50adSKalle Valo enum iw_mgmt_info_element_ids { 217*298e50adSKalle Valo IW_MGMT_INFO_ELEMENT_SSID, /* Service Set Identity */ 218*298e50adSKalle Valo IW_MGMT_INFO_ELEMENT_SUPPORTED_RATES, 219*298e50adSKalle Valo IW_MGMT_INFO_ELEMENT_FH_PARAMETER_SET, 220*298e50adSKalle Valo IW_MGMT_INFO_ELEMENT_DS_PARAMETER_SET, 221*298e50adSKalle Valo IW_MGMT_INFO_ELEMENT_CS_PARAMETER_SET, 222*298e50adSKalle Valo IW_MGMT_INFO_ELEMENT_CS_TIM, /* Traffic Information Map */ 223*298e50adSKalle Valo IW_MGMT_INFO_ELEMENT_IBSS_PARAMETER_SET, 224*298e50adSKalle Valo /* 7-15: Reserved, unused */ 225*298e50adSKalle Valo IW_MGMT_INFO_ELEMENT_CHALLENGE_TEXT = 16, 226*298e50adSKalle Valo /* 17-31 Reserved for challenge text extension */ 227*298e50adSKalle Valo /* 32-255 Reserved, unused */ 228*298e50adSKalle Valo }; 229*298e50adSKalle Valo 230*298e50adSKalle Valo struct iw_mgmt_info_element { 231*298e50adSKalle Valo u8 id; /* one of enum iw_mgmt_info_element_ids, 232*298e50adSKalle Valo but sizeof(enum) > sizeof(u8) :-( */ 233*298e50adSKalle Valo u8 len; 234*298e50adSKalle Valo u8 data[]; 235*298e50adSKalle Valo } __packed; 236*298e50adSKalle Valo 237*298e50adSKalle Valo struct iw_mgmt_essid_pset { 238*298e50adSKalle Valo struct iw_mgmt_info_element el; 239*298e50adSKalle Valo u8 essid[IW_ESSID_MAX_SIZE]; 240*298e50adSKalle Valo } __packed; 241*298e50adSKalle Valo 242*298e50adSKalle Valo /* 243*298e50adSKalle Valo * According to 802.11 Wireless Networks, the definitive guide - O'Reilly 244*298e50adSKalle Valo * Pg 75 245*298e50adSKalle Valo */ 246*298e50adSKalle Valo #define IW_DATA_RATE_MAX_LABELS 8 247*298e50adSKalle Valo 248*298e50adSKalle Valo struct iw_mgmt_data_rset { 249*298e50adSKalle Valo struct iw_mgmt_info_element el; 250*298e50adSKalle Valo u8 data_rate_labels[IW_DATA_RATE_MAX_LABELS]; 251*298e50adSKalle Valo } __packed; 252*298e50adSKalle Valo 253*298e50adSKalle Valo struct iw_mgmt_ds_pset { 254*298e50adSKalle Valo struct iw_mgmt_info_element el; 255*298e50adSKalle Valo u8 chan; 256*298e50adSKalle Valo } __packed; 257*298e50adSKalle Valo 258*298e50adSKalle Valo struct iw_mgmt_cf_pset { 259*298e50adSKalle Valo struct iw_mgmt_info_element el; 260*298e50adSKalle Valo u8 cfp_count; 261*298e50adSKalle Valo u8 cfp_period; 262*298e50adSKalle Valo u16 cfp_max_duration; 263*298e50adSKalle Valo u16 cfp_dur_remaining; 264*298e50adSKalle Valo } __packed; 265*298e50adSKalle Valo 266*298e50adSKalle Valo struct iw_mgmt_ibss_pset { 267*298e50adSKalle Valo struct iw_mgmt_info_element el; 268*298e50adSKalle Valo u16 atim_window; 269*298e50adSKalle Valo } __packed; 270*298e50adSKalle Valo 271*298e50adSKalle Valo struct wl3501_tx_hdr { 272*298e50adSKalle Valo u16 tx_cnt; 273*298e50adSKalle Valo u8 sync[16]; 274*298e50adSKalle Valo u16 sfd; 275*298e50adSKalle Valo u8 signal; 276*298e50adSKalle Valo u8 service; 277*298e50adSKalle Valo u16 len; 278*298e50adSKalle Valo u16 crc16; 279*298e50adSKalle Valo u16 frame_ctrl; 280*298e50adSKalle Valo u16 duration_id; 281*298e50adSKalle Valo u8 addr1[ETH_ALEN]; 282*298e50adSKalle Valo u8 addr2[ETH_ALEN]; 283*298e50adSKalle Valo u8 addr3[ETH_ALEN]; 284*298e50adSKalle Valo u16 seq_ctrl; 285*298e50adSKalle Valo u8 addr4[ETH_ALEN]; 286*298e50adSKalle Valo }; 287*298e50adSKalle Valo 288*298e50adSKalle Valo struct wl3501_rx_hdr { 289*298e50adSKalle Valo u16 rx_next_blk; 290*298e50adSKalle Valo u16 rc_next_frame_blk; 291*298e50adSKalle Valo u8 rx_blk_ctrl; 292*298e50adSKalle Valo u8 rx_next_frame; 293*298e50adSKalle Valo u8 rx_next_frame1; 294*298e50adSKalle Valo u8 rssi; 295*298e50adSKalle Valo char time[8]; 296*298e50adSKalle Valo u8 signal; 297*298e50adSKalle Valo u8 service; 298*298e50adSKalle Valo u16 len; 299*298e50adSKalle Valo u16 crc16; 300*298e50adSKalle Valo u16 frame_ctrl; 301*298e50adSKalle Valo u16 duration; 302*298e50adSKalle Valo u8 addr1[ETH_ALEN]; 303*298e50adSKalle Valo u8 addr2[ETH_ALEN]; 304*298e50adSKalle Valo u8 addr3[ETH_ALEN]; 305*298e50adSKalle Valo u16 seq; 306*298e50adSKalle Valo u8 addr4[ETH_ALEN]; 307*298e50adSKalle Valo }; 308*298e50adSKalle Valo 309*298e50adSKalle Valo struct wl3501_start_req { 310*298e50adSKalle Valo u16 next_blk; 311*298e50adSKalle Valo u8 sig_id; 312*298e50adSKalle Valo u8 bss_type; 313*298e50adSKalle Valo u16 beacon_period; 314*298e50adSKalle Valo u16 dtim_period; 315*298e50adSKalle Valo u16 probe_delay; 316*298e50adSKalle Valo u16 cap_info; 317*298e50adSKalle Valo struct iw_mgmt_essid_pset ssid; 318*298e50adSKalle Valo struct iw_mgmt_data_rset bss_basic_rset; 319*298e50adSKalle Valo struct iw_mgmt_data_rset operational_rset; 320*298e50adSKalle Valo struct iw_mgmt_cf_pset cf_pset; 321*298e50adSKalle Valo struct iw_mgmt_ds_pset ds_pset; 322*298e50adSKalle Valo struct iw_mgmt_ibss_pset ibss_pset; 323*298e50adSKalle Valo }; 324*298e50adSKalle Valo 325*298e50adSKalle Valo struct wl3501_assoc_req { 326*298e50adSKalle Valo u16 next_blk; 327*298e50adSKalle Valo u8 sig_id; 328*298e50adSKalle Valo u8 reserved; 329*298e50adSKalle Valo u16 timeout; 330*298e50adSKalle Valo u16 cap_info; 331*298e50adSKalle Valo u16 listen_interval; 332*298e50adSKalle Valo u8 mac_addr[ETH_ALEN]; 333*298e50adSKalle Valo }; 334*298e50adSKalle Valo 335*298e50adSKalle Valo struct wl3501_assoc_confirm { 336*298e50adSKalle Valo u16 next_blk; 337*298e50adSKalle Valo u8 sig_id; 338*298e50adSKalle Valo u8 reserved; 339*298e50adSKalle Valo u16 status; 340*298e50adSKalle Valo }; 341*298e50adSKalle Valo 342*298e50adSKalle Valo struct wl3501_assoc_ind { 343*298e50adSKalle Valo u16 next_blk; 344*298e50adSKalle Valo u8 sig_id; 345*298e50adSKalle Valo u8 mac_addr[ETH_ALEN]; 346*298e50adSKalle Valo }; 347*298e50adSKalle Valo 348*298e50adSKalle Valo struct wl3501_auth_req { 349*298e50adSKalle Valo u16 next_blk; 350*298e50adSKalle Valo u8 sig_id; 351*298e50adSKalle Valo u8 reserved; 352*298e50adSKalle Valo u16 type; 353*298e50adSKalle Valo u16 timeout; 354*298e50adSKalle Valo u8 mac_addr[ETH_ALEN]; 355*298e50adSKalle Valo }; 356*298e50adSKalle Valo 357*298e50adSKalle Valo struct wl3501_auth_confirm { 358*298e50adSKalle Valo u16 next_blk; 359*298e50adSKalle Valo u8 sig_id; 360*298e50adSKalle Valo u8 reserved; 361*298e50adSKalle Valo u16 type; 362*298e50adSKalle Valo u16 status; 363*298e50adSKalle Valo u8 mac_addr[ETH_ALEN]; 364*298e50adSKalle Valo }; 365*298e50adSKalle Valo 366*298e50adSKalle Valo struct wl3501_get_req { 367*298e50adSKalle Valo u16 next_blk; 368*298e50adSKalle Valo u8 sig_id; 369*298e50adSKalle Valo u8 reserved; 370*298e50adSKalle Valo u16 mib_attrib; 371*298e50adSKalle Valo }; 372*298e50adSKalle Valo 373*298e50adSKalle Valo struct wl3501_get_confirm { 374*298e50adSKalle Valo u16 next_blk; 375*298e50adSKalle Valo u8 sig_id; 376*298e50adSKalle Valo u8 reserved; 377*298e50adSKalle Valo u16 mib_status; 378*298e50adSKalle Valo u16 mib_attrib; 379*298e50adSKalle Valo u8 mib_value[100]; 380*298e50adSKalle Valo }; 381*298e50adSKalle Valo 382*298e50adSKalle Valo struct wl3501_req { 383*298e50adSKalle Valo u16 beacon_period; 384*298e50adSKalle Valo u16 dtim_period; 385*298e50adSKalle Valo u16 cap_info; 386*298e50adSKalle Valo u8 bss_type; 387*298e50adSKalle Valo u8 bssid[ETH_ALEN]; 388*298e50adSKalle Valo struct iw_mgmt_essid_pset ssid; 389*298e50adSKalle Valo struct iw_mgmt_ds_pset ds_pset; 390*298e50adSKalle Valo struct iw_mgmt_cf_pset cf_pset; 391*298e50adSKalle Valo struct iw_mgmt_ibss_pset ibss_pset; 392*298e50adSKalle Valo struct iw_mgmt_data_rset bss_basic_rset; 393*298e50adSKalle Valo }; 394*298e50adSKalle Valo 395*298e50adSKalle Valo struct wl3501_join_req { 396*298e50adSKalle Valo u16 next_blk; 397*298e50adSKalle Valo u8 sig_id; 398*298e50adSKalle Valo u8 reserved; 399*298e50adSKalle Valo struct iw_mgmt_data_rset operational_rset; 400*298e50adSKalle Valo u16 reserved2; 401*298e50adSKalle Valo u16 timeout; 402*298e50adSKalle Valo u16 probe_delay; 403*298e50adSKalle Valo u8 timestamp[8]; 404*298e50adSKalle Valo u8 local_time[8]; 405*298e50adSKalle Valo struct wl3501_req req; 406*298e50adSKalle Valo }; 407*298e50adSKalle Valo 408*298e50adSKalle Valo struct wl3501_join_confirm { 409*298e50adSKalle Valo u16 next_blk; 410*298e50adSKalle Valo u8 sig_id; 411*298e50adSKalle Valo u8 reserved; 412*298e50adSKalle Valo u16 status; 413*298e50adSKalle Valo }; 414*298e50adSKalle Valo 415*298e50adSKalle Valo struct wl3501_pwr_mgmt_req { 416*298e50adSKalle Valo u16 next_blk; 417*298e50adSKalle Valo u8 sig_id; 418*298e50adSKalle Valo u8 pwr_save; 419*298e50adSKalle Valo u8 wake_up; 420*298e50adSKalle Valo u8 receive_dtims; 421*298e50adSKalle Valo }; 422*298e50adSKalle Valo 423*298e50adSKalle Valo struct wl3501_pwr_mgmt_confirm { 424*298e50adSKalle Valo u16 next_blk; 425*298e50adSKalle Valo u8 sig_id; 426*298e50adSKalle Valo u8 reserved; 427*298e50adSKalle Valo u16 status; 428*298e50adSKalle Valo }; 429*298e50adSKalle Valo 430*298e50adSKalle Valo struct wl3501_scan_req { 431*298e50adSKalle Valo u16 next_blk; 432*298e50adSKalle Valo u8 sig_id; 433*298e50adSKalle Valo u8 bss_type; 434*298e50adSKalle Valo u16 probe_delay; 435*298e50adSKalle Valo u16 min_chan_time; 436*298e50adSKalle Valo u16 max_chan_time; 437*298e50adSKalle Valo u8 chan_list[14]; 438*298e50adSKalle Valo u8 bssid[ETH_ALEN]; 439*298e50adSKalle Valo struct iw_mgmt_essid_pset ssid; 440*298e50adSKalle Valo enum wl3501_scan_type scan_type; 441*298e50adSKalle Valo }; 442*298e50adSKalle Valo 443*298e50adSKalle Valo struct wl3501_scan_confirm { 444*298e50adSKalle Valo u16 next_blk; 445*298e50adSKalle Valo u8 sig_id; 446*298e50adSKalle Valo u8 reserved; 447*298e50adSKalle Valo u16 status; 448*298e50adSKalle Valo char timestamp[8]; 449*298e50adSKalle Valo char localtime[8]; 450*298e50adSKalle Valo struct wl3501_req req; 451*298e50adSKalle Valo u8 rssi; 452*298e50adSKalle Valo }; 453*298e50adSKalle Valo 454*298e50adSKalle Valo struct wl3501_start_confirm { 455*298e50adSKalle Valo u16 next_blk; 456*298e50adSKalle Valo u8 sig_id; 457*298e50adSKalle Valo u8 reserved; 458*298e50adSKalle Valo u16 status; 459*298e50adSKalle Valo }; 460*298e50adSKalle Valo 461*298e50adSKalle Valo struct wl3501_md_req { 462*298e50adSKalle Valo u16 next_blk; 463*298e50adSKalle Valo u8 sig_id; 464*298e50adSKalle Valo u8 routing; 465*298e50adSKalle Valo u16 data; 466*298e50adSKalle Valo u16 size; 467*298e50adSKalle Valo u8 pri; 468*298e50adSKalle Valo u8 service_class; 469*298e50adSKalle Valo struct { 470*298e50adSKalle Valo u8 daddr[ETH_ALEN]; 471*298e50adSKalle Valo u8 saddr[ETH_ALEN]; 472*298e50adSKalle Valo } addr; 473*298e50adSKalle Valo }; 474*298e50adSKalle Valo 475*298e50adSKalle Valo struct wl3501_md_ind { 476*298e50adSKalle Valo u16 next_blk; 477*298e50adSKalle Valo u8 sig_id; 478*298e50adSKalle Valo u8 routing; 479*298e50adSKalle Valo u16 data; 480*298e50adSKalle Valo u16 size; 481*298e50adSKalle Valo u8 reception; 482*298e50adSKalle Valo u8 pri; 483*298e50adSKalle Valo u8 service_class; 484*298e50adSKalle Valo struct { 485*298e50adSKalle Valo u8 daddr[ETH_ALEN]; 486*298e50adSKalle Valo u8 saddr[ETH_ALEN]; 487*298e50adSKalle Valo } addr; 488*298e50adSKalle Valo }; 489*298e50adSKalle Valo 490*298e50adSKalle Valo struct wl3501_md_confirm { 491*298e50adSKalle Valo u16 next_blk; 492*298e50adSKalle Valo u8 sig_id; 493*298e50adSKalle Valo u8 reserved; 494*298e50adSKalle Valo u16 data; 495*298e50adSKalle Valo u8 status; 496*298e50adSKalle Valo u8 pri; 497*298e50adSKalle Valo u8 service_class; 498*298e50adSKalle Valo }; 499*298e50adSKalle Valo 500*298e50adSKalle Valo struct wl3501_resync_req { 501*298e50adSKalle Valo u16 next_blk; 502*298e50adSKalle Valo u8 sig_id; 503*298e50adSKalle Valo }; 504*298e50adSKalle Valo 505*298e50adSKalle Valo /* Definitions for supporting clone adapters. */ 506*298e50adSKalle Valo /* System Interface Registers (SIR space) */ 507*298e50adSKalle Valo #define WL3501_NIC_GCR ((u8)0x00) /* SIR0 - General Conf Register */ 508*298e50adSKalle Valo #define WL3501_NIC_BSS ((u8)0x01) /* SIR1 - Bank Switching Select Reg */ 509*298e50adSKalle Valo #define WL3501_NIC_LMAL ((u8)0x02) /* SIR2 - Local Mem addr Reg [7:0] */ 510*298e50adSKalle Valo #define WL3501_NIC_LMAH ((u8)0x03) /* SIR3 - Local Mem addr Reg [14:8] */ 511*298e50adSKalle Valo #define WL3501_NIC_IODPA ((u8)0x04) /* SIR4 - I/O Data Port A */ 512*298e50adSKalle Valo #define WL3501_NIC_IODPB ((u8)0x05) /* SIR5 - I/O Data Port B */ 513*298e50adSKalle Valo #define WL3501_NIC_IODPC ((u8)0x06) /* SIR6 - I/O Data Port C */ 514*298e50adSKalle Valo #define WL3501_NIC_IODPD ((u8)0x07) /* SIR7 - I/O Data Port D */ 515*298e50adSKalle Valo 516*298e50adSKalle Valo /* Bits in GCR */ 517*298e50adSKalle Valo #define WL3501_GCR_SWRESET ((u8)0x80) 518*298e50adSKalle Valo #define WL3501_GCR_CORESET ((u8)0x40) 519*298e50adSKalle Valo #define WL3501_GCR_DISPWDN ((u8)0x20) 520*298e50adSKalle Valo #define WL3501_GCR_ECWAIT ((u8)0x10) 521*298e50adSKalle Valo #define WL3501_GCR_ECINT ((u8)0x08) 522*298e50adSKalle Valo #define WL3501_GCR_INT2EC ((u8)0x04) 523*298e50adSKalle Valo #define WL3501_GCR_ENECINT ((u8)0x02) 524*298e50adSKalle Valo #define WL3501_GCR_DAM ((u8)0x01) 525*298e50adSKalle Valo 526*298e50adSKalle Valo /* Bits in BSS (Bank Switching Select Register) */ 527*298e50adSKalle Valo #define WL3501_BSS_FPAGE0 ((u8)0x20) /* Flash memory page0 */ 528*298e50adSKalle Valo #define WL3501_BSS_FPAGE1 ((u8)0x28) 529*298e50adSKalle Valo #define WL3501_BSS_FPAGE2 ((u8)0x30) 530*298e50adSKalle Valo #define WL3501_BSS_FPAGE3 ((u8)0x38) 531*298e50adSKalle Valo #define WL3501_BSS_SPAGE0 ((u8)0x00) /* SRAM page0 */ 532*298e50adSKalle Valo #define WL3501_BSS_SPAGE1 ((u8)0x08) 533*298e50adSKalle Valo #define WL3501_BSS_SPAGE2 ((u8)0x10) 534*298e50adSKalle Valo #define WL3501_BSS_SPAGE3 ((u8)0x18) 535*298e50adSKalle Valo 536*298e50adSKalle Valo /* Define Driver Interface */ 537*298e50adSKalle Valo /* Refer IEEE 802.11 */ 538*298e50adSKalle Valo /* Tx packet header, include PLCP and MPDU */ 539*298e50adSKalle Valo /* Tx PLCP Header */ 540*298e50adSKalle Valo struct wl3501_80211_tx_plcp_hdr { 541*298e50adSKalle Valo u8 sync[16]; 542*298e50adSKalle Valo u16 sfd; 543*298e50adSKalle Valo u8 signal; 544*298e50adSKalle Valo u8 service; 545*298e50adSKalle Valo u16 len; 546*298e50adSKalle Valo u16 crc16; 547*298e50adSKalle Valo } __packed; 548*298e50adSKalle Valo 549*298e50adSKalle Valo struct wl3501_80211_tx_hdr { 550*298e50adSKalle Valo struct wl3501_80211_tx_plcp_hdr pclp_hdr; 551*298e50adSKalle Valo struct ieee80211_hdr mac_hdr; 552*298e50adSKalle Valo } __packed __aligned(2); 553*298e50adSKalle Valo 554*298e50adSKalle Valo /* 555*298e50adSKalle Valo Reserve the beginning Tx space for descriptor use. 556*298e50adSKalle Valo 557*298e50adSKalle Valo TxBlockOffset --> *----*----*----*----* \ 558*298e50adSKalle Valo (TxFreeDesc) | 0 | 1 | 2 | 3 | \ 559*298e50adSKalle Valo | 4 | 5 | 6 | 7 | | 560*298e50adSKalle Valo | 8 | 9 | 10 | 11 | TX_DESC * 20 561*298e50adSKalle Valo | 12 | 13 | 14 | 15 | | 562*298e50adSKalle Valo | 16 | 17 | 18 | 19 | / 563*298e50adSKalle Valo TxBufferBegin --> *----*----*----*----* / 564*298e50adSKalle Valo (TxBufferHead) | | 565*298e50adSKalle Valo (TxBufferTail) | | 566*298e50adSKalle Valo | Send Buffer | 567*298e50adSKalle Valo | | 568*298e50adSKalle Valo | | 569*298e50adSKalle Valo *-------------------* 570*298e50adSKalle Valo TxBufferEnd -------------------------/ 571*298e50adSKalle Valo 572*298e50adSKalle Valo */ 573*298e50adSKalle Valo 574*298e50adSKalle Valo struct wl3501_card { 575*298e50adSKalle Valo int base_addr; 576*298e50adSKalle Valo u8 mac_addr[ETH_ALEN]; 577*298e50adSKalle Valo spinlock_t lock; 578*298e50adSKalle Valo wait_queue_head_t wait; 579*298e50adSKalle Valo struct wl3501_get_confirm sig_get_confirm; 580*298e50adSKalle Valo struct wl3501_pwr_mgmt_confirm sig_pwr_mgmt_confirm; 581*298e50adSKalle Valo u16 tx_buffer_size; 582*298e50adSKalle Valo u16 tx_buffer_head; 583*298e50adSKalle Valo u16 tx_buffer_tail; 584*298e50adSKalle Valo u16 tx_buffer_cnt; 585*298e50adSKalle Valo u16 esbq_req_start; 586*298e50adSKalle Valo u16 esbq_req_end; 587*298e50adSKalle Valo u16 esbq_req_head; 588*298e50adSKalle Valo u16 esbq_req_tail; 589*298e50adSKalle Valo u16 esbq_confirm_start; 590*298e50adSKalle Valo u16 esbq_confirm_end; 591*298e50adSKalle Valo u16 esbq_confirm; 592*298e50adSKalle Valo struct iw_mgmt_essid_pset essid; 593*298e50adSKalle Valo struct iw_mgmt_essid_pset keep_essid; 594*298e50adSKalle Valo u8 bssid[ETH_ALEN]; 595*298e50adSKalle Valo int net_type; 596*298e50adSKalle Valo char nick[32]; 597*298e50adSKalle Valo char card_name[32]; 598*298e50adSKalle Valo char firmware_date[32]; 599*298e50adSKalle Valo u8 chan; 600*298e50adSKalle Valo u8 cap_info; 601*298e50adSKalle Valo u16 start_seg; 602*298e50adSKalle Valo u16 bss_cnt; 603*298e50adSKalle Valo u16 join_sta_bss; 604*298e50adSKalle Valo u8 rssi; 605*298e50adSKalle Valo u8 adhoc_times; 606*298e50adSKalle Valo u8 reg_domain; 607*298e50adSKalle Valo u8 version[2]; 608*298e50adSKalle Valo struct wl3501_scan_confirm bss_set[20]; 609*298e50adSKalle Valo 610*298e50adSKalle Valo struct iw_statistics wstats; 611*298e50adSKalle Valo struct iw_spy_data spy_data; 612*298e50adSKalle Valo struct iw_public_data wireless_data; 613*298e50adSKalle Valo struct pcmcia_device *p_dev; 614*298e50adSKalle Valo }; 615*298e50adSKalle Valo #endif 616