1*2b27bdccSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2d3466830SKalle Valo /* 3d3466830SKalle Valo * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de> 4d3466830SKalle Valo * 5d3466830SKalle Valo * This driver is a port from stlc45xx: 6d3466830SKalle Valo * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies). 7d3466830SKalle Valo */ 8d3466830SKalle Valo 9d3466830SKalle Valo #ifndef P54SPI_H 10d3466830SKalle Valo #define P54SPI_H 11d3466830SKalle Valo 12d3466830SKalle Valo #include <linux/mutex.h> 13d3466830SKalle Valo #include <linux/list.h> 14d3466830SKalle Valo #include <net/mac80211.h> 15d3466830SKalle Valo 16d3466830SKalle Valo #include "p54.h" 17d3466830SKalle Valo 18d3466830SKalle Valo /* Bit 15 is read/write bit; ON = READ, OFF = WRITE */ 19d3466830SKalle Valo #define SPI_ADRS_READ_BIT_15 0x8000 20d3466830SKalle Valo 21d3466830SKalle Valo #define SPI_ADRS_ARM_INTERRUPTS 0x00 22d3466830SKalle Valo #define SPI_ADRS_ARM_INT_EN 0x04 23d3466830SKalle Valo 24d3466830SKalle Valo #define SPI_ADRS_HOST_INTERRUPTS 0x08 25d3466830SKalle Valo #define SPI_ADRS_HOST_INT_EN 0x0c 26d3466830SKalle Valo #define SPI_ADRS_HOST_INT_ACK 0x10 27d3466830SKalle Valo 28d3466830SKalle Valo #define SPI_ADRS_GEN_PURP_1 0x14 29d3466830SKalle Valo #define SPI_ADRS_GEN_PURP_2 0x18 30d3466830SKalle Valo 31d3466830SKalle Valo #define SPI_ADRS_DEV_CTRL_STAT 0x26 /* high word */ 32d3466830SKalle Valo 33d3466830SKalle Valo #define SPI_ADRS_DMA_DATA 0x28 34d3466830SKalle Valo 35d3466830SKalle Valo #define SPI_ADRS_DMA_WRITE_CTRL 0x2c 36d3466830SKalle Valo #define SPI_ADRS_DMA_WRITE_LEN 0x2e 37d3466830SKalle Valo #define SPI_ADRS_DMA_WRITE_BASE 0x30 38d3466830SKalle Valo 39d3466830SKalle Valo #define SPI_ADRS_DMA_READ_CTRL 0x34 40d3466830SKalle Valo #define SPI_ADRS_DMA_READ_LEN 0x36 41d3466830SKalle Valo #define SPI_ADRS_DMA_READ_BASE 0x38 42d3466830SKalle Valo 43d3466830SKalle Valo #define SPI_CTRL_STAT_HOST_OVERRIDE 0x8000 44d3466830SKalle Valo #define SPI_CTRL_STAT_START_HALTED 0x4000 45d3466830SKalle Valo #define SPI_CTRL_STAT_RAM_BOOT 0x2000 46d3466830SKalle Valo #define SPI_CTRL_STAT_HOST_RESET 0x1000 47d3466830SKalle Valo #define SPI_CTRL_STAT_HOST_CPU_EN 0x0800 48d3466830SKalle Valo 49d3466830SKalle Valo #define SPI_DMA_WRITE_CTRL_ENABLE 0x0001 50d3466830SKalle Valo #define SPI_DMA_READ_CTRL_ENABLE 0x0001 51d3466830SKalle Valo #define HOST_ALLOWED (1 << 7) 52d3466830SKalle Valo 53d3466830SKalle Valo #define SPI_TIMEOUT 100 /* msec */ 54d3466830SKalle Valo 55d3466830SKalle Valo #define SPI_MAX_TX_PACKETS 32 56d3466830SKalle Valo 57d3466830SKalle Valo #define SPI_MAX_PACKET_SIZE 32767 58d3466830SKalle Valo 59d3466830SKalle Valo #define SPI_TARGET_INT_WAKEUP 0x00000001 60d3466830SKalle Valo #define SPI_TARGET_INT_SLEEP 0x00000002 61d3466830SKalle Valo #define SPI_TARGET_INT_RDDONE 0x00000004 62d3466830SKalle Valo 63d3466830SKalle Valo #define SPI_TARGET_INT_CTS 0x00004000 64d3466830SKalle Valo #define SPI_TARGET_INT_DR 0x00008000 65d3466830SKalle Valo 66d3466830SKalle Valo #define SPI_HOST_INT_READY 0x00000001 67d3466830SKalle Valo #define SPI_HOST_INT_WR_READY 0x00000002 68d3466830SKalle Valo #define SPI_HOST_INT_SW_UPDATE 0x00000004 69d3466830SKalle Valo #define SPI_HOST_INT_UPDATE 0x10000000 70d3466830SKalle Valo 71d3466830SKalle Valo /* clear to send */ 72d3466830SKalle Valo #define SPI_HOST_INT_CR 0x00004000 73d3466830SKalle Valo 74d3466830SKalle Valo /* data ready */ 75d3466830SKalle Valo #define SPI_HOST_INT_DR 0x00008000 76d3466830SKalle Valo 77d3466830SKalle Valo #define SPI_HOST_INTS_DEFAULT \ 78d3466830SKalle Valo (SPI_HOST_INT_READY | SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE) 79d3466830SKalle Valo 80d3466830SKalle Valo #define TARGET_BOOT_SLEEP 50 81d3466830SKalle Valo 82d3466830SKalle Valo struct p54s_dma_regs { 83d3466830SKalle Valo __le16 cmd; 84d3466830SKalle Valo __le16 len; 85d3466830SKalle Valo __le32 addr; 86d3466830SKalle Valo } __packed; 87d3466830SKalle Valo 88d3466830SKalle Valo struct p54s_tx_info { 89d3466830SKalle Valo struct list_head tx_list; 90d3466830SKalle Valo }; 91d3466830SKalle Valo 92d3466830SKalle Valo struct p54s_priv { 93d3466830SKalle Valo /* p54_common has to be the first entry */ 94d3466830SKalle Valo struct p54_common common; 95d3466830SKalle Valo struct ieee80211_hw *hw; 96d3466830SKalle Valo struct spi_device *spi; 97d3466830SKalle Valo 98d3466830SKalle Valo struct work_struct work; 99d3466830SKalle Valo 100d3466830SKalle Valo struct mutex mutex; 101d3466830SKalle Valo struct completion fw_comp; 102d3466830SKalle Valo 103d3466830SKalle Valo spinlock_t tx_lock; 104d3466830SKalle Valo 105d3466830SKalle Valo /* protected by tx_lock */ 106d3466830SKalle Valo struct list_head tx_pending; 107d3466830SKalle Valo 108d3466830SKalle Valo enum fw_state fw_state; 109d3466830SKalle Valo const struct firmware *firmware; 110d3466830SKalle Valo }; 111d3466830SKalle Valo 112d3466830SKalle Valo #endif /* P54SPI_H */ 113