1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2eb4f98d5SKalle Valo #ifndef HOSTAP_WLAN_H
3eb4f98d5SKalle Valo #define HOSTAP_WLAN_H
4eb4f98d5SKalle Valo
5eb4f98d5SKalle Valo #include <linux/interrupt.h>
6eb4f98d5SKalle Valo #include <linux/wireless.h>
7eb4f98d5SKalle Valo #include <linux/netdevice.h>
8eb4f98d5SKalle Valo #include <linux/etherdevice.h>
9eb4f98d5SKalle Valo #include <linux/mutex.h>
10552aa585SElena Reshetova #include <linux/refcount.h>
11eb4f98d5SKalle Valo #include <net/iw_handler.h>
12eb4f98d5SKalle Valo #include <net/ieee80211_radiotap.h>
13eb4f98d5SKalle Valo #include <net/lib80211.h>
14eb4f98d5SKalle Valo
15eb4f98d5SKalle Valo #include "hostap_config.h"
16eb4f98d5SKalle Valo #include "hostap_common.h"
17eb4f98d5SKalle Valo
18eb4f98d5SKalle Valo #define MAX_PARM_DEVICES 8
19eb4f98d5SKalle Valo #define PARM_MIN_MAX "1-" __MODULE_STRING(MAX_PARM_DEVICES)
20eb4f98d5SKalle Valo #define DEF_INTS -1, -1, -1, -1, -1, -1, -1
21eb4f98d5SKalle Valo #define GET_INT_PARM(var,idx) var[var[idx] < 0 ? 0 : idx]
22eb4f98d5SKalle Valo
23eb4f98d5SKalle Valo
24eb4f98d5SKalle Valo /* Specific skb->protocol value that indicates that the packet already contains
25eb4f98d5SKalle Valo * txdesc header.
26eb4f98d5SKalle Valo * FIX: This might need own value that would be allocated especially for Prism2
27eb4f98d5SKalle Valo * txdesc; ETH_P_CONTROL is commented as "Card specific control frames".
28eb4f98d5SKalle Valo * However, these skb's should have only minimal path in the kernel side since
29eb4f98d5SKalle Valo * prism2_send_mgmt() sends these with dev_queue_xmit() to prism2_tx(). */
30eb4f98d5SKalle Valo #define ETH_P_HOSTAP ETH_P_CONTROL
31eb4f98d5SKalle Valo
32eb4f98d5SKalle Valo /* ARPHRD_IEEE80211_PRISM uses a bloated version of Prism2 RX frame header
33eb4f98d5SKalle Valo * (from linux-wlan-ng) */
34eb4f98d5SKalle Valo struct linux_wlan_ng_val {
35eb4f98d5SKalle Valo u32 did;
36eb4f98d5SKalle Valo u16 status, len;
37eb4f98d5SKalle Valo u32 data;
38eb4f98d5SKalle Valo } __packed;
39eb4f98d5SKalle Valo
40eb4f98d5SKalle Valo struct linux_wlan_ng_prism_hdr {
41eb4f98d5SKalle Valo u32 msgcode, msglen;
42eb4f98d5SKalle Valo char devname[16];
43eb4f98d5SKalle Valo struct linux_wlan_ng_val hosttime, mactime, channel, rssi, sq, signal,
44eb4f98d5SKalle Valo noise, rate, istx, frmlen;
45eb4f98d5SKalle Valo } __packed;
46eb4f98d5SKalle Valo
47eb4f98d5SKalle Valo struct linux_wlan_ng_cap_hdr {
48eb4f98d5SKalle Valo __be32 version;
49eb4f98d5SKalle Valo __be32 length;
50eb4f98d5SKalle Valo __be64 mactime;
51eb4f98d5SKalle Valo __be64 hosttime;
52eb4f98d5SKalle Valo __be32 phytype;
53eb4f98d5SKalle Valo __be32 channel;
54eb4f98d5SKalle Valo __be32 datarate;
55eb4f98d5SKalle Valo __be32 antenna;
56eb4f98d5SKalle Valo __be32 priority;
57eb4f98d5SKalle Valo __be32 ssi_type;
58eb4f98d5SKalle Valo __be32 ssi_signal;
59eb4f98d5SKalle Valo __be32 ssi_noise;
60eb4f98d5SKalle Valo __be32 preamble;
61eb4f98d5SKalle Valo __be32 encoding;
62eb4f98d5SKalle Valo } __packed;
63eb4f98d5SKalle Valo
64eb4f98d5SKalle Valo struct hostap_radiotap_rx {
65eb4f98d5SKalle Valo struct ieee80211_radiotap_header hdr;
66eb4f98d5SKalle Valo __le64 tsft;
67eb4f98d5SKalle Valo u8 rate;
68eb4f98d5SKalle Valo u8 padding;
69eb4f98d5SKalle Valo __le16 chan_freq;
70eb4f98d5SKalle Valo __le16 chan_flags;
71eb4f98d5SKalle Valo s8 dbm_antsignal;
72eb4f98d5SKalle Valo s8 dbm_antnoise;
73eb4f98d5SKalle Valo } __packed;
74eb4f98d5SKalle Valo
75eb4f98d5SKalle Valo #define LWNG_CAP_DID_BASE (4 | (1 << 6)) /* section 4, group 1 */
76eb4f98d5SKalle Valo #define LWNG_CAPHDR_VERSION 0x80211001
77eb4f98d5SKalle Valo
78eb4f98d5SKalle Valo struct hfa384x_rx_frame {
79eb4f98d5SKalle Valo /* HFA384X RX frame descriptor */
80eb4f98d5SKalle Valo __le16 status; /* HFA384X_RX_STATUS_ flags */
81eb4f98d5SKalle Valo __le32 time; /* timestamp, 1 microsecond resolution */
82eb4f98d5SKalle Valo u8 silence; /* 27 .. 154; seems to be 0 */
83eb4f98d5SKalle Valo u8 signal; /* 27 .. 154 */
84eb4f98d5SKalle Valo u8 rate; /* 10, 20, 55, or 110 */
85eb4f98d5SKalle Valo u8 rxflow;
86eb4f98d5SKalle Valo __le32 reserved;
87eb4f98d5SKalle Valo
88eb4f98d5SKalle Valo /* 802.11 */
89eb4f98d5SKalle Valo __le16 frame_control;
90eb4f98d5SKalle Valo __le16 duration_id;
91eb4f98d5SKalle Valo u8 addr1[ETH_ALEN];
92eb4f98d5SKalle Valo u8 addr2[ETH_ALEN];
93eb4f98d5SKalle Valo u8 addr3[ETH_ALEN];
94eb4f98d5SKalle Valo __le16 seq_ctrl;
95eb4f98d5SKalle Valo u8 addr4[ETH_ALEN];
96eb4f98d5SKalle Valo __le16 data_len;
97eb4f98d5SKalle Valo
98eb4f98d5SKalle Valo /* 802.3 */
99eb4f98d5SKalle Valo u8 dst_addr[ETH_ALEN];
100eb4f98d5SKalle Valo u8 src_addr[ETH_ALEN];
101eb4f98d5SKalle Valo __be16 len;
102eb4f98d5SKalle Valo
103eb4f98d5SKalle Valo /* followed by frame data; max 2304 bytes */
104eb4f98d5SKalle Valo } __packed;
105eb4f98d5SKalle Valo
106eb4f98d5SKalle Valo
107eb4f98d5SKalle Valo struct hfa384x_tx_frame {
108eb4f98d5SKalle Valo /* HFA384X TX frame descriptor */
109eb4f98d5SKalle Valo __le16 status; /* HFA384X_TX_STATUS_ flags */
110eb4f98d5SKalle Valo __le16 reserved1;
111eb4f98d5SKalle Valo __le16 reserved2;
112eb4f98d5SKalle Valo __le32 sw_support;
113eb4f98d5SKalle Valo u8 retry_count; /* not yet implemented */
114eb4f98d5SKalle Valo u8 tx_rate; /* Host AP only; 0 = firmware, or 10, 20, 55, 110 */
115eb4f98d5SKalle Valo __le16 tx_control; /* HFA384X_TX_CTRL_ flags */
116eb4f98d5SKalle Valo
117eb4f98d5SKalle Valo /* 802.11 */
118*601d2293SKees Cook struct_group(header,
119eb4f98d5SKalle Valo __le16 frame_control; /* parts not used */
120eb4f98d5SKalle Valo __le16 duration_id;
121eb4f98d5SKalle Valo u8 addr1[ETH_ALEN];
122eb4f98d5SKalle Valo u8 addr2[ETH_ALEN]; /* filled by firmware */
123eb4f98d5SKalle Valo u8 addr3[ETH_ALEN];
124eb4f98d5SKalle Valo __le16 seq_ctrl; /* filled by firmware */
125*601d2293SKees Cook );
126eb4f98d5SKalle Valo u8 addr4[ETH_ALEN];
127eb4f98d5SKalle Valo __le16 data_len;
128eb4f98d5SKalle Valo
129eb4f98d5SKalle Valo /* 802.3 */
130eb4f98d5SKalle Valo u8 dst_addr[ETH_ALEN];
131eb4f98d5SKalle Valo u8 src_addr[ETH_ALEN];
132eb4f98d5SKalle Valo __be16 len;
133eb4f98d5SKalle Valo
134eb4f98d5SKalle Valo /* followed by frame data; max 2304 bytes */
135eb4f98d5SKalle Valo } __packed;
136eb4f98d5SKalle Valo
137eb4f98d5SKalle Valo
138eb4f98d5SKalle Valo struct hfa384x_rid_hdr
139eb4f98d5SKalle Valo {
140eb4f98d5SKalle Valo __le16 len;
141eb4f98d5SKalle Valo __le16 rid;
142eb4f98d5SKalle Valo } __packed;
143eb4f98d5SKalle Valo
144eb4f98d5SKalle Valo
145eb4f98d5SKalle Valo /* Macro for converting signal levels (range 27 .. 154) to wireless ext
146eb4f98d5SKalle Valo * dBm value with some accuracy */
147eb4f98d5SKalle Valo #define HFA384X_LEVEL_TO_dBm(v) 0x100 + (v) * 100 / 255 - 100
148eb4f98d5SKalle Valo
149eb4f98d5SKalle Valo #define HFA384X_LEVEL_TO_dBm_sign(v) (v) * 100 / 255 - 100
150eb4f98d5SKalle Valo
151eb4f98d5SKalle Valo struct hfa384x_scan_request {
152eb4f98d5SKalle Valo __le16 channel_list;
153eb4f98d5SKalle Valo __le16 txrate; /* HFA384X_RATES_* */
154eb4f98d5SKalle Valo } __packed;
155eb4f98d5SKalle Valo
156eb4f98d5SKalle Valo struct hfa384x_hostscan_request {
157eb4f98d5SKalle Valo __le16 channel_list;
158eb4f98d5SKalle Valo __le16 txrate;
159eb4f98d5SKalle Valo __le16 target_ssid_len;
160eb4f98d5SKalle Valo u8 target_ssid[32];
161eb4f98d5SKalle Valo } __packed;
162eb4f98d5SKalle Valo
163eb4f98d5SKalle Valo struct hfa384x_join_request {
164eb4f98d5SKalle Valo u8 bssid[ETH_ALEN];
165eb4f98d5SKalle Valo __le16 channel;
166eb4f98d5SKalle Valo } __packed;
167eb4f98d5SKalle Valo
168eb4f98d5SKalle Valo struct hfa384x_info_frame {
169eb4f98d5SKalle Valo __le16 len;
170eb4f98d5SKalle Valo __le16 type;
171eb4f98d5SKalle Valo } __packed;
172eb4f98d5SKalle Valo
173eb4f98d5SKalle Valo struct hfa384x_comm_tallies {
174eb4f98d5SKalle Valo __le16 tx_unicast_frames;
175eb4f98d5SKalle Valo __le16 tx_multicast_frames;
176eb4f98d5SKalle Valo __le16 tx_fragments;
177eb4f98d5SKalle Valo __le16 tx_unicast_octets;
178eb4f98d5SKalle Valo __le16 tx_multicast_octets;
179eb4f98d5SKalle Valo __le16 tx_deferred_transmissions;
180eb4f98d5SKalle Valo __le16 tx_single_retry_frames;
181eb4f98d5SKalle Valo __le16 tx_multiple_retry_frames;
182eb4f98d5SKalle Valo __le16 tx_retry_limit_exceeded;
183eb4f98d5SKalle Valo __le16 tx_discards;
184eb4f98d5SKalle Valo __le16 rx_unicast_frames;
185eb4f98d5SKalle Valo __le16 rx_multicast_frames;
186eb4f98d5SKalle Valo __le16 rx_fragments;
187eb4f98d5SKalle Valo __le16 rx_unicast_octets;
188eb4f98d5SKalle Valo __le16 rx_multicast_octets;
189eb4f98d5SKalle Valo __le16 rx_fcs_errors;
190eb4f98d5SKalle Valo __le16 rx_discards_no_buffer;
191eb4f98d5SKalle Valo __le16 tx_discards_wrong_sa;
192eb4f98d5SKalle Valo __le16 rx_discards_wep_undecryptable;
193eb4f98d5SKalle Valo __le16 rx_message_in_msg_fragments;
194eb4f98d5SKalle Valo __le16 rx_message_in_bad_msg_fragments;
195eb4f98d5SKalle Valo } __packed;
196eb4f98d5SKalle Valo
197eb4f98d5SKalle Valo struct hfa384x_comm_tallies32 {
198eb4f98d5SKalle Valo __le32 tx_unicast_frames;
199eb4f98d5SKalle Valo __le32 tx_multicast_frames;
200eb4f98d5SKalle Valo __le32 tx_fragments;
201eb4f98d5SKalle Valo __le32 tx_unicast_octets;
202eb4f98d5SKalle Valo __le32 tx_multicast_octets;
203eb4f98d5SKalle Valo __le32 tx_deferred_transmissions;
204eb4f98d5SKalle Valo __le32 tx_single_retry_frames;
205eb4f98d5SKalle Valo __le32 tx_multiple_retry_frames;
206eb4f98d5SKalle Valo __le32 tx_retry_limit_exceeded;
207eb4f98d5SKalle Valo __le32 tx_discards;
208eb4f98d5SKalle Valo __le32 rx_unicast_frames;
209eb4f98d5SKalle Valo __le32 rx_multicast_frames;
210eb4f98d5SKalle Valo __le32 rx_fragments;
211eb4f98d5SKalle Valo __le32 rx_unicast_octets;
212eb4f98d5SKalle Valo __le32 rx_multicast_octets;
213eb4f98d5SKalle Valo __le32 rx_fcs_errors;
214eb4f98d5SKalle Valo __le32 rx_discards_no_buffer;
215eb4f98d5SKalle Valo __le32 tx_discards_wrong_sa;
216eb4f98d5SKalle Valo __le32 rx_discards_wep_undecryptable;
217eb4f98d5SKalle Valo __le32 rx_message_in_msg_fragments;
218eb4f98d5SKalle Valo __le32 rx_message_in_bad_msg_fragments;
219eb4f98d5SKalle Valo } __packed;
220eb4f98d5SKalle Valo
221eb4f98d5SKalle Valo struct hfa384x_scan_result_hdr {
222eb4f98d5SKalle Valo __le16 reserved;
223eb4f98d5SKalle Valo __le16 scan_reason;
224eb4f98d5SKalle Valo #define HFA384X_SCAN_IN_PROGRESS 0 /* no results available yet */
225eb4f98d5SKalle Valo #define HFA384X_SCAN_HOST_INITIATED 1
226eb4f98d5SKalle Valo #define HFA384X_SCAN_FIRMWARE_INITIATED 2
227eb4f98d5SKalle Valo #define HFA384X_SCAN_INQUIRY_FROM_HOST 3
228eb4f98d5SKalle Valo } __packed;
229eb4f98d5SKalle Valo
230eb4f98d5SKalle Valo #define HFA384X_SCAN_MAX_RESULTS 32
231eb4f98d5SKalle Valo
232eb4f98d5SKalle Valo struct hfa384x_scan_result {
233eb4f98d5SKalle Valo __le16 chid;
234eb4f98d5SKalle Valo __le16 anl;
235eb4f98d5SKalle Valo __le16 sl;
236eb4f98d5SKalle Valo u8 bssid[ETH_ALEN];
237eb4f98d5SKalle Valo __le16 beacon_interval;
238eb4f98d5SKalle Valo __le16 capability;
239eb4f98d5SKalle Valo __le16 ssid_len;
240eb4f98d5SKalle Valo u8 ssid[32];
241eb4f98d5SKalle Valo u8 sup_rates[10];
242eb4f98d5SKalle Valo __le16 rate;
243eb4f98d5SKalle Valo } __packed;
244eb4f98d5SKalle Valo
245eb4f98d5SKalle Valo struct hfa384x_hostscan_result {
246eb4f98d5SKalle Valo __le16 chid;
247eb4f98d5SKalle Valo __le16 anl;
248eb4f98d5SKalle Valo __le16 sl;
249eb4f98d5SKalle Valo u8 bssid[ETH_ALEN];
250eb4f98d5SKalle Valo __le16 beacon_interval;
251eb4f98d5SKalle Valo __le16 capability;
252eb4f98d5SKalle Valo __le16 ssid_len;
253eb4f98d5SKalle Valo u8 ssid[32];
254eb4f98d5SKalle Valo u8 sup_rates[10];
255eb4f98d5SKalle Valo __le16 rate;
256eb4f98d5SKalle Valo __le16 atim;
257eb4f98d5SKalle Valo } __packed;
258eb4f98d5SKalle Valo
259eb4f98d5SKalle Valo struct comm_tallies_sums {
260eb4f98d5SKalle Valo unsigned int tx_unicast_frames;
261eb4f98d5SKalle Valo unsigned int tx_multicast_frames;
262eb4f98d5SKalle Valo unsigned int tx_fragments;
263eb4f98d5SKalle Valo unsigned int tx_unicast_octets;
264eb4f98d5SKalle Valo unsigned int tx_multicast_octets;
265eb4f98d5SKalle Valo unsigned int tx_deferred_transmissions;
266eb4f98d5SKalle Valo unsigned int tx_single_retry_frames;
267eb4f98d5SKalle Valo unsigned int tx_multiple_retry_frames;
268eb4f98d5SKalle Valo unsigned int tx_retry_limit_exceeded;
269eb4f98d5SKalle Valo unsigned int tx_discards;
270eb4f98d5SKalle Valo unsigned int rx_unicast_frames;
271eb4f98d5SKalle Valo unsigned int rx_multicast_frames;
272eb4f98d5SKalle Valo unsigned int rx_fragments;
273eb4f98d5SKalle Valo unsigned int rx_unicast_octets;
274eb4f98d5SKalle Valo unsigned int rx_multicast_octets;
275eb4f98d5SKalle Valo unsigned int rx_fcs_errors;
276eb4f98d5SKalle Valo unsigned int rx_discards_no_buffer;
277eb4f98d5SKalle Valo unsigned int tx_discards_wrong_sa;
278eb4f98d5SKalle Valo unsigned int rx_discards_wep_undecryptable;
279eb4f98d5SKalle Valo unsigned int rx_message_in_msg_fragments;
280eb4f98d5SKalle Valo unsigned int rx_message_in_bad_msg_fragments;
281eb4f98d5SKalle Valo };
282eb4f98d5SKalle Valo
283eb4f98d5SKalle Valo
284eb4f98d5SKalle Valo struct hfa384x_regs {
285eb4f98d5SKalle Valo u16 cmd;
286eb4f98d5SKalle Valo u16 evstat;
287eb4f98d5SKalle Valo u16 offset0;
288eb4f98d5SKalle Valo u16 offset1;
289eb4f98d5SKalle Valo u16 swsupport0;
290eb4f98d5SKalle Valo };
291eb4f98d5SKalle Valo
292eb4f98d5SKalle Valo
293eb4f98d5SKalle Valo #if defined(PRISM2_PCCARD) || defined(PRISM2_PLX)
294eb4f98d5SKalle Valo /* I/O ports for HFA384X Controller access */
295eb4f98d5SKalle Valo #define HFA384X_CMD_OFF 0x00
296eb4f98d5SKalle Valo #define HFA384X_PARAM0_OFF 0x02
297eb4f98d5SKalle Valo #define HFA384X_PARAM1_OFF 0x04
298eb4f98d5SKalle Valo #define HFA384X_PARAM2_OFF 0x06
299eb4f98d5SKalle Valo #define HFA384X_STATUS_OFF 0x08
300eb4f98d5SKalle Valo #define HFA384X_RESP0_OFF 0x0A
301eb4f98d5SKalle Valo #define HFA384X_RESP1_OFF 0x0C
302eb4f98d5SKalle Valo #define HFA384X_RESP2_OFF 0x0E
303eb4f98d5SKalle Valo #define HFA384X_INFOFID_OFF 0x10
304eb4f98d5SKalle Valo #define HFA384X_CONTROL_OFF 0x14
305eb4f98d5SKalle Valo #define HFA384X_SELECT0_OFF 0x18
306eb4f98d5SKalle Valo #define HFA384X_SELECT1_OFF 0x1A
307eb4f98d5SKalle Valo #define HFA384X_OFFSET0_OFF 0x1C
308eb4f98d5SKalle Valo #define HFA384X_OFFSET1_OFF 0x1E
309eb4f98d5SKalle Valo #define HFA384X_RXFID_OFF 0x20
310eb4f98d5SKalle Valo #define HFA384X_ALLOCFID_OFF 0x22
311eb4f98d5SKalle Valo #define HFA384X_TXCOMPLFID_OFF 0x24
312eb4f98d5SKalle Valo #define HFA384X_SWSUPPORT0_OFF 0x28
313eb4f98d5SKalle Valo #define HFA384X_SWSUPPORT1_OFF 0x2A
314eb4f98d5SKalle Valo #define HFA384X_SWSUPPORT2_OFF 0x2C
315eb4f98d5SKalle Valo #define HFA384X_EVSTAT_OFF 0x30
316eb4f98d5SKalle Valo #define HFA384X_INTEN_OFF 0x32
317eb4f98d5SKalle Valo #define HFA384X_EVACK_OFF 0x34
318eb4f98d5SKalle Valo #define HFA384X_DATA0_OFF 0x36
319eb4f98d5SKalle Valo #define HFA384X_DATA1_OFF 0x38
320eb4f98d5SKalle Valo #define HFA384X_AUXPAGE_OFF 0x3A
321eb4f98d5SKalle Valo #define HFA384X_AUXOFFSET_OFF 0x3C
322eb4f98d5SKalle Valo #define HFA384X_AUXDATA_OFF 0x3E
323eb4f98d5SKalle Valo #endif /* PRISM2_PCCARD || PRISM2_PLX */
324eb4f98d5SKalle Valo
325eb4f98d5SKalle Valo #ifdef PRISM2_PCI
326eb4f98d5SKalle Valo /* Memory addresses for ISL3874 controller access */
327eb4f98d5SKalle Valo #define HFA384X_CMD_OFF 0x00
328eb4f98d5SKalle Valo #define HFA384X_PARAM0_OFF 0x04
329eb4f98d5SKalle Valo #define HFA384X_PARAM1_OFF 0x08
330eb4f98d5SKalle Valo #define HFA384X_PARAM2_OFF 0x0C
331eb4f98d5SKalle Valo #define HFA384X_STATUS_OFF 0x10
332eb4f98d5SKalle Valo #define HFA384X_RESP0_OFF 0x14
333eb4f98d5SKalle Valo #define HFA384X_RESP1_OFF 0x18
334eb4f98d5SKalle Valo #define HFA384X_RESP2_OFF 0x1C
335eb4f98d5SKalle Valo #define HFA384X_INFOFID_OFF 0x20
336eb4f98d5SKalle Valo #define HFA384X_CONTROL_OFF 0x28
337eb4f98d5SKalle Valo #define HFA384X_SELECT0_OFF 0x30
338eb4f98d5SKalle Valo #define HFA384X_SELECT1_OFF 0x34
339eb4f98d5SKalle Valo #define HFA384X_OFFSET0_OFF 0x38
340eb4f98d5SKalle Valo #define HFA384X_OFFSET1_OFF 0x3C
341eb4f98d5SKalle Valo #define HFA384X_RXFID_OFF 0x40
342eb4f98d5SKalle Valo #define HFA384X_ALLOCFID_OFF 0x44
343eb4f98d5SKalle Valo #define HFA384X_TXCOMPLFID_OFF 0x48
344eb4f98d5SKalle Valo #define HFA384X_PCICOR_OFF 0x4C
345eb4f98d5SKalle Valo #define HFA384X_SWSUPPORT0_OFF 0x50
346eb4f98d5SKalle Valo #define HFA384X_SWSUPPORT1_OFF 0x54
347eb4f98d5SKalle Valo #define HFA384X_SWSUPPORT2_OFF 0x58
348eb4f98d5SKalle Valo #define HFA384X_PCIHCR_OFF 0x5C
349eb4f98d5SKalle Valo #define HFA384X_EVSTAT_OFF 0x60
350eb4f98d5SKalle Valo #define HFA384X_INTEN_OFF 0x64
351eb4f98d5SKalle Valo #define HFA384X_EVACK_OFF 0x68
352eb4f98d5SKalle Valo #define HFA384X_DATA0_OFF 0x6C
353eb4f98d5SKalle Valo #define HFA384X_DATA1_OFF 0x70
354eb4f98d5SKalle Valo #define HFA384X_AUXPAGE_OFF 0x74
355eb4f98d5SKalle Valo #define HFA384X_AUXOFFSET_OFF 0x78
356eb4f98d5SKalle Valo #define HFA384X_AUXDATA_OFF 0x7C
357eb4f98d5SKalle Valo #define HFA384X_PCI_M0_ADDRH_OFF 0x80
358eb4f98d5SKalle Valo #define HFA384X_PCI_M0_ADDRL_OFF 0x84
359eb4f98d5SKalle Valo #define HFA384X_PCI_M0_LEN_OFF 0x88
360eb4f98d5SKalle Valo #define HFA384X_PCI_M0_CTL_OFF 0x8C
361eb4f98d5SKalle Valo #define HFA384X_PCI_STATUS_OFF 0x98
362eb4f98d5SKalle Valo #define HFA384X_PCI_M1_ADDRH_OFF 0xA0
363eb4f98d5SKalle Valo #define HFA384X_PCI_M1_ADDRL_OFF 0xA4
364eb4f98d5SKalle Valo #define HFA384X_PCI_M1_LEN_OFF 0xA8
365eb4f98d5SKalle Valo #define HFA384X_PCI_M1_CTL_OFF 0xAC
366eb4f98d5SKalle Valo
367eb4f98d5SKalle Valo /* PCI bus master control bits (these are undocumented; based on guessing and
368eb4f98d5SKalle Valo * experimenting..) */
369eb4f98d5SKalle Valo #define HFA384X_PCI_CTL_FROM_BAP (BIT(5) | BIT(1) | BIT(0))
370eb4f98d5SKalle Valo #define HFA384X_PCI_CTL_TO_BAP (BIT(5) | BIT(0))
371eb4f98d5SKalle Valo
372eb4f98d5SKalle Valo #endif /* PRISM2_PCI */
373eb4f98d5SKalle Valo
374eb4f98d5SKalle Valo
375eb4f98d5SKalle Valo /* Command codes for CMD reg. */
376eb4f98d5SKalle Valo #define HFA384X_CMDCODE_INIT 0x00
377eb4f98d5SKalle Valo #define HFA384X_CMDCODE_ENABLE 0x01
378eb4f98d5SKalle Valo #define HFA384X_CMDCODE_DISABLE 0x02
379eb4f98d5SKalle Valo #define HFA384X_CMDCODE_ALLOC 0x0A
380eb4f98d5SKalle Valo #define HFA384X_CMDCODE_TRANSMIT 0x0B
381eb4f98d5SKalle Valo #define HFA384X_CMDCODE_INQUIRE 0x11
382eb4f98d5SKalle Valo #define HFA384X_CMDCODE_ACCESS 0x21
383eb4f98d5SKalle Valo #define HFA384X_CMDCODE_ACCESS_WRITE (0x21 | BIT(8))
384eb4f98d5SKalle Valo #define HFA384X_CMDCODE_DOWNLOAD 0x22
385eb4f98d5SKalle Valo #define HFA384X_CMDCODE_READMIF 0x30
386eb4f98d5SKalle Valo #define HFA384X_CMDCODE_WRITEMIF 0x31
387eb4f98d5SKalle Valo #define HFA384X_CMDCODE_TEST 0x38
388eb4f98d5SKalle Valo
389eb4f98d5SKalle Valo #define HFA384X_CMDCODE_MASK 0x3F
390eb4f98d5SKalle Valo
391eb4f98d5SKalle Valo /* Test mode operations */
392eb4f98d5SKalle Valo #define HFA384X_TEST_CHANGE_CHANNEL 0x08
393eb4f98d5SKalle Valo #define HFA384X_TEST_MONITOR 0x0B
394eb4f98d5SKalle Valo #define HFA384X_TEST_STOP 0x0F
395eb4f98d5SKalle Valo #define HFA384X_TEST_CFG_BITS 0x15
396eb4f98d5SKalle Valo #define HFA384X_TEST_CFG_BIT_ALC BIT(3)
397eb4f98d5SKalle Valo
398eb4f98d5SKalle Valo #define HFA384X_CMD_BUSY BIT(15)
399eb4f98d5SKalle Valo
400eb4f98d5SKalle Valo #define HFA384X_CMD_TX_RECLAIM BIT(8)
401eb4f98d5SKalle Valo
402eb4f98d5SKalle Valo #define HFA384X_OFFSET_ERR BIT(14)
403eb4f98d5SKalle Valo #define HFA384X_OFFSET_BUSY BIT(15)
404eb4f98d5SKalle Valo
405eb4f98d5SKalle Valo
406eb4f98d5SKalle Valo /* ProgMode for download command */
407eb4f98d5SKalle Valo #define HFA384X_PROGMODE_DISABLE 0
408eb4f98d5SKalle Valo #define HFA384X_PROGMODE_ENABLE_VOLATILE 1
409eb4f98d5SKalle Valo #define HFA384X_PROGMODE_ENABLE_NON_VOLATILE 2
410eb4f98d5SKalle Valo #define HFA384X_PROGMODE_PROGRAM_NON_VOLATILE 3
411eb4f98d5SKalle Valo
412eb4f98d5SKalle Valo #define HFA384X_AUX_MAGIC0 0xfe01
413eb4f98d5SKalle Valo #define HFA384X_AUX_MAGIC1 0xdc23
414eb4f98d5SKalle Valo #define HFA384X_AUX_MAGIC2 0xba45
415eb4f98d5SKalle Valo
416eb4f98d5SKalle Valo #define HFA384X_AUX_PORT_DISABLED 0
417eb4f98d5SKalle Valo #define HFA384X_AUX_PORT_DISABLE BIT(14)
418eb4f98d5SKalle Valo #define HFA384X_AUX_PORT_ENABLE BIT(15)
419eb4f98d5SKalle Valo #define HFA384X_AUX_PORT_ENABLED (BIT(14) | BIT(15))
420eb4f98d5SKalle Valo #define HFA384X_AUX_PORT_MASK (BIT(14) | BIT(15))
421eb4f98d5SKalle Valo
422eb4f98d5SKalle Valo #define PRISM2_PDA_SIZE 1024
423eb4f98d5SKalle Valo
424eb4f98d5SKalle Valo
425eb4f98d5SKalle Valo /* Events; EvStat, Interrupt mask (IntEn), and acknowledge bits (EvAck) */
426eb4f98d5SKalle Valo #define HFA384X_EV_TICK BIT(15)
427eb4f98d5SKalle Valo #define HFA384X_EV_WTERR BIT(14)
428eb4f98d5SKalle Valo #define HFA384X_EV_INFDROP BIT(13)
429eb4f98d5SKalle Valo #ifdef PRISM2_PCI
430eb4f98d5SKalle Valo #define HFA384X_EV_PCI_M1 BIT(9)
431eb4f98d5SKalle Valo #define HFA384X_EV_PCI_M0 BIT(8)
432eb4f98d5SKalle Valo #endif /* PRISM2_PCI */
433eb4f98d5SKalle Valo #define HFA384X_EV_INFO BIT(7)
434eb4f98d5SKalle Valo #define HFA384X_EV_DTIM BIT(5)
435eb4f98d5SKalle Valo #define HFA384X_EV_CMD BIT(4)
436eb4f98d5SKalle Valo #define HFA384X_EV_ALLOC BIT(3)
437eb4f98d5SKalle Valo #define HFA384X_EV_TXEXC BIT(2)
438eb4f98d5SKalle Valo #define HFA384X_EV_TX BIT(1)
439eb4f98d5SKalle Valo #define HFA384X_EV_RX BIT(0)
440eb4f98d5SKalle Valo
441eb4f98d5SKalle Valo
442eb4f98d5SKalle Valo /* HFA384X Information frames */
443eb4f98d5SKalle Valo #define HFA384X_INFO_HANDOVERADDR 0xF000 /* AP f/w ? */
444eb4f98d5SKalle Valo #define HFA384X_INFO_HANDOVERDEAUTHADDR 0xF001 /* AP f/w 1.3.7 */
445eb4f98d5SKalle Valo #define HFA384X_INFO_COMMTALLIES 0xF100
446eb4f98d5SKalle Valo #define HFA384X_INFO_SCANRESULTS 0xF101
447eb4f98d5SKalle Valo #define HFA384X_INFO_CHANNELINFORESULTS 0xF102 /* AP f/w only */
448eb4f98d5SKalle Valo #define HFA384X_INFO_HOSTSCANRESULTS 0xF103
449eb4f98d5SKalle Valo #define HFA384X_INFO_LINKSTATUS 0xF200
450eb4f98d5SKalle Valo #define HFA384X_INFO_ASSOCSTATUS 0xF201 /* ? */
451eb4f98d5SKalle Valo #define HFA384X_INFO_AUTHREQ 0xF202 /* ? */
452eb4f98d5SKalle Valo #define HFA384X_INFO_PSUSERCNT 0xF203 /* ? */
453eb4f98d5SKalle Valo #define HFA384X_INFO_KEYIDCHANGED 0xF204 /* ? */
454eb4f98d5SKalle Valo
455eb4f98d5SKalle Valo enum { HFA384X_LINKSTATUS_CONNECTED = 1,
456eb4f98d5SKalle Valo HFA384X_LINKSTATUS_DISCONNECTED = 2,
457eb4f98d5SKalle Valo HFA384X_LINKSTATUS_AP_CHANGE = 3,
458eb4f98d5SKalle Valo HFA384X_LINKSTATUS_AP_OUT_OF_RANGE = 4,
459eb4f98d5SKalle Valo HFA384X_LINKSTATUS_AP_IN_RANGE = 5,
460eb4f98d5SKalle Valo HFA384X_LINKSTATUS_ASSOC_FAILED = 6 };
461eb4f98d5SKalle Valo
462eb4f98d5SKalle Valo enum { HFA384X_PORTTYPE_BSS = 1, HFA384X_PORTTYPE_WDS = 2,
463eb4f98d5SKalle Valo HFA384X_PORTTYPE_PSEUDO_IBSS = 3, HFA384X_PORTTYPE_IBSS = 0,
464eb4f98d5SKalle Valo HFA384X_PORTTYPE_HOSTAP = 6 };
465eb4f98d5SKalle Valo
466eb4f98d5SKalle Valo #define HFA384X_RATES_1MBPS BIT(0)
467eb4f98d5SKalle Valo #define HFA384X_RATES_2MBPS BIT(1)
468eb4f98d5SKalle Valo #define HFA384X_RATES_5MBPS BIT(2)
469eb4f98d5SKalle Valo #define HFA384X_RATES_11MBPS BIT(3)
470eb4f98d5SKalle Valo
471eb4f98d5SKalle Valo #define HFA384X_ROAMING_FIRMWARE 1
472eb4f98d5SKalle Valo #define HFA384X_ROAMING_HOST 2
473eb4f98d5SKalle Valo #define HFA384X_ROAMING_DISABLED 3
474eb4f98d5SKalle Valo
475eb4f98d5SKalle Valo #define HFA384X_WEPFLAGS_PRIVACYINVOKED BIT(0)
476eb4f98d5SKalle Valo #define HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED BIT(1)
477eb4f98d5SKalle Valo #define HFA384X_WEPFLAGS_HOSTENCRYPT BIT(4)
478eb4f98d5SKalle Valo #define HFA384X_WEPFLAGS_HOSTDECRYPT BIT(7)
479eb4f98d5SKalle Valo
480eb4f98d5SKalle Valo #define HFA384X_RX_STATUS_MSGTYPE (BIT(15) | BIT(14) | BIT(13))
481eb4f98d5SKalle Valo #define HFA384X_RX_STATUS_PCF BIT(12)
482eb4f98d5SKalle Valo #define HFA384X_RX_STATUS_MACPORT (BIT(10) | BIT(9) | BIT(8))
483eb4f98d5SKalle Valo #define HFA384X_RX_STATUS_UNDECR BIT(1)
484eb4f98d5SKalle Valo #define HFA384X_RX_STATUS_FCSERR BIT(0)
485eb4f98d5SKalle Valo
486eb4f98d5SKalle Valo #define HFA384X_RX_STATUS_GET_MSGTYPE(s) \
487eb4f98d5SKalle Valo (((s) & HFA384X_RX_STATUS_MSGTYPE) >> 13)
488eb4f98d5SKalle Valo #define HFA384X_RX_STATUS_GET_MACPORT(s) \
489eb4f98d5SKalle Valo (((s) & HFA384X_RX_STATUS_MACPORT) >> 8)
490eb4f98d5SKalle Valo
491eb4f98d5SKalle Valo enum { HFA384X_RX_MSGTYPE_NORMAL = 0, HFA384X_RX_MSGTYPE_RFC1042 = 1,
492eb4f98d5SKalle Valo HFA384X_RX_MSGTYPE_BRIDGETUNNEL = 2, HFA384X_RX_MSGTYPE_MGMT = 4 };
493eb4f98d5SKalle Valo
494eb4f98d5SKalle Valo
495eb4f98d5SKalle Valo #define HFA384X_TX_CTRL_ALT_RTRY BIT(5)
496eb4f98d5SKalle Valo #define HFA384X_TX_CTRL_802_11 BIT(3)
497eb4f98d5SKalle Valo #define HFA384X_TX_CTRL_802_3 0
498eb4f98d5SKalle Valo #define HFA384X_TX_CTRL_TX_EX BIT(2)
499eb4f98d5SKalle Valo #define HFA384X_TX_CTRL_TX_OK BIT(1)
500eb4f98d5SKalle Valo
501eb4f98d5SKalle Valo #define HFA384X_TX_STATUS_RETRYERR BIT(0)
502eb4f98d5SKalle Valo #define HFA384X_TX_STATUS_AGEDERR BIT(1)
503eb4f98d5SKalle Valo #define HFA384X_TX_STATUS_DISCON BIT(2)
504eb4f98d5SKalle Valo #define HFA384X_TX_STATUS_FORMERR BIT(3)
505eb4f98d5SKalle Valo
506eb4f98d5SKalle Valo /* HFA3861/3863 (BBP) Control Registers */
507eb4f98d5SKalle Valo #define HFA386X_CR_TX_CONFIGURE 0x12 /* CR9 */
508eb4f98d5SKalle Valo #define HFA386X_CR_RX_CONFIGURE 0x14 /* CR10 */
509eb4f98d5SKalle Valo #define HFA386X_CR_A_D_TEST_MODES2 0x1A /* CR13 */
510eb4f98d5SKalle Valo #define HFA386X_CR_MANUAL_TX_POWER 0x3E /* CR31 */
511eb4f98d5SKalle Valo #define HFA386X_CR_MEASURED_TX_POWER 0x74 /* CR58 */
512eb4f98d5SKalle Valo
513eb4f98d5SKalle Valo
514eb4f98d5SKalle Valo #ifdef __KERNEL__
515eb4f98d5SKalle Valo
516eb4f98d5SKalle Valo #define PRISM2_TXFID_COUNT 8
517eb4f98d5SKalle Valo #define PRISM2_DATA_MAXLEN 2304
518eb4f98d5SKalle Valo #define PRISM2_TXFID_LEN (PRISM2_DATA_MAXLEN + sizeof(struct hfa384x_tx_frame))
519eb4f98d5SKalle Valo #define PRISM2_TXFID_EMPTY 0xffff
520eb4f98d5SKalle Valo #define PRISM2_TXFID_RESERVED 0xfffe
521eb4f98d5SKalle Valo #define PRISM2_DUMMY_FID 0xffff
522eb4f98d5SKalle Valo #define MAX_SSID_LEN 32
523eb4f98d5SKalle Valo #define MAX_NAME_LEN 32 /* this is assumed to be equal to MAX_SSID_LEN */
524eb4f98d5SKalle Valo
525eb4f98d5SKalle Valo #define PRISM2_DUMP_RX_HDR BIT(0)
526eb4f98d5SKalle Valo #define PRISM2_DUMP_TX_HDR BIT(1)
527eb4f98d5SKalle Valo #define PRISM2_DUMP_TXEXC_HDR BIT(2)
528eb4f98d5SKalle Valo
529eb4f98d5SKalle Valo struct hostap_tx_callback_info {
530eb4f98d5SKalle Valo u16 idx;
531eb4f98d5SKalle Valo void (*func)(struct sk_buff *, int ok, void *);
532eb4f98d5SKalle Valo void *data;
533eb4f98d5SKalle Valo struct hostap_tx_callback_info *next;
534eb4f98d5SKalle Valo };
535eb4f98d5SKalle Valo
536eb4f98d5SKalle Valo
537eb4f98d5SKalle Valo /* IEEE 802.11 requires that STA supports concurrent reception of at least
538eb4f98d5SKalle Valo * three fragmented frames. This define can be increased to support more
539eb4f98d5SKalle Valo * concurrent frames, but it should be noted that each entry can consume about
540eb4f98d5SKalle Valo * 2 kB of RAM and increasing cache size will slow down frame reassembly. */
541eb4f98d5SKalle Valo #define PRISM2_FRAG_CACHE_LEN 4
542eb4f98d5SKalle Valo
543eb4f98d5SKalle Valo struct prism2_frag_entry {
544eb4f98d5SKalle Valo unsigned long first_frag_time;
545eb4f98d5SKalle Valo unsigned int seq;
546eb4f98d5SKalle Valo unsigned int last_frag;
547eb4f98d5SKalle Valo struct sk_buff *skb;
548eb4f98d5SKalle Valo u8 src_addr[ETH_ALEN];
549eb4f98d5SKalle Valo u8 dst_addr[ETH_ALEN];
550eb4f98d5SKalle Valo };
551eb4f98d5SKalle Valo
552eb4f98d5SKalle Valo
553eb4f98d5SKalle Valo struct hostap_cmd_queue {
554eb4f98d5SKalle Valo struct list_head list;
555eb4f98d5SKalle Valo wait_queue_head_t compl;
556eb4f98d5SKalle Valo volatile enum { CMD_SLEEP, CMD_CALLBACK, CMD_COMPLETED } type;
557eb4f98d5SKalle Valo void (*callback)(struct net_device *dev, long context, u16 resp0,
558eb4f98d5SKalle Valo u16 res);
559eb4f98d5SKalle Valo long context;
560eb4f98d5SKalle Valo u16 cmd, param0, param1;
561eb4f98d5SKalle Valo u16 resp0, res;
562eb4f98d5SKalle Valo volatile int issued, issuing;
563eb4f98d5SKalle Valo
564552aa585SElena Reshetova refcount_t usecnt;
565eb4f98d5SKalle Valo int del_req;
566eb4f98d5SKalle Valo };
567eb4f98d5SKalle Valo
568eb4f98d5SKalle Valo /* options for hw_shutdown */
569eb4f98d5SKalle Valo #define HOSTAP_HW_NO_DISABLE BIT(0)
570eb4f98d5SKalle Valo #define HOSTAP_HW_ENABLE_CMDCOMPL BIT(1)
571eb4f98d5SKalle Valo
572eb4f98d5SKalle Valo typedef struct local_info local_info_t;
573eb4f98d5SKalle Valo
574eb4f98d5SKalle Valo struct prism2_helper_functions {
575eb4f98d5SKalle Valo /* these functions are defined in hardware model specific files
576eb4f98d5SKalle Valo * (hostap_{cs,plx,pci}.c */
577eb4f98d5SKalle Valo int (*card_present)(local_info_t *local);
578eb4f98d5SKalle Valo void (*cor_sreset)(local_info_t *local);
579eb4f98d5SKalle Valo void (*genesis_reset)(local_info_t *local, int hcr);
580eb4f98d5SKalle Valo
581eb4f98d5SKalle Valo /* the following functions are from hostap_hw.c, but they may have some
582eb4f98d5SKalle Valo * hardware model specific code */
583eb4f98d5SKalle Valo
584eb4f98d5SKalle Valo /* FIX: low-level commands like cmd might disappear at some point to
585eb4f98d5SKalle Valo * make it easier to change them if needed (e.g., cmd would be replaced
586eb4f98d5SKalle Valo * with write_mif/read_mif/testcmd/inquire); at least get_rid and
587eb4f98d5SKalle Valo * set_rid might move to hostap_{cs,plx,pci}.c */
588eb4f98d5SKalle Valo int (*cmd)(struct net_device *dev, u16 cmd, u16 param0, u16 *param1,
589eb4f98d5SKalle Valo u16 *resp0);
590eb4f98d5SKalle Valo void (*read_regs)(struct net_device *dev, struct hfa384x_regs *regs);
591eb4f98d5SKalle Valo int (*get_rid)(struct net_device *dev, u16 rid, void *buf, int len,
592eb4f98d5SKalle Valo int exact_len);
593eb4f98d5SKalle Valo int (*set_rid)(struct net_device *dev, u16 rid, void *buf, int len);
594eb4f98d5SKalle Valo int (*hw_enable)(struct net_device *dev, int initial);
595eb4f98d5SKalle Valo int (*hw_config)(struct net_device *dev, int initial);
596eb4f98d5SKalle Valo void (*hw_reset)(struct net_device *dev);
597eb4f98d5SKalle Valo void (*hw_shutdown)(struct net_device *dev, int no_disable);
598eb4f98d5SKalle Valo int (*reset_port)(struct net_device *dev);
599eb4f98d5SKalle Valo void (*schedule_reset)(local_info_t *local);
600eb4f98d5SKalle Valo int (*download)(local_info_t *local,
601eb4f98d5SKalle Valo struct prism2_download_param *param);
602eb4f98d5SKalle Valo int (*tx)(struct sk_buff *skb, struct net_device *dev);
603eb4f98d5SKalle Valo int (*set_tim)(struct net_device *dev, int aid, int set);
60497a32539SAlexey Dobriyan const struct proc_ops *read_aux_proc_ops;
605eb4f98d5SKalle Valo
606eb4f98d5SKalle Valo int need_tx_headroom; /* number of bytes of headroom needed before
607eb4f98d5SKalle Valo * IEEE 802.11 header */
608eb4f98d5SKalle Valo enum { HOSTAP_HW_PCCARD, HOSTAP_HW_PLX, HOSTAP_HW_PCI } hw_type;
609eb4f98d5SKalle Valo };
610eb4f98d5SKalle Valo
611eb4f98d5SKalle Valo
612eb4f98d5SKalle Valo struct prism2_download_data {
613eb4f98d5SKalle Valo u32 dl_cmd;
614eb4f98d5SKalle Valo u32 start_addr;
615eb4f98d5SKalle Valo u32 num_areas;
616eb4f98d5SKalle Valo struct prism2_download_data_area {
617eb4f98d5SKalle Valo u32 addr; /* wlan card address */
618eb4f98d5SKalle Valo u32 len;
619eb4f98d5SKalle Valo u8 *data; /* allocated data */
620bc1d50a1SGustavo A. R. Silva } data[];
621eb4f98d5SKalle Valo };
622eb4f98d5SKalle Valo
623eb4f98d5SKalle Valo
624eb4f98d5SKalle Valo #define HOSTAP_MAX_BSS_COUNT 64
625eb4f98d5SKalle Valo #define MAX_WPA_IE_LEN 64
626eb4f98d5SKalle Valo
627eb4f98d5SKalle Valo struct hostap_bss_info {
628eb4f98d5SKalle Valo struct list_head list;
629eb4f98d5SKalle Valo unsigned long last_update;
630eb4f98d5SKalle Valo unsigned int count;
631eb4f98d5SKalle Valo u8 bssid[ETH_ALEN];
632eb4f98d5SKalle Valo u16 capab_info;
633eb4f98d5SKalle Valo u8 ssid[32];
634eb4f98d5SKalle Valo size_t ssid_len;
635eb4f98d5SKalle Valo u8 wpa_ie[MAX_WPA_IE_LEN];
636eb4f98d5SKalle Valo size_t wpa_ie_len;
637eb4f98d5SKalle Valo u8 rsn_ie[MAX_WPA_IE_LEN];
638eb4f98d5SKalle Valo size_t rsn_ie_len;
639eb4f98d5SKalle Valo int chan;
640eb4f98d5SKalle Valo int included;
641eb4f98d5SKalle Valo };
642eb4f98d5SKalle Valo
643eb4f98d5SKalle Valo
644eb4f98d5SKalle Valo /* Per radio private Host AP data - shared by all net devices interfaces used
645eb4f98d5SKalle Valo * by each radio (wlan#, wlan#ap, wlan#sta, WDS).
646eb4f98d5SKalle Valo * ((struct hostap_interface *) netdev_priv(dev))->local points to this
647eb4f98d5SKalle Valo * structure. */
648eb4f98d5SKalle Valo struct local_info {
649eb4f98d5SKalle Valo struct module *hw_module;
650eb4f98d5SKalle Valo int card_idx;
651eb4f98d5SKalle Valo int dev_enabled;
652eb4f98d5SKalle Valo int master_dev_auto_open; /* was master device opened automatically */
653eb4f98d5SKalle Valo int num_dev_open; /* number of open devices */
654eb4f98d5SKalle Valo struct net_device *dev; /* master radio device */
655eb4f98d5SKalle Valo struct net_device *ddev; /* main data device */
656eb4f98d5SKalle Valo struct list_head hostap_interfaces; /* Host AP interface list (contains
657eb4f98d5SKalle Valo * struct hostap_interface entries)
658eb4f98d5SKalle Valo */
659eb4f98d5SKalle Valo rwlock_t iface_lock; /* hostap_interfaces read lock; use write lock
660eb4f98d5SKalle Valo * when removing entries from the list.
661eb4f98d5SKalle Valo * TX and RX paths can use read lock. */
662eb4f98d5SKalle Valo spinlock_t cmdlock, baplock, lock, irq_init_lock;
663eb4f98d5SKalle Valo struct mutex rid_bap_mtx;
664eb4f98d5SKalle Valo u16 infofid; /* MAC buffer id for info frame */
665eb4f98d5SKalle Valo /* txfid, intransmitfid, next_txtid, and next_alloc are protected by
666eb4f98d5SKalle Valo * txfidlock */
667eb4f98d5SKalle Valo spinlock_t txfidlock;
668eb4f98d5SKalle Valo int txfid_len; /* length of allocated TX buffers */
669eb4f98d5SKalle Valo u16 txfid[PRISM2_TXFID_COUNT]; /* buffer IDs for TX frames */
670eb4f98d5SKalle Valo /* buffer IDs for intransmit frames or PRISM2_TXFID_EMPTY if
671eb4f98d5SKalle Valo * corresponding txfid is free for next TX frame */
672eb4f98d5SKalle Valo u16 intransmitfid[PRISM2_TXFID_COUNT];
673eb4f98d5SKalle Valo int next_txfid; /* index to the next txfid to be checked for
674eb4f98d5SKalle Valo * availability */
675eb4f98d5SKalle Valo int next_alloc; /* index to the next intransmitfid to be checked for
676eb4f98d5SKalle Valo * allocation events */
677eb4f98d5SKalle Valo
678eb4f98d5SKalle Valo /* bitfield for atomic bitops */
679eb4f98d5SKalle Valo #define HOSTAP_BITS_TRANSMIT 0
680eb4f98d5SKalle Valo #define HOSTAP_BITS_BAP_TASKLET 1
681eb4f98d5SKalle Valo #define HOSTAP_BITS_BAP_TASKLET2 2
682eb4f98d5SKalle Valo unsigned long bits;
683eb4f98d5SKalle Valo
684eb4f98d5SKalle Valo struct ap_data *ap;
685eb4f98d5SKalle Valo
686eb4f98d5SKalle Valo char essid[MAX_SSID_LEN + 1];
687eb4f98d5SKalle Valo char name[MAX_NAME_LEN + 1];
688eb4f98d5SKalle Valo int name_set;
689eb4f98d5SKalle Valo u16 channel_mask; /* mask of allowed channels */
690eb4f98d5SKalle Valo u16 scan_channel_mask; /* mask of channels to be scanned */
691eb4f98d5SKalle Valo struct comm_tallies_sums comm_tallies;
692eb4f98d5SKalle Valo struct proc_dir_entry *proc;
693eb4f98d5SKalle Valo int iw_mode; /* operating mode (IW_MODE_*) */
694eb4f98d5SKalle Valo int pseudo_adhoc; /* 0: IW_MODE_ADHOC is real 802.11 compliant IBSS
695eb4f98d5SKalle Valo * 1: IW_MODE_ADHOC is "pseudo IBSS" */
696eb4f98d5SKalle Valo char bssid[ETH_ALEN];
697eb4f98d5SKalle Valo int channel;
698eb4f98d5SKalle Valo int beacon_int;
699eb4f98d5SKalle Valo int dtim_period;
700eb4f98d5SKalle Valo int mtu;
701eb4f98d5SKalle Valo int frame_dump; /* dump RX/TX frame headers, PRISM2_DUMP_ flags */
702eb4f98d5SKalle Valo int fw_tx_rate_control;
703eb4f98d5SKalle Valo u16 tx_rate_control;
704eb4f98d5SKalle Valo u16 basic_rates;
705eb4f98d5SKalle Valo int hw_resetting;
706eb4f98d5SKalle Valo int hw_ready;
707eb4f98d5SKalle Valo int hw_reset_tries; /* how many times reset has been tried */
708eb4f98d5SKalle Valo int hw_downloading;
709eb4f98d5SKalle Valo int shutdown;
710eb4f98d5SKalle Valo int pri_only;
711eb4f98d5SKalle Valo int no_pri; /* no PRI f/w present */
712eb4f98d5SKalle Valo int sram_type; /* 8 = x8 SRAM, 16 = x16 SRAM, -1 = unknown */
713eb4f98d5SKalle Valo
714eb4f98d5SKalle Valo enum {
715eb4f98d5SKalle Valo PRISM2_TXPOWER_AUTO = 0, PRISM2_TXPOWER_OFF,
716eb4f98d5SKalle Valo PRISM2_TXPOWER_FIXED, PRISM2_TXPOWER_UNKNOWN
717eb4f98d5SKalle Valo } txpower_type;
718eb4f98d5SKalle Valo int txpower; /* if txpower_type == PRISM2_TXPOWER_FIXED */
719eb4f98d5SKalle Valo
720eb4f98d5SKalle Valo /* command queue for hfa384x_cmd(); protected with cmdlock */
721eb4f98d5SKalle Valo struct list_head cmd_queue;
722eb4f98d5SKalle Valo /* max_len for cmd_queue; in addition, cmd_callback can use two
723eb4f98d5SKalle Valo * additional entries to prevent sleeping commands from stopping
724eb4f98d5SKalle Valo * transmits */
725eb4f98d5SKalle Valo #define HOSTAP_CMD_QUEUE_MAX_LEN 16
726eb4f98d5SKalle Valo int cmd_queue_len; /* number of entries in cmd_queue */
727eb4f98d5SKalle Valo
728eb4f98d5SKalle Valo /* if card timeout is detected in interrupt context, reset_queue is
729eb4f98d5SKalle Valo * used to schedule card reseting to be done in user context */
730eb4f98d5SKalle Valo struct work_struct reset_queue;
731eb4f98d5SKalle Valo
732eb4f98d5SKalle Valo /* For scheduling a change of the promiscuous mode RID */
733eb4f98d5SKalle Valo int is_promisc;
734eb4f98d5SKalle Valo struct work_struct set_multicast_list_queue;
735eb4f98d5SKalle Valo
736eb4f98d5SKalle Valo struct work_struct set_tim_queue;
737eb4f98d5SKalle Valo struct list_head set_tim_list;
738eb4f98d5SKalle Valo spinlock_t set_tim_lock;
739eb4f98d5SKalle Valo
740eb4f98d5SKalle Valo int wds_max_connections;
741eb4f98d5SKalle Valo int wds_connections;
742eb4f98d5SKalle Valo #define HOSTAP_WDS_BROADCAST_RA BIT(0)
743eb4f98d5SKalle Valo #define HOSTAP_WDS_AP_CLIENT BIT(1)
744eb4f98d5SKalle Valo #define HOSTAP_WDS_STANDARD_FRAME BIT(2)
745eb4f98d5SKalle Valo u32 wds_type;
746eb4f98d5SKalle Valo u16 tx_control; /* flags to be used in TX description */
747eb4f98d5SKalle Valo int manual_retry_count; /* -1 = use f/w default; otherwise retry count
748eb4f98d5SKalle Valo * to be used with all frames */
749eb4f98d5SKalle Valo
750eb4f98d5SKalle Valo struct iw_statistics wstats;
751eb4f98d5SKalle Valo unsigned long scan_timestamp; /* Time started to scan */
752eb4f98d5SKalle Valo enum {
753eb4f98d5SKalle Valo PRISM2_MONITOR_80211 = 0, PRISM2_MONITOR_PRISM = 1,
754eb4f98d5SKalle Valo PRISM2_MONITOR_CAPHDR = 2, PRISM2_MONITOR_RADIOTAP = 3
755eb4f98d5SKalle Valo } monitor_type;
756eb4f98d5SKalle Valo int monitor_allow_fcserr;
757eb4f98d5SKalle Valo
758eb4f98d5SKalle Valo int hostapd; /* whether user space daemon, hostapd, is used for AP
759eb4f98d5SKalle Valo * management */
760eb4f98d5SKalle Valo int hostapd_sta; /* whether hostapd is used with an extra STA interface
761eb4f98d5SKalle Valo */
762eb4f98d5SKalle Valo struct net_device *apdev;
763eb4f98d5SKalle Valo struct net_device_stats apdevstats;
764eb4f98d5SKalle Valo
765eb4f98d5SKalle Valo char assoc_ap_addr[ETH_ALEN];
766eb4f98d5SKalle Valo struct net_device *stadev;
767eb4f98d5SKalle Valo struct net_device_stats stadevstats;
768eb4f98d5SKalle Valo
769eb4f98d5SKalle Valo #define WEP_KEYS 4
770eb4f98d5SKalle Valo #define WEP_KEY_LEN 13
771eb4f98d5SKalle Valo struct lib80211_crypt_info crypt_info;
772eb4f98d5SKalle Valo
773eb4f98d5SKalle Valo int open_wep; /* allow unencrypted frames */
774eb4f98d5SKalle Valo int host_encrypt;
775eb4f98d5SKalle Valo int host_decrypt;
776eb4f98d5SKalle Valo int privacy_invoked; /* force privacy invoked flag even if no keys are
777eb4f98d5SKalle Valo * configured */
778eb4f98d5SKalle Valo int fw_encrypt_ok; /* whether firmware-based WEP encrypt is working
779eb4f98d5SKalle Valo * in Host AP mode (STA f/w 1.4.9 or newer) */
780eb4f98d5SKalle Valo int bcrx_sta_key; /* use individual keys to override default keys even
781eb4f98d5SKalle Valo * with RX of broad/multicast frames */
782eb4f98d5SKalle Valo
783eb4f98d5SKalle Valo struct prism2_frag_entry frag_cache[PRISM2_FRAG_CACHE_LEN];
784eb4f98d5SKalle Valo unsigned int frag_next_idx;
785eb4f98d5SKalle Valo
786eb4f98d5SKalle Valo int ieee_802_1x; /* is IEEE 802.1X used */
787eb4f98d5SKalle Valo
788eb4f98d5SKalle Valo int antsel_tx, antsel_rx;
789eb4f98d5SKalle Valo int rts_threshold; /* dot11RTSThreshold */
790eb4f98d5SKalle Valo int fragm_threshold; /* dot11FragmentationThreshold */
791eb4f98d5SKalle Valo int auth_algs; /* PRISM2_AUTH_ flags */
792eb4f98d5SKalle Valo
793eb4f98d5SKalle Valo int enh_sec; /* cnfEnhSecurity options (broadcast SSID hide/ignore) */
794eb4f98d5SKalle Valo int tallies32; /* 32-bit tallies in use */
795eb4f98d5SKalle Valo
796eb4f98d5SKalle Valo struct prism2_helper_functions *func;
797eb4f98d5SKalle Valo
798eb4f98d5SKalle Valo u8 *pda;
799eb4f98d5SKalle Valo int fw_ap;
800eb4f98d5SKalle Valo #define PRISM2_FW_VER(major, minor, variant) \
801eb4f98d5SKalle Valo (((major) << 16) | ((minor) << 8) | variant)
802eb4f98d5SKalle Valo u32 sta_fw_ver;
803eb4f98d5SKalle Valo
804eb4f98d5SKalle Valo /* Tasklets for handling hardware IRQ related operations outside hw IRQ
805eb4f98d5SKalle Valo * handler */
806eb4f98d5SKalle Valo struct tasklet_struct bap_tasklet;
807eb4f98d5SKalle Valo
808eb4f98d5SKalle Valo struct tasklet_struct info_tasklet;
809eb4f98d5SKalle Valo struct sk_buff_head info_list; /* info frames as skb's for
810eb4f98d5SKalle Valo * info_tasklet */
811eb4f98d5SKalle Valo
812eb4f98d5SKalle Valo struct hostap_tx_callback_info *tx_callback; /* registered TX callbacks
813eb4f98d5SKalle Valo */
814eb4f98d5SKalle Valo
815eb4f98d5SKalle Valo struct tasklet_struct rx_tasklet;
816eb4f98d5SKalle Valo struct sk_buff_head rx_list;
817eb4f98d5SKalle Valo
818eb4f98d5SKalle Valo struct tasklet_struct sta_tx_exc_tasklet;
819eb4f98d5SKalle Valo struct sk_buff_head sta_tx_exc_list;
820eb4f98d5SKalle Valo
821eb4f98d5SKalle Valo int host_roaming;
822eb4f98d5SKalle Valo unsigned long last_join_time; /* time of last JoinRequest */
823eb4f98d5SKalle Valo struct hfa384x_hostscan_result *last_scan_results;
824eb4f98d5SKalle Valo int last_scan_results_count;
825eb4f98d5SKalle Valo enum { PRISM2_SCAN, PRISM2_HOSTSCAN } last_scan_type;
826eb4f98d5SKalle Valo struct work_struct info_queue;
827eb4f98d5SKalle Valo unsigned long pending_info; /* bit field of pending info_queue items */
828eb4f98d5SKalle Valo #define PRISM2_INFO_PENDING_LINKSTATUS 0
829eb4f98d5SKalle Valo #define PRISM2_INFO_PENDING_SCANRESULTS 1
830eb4f98d5SKalle Valo int prev_link_status; /* previous received LinkStatus info */
831eb4f98d5SKalle Valo int prev_linkstatus_connected;
832eb4f98d5SKalle Valo u8 preferred_ap[ETH_ALEN]; /* use this AP if possible */
833eb4f98d5SKalle Valo
834eb4f98d5SKalle Valo #ifdef PRISM2_CALLBACK
835eb4f98d5SKalle Valo void *callback_data; /* Can be used in callbacks; e.g., allocate
836eb4f98d5SKalle Valo * on enable event and free on disable event.
837eb4f98d5SKalle Valo * Host AP driver code does not touch this. */
838eb4f98d5SKalle Valo #endif /* PRISM2_CALLBACK */
839eb4f98d5SKalle Valo
840eb4f98d5SKalle Valo wait_queue_head_t hostscan_wq;
841eb4f98d5SKalle Valo
842eb4f98d5SKalle Valo /* Passive scan in Host AP mode */
843eb4f98d5SKalle Valo struct timer_list passive_scan_timer;
844eb4f98d5SKalle Valo int passive_scan_interval; /* in seconds, 0 = disabled */
845eb4f98d5SKalle Valo int passive_scan_channel;
846eb4f98d5SKalle Valo enum { PASSIVE_SCAN_WAIT, PASSIVE_SCAN_LISTEN } passive_scan_state;
847eb4f98d5SKalle Valo
848eb4f98d5SKalle Valo struct timer_list tick_timer;
849eb4f98d5SKalle Valo unsigned long last_tick_timer;
850eb4f98d5SKalle Valo unsigned int sw_tick_stuck;
851eb4f98d5SKalle Valo
852eb4f98d5SKalle Valo /* commsQuality / dBmCommsQuality data from periodic polling; only
853eb4f98d5SKalle Valo * valid for Managed and Ad-hoc modes */
854eb4f98d5SKalle Valo unsigned long last_comms_qual_update;
855eb4f98d5SKalle Valo int comms_qual; /* in some odd unit.. */
856eb4f98d5SKalle Valo int avg_signal; /* in dB (note: negative) */
857eb4f98d5SKalle Valo int avg_noise; /* in dB (note: negative) */
858eb4f98d5SKalle Valo struct work_struct comms_qual_update;
859eb4f98d5SKalle Valo
860eb4f98d5SKalle Valo /* RSSI to dBm adjustment (for RX descriptor fields) */
861eb4f98d5SKalle Valo int rssi_to_dBm; /* subtract from RSSI to get approximate dBm value */
862eb4f98d5SKalle Valo
863eb4f98d5SKalle Valo /* BSS list / protected by local->lock */
864eb4f98d5SKalle Valo struct list_head bss_list;
865eb4f98d5SKalle Valo int num_bss_info;
866eb4f98d5SKalle Valo int wpa; /* WPA support enabled */
867eb4f98d5SKalle Valo int tkip_countermeasures;
868eb4f98d5SKalle Valo int drop_unencrypted;
869eb4f98d5SKalle Valo /* Generic IEEE 802.11 info element to be added to
870eb4f98d5SKalle Valo * ProbeResp/Beacon/(Re)AssocReq */
871eb4f98d5SKalle Valo u8 *generic_elem;
872eb4f98d5SKalle Valo size_t generic_elem_len;
873eb4f98d5SKalle Valo
874eb4f98d5SKalle Valo #ifdef PRISM2_DOWNLOAD_SUPPORT
875eb4f98d5SKalle Valo /* Persistent volatile download data */
876eb4f98d5SKalle Valo struct prism2_download_data *dl_pri;
877eb4f98d5SKalle Valo struct prism2_download_data *dl_sec;
878eb4f98d5SKalle Valo #endif /* PRISM2_DOWNLOAD_SUPPORT */
879eb4f98d5SKalle Valo
880eb4f98d5SKalle Valo #ifdef PRISM2_IO_DEBUG
881eb4f98d5SKalle Valo #define PRISM2_IO_DEBUG_SIZE 10000
882eb4f98d5SKalle Valo u32 io_debug[PRISM2_IO_DEBUG_SIZE];
883eb4f98d5SKalle Valo int io_debug_head;
884eb4f98d5SKalle Valo int io_debug_enabled;
885eb4f98d5SKalle Valo #endif /* PRISM2_IO_DEBUG */
886eb4f98d5SKalle Valo
887eb4f98d5SKalle Valo /* Pointer to hardware model specific (cs,pci,plx) private data. */
888eb4f98d5SKalle Valo void *hw_priv;
889eb4f98d5SKalle Valo };
890eb4f98d5SKalle Valo
891eb4f98d5SKalle Valo
892eb4f98d5SKalle Valo /* Per interface private Host AP data
893eb4f98d5SKalle Valo * Allocated for each net device that Host AP uses (wlan#, wlan#ap, wlan#sta,
894eb4f98d5SKalle Valo * WDS) and netdev_priv(dev) points to this structure. */
895eb4f98d5SKalle Valo struct hostap_interface {
896eb4f98d5SKalle Valo struct list_head list; /* list entry in Host AP interface list */
897eb4f98d5SKalle Valo struct net_device *dev; /* pointer to this device */
898eb4f98d5SKalle Valo struct local_info *local; /* pointer to shared private data */
899eb4f98d5SKalle Valo struct net_device_stats stats;
900eb4f98d5SKalle Valo struct iw_spy_data spy_data; /* iwspy support */
901eb4f98d5SKalle Valo struct iw_public_data wireless_data;
902eb4f98d5SKalle Valo
903eb4f98d5SKalle Valo enum {
904eb4f98d5SKalle Valo HOSTAP_INTERFACE_MASTER,
905eb4f98d5SKalle Valo HOSTAP_INTERFACE_MAIN,
906eb4f98d5SKalle Valo HOSTAP_INTERFACE_AP,
907eb4f98d5SKalle Valo HOSTAP_INTERFACE_STA,
908eb4f98d5SKalle Valo HOSTAP_INTERFACE_WDS,
909eb4f98d5SKalle Valo } type;
910eb4f98d5SKalle Valo
911eb4f98d5SKalle Valo union {
912eb4f98d5SKalle Valo struct hostap_interface_wds {
913eb4f98d5SKalle Valo u8 remote_addr[ETH_ALEN];
914eb4f98d5SKalle Valo } wds;
915eb4f98d5SKalle Valo } u;
916eb4f98d5SKalle Valo };
917eb4f98d5SKalle Valo
918eb4f98d5SKalle Valo
919eb4f98d5SKalle Valo #define HOSTAP_SKB_TX_DATA_MAGIC 0xf08a36a2
920eb4f98d5SKalle Valo
921eb4f98d5SKalle Valo /*
922eb4f98d5SKalle Valo * TX meta data - stored in skb->cb buffer, so this must not be increased over
923eb4f98d5SKalle Valo * the 48-byte limit.
924eb4f98d5SKalle Valo * THE PADDING THIS STARTS WITH IS A HORRIBLE HACK THAT SHOULD NOT LIVE
925eb4f98d5SKalle Valo * TO SEE THE DAY.
926eb4f98d5SKalle Valo */
927eb4f98d5SKalle Valo struct hostap_skb_tx_data {
928eb4f98d5SKalle Valo unsigned int __padding_for_default_qdiscs;
929eb4f98d5SKalle Valo u32 magic; /* HOSTAP_SKB_TX_DATA_MAGIC */
930eb4f98d5SKalle Valo u8 rate; /* transmit rate */
931eb4f98d5SKalle Valo #define HOSTAP_TX_FLAGS_WDS BIT(0)
932eb4f98d5SKalle Valo #define HOSTAP_TX_FLAGS_BUFFERED_FRAME BIT(1)
933eb4f98d5SKalle Valo #define HOSTAP_TX_FLAGS_ADD_MOREDATA BIT(2)
934eb4f98d5SKalle Valo u8 flags; /* HOSTAP_TX_FLAGS_* */
935eb4f98d5SKalle Valo u16 tx_cb_idx;
936eb4f98d5SKalle Valo struct hostap_interface *iface;
937eb4f98d5SKalle Valo unsigned long jiffies; /* queueing timestamp */
938eb4f98d5SKalle Valo unsigned short ethertype;
939eb4f98d5SKalle Valo };
940eb4f98d5SKalle Valo
941eb4f98d5SKalle Valo
942eb4f98d5SKalle Valo #ifndef PRISM2_NO_DEBUG
943eb4f98d5SKalle Valo
944eb4f98d5SKalle Valo #define DEBUG_FID BIT(0)
945eb4f98d5SKalle Valo #define DEBUG_PS BIT(1)
946eb4f98d5SKalle Valo #define DEBUG_FLOW BIT(2)
947eb4f98d5SKalle Valo #define DEBUG_AP BIT(3)
948eb4f98d5SKalle Valo #define DEBUG_HW BIT(4)
949eb4f98d5SKalle Valo #define DEBUG_EXTRA BIT(5)
950eb4f98d5SKalle Valo #define DEBUG_EXTRA2 BIT(6)
951eb4f98d5SKalle Valo #define DEBUG_PS2 BIT(7)
952eb4f98d5SKalle Valo #define DEBUG_MASK (DEBUG_PS | DEBUG_AP | DEBUG_HW | DEBUG_EXTRA)
953eb4f98d5SKalle Valo #define PDEBUG(n, args...) \
954eb4f98d5SKalle Valo do { if ((n) & DEBUG_MASK) printk(KERN_DEBUG args); } while (0)
955eb4f98d5SKalle Valo #define PDEBUG2(n, args...) \
956eb4f98d5SKalle Valo do { if ((n) & DEBUG_MASK) printk(args); } while (0)
957eb4f98d5SKalle Valo
958eb4f98d5SKalle Valo #else /* PRISM2_NO_DEBUG */
959eb4f98d5SKalle Valo
960eb4f98d5SKalle Valo #define PDEBUG(n, args...)
961eb4f98d5SKalle Valo #define PDEBUG2(n, args...)
962eb4f98d5SKalle Valo
963eb4f98d5SKalle Valo #endif /* PRISM2_NO_DEBUG */
964eb4f98d5SKalle Valo
965eb4f98d5SKalle Valo enum { BAP0 = 0, BAP1 = 1 };
966eb4f98d5SKalle Valo
967eb4f98d5SKalle Valo #define PRISM2_IO_DEBUG_CMD_INB 0
968eb4f98d5SKalle Valo #define PRISM2_IO_DEBUG_CMD_INW 1
969eb4f98d5SKalle Valo #define PRISM2_IO_DEBUG_CMD_INSW 2
970eb4f98d5SKalle Valo #define PRISM2_IO_DEBUG_CMD_OUTB 3
971eb4f98d5SKalle Valo #define PRISM2_IO_DEBUG_CMD_OUTW 4
972eb4f98d5SKalle Valo #define PRISM2_IO_DEBUG_CMD_OUTSW 5
973eb4f98d5SKalle Valo #define PRISM2_IO_DEBUG_CMD_ERROR 6
974eb4f98d5SKalle Valo #define PRISM2_IO_DEBUG_CMD_INTERRUPT 7
975eb4f98d5SKalle Valo
976eb4f98d5SKalle Valo #ifdef PRISM2_IO_DEBUG
977eb4f98d5SKalle Valo
978eb4f98d5SKalle Valo #define PRISM2_IO_DEBUG_ENTRY(cmd, reg, value) \
979eb4f98d5SKalle Valo (((cmd) << 24) | ((reg) << 16) | value)
980eb4f98d5SKalle Valo
prism2_io_debug_add(struct net_device * dev,int cmd,int reg,int value)981eb4f98d5SKalle Valo static inline void prism2_io_debug_add(struct net_device *dev, int cmd,
982eb4f98d5SKalle Valo int reg, int value)
983eb4f98d5SKalle Valo {
984eb4f98d5SKalle Valo struct hostap_interface *iface = netdev_priv(dev);
985eb4f98d5SKalle Valo local_info_t *local = iface->local;
986eb4f98d5SKalle Valo
987eb4f98d5SKalle Valo if (!local->io_debug_enabled)
988eb4f98d5SKalle Valo return;
989eb4f98d5SKalle Valo
990eb4f98d5SKalle Valo local->io_debug[local->io_debug_head] = jiffies & 0xffffffff;
991eb4f98d5SKalle Valo if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
992eb4f98d5SKalle Valo local->io_debug_head = 0;
993eb4f98d5SKalle Valo local->io_debug[local->io_debug_head] =
994eb4f98d5SKalle Valo PRISM2_IO_DEBUG_ENTRY(cmd, reg, value);
995eb4f98d5SKalle Valo if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE)
996eb4f98d5SKalle Valo local->io_debug_head = 0;
997eb4f98d5SKalle Valo }
998eb4f98d5SKalle Valo
999eb4f98d5SKalle Valo
prism2_io_debug_error(struct net_device * dev,int err)1000eb4f98d5SKalle Valo static inline void prism2_io_debug_error(struct net_device *dev, int err)
1001eb4f98d5SKalle Valo {
1002eb4f98d5SKalle Valo struct hostap_interface *iface = netdev_priv(dev);
1003eb4f98d5SKalle Valo local_info_t *local = iface->local;
1004eb4f98d5SKalle Valo unsigned long flags;
1005eb4f98d5SKalle Valo
1006eb4f98d5SKalle Valo if (!local->io_debug_enabled)
1007eb4f98d5SKalle Valo return;
1008eb4f98d5SKalle Valo
1009eb4f98d5SKalle Valo spin_lock_irqsave(&local->lock, flags);
1010eb4f98d5SKalle Valo prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_ERROR, 0, err);
1011eb4f98d5SKalle Valo if (local->io_debug_enabled == 1) {
1012eb4f98d5SKalle Valo local->io_debug_enabled = 0;
1013eb4f98d5SKalle Valo printk(KERN_DEBUG "%s: I/O debug stopped\n", dev->name);
1014eb4f98d5SKalle Valo }
1015eb4f98d5SKalle Valo spin_unlock_irqrestore(&local->lock, flags);
1016eb4f98d5SKalle Valo }
1017eb4f98d5SKalle Valo
1018eb4f98d5SKalle Valo #else /* PRISM2_IO_DEBUG */
1019eb4f98d5SKalle Valo
prism2_io_debug_add(struct net_device * dev,int cmd,int reg,int value)1020eb4f98d5SKalle Valo static inline void prism2_io_debug_add(struct net_device *dev, int cmd,
1021eb4f98d5SKalle Valo int reg, int value)
1022eb4f98d5SKalle Valo {
1023eb4f98d5SKalle Valo }
1024eb4f98d5SKalle Valo
prism2_io_debug_error(struct net_device * dev,int err)1025eb4f98d5SKalle Valo static inline void prism2_io_debug_error(struct net_device *dev, int err)
1026eb4f98d5SKalle Valo {
1027eb4f98d5SKalle Valo }
1028eb4f98d5SKalle Valo
1029eb4f98d5SKalle Valo #endif /* PRISM2_IO_DEBUG */
1030eb4f98d5SKalle Valo
1031eb4f98d5SKalle Valo
1032eb4f98d5SKalle Valo #ifdef PRISM2_CALLBACK
1033eb4f98d5SKalle Valo enum {
1034eb4f98d5SKalle Valo /* Called when card is enabled */
1035eb4f98d5SKalle Valo PRISM2_CALLBACK_ENABLE,
1036eb4f98d5SKalle Valo
1037eb4f98d5SKalle Valo /* Called when card is disabled */
1038eb4f98d5SKalle Valo PRISM2_CALLBACK_DISABLE,
1039eb4f98d5SKalle Valo
1040eb4f98d5SKalle Valo /* Called when RX/TX starts/ends */
1041eb4f98d5SKalle Valo PRISM2_CALLBACK_RX_START, PRISM2_CALLBACK_RX_END,
1042eb4f98d5SKalle Valo PRISM2_CALLBACK_TX_START, PRISM2_CALLBACK_TX_END
1043eb4f98d5SKalle Valo };
1044eb4f98d5SKalle Valo void prism2_callback(local_info_t *local, int event);
1045eb4f98d5SKalle Valo #else /* PRISM2_CALLBACK */
1046eb4f98d5SKalle Valo #define prism2_callback(d, e) do { } while (0)
1047eb4f98d5SKalle Valo #endif /* PRISM2_CALLBACK */
1048eb4f98d5SKalle Valo
1049eb4f98d5SKalle Valo #endif /* __KERNEL__ */
1050eb4f98d5SKalle Valo
1051eb4f98d5SKalle Valo #endif /* HOSTAP_WLAN_H */
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