109c434b8SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2eb4f98d5SKalle Valo #define PRISM2_PCI
3eb4f98d5SKalle Valo
4eb4f98d5SKalle Valo /* Host AP driver's support for Intersil Prism2.5 PCI cards is based on
5eb4f98d5SKalle Valo * driver patches from Reyk Floeter <reyk@vantronix.net> and
6eb4f98d5SKalle Valo * Andy Warner <andyw@pobox.com> */
7eb4f98d5SKalle Valo
8eb4f98d5SKalle Valo #include <linux/module.h>
9eb4f98d5SKalle Valo #include <linux/if.h>
10eb4f98d5SKalle Valo #include <linux/skbuff.h>
11eb4f98d5SKalle Valo #include <linux/netdevice.h>
12eb4f98d5SKalle Valo #include <linux/slab.h>
13eb4f98d5SKalle Valo #include <linux/workqueue.h>
14eb4f98d5SKalle Valo #include <linux/wireless.h>
15eb4f98d5SKalle Valo #include <net/iw_handler.h>
16eb4f98d5SKalle Valo
17eb4f98d5SKalle Valo #include <linux/ioport.h>
18eb4f98d5SKalle Valo #include <linux/pci.h>
19eb4f98d5SKalle Valo #include <asm/io.h>
20eb4f98d5SKalle Valo
21eb4f98d5SKalle Valo #include "hostap_wlan.h"
22eb4f98d5SKalle Valo
23eb4f98d5SKalle Valo
24eb4f98d5SKalle Valo static char *dev_info = "hostap_pci";
25eb4f98d5SKalle Valo
26eb4f98d5SKalle Valo
27eb4f98d5SKalle Valo MODULE_AUTHOR("Jouni Malinen");
28eb4f98d5SKalle Valo MODULE_DESCRIPTION("Support for Intersil Prism2.5-based 802.11 wireless LAN "
29eb4f98d5SKalle Valo "PCI cards.");
30eb4f98d5SKalle Valo MODULE_LICENSE("GPL");
31eb4f98d5SKalle Valo
32eb4f98d5SKalle Valo
33eb4f98d5SKalle Valo /* struct local_info::hw_priv */
34eb4f98d5SKalle Valo struct hostap_pci_priv {
35eb4f98d5SKalle Valo void __iomem *mem_start;
36eb4f98d5SKalle Valo };
37eb4f98d5SKalle Valo
38eb4f98d5SKalle Valo
39eb4f98d5SKalle Valo /* FIX: do we need mb/wmb/rmb with memory operations? */
40eb4f98d5SKalle Valo
41eb4f98d5SKalle Valo
42eb4f98d5SKalle Valo static const struct pci_device_id prism2_pci_id_table[] = {
43eb4f98d5SKalle Valo /* Intersil Prism3 ISL3872 11Mb/s WLAN Controller */
44eb4f98d5SKalle Valo { 0x1260, 0x3872, PCI_ANY_ID, PCI_ANY_ID },
45eb4f98d5SKalle Valo /* Intersil Prism2.5 ISL3874 11Mb/s WLAN Controller */
46eb4f98d5SKalle Valo { 0x1260, 0x3873, PCI_ANY_ID, PCI_ANY_ID },
47eb4f98d5SKalle Valo /* Samsung MagicLAN SWL-2210P */
48eb4f98d5SKalle Valo { 0x167d, 0xa000, PCI_ANY_ID, PCI_ANY_ID },
49eb4f98d5SKalle Valo { 0 }
50eb4f98d5SKalle Valo };
51eb4f98d5SKalle Valo
52eb4f98d5SKalle Valo
53eb4f98d5SKalle Valo #ifdef PRISM2_IO_DEBUG
54eb4f98d5SKalle Valo
hfa384x_outb_debug(struct net_device * dev,int a,u8 v)55eb4f98d5SKalle Valo static inline void hfa384x_outb_debug(struct net_device *dev, int a, u8 v)
56eb4f98d5SKalle Valo {
57eb4f98d5SKalle Valo struct hostap_interface *iface;
58eb4f98d5SKalle Valo struct hostap_pci_priv *hw_priv;
59eb4f98d5SKalle Valo local_info_t *local;
60eb4f98d5SKalle Valo unsigned long flags;
61eb4f98d5SKalle Valo
62eb4f98d5SKalle Valo iface = netdev_priv(dev);
63eb4f98d5SKalle Valo local = iface->local;
64eb4f98d5SKalle Valo hw_priv = local->hw_priv;
65eb4f98d5SKalle Valo
66eb4f98d5SKalle Valo spin_lock_irqsave(&local->lock, flags);
67eb4f98d5SKalle Valo prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_OUTB, a, v);
68eb4f98d5SKalle Valo writeb(v, hw_priv->mem_start + a);
69eb4f98d5SKalle Valo spin_unlock_irqrestore(&local->lock, flags);
70eb4f98d5SKalle Valo }
71eb4f98d5SKalle Valo
hfa384x_inb_debug(struct net_device * dev,int a)72eb4f98d5SKalle Valo static inline u8 hfa384x_inb_debug(struct net_device *dev, int a)
73eb4f98d5SKalle Valo {
74eb4f98d5SKalle Valo struct hostap_interface *iface;
75eb4f98d5SKalle Valo struct hostap_pci_priv *hw_priv;
76eb4f98d5SKalle Valo local_info_t *local;
77eb4f98d5SKalle Valo unsigned long flags;
78eb4f98d5SKalle Valo u8 v;
79eb4f98d5SKalle Valo
80eb4f98d5SKalle Valo iface = netdev_priv(dev);
81eb4f98d5SKalle Valo local = iface->local;
82eb4f98d5SKalle Valo hw_priv = local->hw_priv;
83eb4f98d5SKalle Valo
84eb4f98d5SKalle Valo spin_lock_irqsave(&local->lock, flags);
85eb4f98d5SKalle Valo v = readb(hw_priv->mem_start + a);
86eb4f98d5SKalle Valo prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_INB, a, v);
87eb4f98d5SKalle Valo spin_unlock_irqrestore(&local->lock, flags);
88eb4f98d5SKalle Valo return v;
89eb4f98d5SKalle Valo }
90eb4f98d5SKalle Valo
hfa384x_outw_debug(struct net_device * dev,int a,u16 v)91eb4f98d5SKalle Valo static inline void hfa384x_outw_debug(struct net_device *dev, int a, u16 v)
92eb4f98d5SKalle Valo {
93eb4f98d5SKalle Valo struct hostap_interface *iface;
94eb4f98d5SKalle Valo struct hostap_pci_priv *hw_priv;
95eb4f98d5SKalle Valo local_info_t *local;
96eb4f98d5SKalle Valo unsigned long flags;
97eb4f98d5SKalle Valo
98eb4f98d5SKalle Valo iface = netdev_priv(dev);
99eb4f98d5SKalle Valo local = iface->local;
100eb4f98d5SKalle Valo hw_priv = local->hw_priv;
101eb4f98d5SKalle Valo
102eb4f98d5SKalle Valo spin_lock_irqsave(&local->lock, flags);
103eb4f98d5SKalle Valo prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_OUTW, a, v);
104eb4f98d5SKalle Valo writew(v, hw_priv->mem_start + a);
105eb4f98d5SKalle Valo spin_unlock_irqrestore(&local->lock, flags);
106eb4f98d5SKalle Valo }
107eb4f98d5SKalle Valo
hfa384x_inw_debug(struct net_device * dev,int a)108eb4f98d5SKalle Valo static inline u16 hfa384x_inw_debug(struct net_device *dev, int a)
109eb4f98d5SKalle Valo {
110eb4f98d5SKalle Valo struct hostap_interface *iface;
111eb4f98d5SKalle Valo struct hostap_pci_priv *hw_priv;
112eb4f98d5SKalle Valo local_info_t *local;
113eb4f98d5SKalle Valo unsigned long flags;
114eb4f98d5SKalle Valo u16 v;
115eb4f98d5SKalle Valo
116eb4f98d5SKalle Valo iface = netdev_priv(dev);
117eb4f98d5SKalle Valo local = iface->local;
118eb4f98d5SKalle Valo hw_priv = local->hw_priv;
119eb4f98d5SKalle Valo
120eb4f98d5SKalle Valo spin_lock_irqsave(&local->lock, flags);
121eb4f98d5SKalle Valo v = readw(hw_priv->mem_start + a);
122eb4f98d5SKalle Valo prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_INW, a, v);
123eb4f98d5SKalle Valo spin_unlock_irqrestore(&local->lock, flags);
124eb4f98d5SKalle Valo return v;
125eb4f98d5SKalle Valo }
126eb4f98d5SKalle Valo
127eb4f98d5SKalle Valo #define HFA384X_OUTB(v,a) hfa384x_outb_debug(dev, (a), (v))
128eb4f98d5SKalle Valo #define HFA384X_INB(a) hfa384x_inb_debug(dev, (a))
129eb4f98d5SKalle Valo #define HFA384X_OUTW(v,a) hfa384x_outw_debug(dev, (a), (v))
130eb4f98d5SKalle Valo #define HFA384X_INW(a) hfa384x_inw_debug(dev, (a))
131eb4f98d5SKalle Valo #define HFA384X_OUTW_DATA(v,a) hfa384x_outw_debug(dev, (a), le16_to_cpu((v)))
132eb4f98d5SKalle Valo #define HFA384X_INW_DATA(a) cpu_to_le16(hfa384x_inw_debug(dev, (a)))
133eb4f98d5SKalle Valo
134eb4f98d5SKalle Valo #else /* PRISM2_IO_DEBUG */
135eb4f98d5SKalle Valo
hfa384x_outb(struct net_device * dev,int a,u8 v)136eb4f98d5SKalle Valo static inline void hfa384x_outb(struct net_device *dev, int a, u8 v)
137eb4f98d5SKalle Valo {
138eb4f98d5SKalle Valo struct hostap_interface *iface;
139eb4f98d5SKalle Valo struct hostap_pci_priv *hw_priv;
140eb4f98d5SKalle Valo iface = netdev_priv(dev);
141eb4f98d5SKalle Valo hw_priv = iface->local->hw_priv;
142eb4f98d5SKalle Valo writeb(v, hw_priv->mem_start + a);
143eb4f98d5SKalle Valo }
144eb4f98d5SKalle Valo
hfa384x_inb(struct net_device * dev,int a)145eb4f98d5SKalle Valo static inline u8 hfa384x_inb(struct net_device *dev, int a)
146eb4f98d5SKalle Valo {
147eb4f98d5SKalle Valo struct hostap_interface *iface;
148eb4f98d5SKalle Valo struct hostap_pci_priv *hw_priv;
149eb4f98d5SKalle Valo iface = netdev_priv(dev);
150eb4f98d5SKalle Valo hw_priv = iface->local->hw_priv;
151eb4f98d5SKalle Valo return readb(hw_priv->mem_start + a);
152eb4f98d5SKalle Valo }
153eb4f98d5SKalle Valo
hfa384x_outw(struct net_device * dev,int a,u16 v)154eb4f98d5SKalle Valo static inline void hfa384x_outw(struct net_device *dev, int a, u16 v)
155eb4f98d5SKalle Valo {
156eb4f98d5SKalle Valo struct hostap_interface *iface;
157eb4f98d5SKalle Valo struct hostap_pci_priv *hw_priv;
158eb4f98d5SKalle Valo iface = netdev_priv(dev);
159eb4f98d5SKalle Valo hw_priv = iface->local->hw_priv;
160eb4f98d5SKalle Valo writew(v, hw_priv->mem_start + a);
161eb4f98d5SKalle Valo }
162eb4f98d5SKalle Valo
hfa384x_inw(struct net_device * dev,int a)163eb4f98d5SKalle Valo static inline u16 hfa384x_inw(struct net_device *dev, int a)
164eb4f98d5SKalle Valo {
165eb4f98d5SKalle Valo struct hostap_interface *iface;
166eb4f98d5SKalle Valo struct hostap_pci_priv *hw_priv;
167eb4f98d5SKalle Valo iface = netdev_priv(dev);
168eb4f98d5SKalle Valo hw_priv = iface->local->hw_priv;
169eb4f98d5SKalle Valo return readw(hw_priv->mem_start + a);
170eb4f98d5SKalle Valo }
171eb4f98d5SKalle Valo
172eb4f98d5SKalle Valo #define HFA384X_OUTB(v,a) hfa384x_outb(dev, (a), (v))
173eb4f98d5SKalle Valo #define HFA384X_INB(a) hfa384x_inb(dev, (a))
174eb4f98d5SKalle Valo #define HFA384X_OUTW(v,a) hfa384x_outw(dev, (a), (v))
175eb4f98d5SKalle Valo #define HFA384X_INW(a) hfa384x_inw(dev, (a))
176eb4f98d5SKalle Valo #define HFA384X_OUTW_DATA(v,a) hfa384x_outw(dev, (a), le16_to_cpu((v)))
177eb4f98d5SKalle Valo #define HFA384X_INW_DATA(a) cpu_to_le16(hfa384x_inw(dev, (a)))
178eb4f98d5SKalle Valo
179eb4f98d5SKalle Valo #endif /* PRISM2_IO_DEBUG */
180eb4f98d5SKalle Valo
181eb4f98d5SKalle Valo
hfa384x_from_bap(struct net_device * dev,u16 bap,void * buf,int len)182eb4f98d5SKalle Valo static int hfa384x_from_bap(struct net_device *dev, u16 bap, void *buf,
183eb4f98d5SKalle Valo int len)
184eb4f98d5SKalle Valo {
185eb4f98d5SKalle Valo u16 d_off;
186eb4f98d5SKalle Valo __le16 *pos;
187eb4f98d5SKalle Valo
188eb4f98d5SKalle Valo d_off = (bap == 1) ? HFA384X_DATA1_OFF : HFA384X_DATA0_OFF;
189eb4f98d5SKalle Valo pos = (__le16 *) buf;
190eb4f98d5SKalle Valo
191eb4f98d5SKalle Valo for ( ; len > 1; len -= 2)
192eb4f98d5SKalle Valo *pos++ = HFA384X_INW_DATA(d_off);
193eb4f98d5SKalle Valo
194eb4f98d5SKalle Valo if (len & 1)
195eb4f98d5SKalle Valo *((char *) pos) = HFA384X_INB(d_off);
196eb4f98d5SKalle Valo
197eb4f98d5SKalle Valo return 0;
198eb4f98d5SKalle Valo }
199eb4f98d5SKalle Valo
200eb4f98d5SKalle Valo
hfa384x_to_bap(struct net_device * dev,u16 bap,void * buf,int len)201eb4f98d5SKalle Valo static int hfa384x_to_bap(struct net_device *dev, u16 bap, void *buf, int len)
202eb4f98d5SKalle Valo {
203eb4f98d5SKalle Valo u16 d_off;
204eb4f98d5SKalle Valo __le16 *pos;
205eb4f98d5SKalle Valo
206eb4f98d5SKalle Valo d_off = (bap == 1) ? HFA384X_DATA1_OFF : HFA384X_DATA0_OFF;
207eb4f98d5SKalle Valo pos = (__le16 *) buf;
208eb4f98d5SKalle Valo
209eb4f98d5SKalle Valo for ( ; len > 1; len -= 2)
210eb4f98d5SKalle Valo HFA384X_OUTW_DATA(*pos++, d_off);
211eb4f98d5SKalle Valo
212eb4f98d5SKalle Valo if (len & 1)
213eb4f98d5SKalle Valo HFA384X_OUTB(*((char *) pos), d_off);
214eb4f98d5SKalle Valo
215eb4f98d5SKalle Valo return 0;
216eb4f98d5SKalle Valo }
217eb4f98d5SKalle Valo
218eb4f98d5SKalle Valo
219eb4f98d5SKalle Valo /* FIX: This might change at some point.. */
220eb4f98d5SKalle Valo #include "hostap_hw.c"
221eb4f98d5SKalle Valo
prism2_pci_cor_sreset(local_info_t * local)222eb4f98d5SKalle Valo static void prism2_pci_cor_sreset(local_info_t *local)
223eb4f98d5SKalle Valo {
224eb4f98d5SKalle Valo struct net_device *dev = local->dev;
225eb4f98d5SKalle Valo u16 reg;
226eb4f98d5SKalle Valo
227eb4f98d5SKalle Valo reg = HFA384X_INB(HFA384X_PCICOR_OFF);
228eb4f98d5SKalle Valo printk(KERN_DEBUG "%s: Original COR value: 0x%0x\n", dev->name, reg);
229eb4f98d5SKalle Valo
230eb4f98d5SKalle Valo /* linux-wlan-ng uses extremely long hold and settle times for
231eb4f98d5SKalle Valo * COR sreset. A comment in the driver code mentions that the long
232eb4f98d5SKalle Valo * delays appear to be necessary. However, at least IBM 22P6901 seems
233eb4f98d5SKalle Valo * to work fine with shorter delays.
234eb4f98d5SKalle Valo *
235eb4f98d5SKalle Valo * Longer delays can be configured by uncommenting following line: */
236eb4f98d5SKalle Valo /* #define PRISM2_PCI_USE_LONG_DELAYS */
237eb4f98d5SKalle Valo
238eb4f98d5SKalle Valo #ifdef PRISM2_PCI_USE_LONG_DELAYS
239eb4f98d5SKalle Valo int i;
240eb4f98d5SKalle Valo
241eb4f98d5SKalle Valo HFA384X_OUTW(reg | 0x0080, HFA384X_PCICOR_OFF);
242eb4f98d5SKalle Valo mdelay(250);
243eb4f98d5SKalle Valo
244eb4f98d5SKalle Valo HFA384X_OUTW(reg & ~0x0080, HFA384X_PCICOR_OFF);
245eb4f98d5SKalle Valo mdelay(500);
246eb4f98d5SKalle Valo
247eb4f98d5SKalle Valo /* Wait for f/w to complete initialization (CMD:BUSY == 0) */
248eb4f98d5SKalle Valo i = 2000000 / 10;
249eb4f98d5SKalle Valo while ((HFA384X_INW(HFA384X_CMD_OFF) & HFA384X_CMD_BUSY) && --i)
250eb4f98d5SKalle Valo udelay(10);
251eb4f98d5SKalle Valo
252eb4f98d5SKalle Valo #else /* PRISM2_PCI_USE_LONG_DELAYS */
253eb4f98d5SKalle Valo
254eb4f98d5SKalle Valo HFA384X_OUTW(reg | 0x0080, HFA384X_PCICOR_OFF);
255eb4f98d5SKalle Valo mdelay(2);
256eb4f98d5SKalle Valo HFA384X_OUTW(reg & ~0x0080, HFA384X_PCICOR_OFF);
257eb4f98d5SKalle Valo mdelay(2);
258eb4f98d5SKalle Valo
259eb4f98d5SKalle Valo #endif /* PRISM2_PCI_USE_LONG_DELAYS */
260eb4f98d5SKalle Valo
261eb4f98d5SKalle Valo if (HFA384X_INW(HFA384X_CMD_OFF) & HFA384X_CMD_BUSY) {
262eb4f98d5SKalle Valo printk(KERN_DEBUG "%s: COR sreset timeout\n", dev->name);
263eb4f98d5SKalle Valo }
264eb4f98d5SKalle Valo }
265eb4f98d5SKalle Valo
266eb4f98d5SKalle Valo
prism2_pci_genesis_reset(local_info_t * local,int hcr)267eb4f98d5SKalle Valo static void prism2_pci_genesis_reset(local_info_t *local, int hcr)
268eb4f98d5SKalle Valo {
269eb4f98d5SKalle Valo struct net_device *dev = local->dev;
270eb4f98d5SKalle Valo
271eb4f98d5SKalle Valo HFA384X_OUTW(0x00C5, HFA384X_PCICOR_OFF);
272eb4f98d5SKalle Valo mdelay(10);
273eb4f98d5SKalle Valo HFA384X_OUTW(hcr, HFA384X_PCIHCR_OFF);
274eb4f98d5SKalle Valo mdelay(10);
275eb4f98d5SKalle Valo HFA384X_OUTW(0x0045, HFA384X_PCICOR_OFF);
276eb4f98d5SKalle Valo mdelay(10);
277eb4f98d5SKalle Valo }
278eb4f98d5SKalle Valo
279eb4f98d5SKalle Valo
280eb4f98d5SKalle Valo static struct prism2_helper_functions prism2_pci_funcs =
281eb4f98d5SKalle Valo {
282eb4f98d5SKalle Valo .card_present = NULL,
283eb4f98d5SKalle Valo .cor_sreset = prism2_pci_cor_sreset,
284eb4f98d5SKalle Valo .genesis_reset = prism2_pci_genesis_reset,
285eb4f98d5SKalle Valo .hw_type = HOSTAP_HW_PCI,
286eb4f98d5SKalle Valo };
287eb4f98d5SKalle Valo
288eb4f98d5SKalle Valo
prism2_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)289eb4f98d5SKalle Valo static int prism2_pci_probe(struct pci_dev *pdev,
290eb4f98d5SKalle Valo const struct pci_device_id *id)
291eb4f98d5SKalle Valo {
292eb4f98d5SKalle Valo unsigned long phymem;
293eb4f98d5SKalle Valo void __iomem *mem = NULL;
294eb4f98d5SKalle Valo local_info_t *local = NULL;
295eb4f98d5SKalle Valo struct net_device *dev = NULL;
296eb4f98d5SKalle Valo static int cards_found /* = 0 */;
297eb4f98d5SKalle Valo int irq_registered = 0;
298eb4f98d5SKalle Valo struct hostap_interface *iface;
299eb4f98d5SKalle Valo struct hostap_pci_priv *hw_priv;
300eb4f98d5SKalle Valo
301eb4f98d5SKalle Valo hw_priv = kzalloc(sizeof(*hw_priv), GFP_KERNEL);
302eb4f98d5SKalle Valo if (hw_priv == NULL)
303eb4f98d5SKalle Valo return -ENOMEM;
304eb4f98d5SKalle Valo
305eb4f98d5SKalle Valo if (pci_enable_device(pdev))
306eb4f98d5SKalle Valo goto err_out_free;
307eb4f98d5SKalle Valo
308eb4f98d5SKalle Valo phymem = pci_resource_start(pdev, 0);
309eb4f98d5SKalle Valo
310eb4f98d5SKalle Valo if (!request_mem_region(phymem, pci_resource_len(pdev, 0), "Prism2")) {
311eb4f98d5SKalle Valo printk(KERN_ERR "prism2: Cannot reserve PCI memory region\n");
312eb4f98d5SKalle Valo goto err_out_disable;
313eb4f98d5SKalle Valo }
314eb4f98d5SKalle Valo
315eb4f98d5SKalle Valo mem = pci_ioremap_bar(pdev, 0);
316eb4f98d5SKalle Valo if (mem == NULL) {
317eb4f98d5SKalle Valo printk(KERN_ERR "prism2: Cannot remap PCI memory region\n") ;
318eb4f98d5SKalle Valo goto fail;
319eb4f98d5SKalle Valo }
320eb4f98d5SKalle Valo
321eb4f98d5SKalle Valo dev = prism2_init_local_data(&prism2_pci_funcs, cards_found,
322eb4f98d5SKalle Valo &pdev->dev);
323eb4f98d5SKalle Valo if (dev == NULL)
324eb4f98d5SKalle Valo goto fail;
325eb4f98d5SKalle Valo iface = netdev_priv(dev);
326eb4f98d5SKalle Valo local = iface->local;
327eb4f98d5SKalle Valo local->hw_priv = hw_priv;
328eb4f98d5SKalle Valo cards_found++;
329eb4f98d5SKalle Valo
330eb4f98d5SKalle Valo dev->irq = pdev->irq;
331eb4f98d5SKalle Valo hw_priv->mem_start = mem;
332eb4f98d5SKalle Valo dev->base_addr = (unsigned long) mem;
333eb4f98d5SKalle Valo
334eb4f98d5SKalle Valo prism2_pci_cor_sreset(local);
335eb4f98d5SKalle Valo
336eb4f98d5SKalle Valo pci_set_drvdata(pdev, dev);
337eb4f98d5SKalle Valo
338eb4f98d5SKalle Valo if (request_irq(dev->irq, prism2_interrupt, IRQF_SHARED, dev->name,
339eb4f98d5SKalle Valo dev)) {
340eb4f98d5SKalle Valo printk(KERN_WARNING "%s: request_irq failed\n", dev->name);
341eb4f98d5SKalle Valo goto fail;
342eb4f98d5SKalle Valo } else
343eb4f98d5SKalle Valo irq_registered = 1;
344eb4f98d5SKalle Valo
345eb4f98d5SKalle Valo if (!local->pri_only && prism2_hw_config(dev, 1)) {
346eb4f98d5SKalle Valo printk(KERN_DEBUG "%s: hardware initialization failed\n",
347eb4f98d5SKalle Valo dev_info);
348eb4f98d5SKalle Valo goto fail;
349eb4f98d5SKalle Valo }
350eb4f98d5SKalle Valo
351eb4f98d5SKalle Valo printk(KERN_INFO "%s: Intersil Prism2.5 PCI: "
352eb4f98d5SKalle Valo "mem=0x%lx, irq=%d\n", dev->name, phymem, dev->irq);
353eb4f98d5SKalle Valo
354eb4f98d5SKalle Valo return hostap_hw_ready(dev);
355eb4f98d5SKalle Valo
356eb4f98d5SKalle Valo fail:
357eb4f98d5SKalle Valo if (irq_registered && dev)
358eb4f98d5SKalle Valo free_irq(dev->irq, dev);
359eb4f98d5SKalle Valo
360eb4f98d5SKalle Valo if (mem)
361eb4f98d5SKalle Valo iounmap(mem);
362eb4f98d5SKalle Valo
363eb4f98d5SKalle Valo release_mem_region(phymem, pci_resource_len(pdev, 0));
364eb4f98d5SKalle Valo
365eb4f98d5SKalle Valo err_out_disable:
366eb4f98d5SKalle Valo pci_disable_device(pdev);
367eb4f98d5SKalle Valo prism2_free_local_data(dev);
368eb4f98d5SKalle Valo
369eb4f98d5SKalle Valo err_out_free:
370eb4f98d5SKalle Valo kfree(hw_priv);
371eb4f98d5SKalle Valo
372eb4f98d5SKalle Valo return -ENODEV;
373eb4f98d5SKalle Valo }
374eb4f98d5SKalle Valo
375eb4f98d5SKalle Valo
prism2_pci_remove(struct pci_dev * pdev)376eb4f98d5SKalle Valo static void prism2_pci_remove(struct pci_dev *pdev)
377eb4f98d5SKalle Valo {
378eb4f98d5SKalle Valo struct net_device *dev;
379eb4f98d5SKalle Valo struct hostap_interface *iface;
380eb4f98d5SKalle Valo void __iomem *mem_start;
381eb4f98d5SKalle Valo struct hostap_pci_priv *hw_priv;
382eb4f98d5SKalle Valo
383eb4f98d5SKalle Valo dev = pci_get_drvdata(pdev);
384eb4f98d5SKalle Valo iface = netdev_priv(dev);
385eb4f98d5SKalle Valo hw_priv = iface->local->hw_priv;
386eb4f98d5SKalle Valo
387eb4f98d5SKalle Valo /* Reset the hardware, and ensure interrupts are disabled. */
388eb4f98d5SKalle Valo prism2_pci_cor_sreset(iface->local);
389eb4f98d5SKalle Valo hfa384x_disable_interrupts(dev);
390eb4f98d5SKalle Valo
391eb4f98d5SKalle Valo if (dev->irq)
392eb4f98d5SKalle Valo free_irq(dev->irq, dev);
393eb4f98d5SKalle Valo
394eb4f98d5SKalle Valo mem_start = hw_priv->mem_start;
395eb4f98d5SKalle Valo prism2_free_local_data(dev);
396eb4f98d5SKalle Valo kfree(hw_priv);
397eb4f98d5SKalle Valo
398eb4f98d5SKalle Valo iounmap(mem_start);
399eb4f98d5SKalle Valo
400eb4f98d5SKalle Valo release_mem_region(pci_resource_start(pdev, 0),
401eb4f98d5SKalle Valo pci_resource_len(pdev, 0));
402eb4f98d5SKalle Valo pci_disable_device(pdev);
403eb4f98d5SKalle Valo }
404eb4f98d5SKalle Valo
prism2_pci_suspend(struct device * dev_d)405*99aaa1aaSVaibhav Gupta static int __maybe_unused prism2_pci_suspend(struct device *dev_d)
406eb4f98d5SKalle Valo {
407*99aaa1aaSVaibhav Gupta struct net_device *dev = dev_get_drvdata(dev_d);
408eb4f98d5SKalle Valo
409eb4f98d5SKalle Valo if (netif_running(dev)) {
410eb4f98d5SKalle Valo netif_stop_queue(dev);
411eb4f98d5SKalle Valo netif_device_detach(dev);
412eb4f98d5SKalle Valo }
413eb4f98d5SKalle Valo prism2_suspend(dev);
414eb4f98d5SKalle Valo
415eb4f98d5SKalle Valo return 0;
416eb4f98d5SKalle Valo }
417eb4f98d5SKalle Valo
prism2_pci_resume(struct device * dev_d)418*99aaa1aaSVaibhav Gupta static int __maybe_unused prism2_pci_resume(struct device *dev_d)
419eb4f98d5SKalle Valo {
420*99aaa1aaSVaibhav Gupta struct net_device *dev = dev_get_drvdata(dev_d);
421eb4f98d5SKalle Valo
422eb4f98d5SKalle Valo prism2_hw_config(dev, 0);
423eb4f98d5SKalle Valo if (netif_running(dev)) {
424eb4f98d5SKalle Valo netif_device_attach(dev);
425eb4f98d5SKalle Valo netif_start_queue(dev);
426eb4f98d5SKalle Valo }
427eb4f98d5SKalle Valo
428eb4f98d5SKalle Valo return 0;
429eb4f98d5SKalle Valo }
430eb4f98d5SKalle Valo
431eb4f98d5SKalle Valo MODULE_DEVICE_TABLE(pci, prism2_pci_id_table);
432eb4f98d5SKalle Valo
433*99aaa1aaSVaibhav Gupta static SIMPLE_DEV_PM_OPS(prism2_pci_pm_ops,
434*99aaa1aaSVaibhav Gupta prism2_pci_suspend,
435*99aaa1aaSVaibhav Gupta prism2_pci_resume);
436*99aaa1aaSVaibhav Gupta
437eb4f98d5SKalle Valo static struct pci_driver prism2_pci_driver = {
438eb4f98d5SKalle Valo .name = "hostap_pci",
439eb4f98d5SKalle Valo .id_table = prism2_pci_id_table,
440eb4f98d5SKalle Valo .probe = prism2_pci_probe,
441eb4f98d5SKalle Valo .remove = prism2_pci_remove,
442*99aaa1aaSVaibhav Gupta .driver.pm = &prism2_pci_pm_ops,
443eb4f98d5SKalle Valo };
444eb4f98d5SKalle Valo
445eb4f98d5SKalle Valo module_pci_driver(prism2_pci_driver);
446