14273a380SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2e705c121SKalle Valo /******************************************************************************
3e705c121SKalle Valo *
4e705c121SKalle Valo * Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
579b6c8feSLuca Coelho * Copyright (C) 2019 Intel Corporation
6e705c121SKalle Valo *
7e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well
8e705c121SKalle Valo * as portions of the ieee80211 subsystem header files.
9e705c121SKalle Valo *****************************************************************************/
10e705c121SKalle Valo
11e705c121SKalle Valo
12e705c121SKalle Valo #include <linux/kernel.h>
13e705c121SKalle Valo #include <linux/module.h>
14e705c121SKalle Valo #include <linux/slab.h>
15e705c121SKalle Valo #include <net/mac80211.h>
16e705c121SKalle Valo #include "iwl-io.h"
17e705c121SKalle Valo #include "iwl-debug.h"
18e705c121SKalle Valo #include "iwl-trans.h"
19e705c121SKalle Valo #include "iwl-modparams.h"
20e705c121SKalle Valo #include "dev.h"
21e705c121SKalle Valo #include "agn.h"
22e705c121SKalle Valo #include "commands.h"
23e705c121SKalle Valo #include "power.h"
24e705c121SKalle Valo
25e705c121SKalle Valo static bool force_cam = true;
26e705c121SKalle Valo module_param(force_cam, bool, 0644);
27e705c121SKalle Valo MODULE_PARM_DESC(force_cam, "force continuously aware mode (no power saving at all)");
28e705c121SKalle Valo
29e705c121SKalle Valo /*
30e705c121SKalle Valo * Setting power level allows the card to go to sleep when not busy.
31e705c121SKalle Valo *
32e705c121SKalle Valo * We calculate a sleep command based on the required latency, which
33e705c121SKalle Valo * we get from mac80211. In order to handle thermal throttling, we can
34e705c121SKalle Valo * also use pre-defined power levels.
35e705c121SKalle Valo */
36e705c121SKalle Valo
37e705c121SKalle Valo /*
38e705c121SKalle Valo * This defines the old power levels. They are still used by default
39e705c121SKalle Valo * (level 1) and for thermal throttle (levels 3 through 5)
40e705c121SKalle Valo */
41e705c121SKalle Valo
42e705c121SKalle Valo struct iwl_power_vec_entry {
43e705c121SKalle Valo struct iwl_powertable_cmd cmd;
44e705c121SKalle Valo u8 no_dtim; /* number of skip dtim */
45e705c121SKalle Valo };
46e705c121SKalle Valo
47e705c121SKalle Valo #define IWL_DTIM_RANGE_0_MAX 2
48e705c121SKalle Valo #define IWL_DTIM_RANGE_1_MAX 10
49e705c121SKalle Valo
50e705c121SKalle Valo #define NOSLP cpu_to_le16(0), 0, 0
51e705c121SKalle Valo #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
52e705c121SKalle Valo #define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK | \
53e705c121SKalle Valo IWL_POWER_POWER_MANAGEMENT_ENA_MSK | \
54e705c121SKalle Valo IWL_POWER_ADVANCE_PM_ENA_MSK)
55e705c121SKalle Valo #define ASLP_TOUT(T) cpu_to_le32(T)
56e705c121SKalle Valo #define TU_TO_USEC 1024
57e705c121SKalle Valo #define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
58e705c121SKalle Valo #define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
59e705c121SKalle Valo cpu_to_le32(X1), \
60e705c121SKalle Valo cpu_to_le32(X2), \
61e705c121SKalle Valo cpu_to_le32(X3), \
62e705c121SKalle Valo cpu_to_le32(X4)}
63e705c121SKalle Valo /* default power management (not Tx power) table values */
64e705c121SKalle Valo /* for DTIM period 0 through IWL_DTIM_RANGE_0_MAX */
65e705c121SKalle Valo /* DTIM 0 - 2 */
66e705c121SKalle Valo static const struct iwl_power_vec_entry range_0[IWL_POWER_NUM] = {
67e705c121SKalle Valo {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 1, 2, 2, 0xFF)}, 0},
68e705c121SKalle Valo {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0},
69e705c121SKalle Valo {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 2, 2, 2, 0xFF)}, 0},
70e705c121SKalle Valo {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 2, 4, 4, 0xFF)}, 1},
71e705c121SKalle Valo {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 2, 4, 6, 0xFF)}, 2}
72e705c121SKalle Valo };
73e705c121SKalle Valo
74e705c121SKalle Valo
75e705c121SKalle Valo /* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
76e705c121SKalle Valo /* DTIM 3 - 10 */
77e705c121SKalle Valo static const struct iwl_power_vec_entry range_1[IWL_POWER_NUM] = {
78e705c121SKalle Valo {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
79e705c121SKalle Valo {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0},
80e705c121SKalle Valo {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 4, 6, 7, 9)}, 0},
81e705c121SKalle Valo {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 4, 6, 9, 10)}, 1},
82e705c121SKalle Valo {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(2, 4, 6, 10, 10)}, 2}
83e705c121SKalle Valo };
84e705c121SKalle Valo
85e705c121SKalle Valo /* for DTIM period > IWL_DTIM_RANGE_1_MAX */
86e705c121SKalle Valo /* DTIM 11 - */
87e705c121SKalle Valo static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
88e705c121SKalle Valo {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
89e705c121SKalle Valo {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
90e705c121SKalle Valo {{SLP, SLP_TOUT(50), SLP_TOUT(100), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
91e705c121SKalle Valo {{SLP, SLP_TOUT(50), SLP_TOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
92e705c121SKalle Valo {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
93e705c121SKalle Valo };
94e705c121SKalle Valo
95e705c121SKalle Valo /* advance power management */
96e705c121SKalle Valo /* DTIM 0 - 2 */
97e705c121SKalle Valo static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
98e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
99e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
100e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
101e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
102e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
103e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
104e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
105e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
106e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
107e705c121SKalle Valo SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
108e705c121SKalle Valo };
109e705c121SKalle Valo
110e705c121SKalle Valo
111e705c121SKalle Valo /* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
112e705c121SKalle Valo /* DTIM 3 - 10 */
113e705c121SKalle Valo static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
114e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
115e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
116e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
117e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
118e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
119e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
120e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
121e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
122e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
123e705c121SKalle Valo SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
124e705c121SKalle Valo };
125e705c121SKalle Valo
126e705c121SKalle Valo /* for DTIM period > IWL_DTIM_RANGE_1_MAX */
127e705c121SKalle Valo /* DTIM 11 - */
128e705c121SKalle Valo static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
129e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
130e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
131e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
132e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
133e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
134e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
135e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
136e705c121SKalle Valo SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
137e705c121SKalle Valo {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
138e705c121SKalle Valo SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
139e705c121SKalle Valo };
140e705c121SKalle Valo
iwl_static_sleep_cmd(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd,enum iwl_power_level lvl,int period)141e705c121SKalle Valo static void iwl_static_sleep_cmd(struct iwl_priv *priv,
142e705c121SKalle Valo struct iwl_powertable_cmd *cmd,
143e705c121SKalle Valo enum iwl_power_level lvl, int period)
144e705c121SKalle Valo {
145e705c121SKalle Valo const struct iwl_power_vec_entry *table;
146e705c121SKalle Valo int max_sleep[IWL_POWER_VEC_SIZE] = { 0 };
147e705c121SKalle Valo int i;
148e705c121SKalle Valo u8 skip;
149e705c121SKalle Valo u32 slp_itrvl;
150e705c121SKalle Valo
151e705c121SKalle Valo if (priv->lib->adv_pm) {
152e705c121SKalle Valo table = apm_range_2;
153e705c121SKalle Valo if (period <= IWL_DTIM_RANGE_1_MAX)
154e705c121SKalle Valo table = apm_range_1;
155e705c121SKalle Valo if (period <= IWL_DTIM_RANGE_0_MAX)
156e705c121SKalle Valo table = apm_range_0;
157e705c121SKalle Valo } else {
158e705c121SKalle Valo table = range_2;
159e705c121SKalle Valo if (period <= IWL_DTIM_RANGE_1_MAX)
160e705c121SKalle Valo table = range_1;
161e705c121SKalle Valo if (period <= IWL_DTIM_RANGE_0_MAX)
162e705c121SKalle Valo table = range_0;
163e705c121SKalle Valo }
164e705c121SKalle Valo
165e705c121SKalle Valo if (WARN_ON(lvl < 0 || lvl >= IWL_POWER_NUM))
166e705c121SKalle Valo memset(cmd, 0, sizeof(*cmd));
167e705c121SKalle Valo else
168e705c121SKalle Valo *cmd = table[lvl].cmd;
169e705c121SKalle Valo
170e705c121SKalle Valo if (period == 0) {
171e705c121SKalle Valo skip = 0;
172e705c121SKalle Valo period = 1;
173e705c121SKalle Valo for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
174e705c121SKalle Valo max_sleep[i] = 1;
175e705c121SKalle Valo
176e705c121SKalle Valo } else {
177e705c121SKalle Valo skip = table[lvl].no_dtim;
178e705c121SKalle Valo for (i = 0; i < IWL_POWER_VEC_SIZE; i++)
179e705c121SKalle Valo max_sleep[i] = le32_to_cpu(cmd->sleep_interval[i]);
180e705c121SKalle Valo max_sleep[IWL_POWER_VEC_SIZE - 1] = skip + 1;
181e705c121SKalle Valo }
182e705c121SKalle Valo
183e705c121SKalle Valo slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
184e705c121SKalle Valo /* figure out the listen interval based on dtim period and skip */
185e705c121SKalle Valo if (slp_itrvl == 0xFF)
186e705c121SKalle Valo cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
187e705c121SKalle Valo cpu_to_le32(period * (skip + 1));
188e705c121SKalle Valo
189e705c121SKalle Valo slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
190e705c121SKalle Valo if (slp_itrvl > period)
191e705c121SKalle Valo cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
192e705c121SKalle Valo cpu_to_le32((slp_itrvl / period) * period);
193e705c121SKalle Valo
194e705c121SKalle Valo if (skip)
195e705c121SKalle Valo cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
196e705c121SKalle Valo else
197e705c121SKalle Valo cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
198e705c121SKalle Valo
199*7d34a7d7SLuca Coelho if (priv->trans->trans_cfg->base_params->shadow_reg_enable)
200e705c121SKalle Valo cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
201e705c121SKalle Valo else
202e705c121SKalle Valo cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
203e705c121SKalle Valo
204e705c121SKalle Valo if (iwl_advanced_bt_coexist(priv)) {
205e705c121SKalle Valo if (!priv->lib->bt_params->bt_sco_disable)
206e705c121SKalle Valo cmd->flags |= IWL_POWER_BT_SCO_ENA;
207e705c121SKalle Valo else
208e705c121SKalle Valo cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
209e705c121SKalle Valo }
210e705c121SKalle Valo
211e705c121SKalle Valo
212e705c121SKalle Valo slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
213e705c121SKalle Valo if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
214e705c121SKalle Valo cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
215e705c121SKalle Valo cpu_to_le32(IWL_CONN_MAX_LISTEN_INTERVAL);
216e705c121SKalle Valo
217e705c121SKalle Valo /* enforce max sleep interval */
218e705c121SKalle Valo for (i = IWL_POWER_VEC_SIZE - 1; i >= 0 ; i--) {
219e705c121SKalle Valo if (le32_to_cpu(cmd->sleep_interval[i]) >
220e705c121SKalle Valo (max_sleep[i] * period))
221e705c121SKalle Valo cmd->sleep_interval[i] =
222e705c121SKalle Valo cpu_to_le32(max_sleep[i] * period);
223e705c121SKalle Valo if (i != (IWL_POWER_VEC_SIZE - 1)) {
224e705c121SKalle Valo if (le32_to_cpu(cmd->sleep_interval[i]) >
225e705c121SKalle Valo le32_to_cpu(cmd->sleep_interval[i+1]))
226e705c121SKalle Valo cmd->sleep_interval[i] =
227e705c121SKalle Valo cmd->sleep_interval[i+1];
228e705c121SKalle Valo }
229e705c121SKalle Valo }
230e705c121SKalle Valo
231e705c121SKalle Valo if (priv->power_data.bus_pm)
232e705c121SKalle Valo cmd->flags |= IWL_POWER_PCI_PM_MSK;
233e705c121SKalle Valo else
234e705c121SKalle Valo cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
235e705c121SKalle Valo
236e705c121SKalle Valo IWL_DEBUG_POWER(priv, "numSkipDtim = %u, dtimPeriod = %d\n",
237e705c121SKalle Valo skip, period);
238e705c121SKalle Valo /* The power level here is 0-4 (used as array index), but user expects
239e705c121SKalle Valo to see 1-5 (according to spec). */
240e705c121SKalle Valo IWL_DEBUG_POWER(priv, "Sleep command for index %d\n", lvl + 1);
241e705c121SKalle Valo }
242e705c121SKalle Valo
iwl_power_sleep_cam_cmd(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd)243e705c121SKalle Valo static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
244e705c121SKalle Valo struct iwl_powertable_cmd *cmd)
245e705c121SKalle Valo {
246e705c121SKalle Valo memset(cmd, 0, sizeof(*cmd));
247e705c121SKalle Valo
248e705c121SKalle Valo if (priv->power_data.bus_pm)
249e705c121SKalle Valo cmd->flags |= IWL_POWER_PCI_PM_MSK;
250e705c121SKalle Valo
251e705c121SKalle Valo IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
252e705c121SKalle Valo }
253e705c121SKalle Valo
iwl_set_power(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd)254e705c121SKalle Valo static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
255e705c121SKalle Valo {
256e705c121SKalle Valo IWL_DEBUG_POWER(priv, "Sending power/sleep command\n");
257e705c121SKalle Valo IWL_DEBUG_POWER(priv, "Flags value = 0x%08X\n", cmd->flags);
258e705c121SKalle Valo IWL_DEBUG_POWER(priv, "Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
259e705c121SKalle Valo IWL_DEBUG_POWER(priv, "Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
260e705c121SKalle Valo IWL_DEBUG_POWER(priv, "Sleep interval vector = { %d , %d , %d , %d , %d }\n",
261e705c121SKalle Valo le32_to_cpu(cmd->sleep_interval[0]),
262e705c121SKalle Valo le32_to_cpu(cmd->sleep_interval[1]),
263e705c121SKalle Valo le32_to_cpu(cmd->sleep_interval[2]),
264e705c121SKalle Valo le32_to_cpu(cmd->sleep_interval[3]),
265e705c121SKalle Valo le32_to_cpu(cmd->sleep_interval[4]));
266e705c121SKalle Valo
267e705c121SKalle Valo return iwl_dvm_send_cmd_pdu(priv, POWER_TABLE_CMD, 0,
268e705c121SKalle Valo sizeof(struct iwl_powertable_cmd), cmd);
269e705c121SKalle Valo }
270e705c121SKalle Valo
iwl_power_build_cmd(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd)271e705c121SKalle Valo static void iwl_power_build_cmd(struct iwl_priv *priv,
272e705c121SKalle Valo struct iwl_powertable_cmd *cmd)
273e705c121SKalle Valo {
274e705c121SKalle Valo bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
275e705c121SKalle Valo int dtimper;
276e705c121SKalle Valo
277e705c121SKalle Valo if (force_cam) {
278e705c121SKalle Valo iwl_power_sleep_cam_cmd(priv, cmd);
279e705c121SKalle Valo return;
280e705c121SKalle Valo }
281e705c121SKalle Valo
282e705c121SKalle Valo dtimper = priv->hw->conf.ps_dtim_period ?: 1;
283e705c121SKalle Valo
284e705c121SKalle Valo if (priv->wowlan)
285e705c121SKalle Valo iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, dtimper);
286e705c121SKalle Valo else if (!priv->lib->no_idle_support &&
287e705c121SKalle Valo priv->hw->conf.flags & IEEE80211_CONF_IDLE)
288e705c121SKalle Valo iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
289e705c121SKalle Valo else if (iwl_tt_is_low_power_state(priv)) {
290e705c121SKalle Valo /* in thermal throttling low power state */
291e705c121SKalle Valo iwl_static_sleep_cmd(priv, cmd,
292e705c121SKalle Valo iwl_tt_current_power_mode(priv), dtimper);
293e705c121SKalle Valo } else if (!enabled)
294e705c121SKalle Valo iwl_power_sleep_cam_cmd(priv, cmd);
295e705c121SKalle Valo else if (priv->power_data.debug_sleep_level_override >= 0)
296e705c121SKalle Valo iwl_static_sleep_cmd(priv, cmd,
297e705c121SKalle Valo priv->power_data.debug_sleep_level_override,
298e705c121SKalle Valo dtimper);
299e705c121SKalle Valo else {
300e705c121SKalle Valo /* Note that the user parameter is 1-5 (according to spec),
301e705c121SKalle Valo but we pass 0-4 because it acts as an array index. */
302e705c121SKalle Valo if (iwlwifi_mod_params.power_level > IWL_POWER_INDEX_1 &&
303e705c121SKalle Valo iwlwifi_mod_params.power_level <= IWL_POWER_NUM)
304e705c121SKalle Valo iwl_static_sleep_cmd(priv, cmd,
305e705c121SKalle Valo iwlwifi_mod_params.power_level - 1, dtimper);
306e705c121SKalle Valo else
307e705c121SKalle Valo iwl_static_sleep_cmd(priv, cmd,
308e705c121SKalle Valo IWL_POWER_INDEX_1, dtimper);
309e705c121SKalle Valo }
310e705c121SKalle Valo }
311e705c121SKalle Valo
iwl_power_set_mode(struct iwl_priv * priv,struct iwl_powertable_cmd * cmd,bool force)312e705c121SKalle Valo int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
313e705c121SKalle Valo bool force)
314e705c121SKalle Valo {
315e705c121SKalle Valo int ret;
316e705c121SKalle Valo bool update_chains;
317e705c121SKalle Valo
318e705c121SKalle Valo lockdep_assert_held(&priv->mutex);
319e705c121SKalle Valo
320e705c121SKalle Valo /* Don't update the RX chain when chain noise calibration is running */
321e705c121SKalle Valo update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
322e705c121SKalle Valo priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
323e705c121SKalle Valo
324e705c121SKalle Valo if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
325e705c121SKalle Valo return 0;
326e705c121SKalle Valo
327e705c121SKalle Valo if (!iwl_is_ready_rf(priv))
328e705c121SKalle Valo return -EIO;
329e705c121SKalle Valo
330e705c121SKalle Valo /* scan complete use sleep_power_next, need to be updated */
331e705c121SKalle Valo memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
332e705c121SKalle Valo if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
333e705c121SKalle Valo IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
334e705c121SKalle Valo return 0;
335e705c121SKalle Valo }
336e705c121SKalle Valo
337e705c121SKalle Valo if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
338e705c121SKalle Valo iwl_dvm_set_pmi(priv, true);
339e705c121SKalle Valo
340e705c121SKalle Valo ret = iwl_set_power(priv, cmd);
341e705c121SKalle Valo if (!ret) {
342e705c121SKalle Valo if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
343e705c121SKalle Valo iwl_dvm_set_pmi(priv, false);
344e705c121SKalle Valo
345e705c121SKalle Valo if (update_chains)
346e705c121SKalle Valo iwl_update_chain_flags(priv);
347e705c121SKalle Valo else
348e705c121SKalle Valo IWL_DEBUG_POWER(priv,
349e705c121SKalle Valo "Cannot update the power, chain noise "
350e705c121SKalle Valo "calibration running: %d\n",
351e705c121SKalle Valo priv->chain_noise_data.state);
352e705c121SKalle Valo
353e705c121SKalle Valo memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
354e705c121SKalle Valo } else
355e705c121SKalle Valo IWL_ERR(priv, "set power fail, ret = %d\n", ret);
356e705c121SKalle Valo
357e705c121SKalle Valo return ret;
358e705c121SKalle Valo }
359e705c121SKalle Valo
iwl_power_update_mode(struct iwl_priv * priv,bool force)360e705c121SKalle Valo int iwl_power_update_mode(struct iwl_priv *priv, bool force)
361e705c121SKalle Valo {
362e705c121SKalle Valo struct iwl_powertable_cmd cmd;
363e705c121SKalle Valo
364e705c121SKalle Valo iwl_power_build_cmd(priv, &cmd);
365e705c121SKalle Valo return iwl_power_set_mode(priv, &cmd, force);
366e705c121SKalle Valo }
367e705c121SKalle Valo
368e705c121SKalle Valo /* initialize to default */
iwl_power_initialize(struct iwl_priv * priv)369e705c121SKalle Valo void iwl_power_initialize(struct iwl_priv *priv)
370e705c121SKalle Valo {
371e705c121SKalle Valo priv->power_data.bus_pm = priv->trans->pm_support;
372e705c121SKalle Valo
373e705c121SKalle Valo priv->power_data.debug_sleep_level_override = -1;
374e705c121SKalle Valo
375e705c121SKalle Valo memset(&priv->power_data.sleep_cmd, 0,
376e705c121SKalle Valo sizeof(priv->power_data.sleep_cmd));
377e705c121SKalle Valo }
378