xref: /openbmc/linux/drivers/net/wireless/intel/iwlwifi/dvm/commands.h (revision 03ab8e6297acd1bc0eedaa050e2a1635c576fd11)
18e99ea8dSJohannes Berg /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28e99ea8dSJohannes Berg /*
38e99ea8dSJohannes Berg  * Copyright (C) 2005-2014 Intel Corporation
48e99ea8dSJohannes Berg  */
5e705c121SKalle Valo /*
6e705c121SKalle Valo  * Please use this file (commands.h) only for uCode API definitions.
7e705c121SKalle Valo  * Please use iwl-xxxx-hw.h for hardware-related definitions.
8e705c121SKalle Valo  * Please use dev.h for driver implementation definitions.
9e705c121SKalle Valo  */
10e705c121SKalle Valo 
11e705c121SKalle Valo #ifndef __iwl_commands_h__
12e705c121SKalle Valo #define __iwl_commands_h__
13e705c121SKalle Valo 
14e705c121SKalle Valo #include <linux/ieee80211.h>
15e705c121SKalle Valo #include <linux/types.h>
16e705c121SKalle Valo 
17e705c121SKalle Valo 
18e705c121SKalle Valo enum {
19e705c121SKalle Valo 	REPLY_ALIVE = 0x1,
20e705c121SKalle Valo 	REPLY_ERROR = 0x2,
21e705c121SKalle Valo 	REPLY_ECHO = 0x3,		/* test command */
22e705c121SKalle Valo 
23e705c121SKalle Valo 	/* RXON and QOS commands */
24e705c121SKalle Valo 	REPLY_RXON = 0x10,
25e705c121SKalle Valo 	REPLY_RXON_ASSOC = 0x11,
26e705c121SKalle Valo 	REPLY_QOS_PARAM = 0x13,
27e705c121SKalle Valo 	REPLY_RXON_TIMING = 0x14,
28e705c121SKalle Valo 
29e705c121SKalle Valo 	/* Multi-Station support */
30e705c121SKalle Valo 	REPLY_ADD_STA = 0x18,
31e705c121SKalle Valo 	REPLY_REMOVE_STA = 0x19,
32e705c121SKalle Valo 	REPLY_REMOVE_ALL_STA = 0x1a,	/* not used */
33e705c121SKalle Valo 	REPLY_TXFIFO_FLUSH = 0x1e,
34e705c121SKalle Valo 
35e705c121SKalle Valo 	/* Security */
36e705c121SKalle Valo 	REPLY_WEPKEY = 0x20,
37e705c121SKalle Valo 
38e705c121SKalle Valo 	/* RX, TX, LEDs */
39e705c121SKalle Valo 	REPLY_TX = 0x1c,
40e705c121SKalle Valo 	REPLY_LEDS_CMD = 0x48,
41e705c121SKalle Valo 	REPLY_TX_LINK_QUALITY_CMD = 0x4e,
42e705c121SKalle Valo 
43e705c121SKalle Valo 	/* WiMAX coexistence */
44e705c121SKalle Valo 	COEX_PRIORITY_TABLE_CMD = 0x5a,
45e705c121SKalle Valo 	COEX_MEDIUM_NOTIFICATION = 0x5b,
46e705c121SKalle Valo 	COEX_EVENT_CMD = 0x5c,
47e705c121SKalle Valo 
48e705c121SKalle Valo 	/* Calibration */
49e705c121SKalle Valo 	TEMPERATURE_NOTIFICATION = 0x62,
50e705c121SKalle Valo 	CALIBRATION_CFG_CMD = 0x65,
51e705c121SKalle Valo 	CALIBRATION_RES_NOTIFICATION = 0x66,
52e705c121SKalle Valo 	CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
53e705c121SKalle Valo 
54e705c121SKalle Valo 	/* 802.11h related */
55e705c121SKalle Valo 	REPLY_QUIET_CMD = 0x71,		/* not used */
56e705c121SKalle Valo 	REPLY_CHANNEL_SWITCH = 0x72,
57e705c121SKalle Valo 	CHANNEL_SWITCH_NOTIFICATION = 0x73,
58e705c121SKalle Valo 	REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74,
59e705c121SKalle Valo 	SPECTRUM_MEASURE_NOTIFICATION = 0x75,
60e705c121SKalle Valo 
61e705c121SKalle Valo 	/* Power Management */
62e705c121SKalle Valo 	POWER_TABLE_CMD = 0x77,
63e705c121SKalle Valo 	PM_SLEEP_NOTIFICATION = 0x7A,
64e705c121SKalle Valo 	PM_DEBUG_STATISTIC_NOTIFIC = 0x7B,
65e705c121SKalle Valo 
66e705c121SKalle Valo 	/* Scan commands and notifications */
67e705c121SKalle Valo 	REPLY_SCAN_CMD = 0x80,
68e705c121SKalle Valo 	REPLY_SCAN_ABORT_CMD = 0x81,
69e705c121SKalle Valo 	SCAN_START_NOTIFICATION = 0x82,
70e705c121SKalle Valo 	SCAN_RESULTS_NOTIFICATION = 0x83,
71e705c121SKalle Valo 	SCAN_COMPLETE_NOTIFICATION = 0x84,
72e705c121SKalle Valo 
73e705c121SKalle Valo 	/* IBSS/AP commands */
74e705c121SKalle Valo 	BEACON_NOTIFICATION = 0x90,
75e705c121SKalle Valo 	REPLY_TX_BEACON = 0x91,
76e705c121SKalle Valo 	WHO_IS_AWAKE_NOTIFICATION = 0x94,	/* not used */
77e705c121SKalle Valo 
78e705c121SKalle Valo 	/* Miscellaneous commands */
79e705c121SKalle Valo 	REPLY_TX_POWER_DBM_CMD = 0x95,
80e705c121SKalle Valo 	QUIET_NOTIFICATION = 0x96,		/* not used */
81e705c121SKalle Valo 	REPLY_TX_PWR_TABLE_CMD = 0x97,
82e705c121SKalle Valo 	REPLY_TX_POWER_DBM_CMD_V1 = 0x98,	/* old version of API */
83e705c121SKalle Valo 	TX_ANT_CONFIGURATION_CMD = 0x98,
84e705c121SKalle Valo 	MEASURE_ABORT_NOTIFICATION = 0x99,	/* not used */
85e705c121SKalle Valo 
86e705c121SKalle Valo 	/* Bluetooth device coexistence config command */
87e705c121SKalle Valo 	REPLY_BT_CONFIG = 0x9b,
88e705c121SKalle Valo 
89e705c121SKalle Valo 	/* Statistics */
90e705c121SKalle Valo 	REPLY_STATISTICS_CMD = 0x9c,
91e705c121SKalle Valo 	STATISTICS_NOTIFICATION = 0x9d,
92e705c121SKalle Valo 
93e705c121SKalle Valo 	/* RF-KILL commands and notifications */
94e705c121SKalle Valo 	REPLY_CARD_STATE_CMD = 0xa0,
95e705c121SKalle Valo 	CARD_STATE_NOTIFICATION = 0xa1,
96e705c121SKalle Valo 
97e705c121SKalle Valo 	/* Missed beacons notification */
98e705c121SKalle Valo 	MISSED_BEACONS_NOTIFICATION = 0xa2,
99e705c121SKalle Valo 
100e705c121SKalle Valo 	REPLY_CT_KILL_CONFIG_CMD = 0xa4,
101e705c121SKalle Valo 	SENSITIVITY_CMD = 0xa8,
102e705c121SKalle Valo 	REPLY_PHY_CALIBRATION_CMD = 0xb0,
103e705c121SKalle Valo 	REPLY_RX_PHY_CMD = 0xc0,
104e705c121SKalle Valo 	REPLY_RX_MPDU_CMD = 0xc1,
105e705c121SKalle Valo 	REPLY_RX = 0xc3,
106e705c121SKalle Valo 	REPLY_COMPRESSED_BA = 0xc5,
107e705c121SKalle Valo 
108e705c121SKalle Valo 	/* BT Coex */
109e705c121SKalle Valo 	REPLY_BT_COEX_PRIO_TABLE = 0xcc,
110e705c121SKalle Valo 	REPLY_BT_COEX_PROT_ENV = 0xcd,
111e705c121SKalle Valo 	REPLY_BT_COEX_PROFILE_NOTIF = 0xce,
112e705c121SKalle Valo 
113e705c121SKalle Valo 	/* PAN commands */
114e705c121SKalle Valo 	REPLY_WIPAN_PARAMS = 0xb2,
115e705c121SKalle Valo 	REPLY_WIPAN_RXON = 0xb3,	/* use REPLY_RXON structure */
116e705c121SKalle Valo 	REPLY_WIPAN_RXON_TIMING = 0xb4,	/* use REPLY_RXON_TIMING structure */
117e705c121SKalle Valo 	REPLY_WIPAN_RXON_ASSOC = 0xb6,	/* use REPLY_RXON_ASSOC structure */
118e705c121SKalle Valo 	REPLY_WIPAN_QOS_PARAM = 0xb7,	/* use REPLY_QOS_PARAM structure */
119e705c121SKalle Valo 	REPLY_WIPAN_WEPKEY = 0xb8,	/* use REPLY_WEPKEY structure */
120e705c121SKalle Valo 	REPLY_WIPAN_P2P_CHANNEL_SWITCH = 0xb9,
121e705c121SKalle Valo 	REPLY_WIPAN_NOA_NOTIFICATION = 0xbc,
122e705c121SKalle Valo 	REPLY_WIPAN_DEACTIVATION_COMPLETE = 0xbd,
123e705c121SKalle Valo 
124e705c121SKalle Valo 	REPLY_WOWLAN_PATTERNS = 0xe0,
125e705c121SKalle Valo 	REPLY_WOWLAN_WAKEUP_FILTER = 0xe1,
126e705c121SKalle Valo 	REPLY_WOWLAN_TSC_RSC_PARAMS = 0xe2,
127e705c121SKalle Valo 	REPLY_WOWLAN_TKIP_PARAMS = 0xe3,
128e705c121SKalle Valo 	REPLY_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
129e705c121SKalle Valo 	REPLY_WOWLAN_GET_STATUS = 0xe5,
130e705c121SKalle Valo 	REPLY_D3_CONFIG = 0xd3,
131e705c121SKalle Valo 
132e705c121SKalle Valo 	REPLY_MAX = 0xff
133e705c121SKalle Valo };
134e705c121SKalle Valo 
135e705c121SKalle Valo /*
136e705c121SKalle Valo  * Minimum number of queues. MAX_NUM is defined in hw specific files.
137e705c121SKalle Valo  * Set the minimum to accommodate
138e705c121SKalle Valo  *  - 4 standard TX queues
139e705c121SKalle Valo  *  - the command queue
140e705c121SKalle Valo  *  - 4 PAN TX queues
141e705c121SKalle Valo  *  - the PAN multicast queue, and
142e705c121SKalle Valo  *  - the AUX (TX during scan dwell) queue.
143e705c121SKalle Valo  */
144e705c121SKalle Valo #define IWL_MIN_NUM_QUEUES	11
145e705c121SKalle Valo 
146e705c121SKalle Valo /*
147e705c121SKalle Valo  * Command queue depends on iPAN support.
148e705c121SKalle Valo  */
149e705c121SKalle Valo #define IWL_DEFAULT_CMD_QUEUE_NUM	4
150e705c121SKalle Valo #define IWL_IPAN_CMD_QUEUE_NUM		9
151e705c121SKalle Valo 
152e705c121SKalle Valo #define IWL_TX_FIFO_BK		0	/* shared */
153e705c121SKalle Valo #define IWL_TX_FIFO_BE		1
154e705c121SKalle Valo #define IWL_TX_FIFO_VI		2	/* shared */
155e705c121SKalle Valo #define IWL_TX_FIFO_VO		3
156e705c121SKalle Valo #define IWL_TX_FIFO_BK_IPAN	IWL_TX_FIFO_BK
157e705c121SKalle Valo #define IWL_TX_FIFO_BE_IPAN	4
158e705c121SKalle Valo #define IWL_TX_FIFO_VI_IPAN	IWL_TX_FIFO_VI
159e705c121SKalle Valo #define IWL_TX_FIFO_VO_IPAN	5
160e705c121SKalle Valo /* re-uses the VO FIFO, uCode will properly flush/schedule */
161e705c121SKalle Valo #define IWL_TX_FIFO_AUX		5
162e705c121SKalle Valo #define IWL_TX_FIFO_UNUSED	255
163e705c121SKalle Valo 
164e705c121SKalle Valo #define IWLAGN_CMD_FIFO_NUM	7
165e705c121SKalle Valo 
166e705c121SKalle Valo /*
167e705c121SKalle Valo  * This queue number is required for proper operation
168e705c121SKalle Valo  * because the ucode will stop/start the scheduler as
169e705c121SKalle Valo  * required.
170e705c121SKalle Valo  */
171e705c121SKalle Valo #define IWL_IPAN_MCAST_QUEUE	8
172e705c121SKalle Valo 
173e705c121SKalle Valo /******************************************************************************
174e705c121SKalle Valo  * (0)
175e705c121SKalle Valo  * Commonly used structures and definitions:
176e705c121SKalle Valo  * Command header, rate_n_flags, txpower
177e705c121SKalle Valo  *
178e705c121SKalle Valo  *****************************************************************************/
179e705c121SKalle Valo 
180e705c121SKalle Valo /**
181e705c121SKalle Valo  * iwlagn rate_n_flags bit fields
182e705c121SKalle Valo  *
183e705c121SKalle Valo  * rate_n_flags format is used in following iwlagn commands:
184e705c121SKalle Valo  *  REPLY_RX (response only)
185e705c121SKalle Valo  *  REPLY_RX_MPDU (response only)
186e705c121SKalle Valo  *  REPLY_TX (both command and response)
187e705c121SKalle Valo  *  REPLY_TX_LINK_QUALITY_CMD
188e705c121SKalle Valo  *
189e705c121SKalle Valo  * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"):
190e705c121SKalle Valo  *  2-0:  0)   6 Mbps
191e705c121SKalle Valo  *        1)  12 Mbps
192e705c121SKalle Valo  *        2)  18 Mbps
193e705c121SKalle Valo  *        3)  24 Mbps
194e705c121SKalle Valo  *        4)  36 Mbps
195e705c121SKalle Valo  *        5)  48 Mbps
196e705c121SKalle Valo  *        6)  54 Mbps
197e705c121SKalle Valo  *        7)  60 Mbps
198e705c121SKalle Valo  *
199e705c121SKalle Valo  *  4-3:  0)  Single stream (SISO)
200e705c121SKalle Valo  *        1)  Dual stream (MIMO)
201e705c121SKalle Valo  *        2)  Triple stream (MIMO)
202e705c121SKalle Valo  *
203e705c121SKalle Valo  *    5:  Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
204e705c121SKalle Valo  *
205e705c121SKalle Valo  * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"):
206e705c121SKalle Valo  *  3-0:  0xD)   6 Mbps
207e705c121SKalle Valo  *        0xF)   9 Mbps
208e705c121SKalle Valo  *        0x5)  12 Mbps
209e705c121SKalle Valo  *        0x7)  18 Mbps
210e705c121SKalle Valo  *        0x9)  24 Mbps
211e705c121SKalle Valo  *        0xB)  36 Mbps
212e705c121SKalle Valo  *        0x1)  48 Mbps
213e705c121SKalle Valo  *        0x3)  54 Mbps
214e705c121SKalle Valo  *
215e705c121SKalle Valo  * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"):
216e705c121SKalle Valo  *  6-0:   10)  1 Mbps
217e705c121SKalle Valo  *         20)  2 Mbps
218e705c121SKalle Valo  *         55)  5.5 Mbps
219e705c121SKalle Valo  *        110)  11 Mbps
220e705c121SKalle Valo  */
221e705c121SKalle Valo #define RATE_MCS_CODE_MSK 0x7
222e705c121SKalle Valo #define RATE_MCS_SPATIAL_POS 3
223e705c121SKalle Valo #define RATE_MCS_SPATIAL_MSK 0x18
224e705c121SKalle Valo #define RATE_MCS_HT_DUP_POS 5
225e705c121SKalle Valo #define RATE_MCS_HT_DUP_MSK 0x20
226e705c121SKalle Valo /* Both legacy and HT use bits 7:0 as the CCK/OFDM rate or HT MCS */
227e705c121SKalle Valo #define RATE_MCS_RATE_MSK 0xff
228e705c121SKalle Valo 
229e705c121SKalle Valo /* Bit 8: (1) HT format, (0) legacy format in bits 7:0 */
230e705c121SKalle Valo #define RATE_MCS_FLAGS_POS 8
231e705c121SKalle Valo #define RATE_MCS_HT_POS 8
232e705c121SKalle Valo #define RATE_MCS_HT_MSK 0x100
233e705c121SKalle Valo 
234e705c121SKalle Valo /* Bit 9: (1) CCK, (0) OFDM.  HT (bit 8) must be "0" for this bit to be valid */
235e705c121SKalle Valo #define RATE_MCS_CCK_POS 9
236e705c121SKalle Valo #define RATE_MCS_CCK_MSK 0x200
237e705c121SKalle Valo 
238e705c121SKalle Valo /* Bit 10: (1) Use Green Field preamble */
239e705c121SKalle Valo #define RATE_MCS_GF_POS 10
240e705c121SKalle Valo #define RATE_MCS_GF_MSK 0x400
241e705c121SKalle Valo 
242e705c121SKalle Valo /* Bit 11: (1) Use 40Mhz HT40 chnl width, (0) use 20 MHz legacy chnl width */
243e705c121SKalle Valo #define RATE_MCS_HT40_POS 11
244e705c121SKalle Valo #define RATE_MCS_HT40_MSK 0x800
245e705c121SKalle Valo 
246e705c121SKalle Valo /* Bit 12: (1) Duplicate data on both 20MHz chnls. HT40 (bit 11) must be set. */
247e705c121SKalle Valo #define RATE_MCS_DUP_POS 12
248e705c121SKalle Valo #define RATE_MCS_DUP_MSK 0x1000
249e705c121SKalle Valo 
250e705c121SKalle Valo /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
251e705c121SKalle Valo #define RATE_MCS_SGI_POS 13
252e705c121SKalle Valo #define RATE_MCS_SGI_MSK 0x2000
253e705c121SKalle Valo 
254e705c121SKalle Valo /**
255e705c121SKalle Valo  * rate_n_flags Tx antenna masks
256e705c121SKalle Valo  * bit14:16
257e705c121SKalle Valo  */
258e705c121SKalle Valo #define RATE_MCS_ANT_POS	14
259e705c121SKalle Valo #define RATE_MCS_ANT_A_MSK	0x04000
260e705c121SKalle Valo #define RATE_MCS_ANT_B_MSK	0x08000
261e705c121SKalle Valo #define RATE_MCS_ANT_C_MSK	0x10000
262e705c121SKalle Valo #define RATE_MCS_ANT_AB_MSK	(RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK)
263e705c121SKalle Valo #define RATE_MCS_ANT_ABC_MSK	(RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK)
264e705c121SKalle Valo #define RATE_ANT_NUM 3
265e705c121SKalle Valo 
266e705c121SKalle Valo #define POWER_TABLE_NUM_ENTRIES			33
267e705c121SKalle Valo #define POWER_TABLE_NUM_HT_OFDM_ENTRIES		32
268e705c121SKalle Valo #define POWER_TABLE_CCK_ENTRY			32
269e705c121SKalle Valo 
270e705c121SKalle Valo #define IWL_PWR_NUM_HT_OFDM_ENTRIES		24
271e705c121SKalle Valo #define IWL_PWR_CCK_ENTRIES			2
272e705c121SKalle Valo 
273e705c121SKalle Valo /**
274e705c121SKalle Valo  * struct tx_power_dual_stream
275e705c121SKalle Valo  *
276e705c121SKalle Valo  * Table entries in REPLY_TX_PWR_TABLE_CMD, REPLY_CHANNEL_SWITCH
277e705c121SKalle Valo  *
278e705c121SKalle Valo  * Same format as iwl_tx_power_dual_stream, but __le32
279e705c121SKalle Valo  */
280e705c121SKalle Valo struct tx_power_dual_stream {
281e705c121SKalle Valo 	__le32 dw;
282e705c121SKalle Valo } __packed;
283e705c121SKalle Valo 
284e705c121SKalle Valo /**
285e705c121SKalle Valo  * Command REPLY_TX_POWER_DBM_CMD = 0x98
286e705c121SKalle Valo  * struct iwlagn_tx_power_dbm_cmd
287e705c121SKalle Valo  */
288e705c121SKalle Valo #define IWLAGN_TX_POWER_AUTO 0x7f
289e705c121SKalle Valo #define IWLAGN_TX_POWER_NO_CLOSED (0x1 << 6)
290e705c121SKalle Valo 
291e705c121SKalle Valo struct iwlagn_tx_power_dbm_cmd {
292e705c121SKalle Valo 	s8 global_lmt; /*in half-dBm (e.g. 30 = 15 dBm) */
293e705c121SKalle Valo 	u8 flags;
294e705c121SKalle Valo 	s8 srv_chan_lmt; /*in half-dBm (e.g. 30 = 15 dBm) */
295e705c121SKalle Valo 	u8 reserved;
296e705c121SKalle Valo } __packed;
297e705c121SKalle Valo 
298e705c121SKalle Valo /**
299e705c121SKalle Valo  * Command TX_ANT_CONFIGURATION_CMD = 0x98
300e705c121SKalle Valo  * This command is used to configure valid Tx antenna.
301e705c121SKalle Valo  * By default uCode concludes the valid antenna according to the radio flavor.
302e705c121SKalle Valo  * This command enables the driver to override/modify this conclusion.
303e705c121SKalle Valo  */
304e705c121SKalle Valo struct iwl_tx_ant_config_cmd {
305e705c121SKalle Valo 	__le32 valid;
306e705c121SKalle Valo } __packed;
307e705c121SKalle Valo 
308e705c121SKalle Valo /******************************************************************************
309e705c121SKalle Valo  * (0a)
310e705c121SKalle Valo  * Alive and Error Commands & Responses:
311e705c121SKalle Valo  *
312e705c121SKalle Valo  *****************************************************************************/
313e705c121SKalle Valo 
314e705c121SKalle Valo #define UCODE_VALID_OK	cpu_to_le32(0x1)
315e705c121SKalle Valo 
316e705c121SKalle Valo /**
317e705c121SKalle Valo  * REPLY_ALIVE = 0x1 (response only, not a command)
318e705c121SKalle Valo  *
319e705c121SKalle Valo  * uCode issues this "alive" notification once the runtime image is ready
320e705c121SKalle Valo  * to receive commands from the driver.  This is the *second* "alive"
321e705c121SKalle Valo  * notification that the driver will receive after rebooting uCode;
322e705c121SKalle Valo  * this "alive" is indicated by subtype field != 9.
323e705c121SKalle Valo  *
324e705c121SKalle Valo  * See comments documenting "BSM" (bootstrap state machine).
325e705c121SKalle Valo  *
326e705c121SKalle Valo  * This response includes two pointers to structures within the device's
327e705c121SKalle Valo  * data SRAM (access via HBUS_TARG_MEM_* regs) that are useful for debugging:
328e705c121SKalle Valo  *
329e705c121SKalle Valo  * 1)  log_event_table_ptr indicates base of the event log.  This traces
330e705c121SKalle Valo  *     a 256-entry history of uCode execution within a circular buffer.
331e705c121SKalle Valo  *     Its header format is:
332e705c121SKalle Valo  *
333e705c121SKalle Valo  *	__le32 log_size;     log capacity (in number of entries)
334e705c121SKalle Valo  *	__le32 type;         (1) timestamp with each entry, (0) no timestamp
335e705c121SKalle Valo  *	__le32 wraps;        # times uCode has wrapped to top of circular buffer
336e705c121SKalle Valo  *      __le32 write_index;  next circular buffer entry that uCode would fill
337e705c121SKalle Valo  *
338e705c121SKalle Valo  *     The header is followed by the circular buffer of log entries.  Entries
339e705c121SKalle Valo  *     with timestamps have the following format:
340e705c121SKalle Valo  *
341e705c121SKalle Valo  *	__le32 event_id;     range 0 - 1500
342e705c121SKalle Valo  *	__le32 timestamp;    low 32 bits of TSF (of network, if associated)
343e705c121SKalle Valo  *	__le32 data;         event_id-specific data value
344e705c121SKalle Valo  *
345e705c121SKalle Valo  *     Entries without timestamps contain only event_id and data.
346e705c121SKalle Valo  *
347e705c121SKalle Valo  *
348e705c121SKalle Valo  * 2)  error_event_table_ptr indicates base of the error log.  This contains
349e705c121SKalle Valo  *     information about any uCode error that occurs.  For agn, the format
350e705c121SKalle Valo  *     of the error log is defined by struct iwl_error_event_table.
351e705c121SKalle Valo  *
352e705c121SKalle Valo  * The Linux driver can print both logs to the system log when a uCode error
353e705c121SKalle Valo  * occurs.
354e705c121SKalle Valo  */
355e705c121SKalle Valo 
356e705c121SKalle Valo /*
357e705c121SKalle Valo  * Note: This structure is read from the device with IO accesses,
358e705c121SKalle Valo  * and the reading already does the endian conversion. As it is
359e705c121SKalle Valo  * read with u32-sized accesses, any members with a different size
360e705c121SKalle Valo  * need to be ordered correctly though!
361e705c121SKalle Valo  */
362e705c121SKalle Valo struct iwl_error_event_table {
363e705c121SKalle Valo 	u32 valid;		/* (nonzero) valid, (0) log is empty */
364e705c121SKalle Valo 	u32 error_id;		/* type of error */
365e705c121SKalle Valo 	u32 pc;			/* program counter */
366e705c121SKalle Valo 	u32 blink1;		/* branch link */
367e705c121SKalle Valo 	u32 blink2;		/* branch link */
368e705c121SKalle Valo 	u32 ilink1;		/* interrupt link */
369e705c121SKalle Valo 	u32 ilink2;		/* interrupt link */
370e705c121SKalle Valo 	u32 data1;		/* error-specific data */
371e705c121SKalle Valo 	u32 data2;		/* error-specific data */
372e705c121SKalle Valo 	u32 line;		/* source code line of error */
373e705c121SKalle Valo 	u32 bcon_time;		/* beacon timer */
374e705c121SKalle Valo 	u32 tsf_low;		/* network timestamp function timer */
375e705c121SKalle Valo 	u32 tsf_hi;		/* network timestamp function timer */
376e705c121SKalle Valo 	u32 gp1;		/* GP1 timer register */
377e705c121SKalle Valo 	u32 gp2;		/* GP2 timer register */
378e705c121SKalle Valo 	u32 gp3;		/* GP3 timer register */
379e705c121SKalle Valo 	u32 ucode_ver;		/* uCode version */
380e705c121SKalle Valo 	u32 hw_ver;		/* HW Silicon version */
381e705c121SKalle Valo 	u32 brd_ver;		/* HW board version */
382e705c121SKalle Valo 	u32 log_pc;		/* log program counter */
383e705c121SKalle Valo 	u32 frame_ptr;		/* frame pointer */
384e705c121SKalle Valo 	u32 stack_ptr;		/* stack pointer */
385e705c121SKalle Valo 	u32 hcmd;		/* last host command header */
386e705c121SKalle Valo 	u32 isr0;		/* isr status register LMPM_NIC_ISR0:
387e705c121SKalle Valo 				 * rxtx_flag */
388e705c121SKalle Valo 	u32 isr1;		/* isr status register LMPM_NIC_ISR1:
389e705c121SKalle Valo 				 * host_flag */
390e705c121SKalle Valo 	u32 isr2;		/* isr status register LMPM_NIC_ISR2:
391e705c121SKalle Valo 				 * enc_flag */
392e705c121SKalle Valo 	u32 isr3;		/* isr status register LMPM_NIC_ISR3:
393e705c121SKalle Valo 				 * time_flag */
394e705c121SKalle Valo 	u32 isr4;		/* isr status register LMPM_NIC_ISR4:
395e705c121SKalle Valo 				 * wico interrupt */
396e705c121SKalle Valo 	u32 isr_pref;		/* isr status register LMPM_NIC_PREF_STAT */
397e705c121SKalle Valo 	u32 wait_event;		/* wait event() caller address */
398e705c121SKalle Valo 	u32 l2p_control;	/* L2pControlField */
399e705c121SKalle Valo 	u32 l2p_duration;	/* L2pDurationField */
400e705c121SKalle Valo 	u32 l2p_mhvalid;	/* L2pMhValidBits */
401e705c121SKalle Valo 	u32 l2p_addr_match;	/* L2pAddrMatchStat */
402e705c121SKalle Valo 	u32 lmpm_pmg_sel;	/* indicate which clocks are turned on
403e705c121SKalle Valo 				 * (LMPM_PMG_SEL) */
404e705c121SKalle Valo 	u32 u_timestamp;	/* indicate when the date and time of the
405e705c121SKalle Valo 				 * compilation */
406e705c121SKalle Valo 	u32 flow_handler;	/* FH read/write pointers, RX credit */
407e705c121SKalle Valo } __packed;
408e705c121SKalle Valo 
409e705c121SKalle Valo struct iwl_alive_resp {
410e705c121SKalle Valo 	u8 ucode_minor;
411e705c121SKalle Valo 	u8 ucode_major;
412e705c121SKalle Valo 	__le16 reserved1;
413e705c121SKalle Valo 	u8 sw_rev[8];
414e705c121SKalle Valo 	u8 ver_type;
415e705c121SKalle Valo 	u8 ver_subtype;			/* not "9" for runtime alive */
416e705c121SKalle Valo 	__le16 reserved2;
417e705c121SKalle Valo 	__le32 log_event_table_ptr;	/* SRAM address for event log */
418e705c121SKalle Valo 	__le32 error_event_table_ptr;	/* SRAM address for error log */
419e705c121SKalle Valo 	__le32 timestamp;
420e705c121SKalle Valo 	__le32 is_valid;
421e705c121SKalle Valo } __packed;
422e705c121SKalle Valo 
423e705c121SKalle Valo /*
424e705c121SKalle Valo  * REPLY_ERROR = 0x2 (response only, not a command)
425e705c121SKalle Valo  */
426e705c121SKalle Valo struct iwl_error_resp {
427e705c121SKalle Valo 	__le32 error_type;
428e705c121SKalle Valo 	u8 cmd_id;
429e705c121SKalle Valo 	u8 reserved1;
430e705c121SKalle Valo 	__le16 bad_cmd_seq_num;
431e705c121SKalle Valo 	__le32 error_info;
432e705c121SKalle Valo 	__le64 timestamp;
433e705c121SKalle Valo } __packed;
434e705c121SKalle Valo 
435e705c121SKalle Valo /******************************************************************************
436e705c121SKalle Valo  * (1)
437e705c121SKalle Valo  * RXON Commands & Responses:
438e705c121SKalle Valo  *
439e705c121SKalle Valo  *****************************************************************************/
440e705c121SKalle Valo 
441e705c121SKalle Valo /*
442e705c121SKalle Valo  * Rx config defines & structure
443e705c121SKalle Valo  */
444e705c121SKalle Valo /* rx_config device types  */
445e705c121SKalle Valo enum {
446e705c121SKalle Valo 	RXON_DEV_TYPE_AP = 1,
447e705c121SKalle Valo 	RXON_DEV_TYPE_ESS = 3,
448e705c121SKalle Valo 	RXON_DEV_TYPE_IBSS = 4,
449e705c121SKalle Valo 	RXON_DEV_TYPE_SNIFFER = 6,
450e705c121SKalle Valo 	RXON_DEV_TYPE_CP = 7,
451e705c121SKalle Valo 	RXON_DEV_TYPE_2STA = 8,
452e705c121SKalle Valo 	RXON_DEV_TYPE_P2P = 9,
453e705c121SKalle Valo };
454e705c121SKalle Valo 
455e705c121SKalle Valo 
456e705c121SKalle Valo #define RXON_RX_CHAIN_DRIVER_FORCE_MSK		cpu_to_le16(0x1 << 0)
457e705c121SKalle Valo #define RXON_RX_CHAIN_DRIVER_FORCE_POS		(0)
458e705c121SKalle Valo #define RXON_RX_CHAIN_VALID_MSK			cpu_to_le16(0x7 << 1)
459e705c121SKalle Valo #define RXON_RX_CHAIN_VALID_POS			(1)
460e705c121SKalle Valo #define RXON_RX_CHAIN_FORCE_SEL_MSK		cpu_to_le16(0x7 << 4)
461e705c121SKalle Valo #define RXON_RX_CHAIN_FORCE_SEL_POS		(4)
462e705c121SKalle Valo #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK	cpu_to_le16(0x7 << 7)
463e705c121SKalle Valo #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS	(7)
464e705c121SKalle Valo #define RXON_RX_CHAIN_CNT_MSK			cpu_to_le16(0x3 << 10)
465e705c121SKalle Valo #define RXON_RX_CHAIN_CNT_POS			(10)
466e705c121SKalle Valo #define RXON_RX_CHAIN_MIMO_CNT_MSK		cpu_to_le16(0x3 << 12)
467e705c121SKalle Valo #define RXON_RX_CHAIN_MIMO_CNT_POS		(12)
468e705c121SKalle Valo #define RXON_RX_CHAIN_MIMO_FORCE_MSK		cpu_to_le16(0x1 << 14)
469e705c121SKalle Valo #define RXON_RX_CHAIN_MIMO_FORCE_POS		(14)
470e705c121SKalle Valo 
471e705c121SKalle Valo /* rx_config flags */
472e705c121SKalle Valo /* band & modulation selection */
473e705c121SKalle Valo #define RXON_FLG_BAND_24G_MSK           cpu_to_le32(1 << 0)
474e705c121SKalle Valo #define RXON_FLG_CCK_MSK                cpu_to_le32(1 << 1)
475e705c121SKalle Valo /* auto detection enable */
476e705c121SKalle Valo #define RXON_FLG_AUTO_DETECT_MSK        cpu_to_le32(1 << 2)
477e705c121SKalle Valo /* TGg protection when tx */
478e705c121SKalle Valo #define RXON_FLG_TGG_PROTECT_MSK        cpu_to_le32(1 << 3)
479e705c121SKalle Valo /* cck short slot & preamble */
480e705c121SKalle Valo #define RXON_FLG_SHORT_SLOT_MSK          cpu_to_le32(1 << 4)
481e705c121SKalle Valo #define RXON_FLG_SHORT_PREAMBLE_MSK     cpu_to_le32(1 << 5)
482e705c121SKalle Valo /* antenna selection */
483e705c121SKalle Valo #define RXON_FLG_DIS_DIV_MSK            cpu_to_le32(1 << 7)
484e705c121SKalle Valo #define RXON_FLG_ANT_SEL_MSK            cpu_to_le32(0x0f00)
485e705c121SKalle Valo #define RXON_FLG_ANT_A_MSK              cpu_to_le32(1 << 8)
486e705c121SKalle Valo #define RXON_FLG_ANT_B_MSK              cpu_to_le32(1 << 9)
487e705c121SKalle Valo /* radar detection enable */
488e705c121SKalle Valo #define RXON_FLG_RADAR_DETECT_MSK       cpu_to_le32(1 << 12)
489e705c121SKalle Valo #define RXON_FLG_TGJ_NARROW_BAND_MSK    cpu_to_le32(1 << 13)
490e705c121SKalle Valo /* rx response to host with 8-byte TSF
491e705c121SKalle Valo * (according to ON_AIR deassertion) */
492e705c121SKalle Valo #define RXON_FLG_TSF2HOST_MSK           cpu_to_le32(1 << 15)
493e705c121SKalle Valo 
494e705c121SKalle Valo 
495e705c121SKalle Valo /* HT flags */
496e705c121SKalle Valo #define RXON_FLG_CTRL_CHANNEL_LOC_POS		(22)
497e705c121SKalle Valo #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK	cpu_to_le32(0x1 << 22)
498e705c121SKalle Valo 
499e705c121SKalle Valo #define RXON_FLG_HT_OPERATING_MODE_POS		(23)
500e705c121SKalle Valo 
501e705c121SKalle Valo #define RXON_FLG_HT_PROT_MSK			cpu_to_le32(0x1 << 23)
502e705c121SKalle Valo #define RXON_FLG_HT40_PROT_MSK			cpu_to_le32(0x2 << 23)
503e705c121SKalle Valo 
504e705c121SKalle Valo #define RXON_FLG_CHANNEL_MODE_POS		(25)
505e705c121SKalle Valo #define RXON_FLG_CHANNEL_MODE_MSK		cpu_to_le32(0x3 << 25)
506e705c121SKalle Valo 
507e705c121SKalle Valo /* channel mode */
508e705c121SKalle Valo enum {
509e705c121SKalle Valo 	CHANNEL_MODE_LEGACY = 0,
510e705c121SKalle Valo 	CHANNEL_MODE_PURE_40 = 1,
511e705c121SKalle Valo 	CHANNEL_MODE_MIXED = 2,
512e705c121SKalle Valo 	CHANNEL_MODE_RESERVED = 3,
513e705c121SKalle Valo };
514e705c121SKalle Valo #define RXON_FLG_CHANNEL_MODE_LEGACY	cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
515e705c121SKalle Valo #define RXON_FLG_CHANNEL_MODE_PURE_40	cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
516e705c121SKalle Valo #define RXON_FLG_CHANNEL_MODE_MIXED	cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
517e705c121SKalle Valo 
518e705c121SKalle Valo /* CTS to self (if spec allows) flag */
519e705c121SKalle Valo #define RXON_FLG_SELF_CTS_EN			cpu_to_le32(0x1<<30)
520e705c121SKalle Valo 
521e705c121SKalle Valo /* rx_config filter flags */
522e705c121SKalle Valo /* accept all data frames */
523e705c121SKalle Valo #define RXON_FILTER_PROMISC_MSK         cpu_to_le32(1 << 0)
524e705c121SKalle Valo /* pass control & management to host */
525e705c121SKalle Valo #define RXON_FILTER_CTL2HOST_MSK        cpu_to_le32(1 << 1)
526e705c121SKalle Valo /* accept multi-cast */
527e705c121SKalle Valo #define RXON_FILTER_ACCEPT_GRP_MSK      cpu_to_le32(1 << 2)
528e705c121SKalle Valo /* don't decrypt uni-cast frames */
529e705c121SKalle Valo #define RXON_FILTER_DIS_DECRYPT_MSK     cpu_to_le32(1 << 3)
530e705c121SKalle Valo /* don't decrypt multi-cast frames */
531e705c121SKalle Valo #define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
532e705c121SKalle Valo /* STA is associated */
533e705c121SKalle Valo #define RXON_FILTER_ASSOC_MSK           cpu_to_le32(1 << 5)
534e705c121SKalle Valo /* transfer to host non bssid beacons in associated state */
535e705c121SKalle Valo #define RXON_FILTER_BCON_AWARE_MSK      cpu_to_le32(1 << 6)
536e705c121SKalle Valo 
537e705c121SKalle Valo /**
538e705c121SKalle Valo  * REPLY_RXON = 0x10 (command, has simple generic response)
539e705c121SKalle Valo  *
540e705c121SKalle Valo  * RXON tunes the radio tuner to a service channel, and sets up a number
541e705c121SKalle Valo  * of parameters that are used primarily for Rx, but also for Tx operations.
542e705c121SKalle Valo  *
543e705c121SKalle Valo  * NOTE:  When tuning to a new channel, driver must set the
544e705c121SKalle Valo  *        RXON_FILTER_ASSOC_MSK to 0.  This will clear station-dependent
545e705c121SKalle Valo  *        info within the device, including the station tables, tx retry
546e705c121SKalle Valo  *        rate tables, and txpower tables.  Driver must build a new station
547e705c121SKalle Valo  *        table and txpower table before transmitting anything on the RXON
548e705c121SKalle Valo  *        channel.
549e705c121SKalle Valo  *
550e705c121SKalle Valo  * NOTE:  All RXONs wipe clean the internal txpower table.  Driver must
551e705c121SKalle Valo  *        issue a new REPLY_TX_PWR_TABLE_CMD after each REPLY_RXON (0x10),
552e705c121SKalle Valo  *        regardless of whether RXON_FILTER_ASSOC_MSK is set.
553e705c121SKalle Valo  */
554e705c121SKalle Valo 
555e705c121SKalle Valo struct iwl_rxon_cmd {
556e705c121SKalle Valo 	u8 node_addr[6];
557e705c121SKalle Valo 	__le16 reserved1;
558e705c121SKalle Valo 	u8 bssid_addr[6];
559e705c121SKalle Valo 	__le16 reserved2;
560e705c121SKalle Valo 	u8 wlap_bssid_addr[6];
561e705c121SKalle Valo 	__le16 reserved3;
562e705c121SKalle Valo 	u8 dev_type;
563e705c121SKalle Valo 	u8 air_propagation;
564e705c121SKalle Valo 	__le16 rx_chain;
565e705c121SKalle Valo 	u8 ofdm_basic_rates;
566e705c121SKalle Valo 	u8 cck_basic_rates;
567e705c121SKalle Valo 	__le16 assoc_id;
568e705c121SKalle Valo 	__le32 flags;
569e705c121SKalle Valo 	__le32 filter_flags;
570e705c121SKalle Valo 	__le16 channel;
571e705c121SKalle Valo 	u8 ofdm_ht_single_stream_basic_rates;
572e705c121SKalle Valo 	u8 ofdm_ht_dual_stream_basic_rates;
573e705c121SKalle Valo 	u8 ofdm_ht_triple_stream_basic_rates;
574e705c121SKalle Valo 	u8 reserved5;
575e705c121SKalle Valo 	__le16 acquisition_data;
576e705c121SKalle Valo 	__le16 reserved6;
577e705c121SKalle Valo } __packed;
578e705c121SKalle Valo 
579e705c121SKalle Valo /*
580e705c121SKalle Valo  * REPLY_RXON_ASSOC = 0x11 (command, has simple generic response)
581e705c121SKalle Valo  */
582e705c121SKalle Valo struct iwl_rxon_assoc_cmd {
583e705c121SKalle Valo 	__le32 flags;
584e705c121SKalle Valo 	__le32 filter_flags;
585e705c121SKalle Valo 	u8 ofdm_basic_rates;
586e705c121SKalle Valo 	u8 cck_basic_rates;
587e705c121SKalle Valo 	__le16 reserved1;
588e705c121SKalle Valo 	u8 ofdm_ht_single_stream_basic_rates;
589e705c121SKalle Valo 	u8 ofdm_ht_dual_stream_basic_rates;
590e705c121SKalle Valo 	u8 ofdm_ht_triple_stream_basic_rates;
591e705c121SKalle Valo 	u8 reserved2;
592e705c121SKalle Valo 	__le16 rx_chain_select_flags;
593e705c121SKalle Valo 	__le16 acquisition_data;
594e705c121SKalle Valo 	__le32 reserved3;
595e705c121SKalle Valo } __packed;
596e705c121SKalle Valo 
597e705c121SKalle Valo #define IWL_CONN_MAX_LISTEN_INTERVAL	10
598e705c121SKalle Valo #define IWL_MAX_UCODE_BEACON_INTERVAL	4 /* 4096 */
599e705c121SKalle Valo 
600e705c121SKalle Valo /*
601e705c121SKalle Valo  * REPLY_RXON_TIMING = 0x14 (command, has simple generic response)
602e705c121SKalle Valo  */
603e705c121SKalle Valo struct iwl_rxon_time_cmd {
604e705c121SKalle Valo 	__le64 timestamp;
605e705c121SKalle Valo 	__le16 beacon_interval;
606e705c121SKalle Valo 	__le16 atim_window;
607e705c121SKalle Valo 	__le32 beacon_init_val;
608e705c121SKalle Valo 	__le16 listen_interval;
609e705c121SKalle Valo 	u8 dtim_period;
610e705c121SKalle Valo 	u8 delta_cp_bss_tbtts;
611e705c121SKalle Valo } __packed;
612e705c121SKalle Valo 
613e705c121SKalle Valo /*
614e705c121SKalle Valo  * REPLY_CHANNEL_SWITCH = 0x72 (command, has simple generic response)
615e705c121SKalle Valo  */
616e705c121SKalle Valo /**
617e705c121SKalle Valo  * struct iwl5000_channel_switch_cmd
618e705c121SKalle Valo  * @band: 0- 5.2GHz, 1- 2.4GHz
619e705c121SKalle Valo  * @expect_beacon: 0- resume transmits after channel switch
620e705c121SKalle Valo  *		   1- wait for beacon to resume transmits
621e705c121SKalle Valo  * @channel: new channel number
622e705c121SKalle Valo  * @rxon_flags: Rx on flags
623e705c121SKalle Valo  * @rxon_filter_flags: filtering parameters
624e705c121SKalle Valo  * @switch_time: switch time in extended beacon format
625e705c121SKalle Valo  * @reserved: reserved bytes
626e705c121SKalle Valo  */
627e705c121SKalle Valo struct iwl5000_channel_switch_cmd {
628e705c121SKalle Valo 	u8 band;
629e705c121SKalle Valo 	u8 expect_beacon;
630e705c121SKalle Valo 	__le16 channel;
631e705c121SKalle Valo 	__le32 rxon_flags;
632e705c121SKalle Valo 	__le32 rxon_filter_flags;
633e705c121SKalle Valo 	__le32 switch_time;
634e705c121SKalle Valo 	__le32 reserved[2][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
635e705c121SKalle Valo } __packed;
636e705c121SKalle Valo 
637e705c121SKalle Valo /**
638e705c121SKalle Valo  * struct iwl6000_channel_switch_cmd
639e705c121SKalle Valo  * @band: 0- 5.2GHz, 1- 2.4GHz
640e705c121SKalle Valo  * @expect_beacon: 0- resume transmits after channel switch
641e705c121SKalle Valo  *		   1- wait for beacon to resume transmits
642e705c121SKalle Valo  * @channel: new channel number
643e705c121SKalle Valo  * @rxon_flags: Rx on flags
644e705c121SKalle Valo  * @rxon_filter_flags: filtering parameters
645e705c121SKalle Valo  * @switch_time: switch time in extended beacon format
646e705c121SKalle Valo  * @reserved: reserved bytes
647e705c121SKalle Valo  */
648e705c121SKalle Valo struct iwl6000_channel_switch_cmd {
649e705c121SKalle Valo 	u8 band;
650e705c121SKalle Valo 	u8 expect_beacon;
651e705c121SKalle Valo 	__le16 channel;
652e705c121SKalle Valo 	__le32 rxon_flags;
653e705c121SKalle Valo 	__le32 rxon_filter_flags;
654e705c121SKalle Valo 	__le32 switch_time;
655e705c121SKalle Valo 	__le32 reserved[3][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
656e705c121SKalle Valo } __packed;
657e705c121SKalle Valo 
658e705c121SKalle Valo /*
659e705c121SKalle Valo  * CHANNEL_SWITCH_NOTIFICATION = 0x73 (notification only, not a command)
660e705c121SKalle Valo  */
661e705c121SKalle Valo struct iwl_csa_notification {
662e705c121SKalle Valo 	__le16 band;
663e705c121SKalle Valo 	__le16 channel;
664e705c121SKalle Valo 	__le32 status;		/* 0 - OK, 1 - fail */
665e705c121SKalle Valo } __packed;
666e705c121SKalle Valo 
667e705c121SKalle Valo /******************************************************************************
668e705c121SKalle Valo  * (2)
669e705c121SKalle Valo  * Quality-of-Service (QOS) Commands & Responses:
670e705c121SKalle Valo  *
671e705c121SKalle Valo  *****************************************************************************/
672e705c121SKalle Valo 
673e705c121SKalle Valo /**
674e705c121SKalle Valo  * struct iwl_ac_qos -- QOS timing params for REPLY_QOS_PARAM
675e705c121SKalle Valo  * One for each of 4 EDCA access categories in struct iwl_qosparam_cmd
676e705c121SKalle Valo  *
677e705c121SKalle Valo  * @cw_min: Contention window, start value in numbers of slots.
678e705c121SKalle Valo  *          Should be a power-of-2, minus 1.  Device's default is 0x0f.
679e705c121SKalle Valo  * @cw_max: Contention window, max value in numbers of slots.
680e705c121SKalle Valo  *          Should be a power-of-2, minus 1.  Device's default is 0x3f.
681e705c121SKalle Valo  * @aifsn:  Number of slots in Arbitration Interframe Space (before
682e705c121SKalle Valo  *          performing random backoff timing prior to Tx).  Device default 1.
683e705c121SKalle Valo  * @edca_txop:  Length of Tx opportunity, in uSecs.  Device default is 0.
684e705c121SKalle Valo  *
685e705c121SKalle Valo  * Device will automatically increase contention window by (2*CW) + 1 for each
686e705c121SKalle Valo  * transmission retry.  Device uses cw_max as a bit mask, ANDed with new CW
687e705c121SKalle Valo  * value, to cap the CW value.
688e705c121SKalle Valo  */
689e705c121SKalle Valo struct iwl_ac_qos {
690e705c121SKalle Valo 	__le16 cw_min;
691e705c121SKalle Valo 	__le16 cw_max;
692e705c121SKalle Valo 	u8 aifsn;
693e705c121SKalle Valo 	u8 reserved1;
694e705c121SKalle Valo 	__le16 edca_txop;
695e705c121SKalle Valo } __packed;
696e705c121SKalle Valo 
697e705c121SKalle Valo /* QoS flags defines */
698e705c121SKalle Valo #define QOS_PARAM_FLG_UPDATE_EDCA_MSK	cpu_to_le32(0x01)
699e705c121SKalle Valo #define QOS_PARAM_FLG_TGN_MSK		cpu_to_le32(0x02)
700e705c121SKalle Valo #define QOS_PARAM_FLG_TXOP_TYPE_MSK	cpu_to_le32(0x10)
701e705c121SKalle Valo 
702e705c121SKalle Valo /* Number of Access Categories (AC) (EDCA), queues 0..3 */
703e705c121SKalle Valo #define AC_NUM                4
704e705c121SKalle Valo 
705e705c121SKalle Valo /*
706e705c121SKalle Valo  * REPLY_QOS_PARAM = 0x13 (command, has simple generic response)
707e705c121SKalle Valo  *
708e705c121SKalle Valo  * This command sets up timings for each of the 4 prioritized EDCA Tx FIFOs
709e705c121SKalle Valo  * 0: Background, 1: Best Effort, 2: Video, 3: Voice.
710e705c121SKalle Valo  */
711e705c121SKalle Valo struct iwl_qosparam_cmd {
712e705c121SKalle Valo 	__le32 qos_flags;
713e705c121SKalle Valo 	struct iwl_ac_qos ac[AC_NUM];
714e705c121SKalle Valo } __packed;
715e705c121SKalle Valo 
716e705c121SKalle Valo /******************************************************************************
717e705c121SKalle Valo  * (3)
718e705c121SKalle Valo  * Add/Modify Stations Commands & Responses:
719e705c121SKalle Valo  *
720e705c121SKalle Valo  *****************************************************************************/
721e705c121SKalle Valo /*
722e705c121SKalle Valo  * Multi station support
723e705c121SKalle Valo  */
724e705c121SKalle Valo 
725e705c121SKalle Valo /* Special, dedicated locations within device's station table */
726e705c121SKalle Valo #define	IWL_AP_ID		0
727e705c121SKalle Valo #define	IWL_AP_ID_PAN		1
728e705c121SKalle Valo #define	IWL_STA_ID		2
729e705c121SKalle Valo #define IWLAGN_PAN_BCAST_ID	14
730e705c121SKalle Valo #define IWLAGN_BROADCAST_ID	15
731e705c121SKalle Valo #define	IWLAGN_STATION_COUNT	16
732e705c121SKalle Valo 
733e705c121SKalle Valo #define IWL_TID_NON_QOS IWL_MAX_TID_COUNT
734e705c121SKalle Valo 
735e705c121SKalle Valo #define STA_FLG_TX_RATE_MSK		cpu_to_le32(1 << 2)
736e705c121SKalle Valo #define STA_FLG_PWR_SAVE_MSK		cpu_to_le32(1 << 8)
737e705c121SKalle Valo #define STA_FLG_PAN_STATION		cpu_to_le32(1 << 13)
738e705c121SKalle Valo #define STA_FLG_RTS_MIMO_PROT_MSK	cpu_to_le32(1 << 17)
739e705c121SKalle Valo #define STA_FLG_AGG_MPDU_8US_MSK	cpu_to_le32(1 << 18)
740e705c121SKalle Valo #define STA_FLG_MAX_AGG_SIZE_POS	(19)
741e705c121SKalle Valo #define STA_FLG_MAX_AGG_SIZE_MSK	cpu_to_le32(3 << 19)
742e705c121SKalle Valo #define STA_FLG_HT40_EN_MSK		cpu_to_le32(1 << 21)
743e705c121SKalle Valo #define STA_FLG_MIMO_DIS_MSK		cpu_to_le32(1 << 22)
744e705c121SKalle Valo #define STA_FLG_AGG_MPDU_DENSITY_POS	(23)
745e705c121SKalle Valo #define STA_FLG_AGG_MPDU_DENSITY_MSK	cpu_to_le32(7 << 23)
746e705c121SKalle Valo 
747e705c121SKalle Valo /* Use in mode field.  1: modify existing entry, 0: add new station entry */
748e705c121SKalle Valo #define STA_CONTROL_MODIFY_MSK		0x01
749e705c121SKalle Valo 
750e705c121SKalle Valo /* key flags __le16*/
751e705c121SKalle Valo #define STA_KEY_FLG_ENCRYPT_MSK	cpu_to_le16(0x0007)
752e705c121SKalle Valo #define STA_KEY_FLG_NO_ENC	cpu_to_le16(0x0000)
753e705c121SKalle Valo #define STA_KEY_FLG_WEP		cpu_to_le16(0x0001)
754e705c121SKalle Valo #define STA_KEY_FLG_CCMP	cpu_to_le16(0x0002)
755e705c121SKalle Valo #define STA_KEY_FLG_TKIP	cpu_to_le16(0x0003)
756e705c121SKalle Valo 
757e705c121SKalle Valo #define STA_KEY_FLG_KEYID_POS	8
758e705c121SKalle Valo #define STA_KEY_FLG_INVALID 	cpu_to_le16(0x0800)
759e705c121SKalle Valo /* wep key is either from global key (0) or from station info array (1) */
760e705c121SKalle Valo #define STA_KEY_FLG_MAP_KEY_MSK	cpu_to_le16(0x0008)
761e705c121SKalle Valo 
762e705c121SKalle Valo /* wep key in STA: 5-bytes (0) or 13-bytes (1) */
763e705c121SKalle Valo #define STA_KEY_FLG_KEY_SIZE_MSK     cpu_to_le16(0x1000)
764e705c121SKalle Valo #define STA_KEY_MULTICAST_MSK        cpu_to_le16(0x4000)
765e705c121SKalle Valo #define STA_KEY_MAX_NUM		8
766e705c121SKalle Valo #define STA_KEY_MAX_NUM_PAN	16
767e705c121SKalle Valo /* must not match WEP_INVALID_OFFSET */
768e705c121SKalle Valo #define IWLAGN_HW_KEY_DEFAULT	0xfe
769e705c121SKalle Valo 
770e705c121SKalle Valo /* Flags indicate whether to modify vs. don't change various station params */
771e705c121SKalle Valo #define	STA_MODIFY_KEY_MASK		0x01
772e705c121SKalle Valo #define	STA_MODIFY_TID_DISABLE_TX	0x02
773e705c121SKalle Valo #define	STA_MODIFY_TX_RATE_MSK		0x04
774e705c121SKalle Valo #define STA_MODIFY_ADDBA_TID_MSK	0x08
775e705c121SKalle Valo #define STA_MODIFY_DELBA_TID_MSK	0x10
776e705c121SKalle Valo #define STA_MODIFY_SLEEP_TX_COUNT_MSK	0x20
777e705c121SKalle Valo 
778e705c121SKalle Valo /* agn */
779e705c121SKalle Valo struct iwl_keyinfo {
780e705c121SKalle Valo 	__le16 key_flags;
781e705c121SKalle Valo 	u8 tkip_rx_tsc_byte2;	/* TSC[2] for key mix ph1 detection */
782e705c121SKalle Valo 	u8 reserved1;
783e705c121SKalle Valo 	__le16 tkip_rx_ttak[5];	/* 10-byte unicast TKIP TTAK */
784e705c121SKalle Valo 	u8 key_offset;
785e705c121SKalle Valo 	u8 reserved2;
786e705c121SKalle Valo 	u8 key[16];		/* 16-byte unicast decryption key */
787e705c121SKalle Valo 	__le64 tx_secur_seq_cnt;
788e705c121SKalle Valo 	__le64 hw_tkip_mic_rx_key;
789e705c121SKalle Valo 	__le64 hw_tkip_mic_tx_key;
790e705c121SKalle Valo } __packed;
791e705c121SKalle Valo 
792e705c121SKalle Valo /**
793e705c121SKalle Valo  * struct sta_id_modify
794e705c121SKalle Valo  * @addr[ETH_ALEN]: station's MAC address
795e705c121SKalle Valo  * @sta_id: index of station in uCode's station table
796e705c121SKalle Valo  * @modify_mask: STA_MODIFY_*, 1: modify, 0: don't change
797e705c121SKalle Valo  *
798e705c121SKalle Valo  * Driver selects unused table index when adding new station,
799e705c121SKalle Valo  * or the index to a pre-existing station entry when modifying that station.
800e705c121SKalle Valo  * Some indexes have special purposes (IWL_AP_ID, index 0, is for AP).
801e705c121SKalle Valo  *
802e705c121SKalle Valo  * modify_mask flags select which parameters to modify vs. leave alone.
803e705c121SKalle Valo  */
804e705c121SKalle Valo struct sta_id_modify {
805e705c121SKalle Valo 	u8 addr[ETH_ALEN];
806e705c121SKalle Valo 	__le16 reserved1;
807e705c121SKalle Valo 	u8 sta_id;
808e705c121SKalle Valo 	u8 modify_mask;
809e705c121SKalle Valo 	__le16 reserved2;
810e705c121SKalle Valo } __packed;
811e705c121SKalle Valo 
812e705c121SKalle Valo /*
813e705c121SKalle Valo  * REPLY_ADD_STA = 0x18 (command)
814e705c121SKalle Valo  *
815e705c121SKalle Valo  * The device contains an internal table of per-station information,
816e705c121SKalle Valo  * with info on security keys, aggregation parameters, and Tx rates for
817e705c121SKalle Valo  * initial Tx attempt and any retries (agn devices uses
818e705c121SKalle Valo  * REPLY_TX_LINK_QUALITY_CMD,
819e705c121SKalle Valo  *
820e705c121SKalle Valo  * REPLY_ADD_STA sets up the table entry for one station, either creating
821e705c121SKalle Valo  * a new entry, or modifying a pre-existing one.
822e705c121SKalle Valo  *
823e705c121SKalle Valo  * NOTE:  RXON command (without "associated" bit set) wipes the station table
824e705c121SKalle Valo  *        clean.  Moving into RF_KILL state does this also.  Driver must set up
825e705c121SKalle Valo  *        new station table before transmitting anything on the RXON channel
826e705c121SKalle Valo  *        (except active scans or active measurements; those commands carry
827e705c121SKalle Valo  *        their own txpower/rate setup data).
828e705c121SKalle Valo  *
829e705c121SKalle Valo  *        When getting started on a new channel, driver must set up the
830e705c121SKalle Valo  *        IWL_BROADCAST_ID entry (last entry in the table).  For a client
831e705c121SKalle Valo  *        station in a BSS, once an AP is selected, driver sets up the AP STA
832e705c121SKalle Valo  *        in the IWL_AP_ID entry (1st entry in the table).  BROADCAST and AP
833e705c121SKalle Valo  *        are all that are needed for a BSS client station.  If the device is
834e705c121SKalle Valo  *        used as AP, or in an IBSS network, driver must set up station table
835e705c121SKalle Valo  *        entries for all STAs in network, starting with index IWL_STA_ID.
836e705c121SKalle Valo  */
837e705c121SKalle Valo 
838e705c121SKalle Valo struct iwl_addsta_cmd {
839e705c121SKalle Valo 	u8 mode;		/* 1: modify existing, 0: add new station */
840e705c121SKalle Valo 	u8 reserved[3];
841e705c121SKalle Valo 	struct sta_id_modify sta;
842e705c121SKalle Valo 	struct iwl_keyinfo key;
843e705c121SKalle Valo 	__le32 station_flags;		/* STA_FLG_* */
844e705c121SKalle Valo 	__le32 station_flags_msk;	/* STA_FLG_* */
845e705c121SKalle Valo 
846e705c121SKalle Valo 	/* bit field to disable (1) or enable (0) Tx for Traffic ID (TID)
847e705c121SKalle Valo 	 * corresponding to bit (e.g. bit 5 controls TID 5).
848e705c121SKalle Valo 	 * Set modify_mask bit STA_MODIFY_TID_DISABLE_TX to use this field. */
849e705c121SKalle Valo 	__le16 tid_disable_tx;
850e705c121SKalle Valo 	__le16 legacy_reserved;
851e705c121SKalle Valo 
852e705c121SKalle Valo 	/* TID for which to add block-ack support.
853e705c121SKalle Valo 	 * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
854e705c121SKalle Valo 	u8 add_immediate_ba_tid;
855e705c121SKalle Valo 
856e705c121SKalle Valo 	/* TID for which to remove block-ack support.
857e705c121SKalle Valo 	 * Set modify_mask bit STA_MODIFY_DELBA_TID_MSK to use this field. */
858e705c121SKalle Valo 	u8 remove_immediate_ba_tid;
859e705c121SKalle Valo 
860e705c121SKalle Valo 	/* Starting Sequence Number for added block-ack support.
861e705c121SKalle Valo 	 * Set modify_mask bit STA_MODIFY_ADDBA_TID_MSK to use this field. */
862e705c121SKalle Valo 	__le16 add_immediate_ba_ssn;
863e705c121SKalle Valo 
864e705c121SKalle Valo 	/*
865e705c121SKalle Valo 	 * Number of packets OK to transmit to station even though
866e705c121SKalle Valo 	 * it is asleep -- used to synchronise PS-poll and u-APSD
867e705c121SKalle Valo 	 * responses while ucode keeps track of STA sleep state.
868e705c121SKalle Valo 	 */
869e705c121SKalle Valo 	__le16 sleep_tx_count;
870e705c121SKalle Valo 
871e705c121SKalle Valo 	__le16 reserved2;
872e705c121SKalle Valo } __packed;
873e705c121SKalle Valo 
874e705c121SKalle Valo 
875e705c121SKalle Valo #define ADD_STA_SUCCESS_MSK		0x1
876e705c121SKalle Valo #define ADD_STA_NO_ROOM_IN_TABLE	0x2
877e705c121SKalle Valo #define ADD_STA_NO_BLOCK_ACK_RESOURCE	0x4
878e705c121SKalle Valo #define ADD_STA_MODIFY_NON_EXIST_STA	0x8
879e705c121SKalle Valo /*
880e705c121SKalle Valo  * REPLY_ADD_STA = 0x18 (response)
881e705c121SKalle Valo  */
882e705c121SKalle Valo struct iwl_add_sta_resp {
883e705c121SKalle Valo 	u8 status;	/* ADD_STA_* */
884e705c121SKalle Valo } __packed;
885e705c121SKalle Valo 
886e705c121SKalle Valo #define REM_STA_SUCCESS_MSK              0x1
887e705c121SKalle Valo /*
888e705c121SKalle Valo  *  REPLY_REM_STA = 0x19 (response)
889e705c121SKalle Valo  */
890e705c121SKalle Valo struct iwl_rem_sta_resp {
891e705c121SKalle Valo 	u8 status;
892e705c121SKalle Valo } __packed;
893e705c121SKalle Valo 
894e705c121SKalle Valo /*
895e705c121SKalle Valo  *  REPLY_REM_STA = 0x19 (command)
896e705c121SKalle Valo  */
897e705c121SKalle Valo struct iwl_rem_sta_cmd {
898e705c121SKalle Valo 	u8 num_sta;     /* number of removed stations */
899e705c121SKalle Valo 	u8 reserved[3];
900e705c121SKalle Valo 	u8 addr[ETH_ALEN]; /* MAC addr of the first station */
901e705c121SKalle Valo 	u8 reserved2[2];
902e705c121SKalle Valo } __packed;
903e705c121SKalle Valo 
904e705c121SKalle Valo 
905e705c121SKalle Valo /* WiFi queues mask */
906e705c121SKalle Valo #define IWL_SCD_BK_MSK			BIT(0)
907e705c121SKalle Valo #define IWL_SCD_BE_MSK			BIT(1)
908e705c121SKalle Valo #define IWL_SCD_VI_MSK			BIT(2)
909e705c121SKalle Valo #define IWL_SCD_VO_MSK			BIT(3)
910e705c121SKalle Valo #define IWL_SCD_MGMT_MSK		BIT(3)
911e705c121SKalle Valo 
912e705c121SKalle Valo /* PAN queues mask */
913e705c121SKalle Valo #define IWL_PAN_SCD_BK_MSK		BIT(4)
914e705c121SKalle Valo #define IWL_PAN_SCD_BE_MSK		BIT(5)
915e705c121SKalle Valo #define IWL_PAN_SCD_VI_MSK		BIT(6)
916e705c121SKalle Valo #define IWL_PAN_SCD_VO_MSK		BIT(7)
917e705c121SKalle Valo #define IWL_PAN_SCD_MGMT_MSK		BIT(7)
918e705c121SKalle Valo #define IWL_PAN_SCD_MULTICAST_MSK	BIT(8)
919e705c121SKalle Valo 
920e705c121SKalle Valo #define IWL_AGG_TX_QUEUE_MSK		0xffc00
921e705c121SKalle Valo 
922e705c121SKalle Valo #define IWL_DROP_ALL			BIT(1)
923e705c121SKalle Valo 
924e705c121SKalle Valo /*
925e705c121SKalle Valo  * REPLY_TXFIFO_FLUSH = 0x1e(command and response)
926e705c121SKalle Valo  *
927e705c121SKalle Valo  * When using full FIFO flush this command checks the scheduler HW block WR/RD
928e705c121SKalle Valo  * pointers to check if all the frames were transferred by DMA into the
929e705c121SKalle Valo  * relevant TX FIFO queue. Only when the DMA is finished and the queue is
930e705c121SKalle Valo  * empty the command can finish.
931e705c121SKalle Valo  * This command is used to flush the TXFIFO from transmit commands, it may
932e705c121SKalle Valo  * operate on single or multiple queues, the command queue can't be flushed by
933e705c121SKalle Valo  * this command. The command response is returned when all the queue flush
934e705c121SKalle Valo  * operations are done. Each TX command flushed return response with the FLUSH
935e705c121SKalle Valo  * status set in the TX response status. When FIFO flush operation is used,
936e705c121SKalle Valo  * the flush operation ends when both the scheduler DMA done and TXFIFO empty
937e705c121SKalle Valo  * are set.
938e705c121SKalle Valo  *
939e705c121SKalle Valo  * @queue_control: bit mask for which queues to flush
940e705c121SKalle Valo  * @flush_control: flush controls
941e705c121SKalle Valo  *	0: Dump single MSDU
942e705c121SKalle Valo  *	1: Dump multiple MSDU according to PS, INVALID STA, TTL, TID disable.
943e705c121SKalle Valo  *	2: Dump all FIFO
944e705c121SKalle Valo  */
945e705c121SKalle Valo struct iwl_txfifo_flush_cmd_v3 {
946e705c121SKalle Valo 	__le32 queue_control;
947e705c121SKalle Valo 	__le16 flush_control;
948e705c121SKalle Valo 	__le16 reserved;
949e705c121SKalle Valo } __packed;
950e705c121SKalle Valo 
951e705c121SKalle Valo struct iwl_txfifo_flush_cmd_v2 {
952e705c121SKalle Valo 	__le16 queue_control;
953e705c121SKalle Valo 	__le16 flush_control;
954e705c121SKalle Valo } __packed;
955e705c121SKalle Valo 
956e705c121SKalle Valo /*
957e705c121SKalle Valo  * REPLY_WEP_KEY = 0x20
958e705c121SKalle Valo  */
959e705c121SKalle Valo struct iwl_wep_key {
960e705c121SKalle Valo 	u8 key_index;
961e705c121SKalle Valo 	u8 key_offset;
962e705c121SKalle Valo 	u8 reserved1[2];
963e705c121SKalle Valo 	u8 key_size;
964e705c121SKalle Valo 	u8 reserved2[3];
965e705c121SKalle Valo 	u8 key[16];
966e705c121SKalle Valo } __packed;
967e705c121SKalle Valo 
968e705c121SKalle Valo struct iwl_wep_cmd {
969e705c121SKalle Valo 	u8 num_keys;
970e705c121SKalle Valo 	u8 global_key_type;
971e705c121SKalle Valo 	u8 flags;
972e705c121SKalle Valo 	u8 reserved;
97345c21a0eSGustavo A. R. Silva 	struct iwl_wep_key key[];
974e705c121SKalle Valo } __packed;
975e705c121SKalle Valo 
976e705c121SKalle Valo #define WEP_KEY_WEP_TYPE 1
977e705c121SKalle Valo #define WEP_KEYS_MAX 4
978e705c121SKalle Valo #define WEP_INVALID_OFFSET 0xff
979e705c121SKalle Valo #define WEP_KEY_LEN_64 5
980e705c121SKalle Valo #define WEP_KEY_LEN_128 13
981e705c121SKalle Valo 
982e705c121SKalle Valo /******************************************************************************
983e705c121SKalle Valo  * (4)
984e705c121SKalle Valo  * Rx Responses:
985e705c121SKalle Valo  *
986e705c121SKalle Valo  *****************************************************************************/
987e705c121SKalle Valo 
988e705c121SKalle Valo #define RX_RES_STATUS_NO_CRC32_ERROR	cpu_to_le32(1 << 0)
989e705c121SKalle Valo #define RX_RES_STATUS_NO_RXE_OVERFLOW	cpu_to_le32(1 << 1)
990e705c121SKalle Valo 
991e705c121SKalle Valo #define RX_RES_PHY_FLAGS_BAND_24_MSK	cpu_to_le16(1 << 0)
992e705c121SKalle Valo #define RX_RES_PHY_FLAGS_MOD_CCK_MSK		cpu_to_le16(1 << 1)
993e705c121SKalle Valo #define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK	cpu_to_le16(1 << 2)
994e705c121SKalle Valo #define RX_RES_PHY_FLAGS_NARROW_BAND_MSK	cpu_to_le16(1 << 3)
995e705c121SKalle Valo #define RX_RES_PHY_FLAGS_ANTENNA_MSK		0x70
996e705c121SKalle Valo #define RX_RES_PHY_FLAGS_ANTENNA_POS		4
997e705c121SKalle Valo #define RX_RES_PHY_FLAGS_AGG_MSK		cpu_to_le16(1 << 7)
998e705c121SKalle Valo 
999e705c121SKalle Valo #define RX_RES_STATUS_SEC_TYPE_MSK	(0x7 << 8)
1000e705c121SKalle Valo #define RX_RES_STATUS_SEC_TYPE_NONE	(0x0 << 8)
1001e705c121SKalle Valo #define RX_RES_STATUS_SEC_TYPE_WEP	(0x1 << 8)
1002e705c121SKalle Valo #define RX_RES_STATUS_SEC_TYPE_CCMP	(0x2 << 8)
1003e705c121SKalle Valo #define RX_RES_STATUS_SEC_TYPE_TKIP	(0x3 << 8)
1004e705c121SKalle Valo #define	RX_RES_STATUS_SEC_TYPE_ERR	(0x7 << 8)
1005e705c121SKalle Valo 
1006e705c121SKalle Valo #define RX_RES_STATUS_STATION_FOUND	(1<<6)
1007e705c121SKalle Valo #define RX_RES_STATUS_NO_STATION_INFO_MISMATCH	(1<<7)
1008e705c121SKalle Valo 
1009e705c121SKalle Valo #define RX_RES_STATUS_DECRYPT_TYPE_MSK	(0x3 << 11)
1010e705c121SKalle Valo #define RX_RES_STATUS_NOT_DECRYPT	(0x0 << 11)
1011e705c121SKalle Valo #define RX_RES_STATUS_DECRYPT_OK	(0x3 << 11)
1012e705c121SKalle Valo #define RX_RES_STATUS_BAD_ICV_MIC	(0x1 << 11)
1013e705c121SKalle Valo #define RX_RES_STATUS_BAD_KEY_TTAK	(0x2 << 11)
1014e705c121SKalle Valo 
1015e705c121SKalle Valo #define RX_MPDU_RES_STATUS_ICV_OK	(0x20)
1016e705c121SKalle Valo #define RX_MPDU_RES_STATUS_MIC_OK	(0x40)
1017e705c121SKalle Valo #define RX_MPDU_RES_STATUS_TTAK_OK	(1 << 7)
1018e705c121SKalle Valo #define RX_MPDU_RES_STATUS_DEC_DONE_MSK	(0x800)
1019e705c121SKalle Valo 
1020e705c121SKalle Valo 
1021e705c121SKalle Valo #define IWLAGN_RX_RES_PHY_CNT 8
1022e705c121SKalle Valo #define IWLAGN_RX_RES_AGC_IDX     1
1023e705c121SKalle Valo #define IWLAGN_RX_RES_RSSI_AB_IDX 2
1024e705c121SKalle Valo #define IWLAGN_RX_RES_RSSI_C_IDX  3
1025e705c121SKalle Valo #define IWLAGN_OFDM_AGC_MSK 0xfe00
1026e705c121SKalle Valo #define IWLAGN_OFDM_AGC_BIT_POS 9
1027e705c121SKalle Valo #define IWLAGN_OFDM_RSSI_INBAND_A_BITMSK 0x00ff
1028e705c121SKalle Valo #define IWLAGN_OFDM_RSSI_ALLBAND_A_BITMSK 0xff00
1029e705c121SKalle Valo #define IWLAGN_OFDM_RSSI_A_BIT_POS 0
1030e705c121SKalle Valo #define IWLAGN_OFDM_RSSI_INBAND_B_BITMSK 0xff0000
1031e705c121SKalle Valo #define IWLAGN_OFDM_RSSI_ALLBAND_B_BITMSK 0xff000000
1032e705c121SKalle Valo #define IWLAGN_OFDM_RSSI_B_BIT_POS 16
1033e705c121SKalle Valo #define IWLAGN_OFDM_RSSI_INBAND_C_BITMSK 0x00ff
1034e705c121SKalle Valo #define IWLAGN_OFDM_RSSI_ALLBAND_C_BITMSK 0xff00
1035e705c121SKalle Valo #define IWLAGN_OFDM_RSSI_C_BIT_POS 0
1036e705c121SKalle Valo 
1037e705c121SKalle Valo struct iwlagn_non_cfg_phy {
1038e705c121SKalle Valo 	__le32 non_cfg_phy[IWLAGN_RX_RES_PHY_CNT];  /* up to 8 phy entries */
1039e705c121SKalle Valo } __packed;
1040e705c121SKalle Valo 
1041e705c121SKalle Valo 
1042e705c121SKalle Valo /*
1043e705c121SKalle Valo  * REPLY_RX = 0xc3 (response only, not a command)
1044e705c121SKalle Valo  * Used only for legacy (non 11n) frames.
1045e705c121SKalle Valo  */
1046e705c121SKalle Valo struct iwl_rx_phy_res {
1047e705c121SKalle Valo 	u8 non_cfg_phy_cnt;     /* non configurable DSP phy data byte count */
1048e705c121SKalle Valo 	u8 cfg_phy_cnt;		/* configurable DSP phy data byte count */
1049e705c121SKalle Valo 	u8 stat_id;		/* configurable DSP phy data set ID */
1050e705c121SKalle Valo 	u8 reserved1;
1051e705c121SKalle Valo 	__le64 timestamp;	/* TSF at on air rise */
1052e705c121SKalle Valo 	__le32 beacon_time_stamp; /* beacon at on-air rise */
1053e705c121SKalle Valo 	__le16 phy_flags;	/* general phy flags: band, modulation, ... */
1054e705c121SKalle Valo 	__le16 channel;		/* channel number */
1055e705c121SKalle Valo 	u8 non_cfg_phy_buf[32]; /* for various implementations of non_cfg_phy */
1056e705c121SKalle Valo 	__le32 rate_n_flags;	/* RATE_MCS_* */
1057e705c121SKalle Valo 	__le16 byte_count;	/* frame's byte-count */
1058e705c121SKalle Valo 	__le16 frame_time;	/* frame's time on the air */
1059e705c121SKalle Valo } __packed;
1060e705c121SKalle Valo 
1061e705c121SKalle Valo struct iwl_rx_mpdu_res_start {
1062e705c121SKalle Valo 	__le16 byte_count;
1063e705c121SKalle Valo 	__le16 reserved;
1064e705c121SKalle Valo } __packed;
1065e705c121SKalle Valo 
1066e705c121SKalle Valo 
1067e705c121SKalle Valo /******************************************************************************
1068e705c121SKalle Valo  * (5)
1069e705c121SKalle Valo  * Tx Commands & Responses:
1070e705c121SKalle Valo  *
1071e705c121SKalle Valo  * Driver must place each REPLY_TX command into one of the prioritized Tx
1072e705c121SKalle Valo  * queues in host DRAM, shared between driver and device (see comments for
1073e705c121SKalle Valo  * SCD registers and Tx/Rx Queues).  When the device's Tx scheduler and uCode
1074e705c121SKalle Valo  * are preparing to transmit, the device pulls the Tx command over the PCI
1075e705c121SKalle Valo  * bus via one of the device's Tx DMA channels, to fill an internal FIFO
1076e705c121SKalle Valo  * from which data will be transmitted.
1077e705c121SKalle Valo  *
1078e705c121SKalle Valo  * uCode handles all timing and protocol related to control frames
1079e705c121SKalle Valo  * (RTS/CTS/ACK), based on flags in the Tx command.  uCode and Tx scheduler
1080e705c121SKalle Valo  * handle reception of block-acks; uCode updates the host driver via
1081e705c121SKalle Valo  * REPLY_COMPRESSED_BA.
1082e705c121SKalle Valo  *
1083e705c121SKalle Valo  * uCode handles retrying Tx when an ACK is expected but not received.
1084e705c121SKalle Valo  * This includes trying lower data rates than the one requested in the Tx
1085e705c121SKalle Valo  * command, as set up by the REPLY_TX_LINK_QUALITY_CMD (agn).
1086e705c121SKalle Valo  *
1087e705c121SKalle Valo  * Driver sets up transmit power for various rates via REPLY_TX_PWR_TABLE_CMD.
1088e705c121SKalle Valo  * This command must be executed after every RXON command, before Tx can occur.
1089e705c121SKalle Valo  *****************************************************************************/
1090e705c121SKalle Valo 
1091e705c121SKalle Valo /* REPLY_TX Tx flags field */
1092e705c121SKalle Valo 
1093e705c121SKalle Valo /*
1094e705c121SKalle Valo  * 1: Use RTS/CTS protocol or CTS-to-self if spec allows it
1095e705c121SKalle Valo  * before this frame. if CTS-to-self required check
1096e705c121SKalle Valo  * RXON_FLG_SELF_CTS_EN status.
1097e705c121SKalle Valo  */
1098e705c121SKalle Valo #define TX_CMD_FLG_PROT_REQUIRE_MSK cpu_to_le32(1 << 0)
1099e705c121SKalle Valo 
1100e705c121SKalle Valo /* 1: Expect ACK from receiving station
1101e705c121SKalle Valo  * 0: Don't expect ACK (MAC header's duration field s/b 0)
1102e705c121SKalle Valo  * Set this for unicast frames, but not broadcast/multicast. */
1103e705c121SKalle Valo #define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1104e705c121SKalle Valo 
1105e705c121SKalle Valo /* For agn devices:
1106e705c121SKalle Valo  * 1: Use rate scale table (see REPLY_TX_LINK_QUALITY_CMD).
1107e705c121SKalle Valo  *    Tx command's initial_rate_index indicates first rate to try;
1108e705c121SKalle Valo  *    uCode walks through table for additional Tx attempts.
1109e705c121SKalle Valo  * 0: Use Tx rate/MCS from Tx command's rate_n_flags field.
1110e705c121SKalle Valo  *    This rate will be used for all Tx attempts; it will not be scaled. */
1111e705c121SKalle Valo #define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1112e705c121SKalle Valo 
1113e705c121SKalle Valo /* 1: Expect immediate block-ack.
1114e705c121SKalle Valo  * Set when Txing a block-ack request frame.  Also set TX_CMD_FLG_ACK_MSK. */
1115e705c121SKalle Valo #define TX_CMD_FLG_IMM_BA_RSP_MASK  cpu_to_le32(1 << 6)
1116e705c121SKalle Valo 
1117e705c121SKalle Valo /* Tx antenna selection field; reserved (0) for agn devices. */
1118e705c121SKalle Valo #define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1119e705c121SKalle Valo 
1120e705c121SKalle Valo /* 1: Ignore Bluetooth priority for this frame.
1121e705c121SKalle Valo  * 0: Delay Tx until Bluetooth device is done (normal usage). */
1122e705c121SKalle Valo #define TX_CMD_FLG_IGNORE_BT cpu_to_le32(1 << 12)
1123e705c121SKalle Valo 
1124e705c121SKalle Valo /* 1: uCode overrides sequence control field in MAC header.
1125e705c121SKalle Valo  * 0: Driver provides sequence control field in MAC header.
1126e705c121SKalle Valo  * Set this for management frames, non-QOS data frames, non-unicast frames,
1127e705c121SKalle Valo  * and also in Tx command embedded in REPLY_SCAN_CMD for active scans. */
1128e705c121SKalle Valo #define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1129e705c121SKalle Valo 
1130e705c121SKalle Valo /* 1: This frame is non-last MPDU; more fragments are coming.
1131e705c121SKalle Valo  * 0: Last fragment, or not using fragmentation. */
1132e705c121SKalle Valo #define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1133e705c121SKalle Valo 
1134e705c121SKalle Valo /* 1: uCode calculates and inserts Timestamp Function (TSF) in outgoing frame.
1135e705c121SKalle Valo  * 0: No TSF required in outgoing frame.
1136e705c121SKalle Valo  * Set this for transmitting beacons and probe responses. */
1137e705c121SKalle Valo #define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1138e705c121SKalle Valo 
1139e705c121SKalle Valo /* 1: Driver inserted 2 bytes pad after the MAC header, for (required) dword
1140e705c121SKalle Valo  *    alignment of frame's payload data field.
1141e705c121SKalle Valo  * 0: No pad
1142e705c121SKalle Valo  * Set this for MAC headers with 26 or 30 bytes, i.e. those with QOS or ADDR4
1143e705c121SKalle Valo  * field (but not both).  Driver must align frame data (i.e. data following
1144e705c121SKalle Valo  * MAC header) to DWORD boundary. */
1145e705c121SKalle Valo #define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1146e705c121SKalle Valo 
1147e705c121SKalle Valo /* accelerate aggregation support
1148e705c121SKalle Valo  * 0 - no CCMP encryption; 1 - CCMP encryption */
1149e705c121SKalle Valo #define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1150e705c121SKalle Valo 
1151e705c121SKalle Valo /* HCCA-AP - disable duration overwriting. */
1152e705c121SKalle Valo #define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
1153e705c121SKalle Valo 
1154e705c121SKalle Valo 
1155e705c121SKalle Valo /*
1156e705c121SKalle Valo  * TX command security control
1157e705c121SKalle Valo  */
1158e705c121SKalle Valo #define TX_CMD_SEC_WEP  	0x01
1159e705c121SKalle Valo #define TX_CMD_SEC_CCM  	0x02
1160e705c121SKalle Valo #define TX_CMD_SEC_TKIP		0x03
1161e705c121SKalle Valo #define TX_CMD_SEC_MSK		0x03
1162e705c121SKalle Valo #define TX_CMD_SEC_SHIFT	6
1163e705c121SKalle Valo #define TX_CMD_SEC_KEY128	0x08
1164e705c121SKalle Valo 
1165e705c121SKalle Valo /*
1166e705c121SKalle Valo  * REPLY_TX = 0x1c (command)
1167e705c121SKalle Valo  */
1168e705c121SKalle Valo 
1169e705c121SKalle Valo /*
1170e705c121SKalle Valo  * Used for managing Tx retries when expecting block-acks.
1171e705c121SKalle Valo  * Driver should set these fields to 0.
1172e705c121SKalle Valo  */
1173e705c121SKalle Valo struct iwl_dram_scratch {
1174e705c121SKalle Valo 	u8 try_cnt;		/* Tx attempts */
1175e705c121SKalle Valo 	u8 bt_kill_cnt;		/* Tx attempts blocked by Bluetooth device */
1176e705c121SKalle Valo 	__le16 reserved;
1177e705c121SKalle Valo } __packed;
1178e705c121SKalle Valo 
1179e705c121SKalle Valo struct iwl_tx_cmd {
1180e705c121SKalle Valo 	/*
1181e705c121SKalle Valo 	 * MPDU byte count:
1182e705c121SKalle Valo 	 * MAC header (24/26/30/32 bytes) + 2 bytes pad if 26/30 header size,
1183e705c121SKalle Valo 	 * + 8 byte IV for CCM or TKIP (not used for WEP)
1184e705c121SKalle Valo 	 * + Data payload
1185e705c121SKalle Valo 	 * + 8-byte MIC (not used for CCM/WEP)
1186e705c121SKalle Valo 	 * NOTE:  Does not include Tx command bytes, post-MAC pad bytes,
1187e705c121SKalle Valo 	 *        MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.i
1188e705c121SKalle Valo 	 * Range: 14-2342 bytes.
1189e705c121SKalle Valo 	 */
1190e705c121SKalle Valo 	__le16 len;
1191e705c121SKalle Valo 
1192e705c121SKalle Valo 	/*
1193e705c121SKalle Valo 	 * MPDU or MSDU byte count for next frame.
1194e705c121SKalle Valo 	 * Used for fragmentation and bursting, but not 11n aggregation.
1195e705c121SKalle Valo 	 * Same as "len", but for next frame.  Set to 0 if not applicable.
1196e705c121SKalle Valo 	 */
1197e705c121SKalle Valo 	__le16 next_frame_len;
1198e705c121SKalle Valo 
1199e705c121SKalle Valo 	__le32 tx_flags;	/* TX_CMD_FLG_* */
1200e705c121SKalle Valo 
1201e705c121SKalle Valo 	/* uCode may modify this field of the Tx command (in host DRAM!).
1202e705c121SKalle Valo 	 * Driver must also set dram_lsb_ptr and dram_msb_ptr in this cmd. */
1203e705c121SKalle Valo 	struct iwl_dram_scratch scratch;
1204e705c121SKalle Valo 
1205e705c121SKalle Valo 	/* Rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is cleared. */
1206e705c121SKalle Valo 	__le32 rate_n_flags;	/* RATE_MCS_* */
1207e705c121SKalle Valo 
1208e705c121SKalle Valo 	/* Index of destination station in uCode's station table */
1209e705c121SKalle Valo 	u8 sta_id;
1210e705c121SKalle Valo 
1211e705c121SKalle Valo 	/* Type of security encryption:  CCM or TKIP */
1212e705c121SKalle Valo 	u8 sec_ctl;		/* TX_CMD_SEC_* */
1213e705c121SKalle Valo 
1214e705c121SKalle Valo 	/*
1215e705c121SKalle Valo 	 * Index into rate table (see REPLY_TX_LINK_QUALITY_CMD) for initial
1216e705c121SKalle Valo 	 * Tx attempt, if TX_CMD_FLG_STA_RATE_MSK is set.  Normally "0" for
1217e705c121SKalle Valo 	 * data frames, this field may be used to selectively reduce initial
1218e705c121SKalle Valo 	 * rate (via non-0 value) for special frames (e.g. management), while
1219e705c121SKalle Valo 	 * still supporting rate scaling for all frames.
1220e705c121SKalle Valo 	 */
1221e705c121SKalle Valo 	u8 initial_rate_index;
1222e705c121SKalle Valo 	u8 reserved;
1223e705c121SKalle Valo 	u8 key[16];
1224e705c121SKalle Valo 	__le16 next_frame_flags;
1225e705c121SKalle Valo 	__le16 reserved2;
1226e705c121SKalle Valo 	union {
1227e705c121SKalle Valo 		__le32 life_time;
1228e705c121SKalle Valo 		__le32 attempt;
1229e705c121SKalle Valo 	} stop_time;
1230e705c121SKalle Valo 
1231e705c121SKalle Valo 	/* Host DRAM physical address pointer to "scratch" in this command.
1232e705c121SKalle Valo 	 * Must be dword aligned.  "0" in dram_lsb_ptr disables usage. */
1233e705c121SKalle Valo 	__le32 dram_lsb_ptr;
1234e705c121SKalle Valo 	u8 dram_msb_ptr;
1235e705c121SKalle Valo 
1236e705c121SKalle Valo 	u8 rts_retry_limit;	/*byte 50 */
1237e705c121SKalle Valo 	u8 data_retry_limit;	/*byte 51 */
1238e705c121SKalle Valo 	u8 tid_tspec;
1239e705c121SKalle Valo 	union {
1240e705c121SKalle Valo 		__le16 pm_frame_timeout;
1241e705c121SKalle Valo 		__le16 attempt_duration;
1242e705c121SKalle Valo 	} timeout;
1243e705c121SKalle Valo 
1244e705c121SKalle Valo 	/*
1245e705c121SKalle Valo 	 * Duration of EDCA burst Tx Opportunity, in 32-usec units.
1246e705c121SKalle Valo 	 * Set this if txop time is not specified by HCCA protocol (e.g. by AP).
1247e705c121SKalle Valo 	 */
1248e705c121SKalle Valo 	__le16 driver_txop;
1249e705c121SKalle Valo 
1250e705c121SKalle Valo 	/*
1251e705c121SKalle Valo 	 * MAC header goes here, followed by 2 bytes padding if MAC header
1252e705c121SKalle Valo 	 * length is 26 or 30 bytes, followed by payload data
1253e705c121SKalle Valo 	 */
1254*fa7845cfSKees Cook 	union {
1255*fa7845cfSKees Cook 		DECLARE_FLEX_ARRAY(u8, payload);
1256*fa7845cfSKees Cook 		DECLARE_FLEX_ARRAY(struct ieee80211_hdr, hdr);
1257*fa7845cfSKees Cook 	};
1258e705c121SKalle Valo } __packed;
1259e705c121SKalle Valo 
1260e705c121SKalle Valo /*
1261e705c121SKalle Valo  * TX command response is sent after *agn* transmission attempts.
1262e705c121SKalle Valo  *
1263e705c121SKalle Valo  * both postpone and abort status are expected behavior from uCode. there is
1264e705c121SKalle Valo  * no special operation required from driver; except for RFKILL_FLUSH,
1265e705c121SKalle Valo  * which required tx flush host command to flush all the tx frames in queues
1266e705c121SKalle Valo  */
1267e705c121SKalle Valo enum {
1268e705c121SKalle Valo 	TX_STATUS_SUCCESS = 0x01,
1269e705c121SKalle Valo 	TX_STATUS_DIRECT_DONE = 0x02,
1270e705c121SKalle Valo 	/* postpone TX */
1271e705c121SKalle Valo 	TX_STATUS_POSTPONE_DELAY = 0x40,
1272e705c121SKalle Valo 	TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
1273e705c121SKalle Valo 	TX_STATUS_POSTPONE_BT_PRIO = 0x42,
1274e705c121SKalle Valo 	TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
1275e705c121SKalle Valo 	TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
1276e705c121SKalle Valo 	/* abort TX */
1277e705c121SKalle Valo 	TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
1278e705c121SKalle Valo 	TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
1279e705c121SKalle Valo 	TX_STATUS_FAIL_LONG_LIMIT = 0x83,
1280e705c121SKalle Valo 	TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
1281e705c121SKalle Valo 	TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
1282e705c121SKalle Valo 	TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
1283e705c121SKalle Valo 	TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
1284e705c121SKalle Valo 	TX_STATUS_FAIL_DEST_PS = 0x88,
1285e705c121SKalle Valo 	TX_STATUS_FAIL_HOST_ABORTED = 0x89,
1286e705c121SKalle Valo 	TX_STATUS_FAIL_BT_RETRY = 0x8a,
1287e705c121SKalle Valo 	TX_STATUS_FAIL_STA_INVALID = 0x8b,
1288e705c121SKalle Valo 	TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
1289e705c121SKalle Valo 	TX_STATUS_FAIL_TID_DISABLE = 0x8d,
1290e705c121SKalle Valo 	TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
1291e705c121SKalle Valo 	TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
1292e705c121SKalle Valo 	TX_STATUS_FAIL_PASSIVE_NO_RX = 0x90,
1293e705c121SKalle Valo 	TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
1294e705c121SKalle Valo };
1295e705c121SKalle Valo 
1296e705c121SKalle Valo #define	TX_PACKET_MODE_REGULAR		0x0000
1297e705c121SKalle Valo #define	TX_PACKET_MODE_BURST_SEQ	0x0100
1298e705c121SKalle Valo #define	TX_PACKET_MODE_BURST_FIRST	0x0200
1299e705c121SKalle Valo 
1300e705c121SKalle Valo enum {
1301e705c121SKalle Valo 	TX_POWER_PA_NOT_ACTIVE = 0x0,
1302e705c121SKalle Valo };
1303e705c121SKalle Valo 
1304e705c121SKalle Valo enum {
1305e705c121SKalle Valo 	TX_STATUS_MSK = 0x000000ff,		/* bits 0:7 */
1306e705c121SKalle Valo 	TX_STATUS_DELAY_MSK = 0x00000040,
1307e705c121SKalle Valo 	TX_STATUS_ABORT_MSK = 0x00000080,
1308e705c121SKalle Valo 	TX_PACKET_MODE_MSK = 0x0000ff00,	/* bits 8:15 */
1309e705c121SKalle Valo 	TX_FIFO_NUMBER_MSK = 0x00070000,	/* bits 16:18 */
1310e705c121SKalle Valo 	TX_RESERVED = 0x00780000,		/* bits 19:22 */
1311e705c121SKalle Valo 	TX_POWER_PA_DETECT_MSK = 0x7f800000,	/* bits 23:30 */
1312e705c121SKalle Valo 	TX_ABORT_REQUIRED_MSK = 0x80000000,	/* bits 31:31 */
1313e705c121SKalle Valo };
1314e705c121SKalle Valo 
1315e705c121SKalle Valo /* *******************************
1316e705c121SKalle Valo  * TX aggregation status
1317e705c121SKalle Valo  ******************************* */
1318e705c121SKalle Valo 
1319e705c121SKalle Valo enum {
1320e705c121SKalle Valo 	AGG_TX_STATE_TRANSMITTED = 0x00,
1321e705c121SKalle Valo 	AGG_TX_STATE_UNDERRUN_MSK = 0x01,
1322e705c121SKalle Valo 	AGG_TX_STATE_BT_PRIO_MSK = 0x02,
1323e705c121SKalle Valo 	AGG_TX_STATE_FEW_BYTES_MSK = 0x04,
1324e705c121SKalle Valo 	AGG_TX_STATE_ABORT_MSK = 0x08,
1325e705c121SKalle Valo 	AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10,
1326e705c121SKalle Valo 	AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20,
1327e705c121SKalle Valo 	AGG_TX_STATE_LAST_SENT_BT_KILL_MSK = 0x40,
1328e705c121SKalle Valo 	AGG_TX_STATE_SCD_QUERY_MSK = 0x80,
1329e705c121SKalle Valo 	AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100,
1330e705c121SKalle Valo 	AGG_TX_STATE_RESPONSE_MSK = 0x1ff,
1331e705c121SKalle Valo 	AGG_TX_STATE_DUMP_TX_MSK = 0x200,
1332e705c121SKalle Valo 	AGG_TX_STATE_DELAY_TX_MSK = 0x400
1333e705c121SKalle Valo };
1334e705c121SKalle Valo 
1335e705c121SKalle Valo #define AGG_TX_STATUS_MSK	0x00000fff	/* bits 0:11 */
1336e705c121SKalle Valo #define AGG_TX_TRY_MSK		0x0000f000	/* bits 12:15 */
1337e705c121SKalle Valo #define AGG_TX_TRY_POS		12
1338e705c121SKalle Valo 
1339e705c121SKalle Valo #define AGG_TX_STATE_LAST_SENT_MSK  (AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1340e705c121SKalle Valo 				     AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK | \
1341e705c121SKalle Valo 				     AGG_TX_STATE_LAST_SENT_BT_KILL_MSK)
1342e705c121SKalle Valo 
1343e705c121SKalle Valo /* # tx attempts for first frame in aggregation */
1344e705c121SKalle Valo #define AGG_TX_STATE_TRY_CNT_POS 12
1345e705c121SKalle Valo #define AGG_TX_STATE_TRY_CNT_MSK 0xf000
1346e705c121SKalle Valo 
1347e705c121SKalle Valo /* Command ID and sequence number of Tx command for this frame */
1348e705c121SKalle Valo #define AGG_TX_STATE_SEQ_NUM_POS 16
1349e705c121SKalle Valo #define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1350e705c121SKalle Valo 
1351e705c121SKalle Valo /*
1352e705c121SKalle Valo  * REPLY_TX = 0x1c (response)
1353e705c121SKalle Valo  *
1354e705c121SKalle Valo  * This response may be in one of two slightly different formats, indicated
1355e705c121SKalle Valo  * by the frame_count field:
1356e705c121SKalle Valo  *
1357e705c121SKalle Valo  * 1)  No aggregation (frame_count == 1).  This reports Tx results for
1358e705c121SKalle Valo  *     a single frame.  Multiple attempts, at various bit rates, may have
1359e705c121SKalle Valo  *     been made for this frame.
1360e705c121SKalle Valo  *
1361e705c121SKalle Valo  * 2)  Aggregation (frame_count > 1).  This reports Tx results for
1362e705c121SKalle Valo  *     2 or more frames that used block-acknowledge.  All frames were
1363e705c121SKalle Valo  *     transmitted at same rate.  Rate scaling may have been used if first
1364e705c121SKalle Valo  *     frame in this new agg block failed in previous agg block(s).
1365e705c121SKalle Valo  *
1366e705c121SKalle Valo  *     Note that, for aggregation, ACK (block-ack) status is not delivered here;
1367e705c121SKalle Valo  *     block-ack has not been received by the time the agn device records
1368e705c121SKalle Valo  *     this status.
1369e705c121SKalle Valo  *     This status relates to reasons the tx might have been blocked or aborted
1370e705c121SKalle Valo  *     within the sending station (this agn device), rather than whether it was
1371e705c121SKalle Valo  *     received successfully by the destination station.
1372e705c121SKalle Valo  */
1373e705c121SKalle Valo struct agg_tx_status {
1374e705c121SKalle Valo 	__le16 status;
1375e705c121SKalle Valo 	__le16 sequence;
1376e705c121SKalle Valo } __packed;
1377e705c121SKalle Valo 
1378e705c121SKalle Valo /* refer to ra_tid */
1379e705c121SKalle Valo #define IWLAGN_TX_RES_TID_POS	0
1380e705c121SKalle Valo #define IWLAGN_TX_RES_TID_MSK	0x0f
1381e705c121SKalle Valo #define IWLAGN_TX_RES_RA_POS	4
1382e705c121SKalle Valo #define IWLAGN_TX_RES_RA_MSK	0xf0
1383e705c121SKalle Valo 
1384e705c121SKalle Valo struct iwlagn_tx_resp {
1385e705c121SKalle Valo 	u8 frame_count;		/* 1 no aggregation, >1 aggregation */
1386e705c121SKalle Valo 	u8 bt_kill_count;	/* # blocked by bluetooth (unused for agg) */
1387e705c121SKalle Valo 	u8 failure_rts;		/* # failures due to unsuccessful RTS */
1388e705c121SKalle Valo 	u8 failure_frame;	/* # failures due to no ACK (unused for agg) */
1389e705c121SKalle Valo 
1390e705c121SKalle Valo 	/* For non-agg:  Rate at which frame was successful.
1391e705c121SKalle Valo 	 * For agg:  Rate at which all frames were transmitted. */
1392e705c121SKalle Valo 	__le32 rate_n_flags;	/* RATE_MCS_*  */
1393e705c121SKalle Valo 
1394e705c121SKalle Valo 	/* For non-agg:  RTS + CTS + frame tx attempts time + ACK.
1395e705c121SKalle Valo 	 * For agg:  RTS + CTS + aggregation tx time + block-ack time. */
1396e705c121SKalle Valo 	__le16 wireless_media_time;	/* uSecs */
1397e705c121SKalle Valo 
1398e705c121SKalle Valo 	u8 pa_status;		/* RF power amplifier measurement (not used) */
1399e705c121SKalle Valo 	u8 pa_integ_res_a[3];
1400e705c121SKalle Valo 	u8 pa_integ_res_b[3];
1401e705c121SKalle Valo 	u8 pa_integ_res_C[3];
1402e705c121SKalle Valo 
1403e705c121SKalle Valo 	__le32 tfd_info;
1404e705c121SKalle Valo 	__le16 seq_ctl;
1405e705c121SKalle Valo 	__le16 byte_cnt;
1406e705c121SKalle Valo 	u8 tlc_info;
1407e705c121SKalle Valo 	u8 ra_tid;		/* tid (0:3), sta_id (4:7) */
1408e705c121SKalle Valo 	__le16 frame_ctrl;
1409e705c121SKalle Valo 	/*
1410e705c121SKalle Valo 	 * For non-agg:  frame status TX_STATUS_*
1411e705c121SKalle Valo 	 * For agg:  status of 1st frame, AGG_TX_STATE_*; other frame status
1412e705c121SKalle Valo 	 *           fields follow this one, up to frame_count.
1413e705c121SKalle Valo 	 *           Bit fields:
1414e705c121SKalle Valo 	 *           11- 0:  AGG_TX_STATE_* status code
1415e705c121SKalle Valo 	 *           15-12:  Retry count for 1st frame in aggregation (retries
1416e705c121SKalle Valo 	 *                   occur if tx failed for this frame when it was a
1417e705c121SKalle Valo 	 *                   member of a previous aggregation block).  If rate
1418e705c121SKalle Valo 	 *                   scaling is used, retry count indicates the rate
1419e705c121SKalle Valo 	 *                   table entry used for all frames in the new agg.
1420e705c121SKalle Valo 	 *           31-16:  Sequence # for this frame's Tx cmd (not SSN!)
1421e705c121SKalle Valo 	 */
1422e705c121SKalle Valo 	struct agg_tx_status status;	/* TX status (in aggregation -
1423e705c121SKalle Valo 					 * status of 1st frame) */
1424e705c121SKalle Valo } __packed;
1425e705c121SKalle Valo /*
1426e705c121SKalle Valo  * REPLY_COMPRESSED_BA = 0xc5 (response only, not a command)
1427e705c121SKalle Valo  *
1428e705c121SKalle Valo  * Reports Block-Acknowledge from recipient station
1429e705c121SKalle Valo  */
1430e705c121SKalle Valo struct iwl_compressed_ba_resp {
1431e705c121SKalle Valo 	__le32 sta_addr_lo32;
1432e705c121SKalle Valo 	__le16 sta_addr_hi16;
1433e705c121SKalle Valo 	__le16 reserved;
1434e705c121SKalle Valo 
1435e705c121SKalle Valo 	/* Index of recipient (BA-sending) station in uCode's station table */
1436e705c121SKalle Valo 	u8 sta_id;
1437e705c121SKalle Valo 	u8 tid;
1438e705c121SKalle Valo 	__le16 seq_ctl;
1439e705c121SKalle Valo 	__le64 bitmap;
1440e705c121SKalle Valo 	__le16 scd_flow;
1441e705c121SKalle Valo 	__le16 scd_ssn;
1442e705c121SKalle Valo 	u8 txed;	/* number of frames sent */
1443e705c121SKalle Valo 	u8 txed_2_done; /* number of frames acked */
1444e705c121SKalle Valo 	__le16 reserved1;
1445e705c121SKalle Valo } __packed;
1446e705c121SKalle Valo 
1447e705c121SKalle Valo /*
1448e705c121SKalle Valo  * REPLY_TX_PWR_TABLE_CMD = 0x97 (command, has simple generic response)
1449e705c121SKalle Valo  *
1450e705c121SKalle Valo  */
1451e705c121SKalle Valo 
1452e705c121SKalle Valo /*RS_NEW_API: only TLC_RTS remains and moved to bit 0 */
1453e705c121SKalle Valo #define  LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK	(1 << 0)
1454e705c121SKalle Valo 
1455e705c121SKalle Valo /* # of EDCA prioritized tx fifos */
1456e705c121SKalle Valo #define  LINK_QUAL_AC_NUM AC_NUM
1457e705c121SKalle Valo 
1458e705c121SKalle Valo /* # entries in rate scale table to support Tx retries */
1459e705c121SKalle Valo #define  LINK_QUAL_MAX_RETRY_NUM 16
1460e705c121SKalle Valo 
1461e705c121SKalle Valo /* Tx antenna selection values */
1462e705c121SKalle Valo #define  LINK_QUAL_ANT_A_MSK (1 << 0)
1463e705c121SKalle Valo #define  LINK_QUAL_ANT_B_MSK (1 << 1)
1464e705c121SKalle Valo #define  LINK_QUAL_ANT_MSK   (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK)
1465e705c121SKalle Valo 
1466e705c121SKalle Valo 
1467e705c121SKalle Valo /**
1468e705c121SKalle Valo  * struct iwl_link_qual_general_params
1469e705c121SKalle Valo  *
1470e705c121SKalle Valo  * Used in REPLY_TX_LINK_QUALITY_CMD
1471e705c121SKalle Valo  */
1472e705c121SKalle Valo struct iwl_link_qual_general_params {
1473e705c121SKalle Valo 	u8 flags;
1474e705c121SKalle Valo 
1475e705c121SKalle Valo 	/* No entries at or above this (driver chosen) index contain MIMO */
1476e705c121SKalle Valo 	u8 mimo_delimiter;
1477e705c121SKalle Valo 
1478e705c121SKalle Valo 	/* Best single antenna to use for single stream (legacy, SISO). */
1479e705c121SKalle Valo 	u8 single_stream_ant_msk;	/* LINK_QUAL_ANT_* */
1480e705c121SKalle Valo 
1481fb70d49fSLuca Coelho 	/* Best antennas to use for MIMO */
1482e705c121SKalle Valo 	u8 dual_stream_ant_msk;		/* LINK_QUAL_ANT_* */
1483e705c121SKalle Valo 
1484e705c121SKalle Valo 	/*
1485e705c121SKalle Valo 	 * If driver needs to use different initial rates for different
1486e705c121SKalle Valo 	 * EDCA QOS access categories (as implemented by tx fifos 0-3),
1487e705c121SKalle Valo 	 * this table will set that up, by indicating the indexes in the
1488e705c121SKalle Valo 	 * rs_table[LINK_QUAL_MAX_RETRY_NUM] rate table at which to start.
1489e705c121SKalle Valo 	 * Otherwise, driver should set all entries to 0.
1490e705c121SKalle Valo 	 *
1491e705c121SKalle Valo 	 * Entry usage:
1492e705c121SKalle Valo 	 * 0 = Background, 1 = Best Effort (normal), 2 = Video, 3 = Voice
1493e705c121SKalle Valo 	 * TX FIFOs above 3 use same value (typically 0) as TX FIFO 3.
1494e705c121SKalle Valo 	 */
1495e705c121SKalle Valo 	u8 start_rate_index[LINK_QUAL_AC_NUM];
1496e705c121SKalle Valo } __packed;
1497e705c121SKalle Valo 
1498e705c121SKalle Valo #define LINK_QUAL_AGG_TIME_LIMIT_DEF	(4000) /* 4 milliseconds */
1499e705c121SKalle Valo #define LINK_QUAL_AGG_TIME_LIMIT_MAX	(8000)
1500e705c121SKalle Valo #define LINK_QUAL_AGG_TIME_LIMIT_MIN	(100)
1501e705c121SKalle Valo 
1502e705c121SKalle Valo #define LINK_QUAL_AGG_DISABLE_START_DEF	(3)
1503e705c121SKalle Valo #define LINK_QUAL_AGG_DISABLE_START_MAX	(255)
1504e705c121SKalle Valo #define LINK_QUAL_AGG_DISABLE_START_MIN	(0)
1505e705c121SKalle Valo 
1506e705c121SKalle Valo #define LINK_QUAL_AGG_FRAME_LIMIT_DEF	(63)
1507e705c121SKalle Valo #define LINK_QUAL_AGG_FRAME_LIMIT_MAX	(63)
1508e705c121SKalle Valo #define LINK_QUAL_AGG_FRAME_LIMIT_MIN	(0)
1509e705c121SKalle Valo 
1510e705c121SKalle Valo /**
1511e705c121SKalle Valo  * struct iwl_link_qual_agg_params
1512e705c121SKalle Valo  *
1513e705c121SKalle Valo  * Used in REPLY_TX_LINK_QUALITY_CMD
1514e705c121SKalle Valo  */
1515e705c121SKalle Valo struct iwl_link_qual_agg_params {
1516e705c121SKalle Valo 
1517e705c121SKalle Valo 	/*
1518e705c121SKalle Valo 	 *Maximum number of uSec in aggregation.
1519e705c121SKalle Valo 	 * default set to 4000 (4 milliseconds) if not configured in .cfg
1520e705c121SKalle Valo 	 */
1521e705c121SKalle Valo 	__le16 agg_time_limit;
1522e705c121SKalle Valo 
1523e705c121SKalle Valo 	/*
1524e705c121SKalle Valo 	 * Number of Tx retries allowed for a frame, before that frame will
1525e705c121SKalle Valo 	 * no longer be considered for the start of an aggregation sequence
1526e705c121SKalle Valo 	 * (scheduler will then try to tx it as single frame).
1527e705c121SKalle Valo 	 * Driver should set this to 3.
1528e705c121SKalle Valo 	 */
1529e705c121SKalle Valo 	u8 agg_dis_start_th;
1530e705c121SKalle Valo 
1531e705c121SKalle Valo 	/*
1532e705c121SKalle Valo 	 * Maximum number of frames in aggregation.
1533e705c121SKalle Valo 	 * 0 = no limit (default).  1 = no aggregation.
1534e705c121SKalle Valo 	 * Other values = max # frames in aggregation.
1535e705c121SKalle Valo 	 */
1536e705c121SKalle Valo 	u8 agg_frame_cnt_limit;
1537e705c121SKalle Valo 
1538e705c121SKalle Valo 	__le32 reserved;
1539e705c121SKalle Valo } __packed;
1540e705c121SKalle Valo 
1541e705c121SKalle Valo /*
1542e705c121SKalle Valo  * REPLY_TX_LINK_QUALITY_CMD = 0x4e (command, has simple generic response)
1543e705c121SKalle Valo  *
1544e705c121SKalle Valo  * For agn devices
1545e705c121SKalle Valo  *
1546e705c121SKalle Valo  * Each station in the agn device's internal station table has its own table
1547e705c121SKalle Valo  * of 16
1548e705c121SKalle Valo  * Tx rates and modulation modes (e.g. legacy/SISO/MIMO) for retrying Tx when
1549e705c121SKalle Valo  * an ACK is not received.  This command replaces the entire table for
1550e705c121SKalle Valo  * one station.
1551e705c121SKalle Valo  *
1552e705c121SKalle Valo  * NOTE:  Station must already be in agn device's station table.
1553e705c121SKalle Valo  *	  Use REPLY_ADD_STA.
1554e705c121SKalle Valo  *
1555e705c121SKalle Valo  * The rate scaling procedures described below work well.  Of course, other
1556e705c121SKalle Valo  * procedures are possible, and may work better for particular environments.
1557e705c121SKalle Valo  *
1558e705c121SKalle Valo  *
1559e705c121SKalle Valo  * FILLING THE RATE TABLE
1560e705c121SKalle Valo  *
1561e705c121SKalle Valo  * Given a particular initial rate and mode, as determined by the rate
1562e705c121SKalle Valo  * scaling algorithm described below, the Linux driver uses the following
1563e705c121SKalle Valo  * formula to fill the rs_table[LINK_QUAL_MAX_RETRY_NUM] rate table in the
1564e705c121SKalle Valo  * Link Quality command:
1565e705c121SKalle Valo  *
1566e705c121SKalle Valo  *
1567e705c121SKalle Valo  * 1)  If using High-throughput (HT) (SISO or MIMO) initial rate:
1568e705c121SKalle Valo  *     a) Use this same initial rate for first 3 entries.
1569e705c121SKalle Valo  *     b) Find next lower available rate using same mode (SISO or MIMO),
1570e705c121SKalle Valo  *        use for next 3 entries.  If no lower rate available, switch to
1571e705c121SKalle Valo  *        legacy mode (no HT40 channel, no MIMO, no short guard interval).
1572e705c121SKalle Valo  *     c) If using MIMO, set command's mimo_delimiter to number of entries
1573e705c121SKalle Valo  *        using MIMO (3 or 6).
1574e705c121SKalle Valo  *     d) After trying 2 HT rates, switch to legacy mode (no HT40 channel,
1575e705c121SKalle Valo  *        no MIMO, no short guard interval), at the next lower bit rate
1576e705c121SKalle Valo  *        (e.g. if second HT bit rate was 54, try 48 legacy), and follow
1577e705c121SKalle Valo  *        legacy procedure for remaining table entries.
1578e705c121SKalle Valo  *
1579e705c121SKalle Valo  * 2)  If using legacy initial rate:
1580e705c121SKalle Valo  *     a) Use the initial rate for only one entry.
1581e705c121SKalle Valo  *     b) For each following entry, reduce the rate to next lower available
1582e705c121SKalle Valo  *        rate, until reaching the lowest available rate.
1583e705c121SKalle Valo  *     c) When reducing rate, also switch antenna selection.
1584e705c121SKalle Valo  *     d) Once lowest available rate is reached, repeat this rate until
1585e705c121SKalle Valo  *        rate table is filled (16 entries), switching antenna each entry.
1586e705c121SKalle Valo  *
1587e705c121SKalle Valo  *
1588e705c121SKalle Valo  * ACCUMULATING HISTORY
1589e705c121SKalle Valo  *
1590e705c121SKalle Valo  * The rate scaling algorithm for agn devices, as implemented in Linux driver,
1591e705c121SKalle Valo  * uses two sets of frame Tx success history:  One for the current/active
1592e705c121SKalle Valo  * modulation mode, and one for a speculative/search mode that is being
1593e705c121SKalle Valo  * attempted. If the speculative mode turns out to be more effective (i.e.
1594e705c121SKalle Valo  * actual transfer rate is better), then the driver continues to use the
1595e705c121SKalle Valo  * speculative mode as the new current active mode.
1596e705c121SKalle Valo  *
1597e705c121SKalle Valo  * Each history set contains, separately for each possible rate, data for a
1598e705c121SKalle Valo  * sliding window of the 62 most recent tx attempts at that rate.  The data
1599e705c121SKalle Valo  * includes a shifting bitmap of success(1)/failure(0), and sums of successful
1600e705c121SKalle Valo  * and attempted frames, from which the driver can additionally calculate a
1601e705c121SKalle Valo  * success ratio (success / attempted) and number of failures
1602e705c121SKalle Valo  * (attempted - success), and control the size of the window (attempted).
1603e705c121SKalle Valo  * The driver uses the bit map to remove successes from the success sum, as
1604e705c121SKalle Valo  * the oldest tx attempts fall out of the window.
1605e705c121SKalle Valo  *
1606e705c121SKalle Valo  * When the agn device makes multiple tx attempts for a given frame, each
1607e705c121SKalle Valo  * attempt might be at a different rate, and have different modulation
1608e705c121SKalle Valo  * characteristics (e.g. antenna, fat channel, short guard interval), as set
1609e705c121SKalle Valo  * up in the rate scaling table in the Link Quality command.  The driver must
1610e705c121SKalle Valo  * determine which rate table entry was used for each tx attempt, to determine
1611e705c121SKalle Valo  * which rate-specific history to update, and record only those attempts that
1612e705c121SKalle Valo  * match the modulation characteristics of the history set.
1613e705c121SKalle Valo  *
1614e705c121SKalle Valo  * When using block-ack (aggregation), all frames are transmitted at the same
1615e705c121SKalle Valo  * rate, since there is no per-attempt acknowledgment from the destination
1616e705c121SKalle Valo  * station.  The Tx response struct iwl_tx_resp indicates the Tx rate in
1617e705c121SKalle Valo  * rate_n_flags field.  After receiving a block-ack, the driver can update
1618e705c121SKalle Valo  * history for the entire block all at once.
1619e705c121SKalle Valo  *
1620e705c121SKalle Valo  *
1621e705c121SKalle Valo  * FINDING BEST STARTING RATE:
1622e705c121SKalle Valo  *
1623e705c121SKalle Valo  * When working with a selected initial modulation mode (see below), the
1624e705c121SKalle Valo  * driver attempts to find a best initial rate.  The initial rate is the
1625e705c121SKalle Valo  * first entry in the Link Quality command's rate table.
1626e705c121SKalle Valo  *
1627e705c121SKalle Valo  * 1)  Calculate actual throughput (success ratio * expected throughput, see
1628e705c121SKalle Valo  *     table below) for current initial rate.  Do this only if enough frames
1629e705c121SKalle Valo  *     have been attempted to make the value meaningful:  at least 6 failed
1630e705c121SKalle Valo  *     tx attempts, or at least 8 successes.  If not enough, don't try rate
1631e705c121SKalle Valo  *     scaling yet.
1632e705c121SKalle Valo  *
1633e705c121SKalle Valo  * 2)  Find available rates adjacent to current initial rate.  Available means:
1634e705c121SKalle Valo  *     a)  supported by hardware &&
1635e705c121SKalle Valo  *     b)  supported by association &&
1636e705c121SKalle Valo  *     c)  within any constraints selected by user
1637e705c121SKalle Valo  *
1638e705c121SKalle Valo  * 3)  Gather measured throughputs for adjacent rates.  These might not have
1639e705c121SKalle Valo  *     enough history to calculate a throughput.  That's okay, we might try
1640e705c121SKalle Valo  *     using one of them anyway!
1641e705c121SKalle Valo  *
1642e705c121SKalle Valo  * 4)  Try decreasing rate if, for current rate:
1643e705c121SKalle Valo  *     a)  success ratio is < 15% ||
1644e705c121SKalle Valo  *     b)  lower adjacent rate has better measured throughput ||
1645e705c121SKalle Valo  *     c)  higher adjacent rate has worse throughput, and lower is unmeasured
1646e705c121SKalle Valo  *
1647e705c121SKalle Valo  *     As a sanity check, if decrease was determined above, leave rate
1648e705c121SKalle Valo  *     unchanged if:
1649e705c121SKalle Valo  *     a)  lower rate unavailable
1650e705c121SKalle Valo  *     b)  success ratio at current rate > 85% (very good)
1651e705c121SKalle Valo  *     c)  current measured throughput is better than expected throughput
1652e705c121SKalle Valo  *         of lower rate (under perfect 100% tx conditions, see table below)
1653e705c121SKalle Valo  *
1654e705c121SKalle Valo  * 5)  Try increasing rate if, for current rate:
1655e705c121SKalle Valo  *     a)  success ratio is < 15% ||
1656e705c121SKalle Valo  *     b)  both adjacent rates' throughputs are unmeasured (try it!) ||
1657e705c121SKalle Valo  *     b)  higher adjacent rate has better measured throughput ||
1658e705c121SKalle Valo  *     c)  lower adjacent rate has worse throughput, and higher is unmeasured
1659e705c121SKalle Valo  *
1660e705c121SKalle Valo  *     As a sanity check, if increase was determined above, leave rate
1661e705c121SKalle Valo  *     unchanged if:
1662e705c121SKalle Valo  *     a)  success ratio at current rate < 70%.  This is not particularly
1663e705c121SKalle Valo  *         good performance; higher rate is sure to have poorer success.
1664e705c121SKalle Valo  *
1665e705c121SKalle Valo  * 6)  Re-evaluate the rate after each tx frame.  If working with block-
1666e705c121SKalle Valo  *     acknowledge, history and statistics may be calculated for the entire
1667e705c121SKalle Valo  *     block (including prior history that fits within the history windows),
1668e705c121SKalle Valo  *     before re-evaluation.
1669e705c121SKalle Valo  *
1670e705c121SKalle Valo  * FINDING BEST STARTING MODULATION MODE:
1671e705c121SKalle Valo  *
1672e705c121SKalle Valo  * After working with a modulation mode for a "while" (and doing rate scaling),
1673e705c121SKalle Valo  * the driver searches for a new initial mode in an attempt to improve
1674e705c121SKalle Valo  * throughput.  The "while" is measured by numbers of attempted frames:
1675e705c121SKalle Valo  *
1676e705c121SKalle Valo  * For legacy mode, search for new mode after:
1677e705c121SKalle Valo  *   480 successful frames, or 160 failed frames
1678e705c121SKalle Valo  * For high-throughput modes (SISO or MIMO), search for new mode after:
1679e705c121SKalle Valo  *   4500 successful frames, or 400 failed frames
1680e705c121SKalle Valo  *
1681e705c121SKalle Valo  * Mode switch possibilities are (3 for each mode):
1682e705c121SKalle Valo  *
1683e705c121SKalle Valo  * For legacy:
1684e705c121SKalle Valo  *   Change antenna, try SISO (if HT association), try MIMO (if HT association)
1685e705c121SKalle Valo  * For SISO:
1686e705c121SKalle Valo  *   Change antenna, try MIMO, try shortened guard interval (SGI)
1687e705c121SKalle Valo  * For MIMO:
1688e705c121SKalle Valo  *   Try SISO antenna A, SISO antenna B, try shortened guard interval (SGI)
1689e705c121SKalle Valo  *
1690e705c121SKalle Valo  * When trying a new mode, use the same bit rate as the old/current mode when
1691e705c121SKalle Valo  * trying antenna switches and shortened guard interval.  When switching to
1692e705c121SKalle Valo  * SISO from MIMO or legacy, or to MIMO from SISO or legacy, use a rate
1693e705c121SKalle Valo  * for which the expected throughput (under perfect conditions) is about the
1694e705c121SKalle Valo  * same or slightly better than the actual measured throughput delivered by
1695e705c121SKalle Valo  * the old/current mode.
1696e705c121SKalle Valo  *
1697e705c121SKalle Valo  * Actual throughput can be estimated by multiplying the expected throughput
1698e705c121SKalle Valo  * by the success ratio (successful / attempted tx frames).  Frame size is
1699e705c121SKalle Valo  * not considered in this calculation; it assumes that frame size will average
1700e705c121SKalle Valo  * out to be fairly consistent over several samples.  The following are
1701e705c121SKalle Valo  * metric values for expected throughput assuming 100% success ratio.
1702e705c121SKalle Valo  * Only G band has support for CCK rates:
1703e705c121SKalle Valo  *
1704e705c121SKalle Valo  *           RATE:  1    2    5   11    6   9   12   18   24   36   48   54   60
1705e705c121SKalle Valo  *
1706e705c121SKalle Valo  *              G:  7   13   35   58   40  57   72   98  121  154  177  186  186
1707e705c121SKalle Valo  *              A:  0    0    0    0   40  57   72   98  121  154  177  186  186
1708e705c121SKalle Valo  *     SISO 20MHz:  0    0    0    0   42  42   76  102  124  159  183  193  202
1709e705c121SKalle Valo  * SGI SISO 20MHz:  0    0    0    0   46  46   82  110  132  168  192  202  211
1710e705c121SKalle Valo  *     MIMO 20MHz:  0    0    0    0   74  74  123  155  179  214  236  244  251
1711e705c121SKalle Valo  * SGI MIMO 20MHz:  0    0    0    0   81  81  131  164  188  222  243  251  257
1712e705c121SKalle Valo  *     SISO 40MHz:  0    0    0    0   77  77  127  160  184  220  242  250  257
1713e705c121SKalle Valo  * SGI SISO 40MHz:  0    0    0    0   83  83  135  169  193  229  250  257  264
1714e705c121SKalle Valo  *     MIMO 40MHz:  0    0    0    0  123 123  182  214  235  264  279  285  289
1715e705c121SKalle Valo  * SGI MIMO 40MHz:  0    0    0    0  131 131  191  222  242  270  284  289  293
1716e705c121SKalle Valo  *
1717e705c121SKalle Valo  * After the new mode has been tried for a short while (minimum of 6 failed
1718e705c121SKalle Valo  * frames or 8 successful frames), compare success ratio and actual throughput
1719e705c121SKalle Valo  * estimate of the new mode with the old.  If either is better with the new
1720e705c121SKalle Valo  * mode, continue to use the new mode.
1721e705c121SKalle Valo  *
1722e705c121SKalle Valo  * Continue comparing modes until all 3 possibilities have been tried.
1723e705c121SKalle Valo  * If moving from legacy to HT, try all 3 possibilities from the new HT
1724e705c121SKalle Valo  * mode.  After trying all 3, a best mode is found.  Continue to use this mode
1725e705c121SKalle Valo  * for the longer "while" described above (e.g. 480 successful frames for
1726e705c121SKalle Valo  * legacy), and then repeat the search process.
1727e705c121SKalle Valo  *
1728e705c121SKalle Valo  */
1729e705c121SKalle Valo struct iwl_link_quality_cmd {
1730e705c121SKalle Valo 
1731e705c121SKalle Valo 	/* Index of destination/recipient station in uCode's station table */
1732e705c121SKalle Valo 	u8 sta_id;
1733e705c121SKalle Valo 	u8 reserved1;
1734e705c121SKalle Valo 	__le16 control;		/* not used */
1735e705c121SKalle Valo 	struct iwl_link_qual_general_params general_params;
1736e705c121SKalle Valo 	struct iwl_link_qual_agg_params agg_params;
1737e705c121SKalle Valo 
1738e705c121SKalle Valo 	/*
1739e705c121SKalle Valo 	 * Rate info; when using rate-scaling, Tx command's initial_rate_index
1740e705c121SKalle Valo 	 * specifies 1st Tx rate attempted, via index into this table.
1741e705c121SKalle Valo 	 * agn devices works its way through table when retrying Tx.
1742e705c121SKalle Valo 	 */
1743e705c121SKalle Valo 	struct {
1744e705c121SKalle Valo 		__le32 rate_n_flags;	/* RATE_MCS_*, IWL_RATE_* */
1745e705c121SKalle Valo 	} rs_table[LINK_QUAL_MAX_RETRY_NUM];
1746e705c121SKalle Valo 	__le32 reserved2;
1747e705c121SKalle Valo } __packed;
1748e705c121SKalle Valo 
1749e705c121SKalle Valo /*
1750e705c121SKalle Valo  * BT configuration enable flags:
1751e705c121SKalle Valo  *   bit 0 - 1: BT channel announcement enabled
1752e705c121SKalle Valo  *           0: disable
1753e705c121SKalle Valo  *   bit 1 - 1: priority of BT device enabled
1754e705c121SKalle Valo  *           0: disable
1755e705c121SKalle Valo  *   bit 2 - 1: BT 2 wire support enabled
1756e705c121SKalle Valo  *           0: disable
1757e705c121SKalle Valo  */
1758e705c121SKalle Valo #define BT_COEX_DISABLE (0x0)
1759e705c121SKalle Valo #define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
1760e705c121SKalle Valo #define BT_ENABLE_PRIORITY	   BIT(1)
1761e705c121SKalle Valo #define BT_ENABLE_2_WIRE	   BIT(2)
1762e705c121SKalle Valo 
1763e705c121SKalle Valo #define BT_COEX_DISABLE (0x0)
1764e705c121SKalle Valo #define BT_COEX_ENABLE  (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY)
1765e705c121SKalle Valo 
1766e705c121SKalle Valo #define BT_LEAD_TIME_MIN (0x0)
1767e705c121SKalle Valo #define BT_LEAD_TIME_DEF (0x1E)
1768e705c121SKalle Valo #define BT_LEAD_TIME_MAX (0xFF)
1769e705c121SKalle Valo 
1770e705c121SKalle Valo #define BT_MAX_KILL_MIN (0x1)
1771e705c121SKalle Valo #define BT_MAX_KILL_DEF (0x5)
1772e705c121SKalle Valo #define BT_MAX_KILL_MAX (0xFF)
1773e705c121SKalle Valo 
1774e705c121SKalle Valo #define BT_DURATION_LIMIT_DEF	625
1775e705c121SKalle Valo #define BT_DURATION_LIMIT_MAX	1250
1776e705c121SKalle Valo #define BT_DURATION_LIMIT_MIN	625
1777e705c121SKalle Valo 
1778e705c121SKalle Valo #define BT_ON_THRESHOLD_DEF	4
1779e705c121SKalle Valo #define BT_ON_THRESHOLD_MAX	1000
1780e705c121SKalle Valo #define BT_ON_THRESHOLD_MIN	1
1781e705c121SKalle Valo 
1782e705c121SKalle Valo #define BT_FRAG_THRESHOLD_DEF	0
1783e705c121SKalle Valo #define BT_FRAG_THRESHOLD_MAX	0
1784e705c121SKalle Valo #define BT_FRAG_THRESHOLD_MIN	0
1785e705c121SKalle Valo 
1786e705c121SKalle Valo #define BT_AGG_THRESHOLD_DEF	1200
1787e705c121SKalle Valo #define BT_AGG_THRESHOLD_MAX	8000
1788e705c121SKalle Valo #define BT_AGG_THRESHOLD_MIN	400
1789e705c121SKalle Valo 
1790e705c121SKalle Valo /*
1791e705c121SKalle Valo  * REPLY_BT_CONFIG = 0x9b (command, has simple generic response)
1792e705c121SKalle Valo  *
1793e705c121SKalle Valo  * agn devices support hardware handshake with Bluetooth device on
1794e705c121SKalle Valo  * same platform.  Bluetooth device alerts wireless device when it will Tx;
1795e705c121SKalle Valo  * wireless device can delay or kill its own Tx to accommodate.
1796e705c121SKalle Valo  */
1797e705c121SKalle Valo struct iwl_bt_cmd {
1798e705c121SKalle Valo 	u8 flags;
1799e705c121SKalle Valo 	u8 lead_time;
1800e705c121SKalle Valo 	u8 max_kill;
1801e705c121SKalle Valo 	u8 reserved;
1802e705c121SKalle Valo 	__le32 kill_ack_mask;
1803e705c121SKalle Valo 	__le32 kill_cts_mask;
1804e705c121SKalle Valo } __packed;
1805e705c121SKalle Valo 
1806e705c121SKalle Valo #define IWLAGN_BT_FLAG_CHANNEL_INHIBITION	BIT(0)
1807e705c121SKalle Valo 
1808e705c121SKalle Valo #define IWLAGN_BT_FLAG_COEX_MODE_MASK		(BIT(3)|BIT(4)|BIT(5))
1809e705c121SKalle Valo #define IWLAGN_BT_FLAG_COEX_MODE_SHIFT		3
1810e705c121SKalle Valo #define IWLAGN_BT_FLAG_COEX_MODE_DISABLED	0
1811e705c121SKalle Valo #define IWLAGN_BT_FLAG_COEX_MODE_LEGACY_2W	1
1812e705c121SKalle Valo #define IWLAGN_BT_FLAG_COEX_MODE_3W		2
1813e705c121SKalle Valo #define IWLAGN_BT_FLAG_COEX_MODE_4W		3
1814e705c121SKalle Valo 
1815e705c121SKalle Valo #define IWLAGN_BT_FLAG_UCODE_DEFAULT		BIT(6)
1816e705c121SKalle Valo /* Disable Sync PSPoll on SCO/eSCO */
1817e705c121SKalle Valo #define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE	BIT(7)
1818e705c121SKalle Valo 
1819e705c121SKalle Valo #define IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD	-75 /* dBm */
1820e705c121SKalle Valo #define IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD	-65 /* dBm */
1821e705c121SKalle Valo 
1822e705c121SKalle Valo #define IWLAGN_BT_PRIO_BOOST_MAX	0xFF
1823e705c121SKalle Valo #define IWLAGN_BT_PRIO_BOOST_MIN	0x00
1824e705c121SKalle Valo #define IWLAGN_BT_PRIO_BOOST_DEFAULT	0xF0
1825e705c121SKalle Valo #define IWLAGN_BT_PRIO_BOOST_DEFAULT32	0xF0F0F0F0
1826e705c121SKalle Valo 
1827e705c121SKalle Valo #define IWLAGN_BT_MAX_KILL_DEFAULT	5
1828e705c121SKalle Valo 
1829e705c121SKalle Valo #define IWLAGN_BT3_T7_DEFAULT		1
1830e705c121SKalle Valo 
1831e705c121SKalle Valo enum iwl_bt_kill_idx {
1832e705c121SKalle Valo 	IWL_BT_KILL_DEFAULT = 0,
1833e705c121SKalle Valo 	IWL_BT_KILL_OVERRIDE = 1,
1834e705c121SKalle Valo 	IWL_BT_KILL_REDUCE = 2,
1835e705c121SKalle Valo };
1836e705c121SKalle Valo 
1837e705c121SKalle Valo #define IWLAGN_BT_KILL_ACK_MASK_DEFAULT	cpu_to_le32(0xffff0000)
1838e705c121SKalle Valo #define IWLAGN_BT_KILL_CTS_MASK_DEFAULT	cpu_to_le32(0xffff0000)
1839e705c121SKalle Valo #define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO	cpu_to_le32(0xffffffff)
1840e705c121SKalle Valo #define IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE	cpu_to_le32(0)
1841e705c121SKalle Valo 
1842e705c121SKalle Valo #define IWLAGN_BT3_PRIO_SAMPLE_DEFAULT	2
1843e705c121SKalle Valo 
1844e705c121SKalle Valo #define IWLAGN_BT3_T2_DEFAULT		0xc
1845e705c121SKalle Valo 
1846e705c121SKalle Valo #define IWLAGN_BT_VALID_ENABLE_FLAGS	cpu_to_le16(BIT(0))
1847e705c121SKalle Valo #define IWLAGN_BT_VALID_BOOST		cpu_to_le16(BIT(1))
1848e705c121SKalle Valo #define IWLAGN_BT_VALID_MAX_KILL	cpu_to_le16(BIT(2))
1849e705c121SKalle Valo #define IWLAGN_BT_VALID_3W_TIMERS	cpu_to_le16(BIT(3))
1850e705c121SKalle Valo #define IWLAGN_BT_VALID_KILL_ACK_MASK	cpu_to_le16(BIT(4))
1851e705c121SKalle Valo #define IWLAGN_BT_VALID_KILL_CTS_MASK	cpu_to_le16(BIT(5))
1852e705c121SKalle Valo #define IWLAGN_BT_VALID_REDUCED_TX_PWR	cpu_to_le16(BIT(6))
1853e705c121SKalle Valo #define IWLAGN_BT_VALID_3W_LUT		cpu_to_le16(BIT(7))
1854e705c121SKalle Valo 
1855e705c121SKalle Valo #define IWLAGN_BT_ALL_VALID_MSK		(IWLAGN_BT_VALID_ENABLE_FLAGS | \
1856e705c121SKalle Valo 					IWLAGN_BT_VALID_BOOST | \
1857e705c121SKalle Valo 					IWLAGN_BT_VALID_MAX_KILL | \
1858e705c121SKalle Valo 					IWLAGN_BT_VALID_3W_TIMERS | \
1859e705c121SKalle Valo 					IWLAGN_BT_VALID_KILL_ACK_MASK | \
1860e705c121SKalle Valo 					IWLAGN_BT_VALID_KILL_CTS_MASK | \
1861e705c121SKalle Valo 					IWLAGN_BT_VALID_REDUCED_TX_PWR | \
1862e705c121SKalle Valo 					IWLAGN_BT_VALID_3W_LUT)
1863e705c121SKalle Valo 
1864e705c121SKalle Valo #define IWLAGN_BT_REDUCED_TX_PWR	BIT(0)
1865e705c121SKalle Valo 
1866e705c121SKalle Valo #define IWLAGN_BT_DECISION_LUT_SIZE	12
1867e705c121SKalle Valo 
1868e705c121SKalle Valo struct iwl_basic_bt_cmd {
1869e705c121SKalle Valo 	u8 flags;
1870e705c121SKalle Valo 	u8 ledtime; /* unused */
1871e705c121SKalle Valo 	u8 max_kill;
1872e705c121SKalle Valo 	u8 bt3_timer_t7_value;
1873e705c121SKalle Valo 	__le32 kill_ack_mask;
1874e705c121SKalle Valo 	__le32 kill_cts_mask;
1875e705c121SKalle Valo 	u8 bt3_prio_sample_time;
1876e705c121SKalle Valo 	u8 bt3_timer_t2_value;
1877e705c121SKalle Valo 	__le16 bt4_reaction_time; /* unused */
1878e705c121SKalle Valo 	__le32 bt3_lookup_table[IWLAGN_BT_DECISION_LUT_SIZE];
1879e705c121SKalle Valo 	/*
1880e705c121SKalle Valo 	 * bit 0: use reduced tx power for control frame
1881e705c121SKalle Valo 	 * bit 1 - 7: reserved
1882e705c121SKalle Valo 	 */
1883e705c121SKalle Valo 	u8 reduce_txpower;
1884e705c121SKalle Valo 	u8 reserved;
1885e705c121SKalle Valo 	__le16 valid;
1886e705c121SKalle Valo };
1887e705c121SKalle Valo 
1888e705c121SKalle Valo struct iwl_bt_cmd_v1 {
1889e705c121SKalle Valo 	struct iwl_basic_bt_cmd basic;
1890e705c121SKalle Valo 	u8 prio_boost;
1891e705c121SKalle Valo 	/*
1892e705c121SKalle Valo 	 * set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask
1893e705c121SKalle Valo 	 * if configure the following patterns
1894e705c121SKalle Valo 	 */
1895e705c121SKalle Valo 	u8 tx_prio_boost;	/* SW boost of WiFi tx priority */
1896e705c121SKalle Valo 	__le16 rx_prio_boost;	/* SW boost of WiFi rx priority */
1897e705c121SKalle Valo };
1898e705c121SKalle Valo 
1899e705c121SKalle Valo struct iwl_bt_cmd_v2 {
1900e705c121SKalle Valo 	struct iwl_basic_bt_cmd basic;
1901e705c121SKalle Valo 	__le32 prio_boost;
1902e705c121SKalle Valo 	/*
1903e705c121SKalle Valo 	 * set IWLAGN_BT_VALID_BOOST to "1" in "valid" bitmask
1904e705c121SKalle Valo 	 * if configure the following patterns
1905e705c121SKalle Valo 	 */
1906e705c121SKalle Valo 	u8 reserved;
1907e705c121SKalle Valo 	u8 tx_prio_boost;	/* SW boost of WiFi tx priority */
1908e705c121SKalle Valo 	__le16 rx_prio_boost;	/* SW boost of WiFi rx priority */
1909e705c121SKalle Valo };
1910e705c121SKalle Valo 
1911e705c121SKalle Valo #define IWLAGN_BT_SCO_ACTIVE	cpu_to_le32(BIT(0))
1912e705c121SKalle Valo 
1913e705c121SKalle Valo struct iwlagn_bt_sco_cmd {
1914e705c121SKalle Valo 	__le32 flags;
1915e705c121SKalle Valo };
1916e705c121SKalle Valo 
1917e705c121SKalle Valo /******************************************************************************
1918e705c121SKalle Valo  * (6)
1919e705c121SKalle Valo  * Spectrum Management (802.11h) Commands, Responses, Notifications:
1920e705c121SKalle Valo  *
1921e705c121SKalle Valo  *****************************************************************************/
1922e705c121SKalle Valo 
1923e705c121SKalle Valo /*
1924e705c121SKalle Valo  * Spectrum Management
1925e705c121SKalle Valo  */
1926e705c121SKalle Valo #define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK         | \
1927e705c121SKalle Valo 				 RXON_FILTER_CTL2HOST_MSK        | \
1928e705c121SKalle Valo 				 RXON_FILTER_ACCEPT_GRP_MSK      | \
1929e705c121SKalle Valo 				 RXON_FILTER_DIS_DECRYPT_MSK     | \
1930e705c121SKalle Valo 				 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
1931e705c121SKalle Valo 				 RXON_FILTER_ASSOC_MSK           | \
1932e705c121SKalle Valo 				 RXON_FILTER_BCON_AWARE_MSK)
1933e705c121SKalle Valo 
1934e705c121SKalle Valo struct iwl_measure_channel {
1935e705c121SKalle Valo 	__le32 duration;	/* measurement duration in extended beacon
1936e705c121SKalle Valo 				 * format */
1937e705c121SKalle Valo 	u8 channel;		/* channel to measure */
1938e705c121SKalle Valo 	u8 type;		/* see enum iwl_measure_type */
1939e705c121SKalle Valo 	__le16 reserved;
1940e705c121SKalle Valo } __packed;
1941e705c121SKalle Valo 
1942e705c121SKalle Valo /*
1943e705c121SKalle Valo  * REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74 (command)
1944e705c121SKalle Valo  */
1945e705c121SKalle Valo struct iwl_spectrum_cmd {
1946e705c121SKalle Valo 	__le16 len;		/* number of bytes starting from token */
1947e705c121SKalle Valo 	u8 token;		/* token id */
1948e705c121SKalle Valo 	u8 id;			/* measurement id -- 0 or 1 */
1949e705c121SKalle Valo 	u8 origin;		/* 0 = TGh, 1 = other, 2 = TGk */
1950e705c121SKalle Valo 	u8 periodic;		/* 1 = periodic */
1951e705c121SKalle Valo 	__le16 path_loss_timeout;
1952e705c121SKalle Valo 	__le32 start_time;	/* start time in extended beacon format */
1953e705c121SKalle Valo 	__le32 reserved2;
1954e705c121SKalle Valo 	__le32 flags;		/* rxon flags */
1955e705c121SKalle Valo 	__le32 filter_flags;	/* rxon filter flags */
1956e705c121SKalle Valo 	__le16 channel_count;	/* minimum 1, maximum 10 */
1957e705c121SKalle Valo 	__le16 reserved3;
1958e705c121SKalle Valo 	struct iwl_measure_channel channels[10];
1959e705c121SKalle Valo } __packed;
1960e705c121SKalle Valo 
1961e705c121SKalle Valo /*
1962e705c121SKalle Valo  * REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74 (response)
1963e705c121SKalle Valo  */
1964e705c121SKalle Valo struct iwl_spectrum_resp {
1965e705c121SKalle Valo 	u8 token;
1966e705c121SKalle Valo 	u8 id;			/* id of the prior command replaced, or 0xff */
1967e705c121SKalle Valo 	__le16 status;		/* 0 - command will be handled
1968e705c121SKalle Valo 				 * 1 - cannot handle (conflicts with another
1969e705c121SKalle Valo 				 *     measurement) */
1970e705c121SKalle Valo } __packed;
1971e705c121SKalle Valo 
1972e705c121SKalle Valo enum iwl_measurement_state {
1973e705c121SKalle Valo 	IWL_MEASUREMENT_START = 0,
1974e705c121SKalle Valo 	IWL_MEASUREMENT_STOP = 1,
1975e705c121SKalle Valo };
1976e705c121SKalle Valo 
1977e705c121SKalle Valo enum iwl_measurement_status {
1978e705c121SKalle Valo 	IWL_MEASUREMENT_OK = 0,
1979e705c121SKalle Valo 	IWL_MEASUREMENT_CONCURRENT = 1,
1980e705c121SKalle Valo 	IWL_MEASUREMENT_CSA_CONFLICT = 2,
1981e705c121SKalle Valo 	IWL_MEASUREMENT_TGH_CONFLICT = 3,
1982e705c121SKalle Valo 	/* 4-5 reserved */
1983e705c121SKalle Valo 	IWL_MEASUREMENT_STOPPED = 6,
1984e705c121SKalle Valo 	IWL_MEASUREMENT_TIMEOUT = 7,
1985e705c121SKalle Valo 	IWL_MEASUREMENT_PERIODIC_FAILED = 8,
1986e705c121SKalle Valo };
1987e705c121SKalle Valo 
1988e705c121SKalle Valo #define NUM_ELEMENTS_IN_HISTOGRAM 8
1989e705c121SKalle Valo 
1990e705c121SKalle Valo struct iwl_measurement_histogram {
1991e705c121SKalle Valo 	__le32 ofdm[NUM_ELEMENTS_IN_HISTOGRAM];	/* in 0.8usec counts */
1992e705c121SKalle Valo 	__le32 cck[NUM_ELEMENTS_IN_HISTOGRAM];	/* in 1usec counts */
1993e705c121SKalle Valo } __packed;
1994e705c121SKalle Valo 
1995e705c121SKalle Valo /* clear channel availability counters */
1996e705c121SKalle Valo struct iwl_measurement_cca_counters {
1997e705c121SKalle Valo 	__le32 ofdm;
1998e705c121SKalle Valo 	__le32 cck;
1999e705c121SKalle Valo } __packed;
2000e705c121SKalle Valo 
2001e705c121SKalle Valo enum iwl_measure_type {
2002e705c121SKalle Valo 	IWL_MEASURE_BASIC = (1 << 0),
2003e705c121SKalle Valo 	IWL_MEASURE_CHANNEL_LOAD = (1 << 1),
2004e705c121SKalle Valo 	IWL_MEASURE_HISTOGRAM_RPI = (1 << 2),
2005e705c121SKalle Valo 	IWL_MEASURE_HISTOGRAM_NOISE = (1 << 3),
2006e705c121SKalle Valo 	IWL_MEASURE_FRAME = (1 << 4),
2007e705c121SKalle Valo 	/* bits 5:6 are reserved */
2008e705c121SKalle Valo 	IWL_MEASURE_IDLE = (1 << 7),
2009e705c121SKalle Valo };
2010e705c121SKalle Valo 
2011e705c121SKalle Valo /*
2012e705c121SKalle Valo  * SPECTRUM_MEASURE_NOTIFICATION = 0x75 (notification only, not a command)
2013e705c121SKalle Valo  */
2014e705c121SKalle Valo struct iwl_spectrum_notification {
2015e705c121SKalle Valo 	u8 id;			/* measurement id -- 0 or 1 */
2016e705c121SKalle Valo 	u8 token;
2017e705c121SKalle Valo 	u8 channel_index;	/* index in measurement channel list */
2018e705c121SKalle Valo 	u8 state;		/* 0 - start, 1 - stop */
2019e705c121SKalle Valo 	__le32 start_time;	/* lower 32-bits of TSF */
2020e705c121SKalle Valo 	u8 band;		/* 0 - 5.2GHz, 1 - 2.4GHz */
2021e705c121SKalle Valo 	u8 channel;
2022e705c121SKalle Valo 	u8 type;		/* see enum iwl_measurement_type */
2023e705c121SKalle Valo 	u8 reserved1;
2024e705c121SKalle Valo 	/* NOTE:  cca_ofdm, cca_cck, basic_type, and histogram are only only
2025e705c121SKalle Valo 	 * valid if applicable for measurement type requested. */
2026e705c121SKalle Valo 	__le32 cca_ofdm;	/* cca fraction time in 40Mhz clock periods */
2027e705c121SKalle Valo 	__le32 cca_cck;		/* cca fraction time in 44Mhz clock periods */
2028e705c121SKalle Valo 	__le32 cca_time;	/* channel load time in usecs */
2029e705c121SKalle Valo 	u8 basic_type;		/* 0 - bss, 1 - ofdm preamble, 2 -
2030e705c121SKalle Valo 				 * unidentified */
2031e705c121SKalle Valo 	u8 reserved2[3];
2032e705c121SKalle Valo 	struct iwl_measurement_histogram histogram;
2033e705c121SKalle Valo 	__le32 stop_time;	/* lower 32-bits of TSF */
2034e705c121SKalle Valo 	__le32 status;		/* see iwl_measurement_status */
2035e705c121SKalle Valo } __packed;
2036e705c121SKalle Valo 
2037e705c121SKalle Valo /******************************************************************************
2038e705c121SKalle Valo  * (7)
2039e705c121SKalle Valo  * Power Management Commands, Responses, Notifications:
2040e705c121SKalle Valo  *
2041e705c121SKalle Valo  *****************************************************************************/
2042e705c121SKalle Valo 
2043e705c121SKalle Valo /**
2044e705c121SKalle Valo  * struct iwl_powertable_cmd - Power Table Command
2045e705c121SKalle Valo  * @flags: See below:
2046e705c121SKalle Valo  *
2047e705c121SKalle Valo  * POWER_TABLE_CMD = 0x77 (command, has simple generic response)
2048e705c121SKalle Valo  *
2049e705c121SKalle Valo  * PM allow:
2050e705c121SKalle Valo  *   bit 0 - '0' Driver not allow power management
2051e705c121SKalle Valo  *           '1' Driver allow PM (use rest of parameters)
2052e705c121SKalle Valo  *
2053e705c121SKalle Valo  * uCode send sleep notifications:
2054e705c121SKalle Valo  *   bit 1 - '0' Don't send sleep notification
2055e705c121SKalle Valo  *           '1' send sleep notification (SEND_PM_NOTIFICATION)
2056e705c121SKalle Valo  *
2057e705c121SKalle Valo  * Sleep over DTIM
2058e705c121SKalle Valo  *   bit 2 - '0' PM have to walk up every DTIM
2059e705c121SKalle Valo  *           '1' PM could sleep over DTIM till listen Interval.
2060e705c121SKalle Valo  *
2061e705c121SKalle Valo  * PCI power managed
2062e705c121SKalle Valo  *   bit 3 - '0' (PCI_CFG_LINK_CTRL & 0x1)
2063e705c121SKalle Valo  *           '1' !(PCI_CFG_LINK_CTRL & 0x1)
2064e705c121SKalle Valo  *
2065e705c121SKalle Valo  * Fast PD
2066e705c121SKalle Valo  *   bit 4 - '1' Put radio to sleep when receiving frame for others
2067e705c121SKalle Valo  *
2068e705c121SKalle Valo  * Force sleep Modes
2069e705c121SKalle Valo  *   bit 31/30- '00' use both mac/xtal sleeps
2070e705c121SKalle Valo  *              '01' force Mac sleep
2071e705c121SKalle Valo  *              '10' force xtal sleep
2072e705c121SKalle Valo  *              '11' Illegal set
2073e705c121SKalle Valo  *
2074e705c121SKalle Valo  * NOTE: if sleep_interval[SLEEP_INTRVL_TABLE_SIZE-1] > DTIM period then
2075e705c121SKalle Valo  * ucode assume sleep over DTIM is allowed and we don't need to wake up
2076e705c121SKalle Valo  * for every DTIM.
2077e705c121SKalle Valo  */
2078e705c121SKalle Valo #define IWL_POWER_VEC_SIZE 5
2079e705c121SKalle Valo 
2080e705c121SKalle Valo #define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK	cpu_to_le16(BIT(0))
2081e705c121SKalle Valo #define IWL_POWER_POWER_SAVE_ENA_MSK		cpu_to_le16(BIT(0))
2082e705c121SKalle Valo #define IWL_POWER_POWER_MANAGEMENT_ENA_MSK	cpu_to_le16(BIT(1))
2083e705c121SKalle Valo #define IWL_POWER_SLEEP_OVER_DTIM_MSK		cpu_to_le16(BIT(2))
2084e705c121SKalle Valo #define IWL_POWER_PCI_PM_MSK			cpu_to_le16(BIT(3))
2085e705c121SKalle Valo #define IWL_POWER_FAST_PD			cpu_to_le16(BIT(4))
2086e705c121SKalle Valo #define IWL_POWER_BEACON_FILTERING		cpu_to_le16(BIT(5))
2087e705c121SKalle Valo #define IWL_POWER_SHADOW_REG_ENA		cpu_to_le16(BIT(6))
2088e705c121SKalle Valo #define IWL_POWER_CT_KILL_SET			cpu_to_le16(BIT(7))
2089e705c121SKalle Valo #define IWL_POWER_BT_SCO_ENA			cpu_to_le16(BIT(8))
2090e705c121SKalle Valo #define IWL_POWER_ADVANCE_PM_ENA_MSK		cpu_to_le16(BIT(9))
2091e705c121SKalle Valo 
2092e705c121SKalle Valo struct iwl_powertable_cmd {
2093e705c121SKalle Valo 	__le16 flags;
2094e705c121SKalle Valo 	u8 keep_alive_seconds;
2095e705c121SKalle Valo 	u8 debug_flags;
2096e705c121SKalle Valo 	__le32 rx_data_timeout;
2097e705c121SKalle Valo 	__le32 tx_data_timeout;
2098e705c121SKalle Valo 	__le32 sleep_interval[IWL_POWER_VEC_SIZE];
2099e705c121SKalle Valo 	__le32 keep_alive_beacons;
2100e705c121SKalle Valo } __packed;
2101e705c121SKalle Valo 
2102e705c121SKalle Valo /*
2103e705c121SKalle Valo  * PM_SLEEP_NOTIFICATION = 0x7A (notification only, not a command)
2104e705c121SKalle Valo  * all devices identical.
2105e705c121SKalle Valo  */
2106e705c121SKalle Valo struct iwl_sleep_notification {
2107e705c121SKalle Valo 	u8 pm_sleep_mode;
2108e705c121SKalle Valo 	u8 pm_wakeup_src;
2109e705c121SKalle Valo 	__le16 reserved;
2110e705c121SKalle Valo 	__le32 sleep_time;
2111e705c121SKalle Valo 	__le32 tsf_low;
2112e705c121SKalle Valo 	__le32 bcon_timer;
2113e705c121SKalle Valo } __packed;
2114e705c121SKalle Valo 
2115e705c121SKalle Valo /* Sleep states.  all devices identical. */
2116e705c121SKalle Valo enum {
2117e705c121SKalle Valo 	IWL_PM_NO_SLEEP = 0,
2118e705c121SKalle Valo 	IWL_PM_SLP_MAC = 1,
2119e705c121SKalle Valo 	IWL_PM_SLP_FULL_MAC_UNASSOCIATE = 2,
2120e705c121SKalle Valo 	IWL_PM_SLP_FULL_MAC_CARD_STATE = 3,
2121e705c121SKalle Valo 	IWL_PM_SLP_PHY = 4,
2122e705c121SKalle Valo 	IWL_PM_SLP_REPENT = 5,
2123e705c121SKalle Valo 	IWL_PM_WAKEUP_BY_TIMER = 6,
2124e705c121SKalle Valo 	IWL_PM_WAKEUP_BY_DRIVER = 7,
2125e705c121SKalle Valo 	IWL_PM_WAKEUP_BY_RFKILL = 8,
2126e705c121SKalle Valo 	/* 3 reserved */
2127e705c121SKalle Valo 	IWL_PM_NUM_OF_MODES = 12,
2128e705c121SKalle Valo };
2129e705c121SKalle Valo 
2130e705c121SKalle Valo /*
2131e705c121SKalle Valo  * REPLY_CARD_STATE_CMD = 0xa0 (command, has simple generic response)
2132e705c121SKalle Valo  */
2133e705c121SKalle Valo #define CARD_STATE_CMD_DISABLE 0x00	/* Put card to sleep */
2134e705c121SKalle Valo #define CARD_STATE_CMD_ENABLE  0x01	/* Wake up card */
2135e705c121SKalle Valo #define CARD_STATE_CMD_HALT    0x02	/* Power down permanently */
2136e705c121SKalle Valo struct iwl_card_state_cmd {
2137e705c121SKalle Valo 	__le32 status;		/* CARD_STATE_CMD_* request new power state */
2138e705c121SKalle Valo } __packed;
2139e705c121SKalle Valo 
2140e705c121SKalle Valo /*
2141e705c121SKalle Valo  * CARD_STATE_NOTIFICATION = 0xa1 (notification only, not a command)
2142e705c121SKalle Valo  */
2143e705c121SKalle Valo struct iwl_card_state_notif {
2144e705c121SKalle Valo 	__le32 flags;
2145e705c121SKalle Valo } __packed;
2146e705c121SKalle Valo 
2147e705c121SKalle Valo #define HW_CARD_DISABLED   0x01
2148e705c121SKalle Valo #define SW_CARD_DISABLED   0x02
2149e705c121SKalle Valo #define CT_CARD_DISABLED   0x04
2150e705c121SKalle Valo #define RXON_CARD_DISABLED 0x10
2151e705c121SKalle Valo 
2152e705c121SKalle Valo struct iwl_ct_kill_config {
2153e705c121SKalle Valo 	__le32   reserved;
2154e705c121SKalle Valo 	__le32   critical_temperature_M;
2155e705c121SKalle Valo 	__le32   critical_temperature_R;
2156e705c121SKalle Valo }  __packed;
2157e705c121SKalle Valo 
2158e705c121SKalle Valo /* 1000, and 6x00 */
2159e705c121SKalle Valo struct iwl_ct_kill_throttling_config {
2160e705c121SKalle Valo 	__le32   critical_temperature_exit;
2161e705c121SKalle Valo 	__le32   reserved;
2162e705c121SKalle Valo 	__le32   critical_temperature_enter;
2163e705c121SKalle Valo }  __packed;
2164e705c121SKalle Valo 
2165e705c121SKalle Valo /******************************************************************************
2166e705c121SKalle Valo  * (8)
2167e705c121SKalle Valo  * Scan Commands, Responses, Notifications:
2168e705c121SKalle Valo  *
2169e705c121SKalle Valo  *****************************************************************************/
2170e705c121SKalle Valo 
2171e705c121SKalle Valo #define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2172e705c121SKalle Valo #define SCAN_CHANNEL_TYPE_ACTIVE  cpu_to_le32(1)
2173e705c121SKalle Valo 
2174e705c121SKalle Valo /**
2175e705c121SKalle Valo  * struct iwl_scan_channel - entry in REPLY_SCAN_CMD channel table
2176e705c121SKalle Valo  *
2177e705c121SKalle Valo  * One for each channel in the scan list.
2178e705c121SKalle Valo  * Each channel can independently select:
2179e705c121SKalle Valo  * 1)  SSID for directed active scans
2180e705c121SKalle Valo  * 2)  Txpower setting (for rate specified within Tx command)
2181e705c121SKalle Valo  * 3)  How long to stay on-channel (behavior may be modified by quiet_time,
2182e705c121SKalle Valo  *     quiet_plcp_th, good_CRC_th)
2183e705c121SKalle Valo  *
2184e705c121SKalle Valo  * To avoid uCode errors, make sure the following are true (see comments
2185e705c121SKalle Valo  * under struct iwl_scan_cmd about max_out_time and quiet_time):
2186e705c121SKalle Valo  * 1)  If using passive_dwell (i.e. passive_dwell != 0):
2187e705c121SKalle Valo  *     active_dwell <= passive_dwell (< max_out_time if max_out_time != 0)
2188e705c121SKalle Valo  * 2)  quiet_time <= active_dwell
2189e705c121SKalle Valo  * 3)  If restricting off-channel time (i.e. max_out_time !=0):
2190e705c121SKalle Valo  *     passive_dwell < max_out_time
2191e705c121SKalle Valo  *     active_dwell < max_out_time
2192e705c121SKalle Valo  */
2193e705c121SKalle Valo 
2194e705c121SKalle Valo struct iwl_scan_channel {
2195e705c121SKalle Valo 	/*
2196e705c121SKalle Valo 	 * type is defined as:
2197e705c121SKalle Valo 	 * 0:0 1 = active, 0 = passive
2198e705c121SKalle Valo 	 * 1:20 SSID direct bit map; if a bit is set, then corresponding
2199e705c121SKalle Valo 	 *     SSID IE is transmitted in probe request.
2200e705c121SKalle Valo 	 * 21:31 reserved
2201e705c121SKalle Valo 	 */
2202e705c121SKalle Valo 	__le32 type;
2203e705c121SKalle Valo 	__le16 channel;	/* band is selected by iwl_scan_cmd "flags" field */
2204e705c121SKalle Valo 	u8 tx_gain;		/* gain for analog radio */
2205e705c121SKalle Valo 	u8 dsp_atten;		/* gain for DSP */
2206e705c121SKalle Valo 	__le16 active_dwell;	/* in 1024-uSec TU (time units), typ 5-50 */
2207e705c121SKalle Valo 	__le16 passive_dwell;	/* in 1024-uSec TU (time units), typ 20-500 */
2208e705c121SKalle Valo } __packed;
2209e705c121SKalle Valo 
2210e705c121SKalle Valo /* set number of direct probes __le32 type */
2211e705c121SKalle Valo #define IWL_SCAN_PROBE_MASK(n) 	cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2212e705c121SKalle Valo 
2213e705c121SKalle Valo /**
2214e705c121SKalle Valo  * struct iwl_ssid_ie - directed scan network information element
2215e705c121SKalle Valo  *
2216e705c121SKalle Valo  * Up to 20 of these may appear in REPLY_SCAN_CMD,
2217e705c121SKalle Valo  * selected by "type" bit field in struct iwl_scan_channel;
2218e705c121SKalle Valo  * each channel may select different ssids from among the 20 entries.
2219e705c121SKalle Valo  * SSID IEs get transmitted in reverse order of entry.
2220e705c121SKalle Valo  */
2221e705c121SKalle Valo struct iwl_ssid_ie {
2222e705c121SKalle Valo 	u8 id;
2223e705c121SKalle Valo 	u8 len;
2224e705c121SKalle Valo 	u8 ssid[32];
2225e705c121SKalle Valo } __packed;
2226e705c121SKalle Valo 
2227e705c121SKalle Valo #define PROBE_OPTION_MAX		20
2228e705c121SKalle Valo #define TX_CMD_LIFE_TIME_INFINITE	cpu_to_le32(0xFFFFFFFF)
2229e705c121SKalle Valo #define IWL_GOOD_CRC_TH_DISABLED	0
2230e705c121SKalle Valo #define IWL_GOOD_CRC_TH_DEFAULT		cpu_to_le16(1)
2231e705c121SKalle Valo #define IWL_GOOD_CRC_TH_NEVER		cpu_to_le16(0xffff)
2232e705c121SKalle Valo #define IWL_MAX_CMD_SIZE 4096
2233e705c121SKalle Valo 
2234e705c121SKalle Valo /*
2235e705c121SKalle Valo  * REPLY_SCAN_CMD = 0x80 (command)
2236e705c121SKalle Valo  *
2237e705c121SKalle Valo  * The hardware scan command is very powerful; the driver can set it up to
2238e705c121SKalle Valo  * maintain (relatively) normal network traffic while doing a scan in the
2239e705c121SKalle Valo  * background.  The max_out_time and suspend_time control the ratio of how
2240e705c121SKalle Valo  * long the device stays on an associated network channel ("service channel")
2241e705c121SKalle Valo  * vs. how long it's away from the service channel, i.e. tuned to other channels
2242e705c121SKalle Valo  * for scanning.
2243e705c121SKalle Valo  *
2244e705c121SKalle Valo  * max_out_time is the max time off-channel (in usec), and suspend_time
2245e705c121SKalle Valo  * is how long (in "extended beacon" format) that the scan is "suspended"
2246e705c121SKalle Valo  * after returning to the service channel.  That is, suspend_time is the
2247e705c121SKalle Valo  * time that we stay on the service channel, doing normal work, between
2248e705c121SKalle Valo  * scan segments.  The driver may set these parameters differently to support
2249e705c121SKalle Valo  * scanning when associated vs. not associated, and light vs. heavy traffic
2250e705c121SKalle Valo  * loads when associated.
2251e705c121SKalle Valo  *
2252e705c121SKalle Valo  * After receiving this command, the device's scan engine does the following;
2253e705c121SKalle Valo  *
2254e705c121SKalle Valo  * 1)  Sends SCAN_START notification to driver
2255e705c121SKalle Valo  * 2)  Checks to see if it has time to do scan for one channel
2256e705c121SKalle Valo  * 3)  Sends NULL packet, with power-save (PS) bit set to 1,
2257e705c121SKalle Valo  *     to tell AP that we're going off-channel
2258e705c121SKalle Valo  * 4)  Tunes to first channel in scan list, does active or passive scan
2259e705c121SKalle Valo  * 5)  Sends SCAN_RESULT notification to driver
2260e705c121SKalle Valo  * 6)  Checks to see if it has time to do scan on *next* channel in list
2261e705c121SKalle Valo  * 7)  Repeats 4-6 until it no longer has time to scan the next channel
2262e705c121SKalle Valo  *     before max_out_time expires
2263e705c121SKalle Valo  * 8)  Returns to service channel
2264e705c121SKalle Valo  * 9)  Sends NULL packet with PS=0 to tell AP that we're back
2265e705c121SKalle Valo  * 10) Stays on service channel until suspend_time expires
2266e705c121SKalle Valo  * 11) Repeats entire process 2-10 until list is complete
2267e705c121SKalle Valo  * 12) Sends SCAN_COMPLETE notification
2268e705c121SKalle Valo  *
2269e705c121SKalle Valo  * For fast, efficient scans, the scan command also has support for staying on
2270e705c121SKalle Valo  * a channel for just a short time, if doing active scanning and getting no
2271e705c121SKalle Valo  * responses to the transmitted probe request.  This time is controlled by
2272e705c121SKalle Valo  * quiet_time, and the number of received packets below which a channel is
2273e705c121SKalle Valo  * considered "quiet" is controlled by quiet_plcp_threshold.
2274e705c121SKalle Valo  *
2275e705c121SKalle Valo  * For active scanning on channels that have regulatory restrictions against
2276e705c121SKalle Valo  * blindly transmitting, the scan can listen before transmitting, to make sure
2277e705c121SKalle Valo  * that there is already legitimate activity on the channel.  If enough
2278e705c121SKalle Valo  * packets are cleanly received on the channel (controlled by good_CRC_th,
2279e705c121SKalle Valo  * typical value 1), the scan engine starts transmitting probe requests.
2280e705c121SKalle Valo  *
2281e705c121SKalle Valo  * Driver must use separate scan commands for 2.4 vs. 5 GHz bands.
2282e705c121SKalle Valo  *
2283e705c121SKalle Valo  * To avoid uCode errors, see timing restrictions described under
2284e705c121SKalle Valo  * struct iwl_scan_channel.
2285e705c121SKalle Valo  */
2286e705c121SKalle Valo 
2287e705c121SKalle Valo enum iwl_scan_flags {
2288e705c121SKalle Valo 	/* BIT(0) currently unused */
2289e705c121SKalle Valo 	IWL_SCAN_FLAGS_ACTION_FRAME_TX	= BIT(1),
2290e705c121SKalle Valo 	/* bits 2-7 reserved */
2291e705c121SKalle Valo };
2292e705c121SKalle Valo 
2293e705c121SKalle Valo struct iwl_scan_cmd {
2294e705c121SKalle Valo 	__le16 len;
2295e705c121SKalle Valo 	u8 scan_flags;		/* scan flags: see enum iwl_scan_flags */
2296e705c121SKalle Valo 	u8 channel_count;	/* # channels in channel list */
2297e705c121SKalle Valo 	__le16 quiet_time;	/* dwell only this # millisecs on quiet channel
2298e705c121SKalle Valo 				 * (only for active scan) */
2299e705c121SKalle Valo 	__le16 quiet_plcp_th;	/* quiet chnl is < this # pkts (typ. 1) */
2300e705c121SKalle Valo 	__le16 good_CRC_th;	/* passive -> active promotion threshold */
2301e705c121SKalle Valo 	__le16 rx_chain;	/* RXON_RX_CHAIN_* */
2302e705c121SKalle Valo 	__le32 max_out_time;	/* max usec to be away from associated (service)
2303e705c121SKalle Valo 				 * channel */
2304e705c121SKalle Valo 	__le32 suspend_time;	/* pause scan this long (in "extended beacon
2305e705c121SKalle Valo 				 * format") when returning to service chnl:
2306e705c121SKalle Valo 				 */
2307e705c121SKalle Valo 	__le32 flags;		/* RXON_FLG_* */
2308e705c121SKalle Valo 	__le32 filter_flags;	/* RXON_FILTER_* */
2309e705c121SKalle Valo 
2310e705c121SKalle Valo 	/* For active scans (set to all-0s for passive scans).
2311e705c121SKalle Valo 	 * Does not include payload.  Must specify Tx rate; no rate scaling. */
2312e705c121SKalle Valo 	struct iwl_tx_cmd tx_cmd;
2313e705c121SKalle Valo 
2314e705c121SKalle Valo 	/* For directed active scans (set to all-0s otherwise) */
2315e705c121SKalle Valo 	struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX];
2316e705c121SKalle Valo 
2317e705c121SKalle Valo 	/*
2318e705c121SKalle Valo 	 * Probe request frame, followed by channel list.
2319e705c121SKalle Valo 	 *
2320e705c121SKalle Valo 	 * Size of probe request frame is specified by byte count in tx_cmd.
2321e705c121SKalle Valo 	 * Channel list follows immediately after probe request frame.
2322e705c121SKalle Valo 	 * Number of channels in list is specified by channel_count.
2323e705c121SKalle Valo 	 * Each channel in list is of type:
2324e705c121SKalle Valo 	 *
2325e705c121SKalle Valo 	 * struct iwl_scan_channel channels[0];
2326e705c121SKalle Valo 	 *
2327e705c121SKalle Valo 	 * NOTE:  Only one band of channels can be scanned per pass.  You
2328e705c121SKalle Valo 	 * must not mix 2.4GHz channels and 5.2GHz channels, and you must wait
2329e705c121SKalle Valo 	 * for one scan to complete (i.e. receive SCAN_COMPLETE_NOTIFICATION)
2330e705c121SKalle Valo 	 * before requesting another scan.
2331e705c121SKalle Valo 	 */
233245c21a0eSGustavo A. R. Silva 	u8 data[];
2333e705c121SKalle Valo } __packed;
2334e705c121SKalle Valo 
2335e705c121SKalle Valo /* Can abort will notify by complete notification with abort status. */
2336e705c121SKalle Valo #define CAN_ABORT_STATUS	cpu_to_le32(0x1)
2337e705c121SKalle Valo /* complete notification statuses */
2338e705c121SKalle Valo #define ABORT_STATUS            0x2
2339e705c121SKalle Valo 
2340e705c121SKalle Valo /*
2341e705c121SKalle Valo  * REPLY_SCAN_CMD = 0x80 (response)
2342e705c121SKalle Valo  */
2343e705c121SKalle Valo struct iwl_scanreq_notification {
2344e705c121SKalle Valo 	__le32 status;		/* 1: okay, 2: cannot fulfill request */
2345e705c121SKalle Valo } __packed;
2346e705c121SKalle Valo 
2347e705c121SKalle Valo /*
2348e705c121SKalle Valo  * SCAN_START_NOTIFICATION = 0x82 (notification only, not a command)
2349e705c121SKalle Valo  */
2350e705c121SKalle Valo struct iwl_scanstart_notification {
2351e705c121SKalle Valo 	__le32 tsf_low;
2352e705c121SKalle Valo 	__le32 tsf_high;
2353e705c121SKalle Valo 	__le32 beacon_timer;
2354e705c121SKalle Valo 	u8 channel;
2355e705c121SKalle Valo 	u8 band;
2356e705c121SKalle Valo 	u8 reserved[2];
2357e705c121SKalle Valo 	__le32 status;
2358e705c121SKalle Valo } __packed;
2359e705c121SKalle Valo 
2360e705c121SKalle Valo #define  SCAN_OWNER_STATUS 0x1
2361e705c121SKalle Valo #define  MEASURE_OWNER_STATUS 0x2
2362e705c121SKalle Valo 
2363e705c121SKalle Valo #define IWL_PROBE_STATUS_OK		0
2364e705c121SKalle Valo #define IWL_PROBE_STATUS_TX_FAILED	BIT(0)
2365e705c121SKalle Valo /* error statuses combined with TX_FAILED */
2366e705c121SKalle Valo #define IWL_PROBE_STATUS_FAIL_TTL	BIT(1)
2367e705c121SKalle Valo #define IWL_PROBE_STATUS_FAIL_BT	BIT(2)
2368e705c121SKalle Valo 
2369e705c121SKalle Valo #define NUMBER_OF_STATISTICS 1	/* first __le32 is good CRC */
2370e705c121SKalle Valo /*
2371e705c121SKalle Valo  * SCAN_RESULTS_NOTIFICATION = 0x83 (notification only, not a command)
2372e705c121SKalle Valo  */
2373e705c121SKalle Valo struct iwl_scanresults_notification {
2374e705c121SKalle Valo 	u8 channel;
2375e705c121SKalle Valo 	u8 band;
2376e705c121SKalle Valo 	u8 probe_status;
2377e705c121SKalle Valo 	u8 num_probe_not_sent; /* not enough time to send */
2378e705c121SKalle Valo 	__le32 tsf_low;
2379e705c121SKalle Valo 	__le32 tsf_high;
2380e705c121SKalle Valo 	__le32 statistics[NUMBER_OF_STATISTICS];
2381e705c121SKalle Valo } __packed;
2382e705c121SKalle Valo 
2383e705c121SKalle Valo /*
2384e705c121SKalle Valo  * SCAN_COMPLETE_NOTIFICATION = 0x84 (notification only, not a command)
2385e705c121SKalle Valo  */
2386e705c121SKalle Valo struct iwl_scancomplete_notification {
2387e705c121SKalle Valo 	u8 scanned_channels;
2388e705c121SKalle Valo 	u8 status;
2389e705c121SKalle Valo 	u8 bt_status;	/* BT On/Off status */
2390e705c121SKalle Valo 	u8 last_channel;
2391e705c121SKalle Valo 	__le32 tsf_low;
2392e705c121SKalle Valo 	__le32 tsf_high;
2393e705c121SKalle Valo } __packed;
2394e705c121SKalle Valo 
2395e705c121SKalle Valo 
2396e705c121SKalle Valo /******************************************************************************
2397e705c121SKalle Valo  * (9)
2398e705c121SKalle Valo  * IBSS/AP Commands and Notifications:
2399e705c121SKalle Valo  *
2400e705c121SKalle Valo  *****************************************************************************/
2401e705c121SKalle Valo 
2402e705c121SKalle Valo enum iwl_ibss_manager {
2403e705c121SKalle Valo 	IWL_NOT_IBSS_MANAGER = 0,
2404e705c121SKalle Valo 	IWL_IBSS_MANAGER = 1,
2405e705c121SKalle Valo };
2406e705c121SKalle Valo 
2407e705c121SKalle Valo /*
2408e705c121SKalle Valo  * BEACON_NOTIFICATION = 0x90 (notification only, not a command)
2409e705c121SKalle Valo  */
2410e705c121SKalle Valo 
2411e705c121SKalle Valo struct iwlagn_beacon_notif {
2412e705c121SKalle Valo 	struct iwlagn_tx_resp beacon_notify_hdr;
2413e705c121SKalle Valo 	__le32 low_tsf;
2414e705c121SKalle Valo 	__le32 high_tsf;
2415e705c121SKalle Valo 	__le32 ibss_mgr_status;
2416e705c121SKalle Valo } __packed;
2417e705c121SKalle Valo 
2418e705c121SKalle Valo /*
2419e705c121SKalle Valo  * REPLY_TX_BEACON = 0x91 (command, has simple generic response)
2420e705c121SKalle Valo  */
2421e705c121SKalle Valo 
2422e705c121SKalle Valo struct iwl_tx_beacon_cmd {
2423e705c121SKalle Valo 	struct iwl_tx_cmd tx;
2424e705c121SKalle Valo 	__le16 tim_idx;
2425e705c121SKalle Valo 	u8 tim_size;
2426e705c121SKalle Valo 	u8 reserved1;
242745c21a0eSGustavo A. R. Silva 	struct ieee80211_hdr frame[];	/* beacon frame */
2428e705c121SKalle Valo } __packed;
2429e705c121SKalle Valo 
2430e705c121SKalle Valo /******************************************************************************
2431e705c121SKalle Valo  * (10)
2432e705c121SKalle Valo  * Statistics Commands and Notifications:
2433e705c121SKalle Valo  *
2434e705c121SKalle Valo  *****************************************************************************/
2435e705c121SKalle Valo 
2436e705c121SKalle Valo #define IWL_TEMP_CONVERT 260
2437e705c121SKalle Valo 
2438e705c121SKalle Valo #define SUP_RATE_11A_MAX_NUM_CHANNELS  8
2439e705c121SKalle Valo #define SUP_RATE_11B_MAX_NUM_CHANNELS  4
2440e705c121SKalle Valo #define SUP_RATE_11G_MAX_NUM_CHANNELS  12
2441e705c121SKalle Valo 
2442e705c121SKalle Valo /* Used for passing to driver number of successes and failures per rate */
2443e705c121SKalle Valo struct rate_histogram {
2444e705c121SKalle Valo 	union {
2445e705c121SKalle Valo 		__le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2446e705c121SKalle Valo 		__le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2447e705c121SKalle Valo 		__le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2448e705c121SKalle Valo 	} success;
2449e705c121SKalle Valo 	union {
2450e705c121SKalle Valo 		__le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2451e705c121SKalle Valo 		__le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2452e705c121SKalle Valo 		__le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2453e705c121SKalle Valo 	} failed;
2454e705c121SKalle Valo } __packed;
2455e705c121SKalle Valo 
2456e705c121SKalle Valo /* statistics command response */
2457e705c121SKalle Valo 
2458e705c121SKalle Valo struct statistics_dbg {
2459e705c121SKalle Valo 	__le32 burst_check;
2460e705c121SKalle Valo 	__le32 burst_count;
2461e705c121SKalle Valo 	__le32 wait_for_silence_timeout_cnt;
2462e705c121SKalle Valo 	__le32 reserved[3];
2463e705c121SKalle Valo } __packed;
2464e705c121SKalle Valo 
2465e705c121SKalle Valo struct statistics_rx_phy {
2466e705c121SKalle Valo 	__le32 ina_cnt;
2467e705c121SKalle Valo 	__le32 fina_cnt;
2468e705c121SKalle Valo 	__le32 plcp_err;
2469e705c121SKalle Valo 	__le32 crc32_err;
2470e705c121SKalle Valo 	__le32 overrun_err;
2471e705c121SKalle Valo 	__le32 early_overrun_err;
2472e705c121SKalle Valo 	__le32 crc32_good;
2473e705c121SKalle Valo 	__le32 false_alarm_cnt;
2474e705c121SKalle Valo 	__le32 fina_sync_err_cnt;
2475e705c121SKalle Valo 	__le32 sfd_timeout;
2476e705c121SKalle Valo 	__le32 fina_timeout;
2477e705c121SKalle Valo 	__le32 unresponded_rts;
2478e705c121SKalle Valo 	__le32 rxe_frame_limit_overrun;
2479e705c121SKalle Valo 	__le32 sent_ack_cnt;
2480e705c121SKalle Valo 	__le32 sent_cts_cnt;
2481e705c121SKalle Valo 	__le32 sent_ba_rsp_cnt;
2482e705c121SKalle Valo 	__le32 dsp_self_kill;
2483e705c121SKalle Valo 	__le32 mh_format_err;
2484e705c121SKalle Valo 	__le32 re_acq_main_rssi_sum;
2485e705c121SKalle Valo 	__le32 reserved3;
2486e705c121SKalle Valo } __packed;
2487e705c121SKalle Valo 
2488e705c121SKalle Valo struct statistics_rx_ht_phy {
2489e705c121SKalle Valo 	__le32 plcp_err;
2490e705c121SKalle Valo 	__le32 overrun_err;
2491e705c121SKalle Valo 	__le32 early_overrun_err;
2492e705c121SKalle Valo 	__le32 crc32_good;
2493e705c121SKalle Valo 	__le32 crc32_err;
2494e705c121SKalle Valo 	__le32 mh_format_err;
2495e705c121SKalle Valo 	__le32 agg_crc32_good;
2496e705c121SKalle Valo 	__le32 agg_mpdu_cnt;
2497e705c121SKalle Valo 	__le32 agg_cnt;
2498e705c121SKalle Valo 	__le32 unsupport_mcs;
2499e705c121SKalle Valo } __packed;
2500e705c121SKalle Valo 
2501e705c121SKalle Valo #define INTERFERENCE_DATA_AVAILABLE      cpu_to_le32(1)
2502e705c121SKalle Valo 
2503e705c121SKalle Valo struct statistics_rx_non_phy {
2504e705c121SKalle Valo 	__le32 bogus_cts;	/* CTS received when not expecting CTS */
2505e705c121SKalle Valo 	__le32 bogus_ack;	/* ACK received when not expecting ACK */
2506e705c121SKalle Valo 	__le32 non_bssid_frames;	/* number of frames with BSSID that
2507e705c121SKalle Valo 					 * doesn't belong to the STA BSSID */
2508e705c121SKalle Valo 	__le32 filtered_frames;	/* count frames that were dumped in the
2509e705c121SKalle Valo 				 * filtering process */
2510e705c121SKalle Valo 	__le32 non_channel_beacons;	/* beacons with our bss id but not on
2511e705c121SKalle Valo 					 * our serving channel */
2512e705c121SKalle Valo 	__le32 channel_beacons;	/* beacons with our bss id and in our
2513e705c121SKalle Valo 				 * serving channel */
2514e705c121SKalle Valo 	__le32 num_missed_bcon;	/* number of missed beacons */
2515e705c121SKalle Valo 	__le32 adc_rx_saturation_time;	/* count in 0.8us units the time the
2516e705c121SKalle Valo 					 * ADC was in saturation */
2517e705c121SKalle Valo 	__le32 ina_detection_search_time;/* total time (in 0.8us) searched
2518e705c121SKalle Valo 					  * for INA */
2519e705c121SKalle Valo 	__le32 beacon_silence_rssi_a;	/* RSSI silence after beacon frame */
2520e705c121SKalle Valo 	__le32 beacon_silence_rssi_b;	/* RSSI silence after beacon frame */
2521e705c121SKalle Valo 	__le32 beacon_silence_rssi_c;	/* RSSI silence after beacon frame */
2522e705c121SKalle Valo 	__le32 interference_data_flag;	/* flag for interference data
2523e705c121SKalle Valo 					 * availability. 1 when data is
2524e705c121SKalle Valo 					 * available. */
2525e705c121SKalle Valo 	__le32 channel_load;		/* counts RX Enable time in uSec */
2526e705c121SKalle Valo 	__le32 dsp_false_alarms;	/* DSP false alarm (both OFDM
2527e705c121SKalle Valo 					 * and CCK) counter */
2528e705c121SKalle Valo 	__le32 beacon_rssi_a;
2529e705c121SKalle Valo 	__le32 beacon_rssi_b;
2530e705c121SKalle Valo 	__le32 beacon_rssi_c;
2531e705c121SKalle Valo 	__le32 beacon_energy_a;
2532e705c121SKalle Valo 	__le32 beacon_energy_b;
2533e705c121SKalle Valo 	__le32 beacon_energy_c;
2534e705c121SKalle Valo } __packed;
2535e705c121SKalle Valo 
2536e705c121SKalle Valo struct statistics_rx_non_phy_bt {
2537e705c121SKalle Valo 	struct statistics_rx_non_phy common;
2538e705c121SKalle Valo 	/* additional stats for bt */
2539e705c121SKalle Valo 	__le32 num_bt_kills;
2540e705c121SKalle Valo 	__le32 reserved[2];
2541e705c121SKalle Valo } __packed;
2542e705c121SKalle Valo 
2543e705c121SKalle Valo struct statistics_rx {
2544e705c121SKalle Valo 	struct statistics_rx_phy ofdm;
2545e705c121SKalle Valo 	struct statistics_rx_phy cck;
2546e705c121SKalle Valo 	struct statistics_rx_non_phy general;
2547e705c121SKalle Valo 	struct statistics_rx_ht_phy ofdm_ht;
2548e705c121SKalle Valo } __packed;
2549e705c121SKalle Valo 
2550e705c121SKalle Valo struct statistics_rx_bt {
2551e705c121SKalle Valo 	struct statistics_rx_phy ofdm;
2552e705c121SKalle Valo 	struct statistics_rx_phy cck;
2553e705c121SKalle Valo 	struct statistics_rx_non_phy_bt general;
2554e705c121SKalle Valo 	struct statistics_rx_ht_phy ofdm_ht;
2555e705c121SKalle Valo } __packed;
2556e705c121SKalle Valo 
2557e705c121SKalle Valo /**
2558e705c121SKalle Valo  * struct statistics_tx_power - current tx power
2559e705c121SKalle Valo  *
2560e705c121SKalle Valo  * @ant_a: current tx power on chain a in 1/2 dB step
2561e705c121SKalle Valo  * @ant_b: current tx power on chain b in 1/2 dB step
2562e705c121SKalle Valo  * @ant_c: current tx power on chain c in 1/2 dB step
2563e705c121SKalle Valo  */
2564e705c121SKalle Valo struct statistics_tx_power {
2565e705c121SKalle Valo 	u8 ant_a;
2566e705c121SKalle Valo 	u8 ant_b;
2567e705c121SKalle Valo 	u8 ant_c;
2568e705c121SKalle Valo 	u8 reserved;
2569e705c121SKalle Valo } __packed;
2570e705c121SKalle Valo 
2571e705c121SKalle Valo struct statistics_tx_non_phy_agg {
2572e705c121SKalle Valo 	__le32 ba_timeout;
2573e705c121SKalle Valo 	__le32 ba_reschedule_frames;
2574e705c121SKalle Valo 	__le32 scd_query_agg_frame_cnt;
2575e705c121SKalle Valo 	__le32 scd_query_no_agg;
2576e705c121SKalle Valo 	__le32 scd_query_agg;
2577e705c121SKalle Valo 	__le32 scd_query_mismatch;
2578e705c121SKalle Valo 	__le32 frame_not_ready;
2579e705c121SKalle Valo 	__le32 underrun;
2580e705c121SKalle Valo 	__le32 bt_prio_kill;
2581e705c121SKalle Valo 	__le32 rx_ba_rsp_cnt;
2582e705c121SKalle Valo } __packed;
2583e705c121SKalle Valo 
2584e705c121SKalle Valo struct statistics_tx {
2585e705c121SKalle Valo 	__le32 preamble_cnt;
2586e705c121SKalle Valo 	__le32 rx_detected_cnt;
2587e705c121SKalle Valo 	__le32 bt_prio_defer_cnt;
2588e705c121SKalle Valo 	__le32 bt_prio_kill_cnt;
2589e705c121SKalle Valo 	__le32 few_bytes_cnt;
2590e705c121SKalle Valo 	__le32 cts_timeout;
2591e705c121SKalle Valo 	__le32 ack_timeout;
2592e705c121SKalle Valo 	__le32 expected_ack_cnt;
2593e705c121SKalle Valo 	__le32 actual_ack_cnt;
2594e705c121SKalle Valo 	__le32 dump_msdu_cnt;
2595e705c121SKalle Valo 	__le32 burst_abort_next_frame_mismatch_cnt;
2596e705c121SKalle Valo 	__le32 burst_abort_missing_next_frame_cnt;
2597e705c121SKalle Valo 	__le32 cts_timeout_collision;
2598e705c121SKalle Valo 	__le32 ack_or_ba_timeout_collision;
2599e705c121SKalle Valo 	struct statistics_tx_non_phy_agg agg;
2600e705c121SKalle Valo 	/*
2601e705c121SKalle Valo 	 * "tx_power" are optional parameters provided by uCode,
2602e705c121SKalle Valo 	 * 6000 series is the only device provide the information,
2603e705c121SKalle Valo 	 * Those are reserved fields for all the other devices
2604e705c121SKalle Valo 	 */
2605e705c121SKalle Valo 	struct statistics_tx_power tx_power;
2606e705c121SKalle Valo 	__le32 reserved1;
2607e705c121SKalle Valo } __packed;
2608e705c121SKalle Valo 
2609e705c121SKalle Valo 
2610e705c121SKalle Valo struct statistics_div {
2611e705c121SKalle Valo 	__le32 tx_on_a;
2612e705c121SKalle Valo 	__le32 tx_on_b;
2613e705c121SKalle Valo 	__le32 exec_time;
2614e705c121SKalle Valo 	__le32 probe_time;
2615e705c121SKalle Valo 	__le32 reserved1;
2616e705c121SKalle Valo 	__le32 reserved2;
2617e705c121SKalle Valo } __packed;
2618e705c121SKalle Valo 
2619e705c121SKalle Valo struct statistics_general_common {
2620e705c121SKalle Valo 	__le32 temperature;   /* radio temperature */
2621e705c121SKalle Valo 	__le32 temperature_m; /* radio voltage */
2622e705c121SKalle Valo 	struct statistics_dbg dbg;
2623e705c121SKalle Valo 	__le32 sleep_time;
2624e705c121SKalle Valo 	__le32 slots_out;
2625e705c121SKalle Valo 	__le32 slots_idle;
2626e705c121SKalle Valo 	__le32 ttl_timestamp;
2627e705c121SKalle Valo 	struct statistics_div div;
2628e705c121SKalle Valo 	__le32 rx_enable_counter;
2629e705c121SKalle Valo 	/*
2630e705c121SKalle Valo 	 * num_of_sos_states:
2631e705c121SKalle Valo 	 *  count the number of times we have to re-tune
2632e705c121SKalle Valo 	 *  in order to get out of bad PHY status
2633e705c121SKalle Valo 	 */
2634e705c121SKalle Valo 	__le32 num_of_sos_states;
2635e705c121SKalle Valo } __packed;
2636e705c121SKalle Valo 
2637e705c121SKalle Valo struct statistics_bt_activity {
2638e705c121SKalle Valo 	/* Tx statistics */
2639e705c121SKalle Valo 	__le32 hi_priority_tx_req_cnt;
2640e705c121SKalle Valo 	__le32 hi_priority_tx_denied_cnt;
2641e705c121SKalle Valo 	__le32 lo_priority_tx_req_cnt;
2642e705c121SKalle Valo 	__le32 lo_priority_tx_denied_cnt;
2643e705c121SKalle Valo 	/* Rx statistics */
2644e705c121SKalle Valo 	__le32 hi_priority_rx_req_cnt;
2645e705c121SKalle Valo 	__le32 hi_priority_rx_denied_cnt;
2646e705c121SKalle Valo 	__le32 lo_priority_rx_req_cnt;
2647e705c121SKalle Valo 	__le32 lo_priority_rx_denied_cnt;
2648e705c121SKalle Valo } __packed;
2649e705c121SKalle Valo 
2650e705c121SKalle Valo struct statistics_general {
2651e705c121SKalle Valo 	struct statistics_general_common common;
2652e705c121SKalle Valo 	__le32 reserved2;
2653e705c121SKalle Valo 	__le32 reserved3;
2654e705c121SKalle Valo } __packed;
2655e705c121SKalle Valo 
2656e705c121SKalle Valo struct statistics_general_bt {
2657e705c121SKalle Valo 	struct statistics_general_common common;
2658e705c121SKalle Valo 	struct statistics_bt_activity activity;
2659e705c121SKalle Valo 	__le32 reserved2;
2660e705c121SKalle Valo 	__le32 reserved3;
2661e705c121SKalle Valo } __packed;
2662e705c121SKalle Valo 
2663e705c121SKalle Valo #define UCODE_STATISTICS_CLEAR_MSK		(0x1 << 0)
2664e705c121SKalle Valo #define UCODE_STATISTICS_FREQUENCY_MSK		(0x1 << 1)
2665e705c121SKalle Valo #define UCODE_STATISTICS_NARROW_BAND_MSK	(0x1 << 2)
2666e705c121SKalle Valo 
2667e705c121SKalle Valo /*
2668e705c121SKalle Valo  * REPLY_STATISTICS_CMD = 0x9c,
2669e705c121SKalle Valo  * all devices identical.
2670e705c121SKalle Valo  *
2671e705c121SKalle Valo  * This command triggers an immediate response containing uCode statistics.
2672e705c121SKalle Valo  * The response is in the same format as STATISTICS_NOTIFICATION 0x9d, below.
2673e705c121SKalle Valo  *
2674e705c121SKalle Valo  * If the CLEAR_STATS configuration flag is set, uCode will clear its
2675e705c121SKalle Valo  * internal copy of the statistics (counters) after issuing the response.
2676e705c121SKalle Valo  * This flag does not affect STATISTICS_NOTIFICATIONs after beacons (see below).
2677e705c121SKalle Valo  *
2678e705c121SKalle Valo  * If the DISABLE_NOTIF configuration flag is set, uCode will not issue
2679e705c121SKalle Valo  * STATISTICS_NOTIFICATIONs after received beacons (see below).  This flag
2680e705c121SKalle Valo  * does not affect the response to the REPLY_STATISTICS_CMD 0x9c itself.
2681e705c121SKalle Valo  */
2682e705c121SKalle Valo #define IWL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1)	/* see above */
2683e705c121SKalle Valo #define IWL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)/* see above */
2684e705c121SKalle Valo struct iwl_statistics_cmd {
2685e705c121SKalle Valo 	__le32 configuration_flags;	/* IWL_STATS_CONF_* */
2686e705c121SKalle Valo } __packed;
2687e705c121SKalle Valo 
2688e705c121SKalle Valo /*
2689e705c121SKalle Valo  * STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
2690e705c121SKalle Valo  *
2691e705c121SKalle Valo  * By default, uCode issues this notification after receiving a beacon
2692e705c121SKalle Valo  * while associated.  To disable this behavior, set DISABLE_NOTIF flag in the
2693e705c121SKalle Valo  * REPLY_STATISTICS_CMD 0x9c, above.
2694e705c121SKalle Valo  *
2695e705c121SKalle Valo  * Statistics counters continue to increment beacon after beacon, but are
2696e705c121SKalle Valo  * cleared when changing channels or when driver issues REPLY_STATISTICS_CMD
2697e705c121SKalle Valo  * 0x9c with CLEAR_STATS bit set (see above).
2698e705c121SKalle Valo  *
2699e705c121SKalle Valo  * uCode also issues this notification during scans.  uCode clears statistics
2700e705c121SKalle Valo  * appropriately so that each notification contains statistics for only the
2701e705c121SKalle Valo  * one channel that has just been scanned.
2702e705c121SKalle Valo  */
2703e705c121SKalle Valo #define STATISTICS_REPLY_FLG_BAND_24G_MSK         cpu_to_le32(0x2)
2704e705c121SKalle Valo #define STATISTICS_REPLY_FLG_HT40_MODE_MSK        cpu_to_le32(0x8)
2705e705c121SKalle Valo 
2706e705c121SKalle Valo struct iwl_notif_statistics {
2707e705c121SKalle Valo 	__le32 flag;
2708e705c121SKalle Valo 	struct statistics_rx rx;
2709e705c121SKalle Valo 	struct statistics_tx tx;
2710e705c121SKalle Valo 	struct statistics_general general;
2711e705c121SKalle Valo } __packed;
2712e705c121SKalle Valo 
2713e705c121SKalle Valo struct iwl_bt_notif_statistics {
2714e705c121SKalle Valo 	__le32 flag;
2715e705c121SKalle Valo 	struct statistics_rx_bt rx;
2716e705c121SKalle Valo 	struct statistics_tx tx;
2717e705c121SKalle Valo 	struct statistics_general_bt general;
2718e705c121SKalle Valo } __packed;
2719e705c121SKalle Valo 
2720e705c121SKalle Valo /*
2721e705c121SKalle Valo  * MISSED_BEACONS_NOTIFICATION = 0xa2 (notification only, not a command)
2722e705c121SKalle Valo  *
2723e705c121SKalle Valo  * uCode send MISSED_BEACONS_NOTIFICATION to driver when detect beacon missed
2724e705c121SKalle Valo  * in regardless of how many missed beacons, which mean when driver receive the
2725e705c121SKalle Valo  * notification, inside the command, it can find all the beacons information
2726e705c121SKalle Valo  * which include number of total missed beacons, number of consecutive missed
2727e705c121SKalle Valo  * beacons, number of beacons received and number of beacons expected to
2728e705c121SKalle Valo  * receive.
2729e705c121SKalle Valo  *
2730e705c121SKalle Valo  * If uCode detected consecutive_missed_beacons > 5, it will reset the radio
2731e705c121SKalle Valo  * in order to bring the radio/PHY back to working state; which has no relation
2732e705c121SKalle Valo  * to when driver will perform sensitivity calibration.
2733e705c121SKalle Valo  *
2734e705c121SKalle Valo  * Driver should set it own missed_beacon_threshold to decide when to perform
2735e705c121SKalle Valo  * sensitivity calibration based on number of consecutive missed beacons in
2736e705c121SKalle Valo  * order to improve overall performance, especially in noisy environment.
2737e705c121SKalle Valo  *
2738e705c121SKalle Valo  */
2739e705c121SKalle Valo 
2740e705c121SKalle Valo #define IWL_MISSED_BEACON_THRESHOLD_MIN	(1)
2741e705c121SKalle Valo #define IWL_MISSED_BEACON_THRESHOLD_DEF	(5)
2742e705c121SKalle Valo #define IWL_MISSED_BEACON_THRESHOLD_MAX	IWL_MISSED_BEACON_THRESHOLD_DEF
2743e705c121SKalle Valo 
2744e705c121SKalle Valo struct iwl_missed_beacon_notif {
2745e705c121SKalle Valo 	__le32 consecutive_missed_beacons;
2746e705c121SKalle Valo 	__le32 total_missed_becons;
2747e705c121SKalle Valo 	__le32 num_expected_beacons;
2748e705c121SKalle Valo 	__le32 num_recvd_beacons;
2749e705c121SKalle Valo } __packed;
2750e705c121SKalle Valo 
2751e705c121SKalle Valo 
2752e705c121SKalle Valo /******************************************************************************
2753e705c121SKalle Valo  * (11)
2754e705c121SKalle Valo  * Rx Calibration Commands:
2755e705c121SKalle Valo  *
2756e705c121SKalle Valo  * With the uCode used for open source drivers, most Tx calibration (except
2757e705c121SKalle Valo  * for Tx Power) and most Rx calibration is done by uCode during the
2758e705c121SKalle Valo  * "initialize" phase of uCode boot.  Driver must calibrate only:
2759e705c121SKalle Valo  *
2760e705c121SKalle Valo  * 1)  Tx power (depends on temperature), described elsewhere
2761e705c121SKalle Valo  * 2)  Receiver gain balance (optimize MIMO, and detect disconnected antennas)
2762e705c121SKalle Valo  * 3)  Receiver sensitivity (to optimize signal detection)
2763e705c121SKalle Valo  *
2764e705c121SKalle Valo  *****************************************************************************/
2765e705c121SKalle Valo 
2766e705c121SKalle Valo /**
2767e705c121SKalle Valo  * SENSITIVITY_CMD = 0xa8 (command, has simple generic response)
2768e705c121SKalle Valo  *
2769e705c121SKalle Valo  * This command sets up the Rx signal detector for a sensitivity level that
2770e705c121SKalle Valo  * is high enough to lock onto all signals within the associated network,
2771e705c121SKalle Valo  * but low enough to ignore signals that are below a certain threshold, so as
2772e705c121SKalle Valo  * not to have too many "false alarms".  False alarms are signals that the
2773e705c121SKalle Valo  * Rx DSP tries to lock onto, but then discards after determining that they
2774e705c121SKalle Valo  * are noise.
2775e705c121SKalle Valo  *
2776e705c121SKalle Valo  * The optimum number of false alarms is between 5 and 50 per 200 TUs
2777e705c121SKalle Valo  * (200 * 1024 uSecs, i.e. 204.8 milliseconds) of actual Rx time (i.e.
2778e705c121SKalle Valo  * time listening, not transmitting).  Driver must adjust sensitivity so that
2779e705c121SKalle Valo  * the ratio of actual false alarms to actual Rx time falls within this range.
2780e705c121SKalle Valo  *
2781e705c121SKalle Valo  * While associated, uCode delivers STATISTICS_NOTIFICATIONs after each
2782e705c121SKalle Valo  * received beacon.  These provide information to the driver to analyze the
2783e705c121SKalle Valo  * sensitivity.  Don't analyze statistics that come in from scanning, or any
2784e705c121SKalle Valo  * other non-associated-network source.  Pertinent statistics include:
2785e705c121SKalle Valo  *
2786e705c121SKalle Valo  * From "general" statistics (struct statistics_rx_non_phy):
2787e705c121SKalle Valo  *
2788e705c121SKalle Valo  * (beacon_energy_[abc] & 0x0FF00) >> 8 (unsigned, higher value is lower level)
2789e705c121SKalle Valo  *   Measure of energy of desired signal.  Used for establishing a level
2790e705c121SKalle Valo  *   below which the device does not detect signals.
2791e705c121SKalle Valo  *
2792e705c121SKalle Valo  * (beacon_silence_rssi_[abc] & 0x0FF00) >> 8 (unsigned, units in dB)
2793e705c121SKalle Valo  *   Measure of background noise in silent period after beacon.
2794e705c121SKalle Valo  *
2795e705c121SKalle Valo  * channel_load
2796e705c121SKalle Valo  *   uSecs of actual Rx time during beacon period (varies according to
2797e705c121SKalle Valo  *   how much time was spent transmitting).
2798e705c121SKalle Valo  *
2799e705c121SKalle Valo  * From "cck" and "ofdm" statistics (struct statistics_rx_phy), separately:
2800e705c121SKalle Valo  *
2801e705c121SKalle Valo  * false_alarm_cnt
2802e705c121SKalle Valo  *   Signal locks abandoned early (before phy-level header).
2803e705c121SKalle Valo  *
2804e705c121SKalle Valo  * plcp_err
2805e705c121SKalle Valo  *   Signal locks abandoned late (during phy-level header).
2806e705c121SKalle Valo  *
2807e705c121SKalle Valo  * NOTE:  Both false_alarm_cnt and plcp_err increment monotonically from
2808e705c121SKalle Valo  *        beacon to beacon, i.e. each value is an accumulation of all errors
2809e705c121SKalle Valo  *        before and including the latest beacon.  Values will wrap around to 0
2810e705c121SKalle Valo  *        after counting up to 2^32 - 1.  Driver must differentiate vs.
2811e705c121SKalle Valo  *        previous beacon's values to determine # false alarms in the current
2812e705c121SKalle Valo  *        beacon period.
2813e705c121SKalle Valo  *
2814e705c121SKalle Valo  * Total number of false alarms = false_alarms + plcp_errs
2815e705c121SKalle Valo  *
2816e705c121SKalle Valo  * For OFDM, adjust the following table entries in struct iwl_sensitivity_cmd
2817e705c121SKalle Valo  * (notice that the start points for OFDM are at or close to settings for
2818e705c121SKalle Valo  * maximum sensitivity):
2819e705c121SKalle Valo  *
2820e705c121SKalle Valo  *                                             START  /  MIN  /  MAX
2821e705c121SKalle Valo  *   HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX          90   /   85  /  120
2822e705c121SKalle Valo  *   HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX     170   /  170  /  210
2823e705c121SKalle Valo  *   HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX         105   /  105  /  140
2824e705c121SKalle Valo  *   HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX     220   /  220  /  270
2825e705c121SKalle Valo  *
2826e705c121SKalle Valo  *   If actual rate of OFDM false alarms (+ plcp_errors) is too high
2827e705c121SKalle Valo  *   (greater than 50 for each 204.8 msecs listening), reduce sensitivity
2828e705c121SKalle Valo  *   by *adding* 1 to all 4 of the table entries above, up to the max for
2829e705c121SKalle Valo  *   each entry.  Conversely, if false alarm rate is too low (less than 5
2830e705c121SKalle Valo  *   for each 204.8 msecs listening), *subtract* 1 from each entry to
2831e705c121SKalle Valo  *   increase sensitivity.
2832e705c121SKalle Valo  *
2833e705c121SKalle Valo  * For CCK sensitivity, keep track of the following:
2834e705c121SKalle Valo  *
2835e705c121SKalle Valo  *   1).  20-beacon history of maximum background noise, indicated by
2836e705c121SKalle Valo  *        (beacon_silence_rssi_[abc] & 0x0FF00), units in dB, across the
2837e705c121SKalle Valo  *        3 receivers.  For any given beacon, the "silence reference" is
2838e705c121SKalle Valo  *        the maximum of last 60 samples (20 beacons * 3 receivers).
2839e705c121SKalle Valo  *
2840e705c121SKalle Valo  *   2).  10-beacon history of strongest signal level, as indicated
2841e705c121SKalle Valo  *        by (beacon_energy_[abc] & 0x0FF00) >> 8, across the 3 receivers,
2842e705c121SKalle Valo  *        i.e. the strength of the signal through the best receiver at the
2843e705c121SKalle Valo  *        moment.  These measurements are "upside down", with lower values
2844e705c121SKalle Valo  *        for stronger signals, so max energy will be *minimum* value.
2845e705c121SKalle Valo  *
2846e705c121SKalle Valo  *        Then for any given beacon, the driver must determine the *weakest*
2847e705c121SKalle Valo  *        of the strongest signals; this is the minimum level that needs to be
2848e705c121SKalle Valo  *        successfully detected, when using the best receiver at the moment.
2849e705c121SKalle Valo  *        "Max cck energy" is the maximum (higher value means lower energy!)
2850e705c121SKalle Valo  *        of the last 10 minima.  Once this is determined, driver must add
2851e705c121SKalle Valo  *        a little margin by adding "6" to it.
2852e705c121SKalle Valo  *
2853e705c121SKalle Valo  *   3).  Number of consecutive beacon periods with too few false alarms.
2854e705c121SKalle Valo  *        Reset this to 0 at the first beacon period that falls within the
2855e705c121SKalle Valo  *        "good" range (5 to 50 false alarms per 204.8 milliseconds rx).
2856e705c121SKalle Valo  *
2857e705c121SKalle Valo  * Then, adjust the following CCK table entries in struct iwl_sensitivity_cmd
2858e705c121SKalle Valo  * (notice that the start points for CCK are at maximum sensitivity):
2859e705c121SKalle Valo  *
2860e705c121SKalle Valo  *                                             START  /  MIN  /  MAX
2861e705c121SKalle Valo  *   HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX         125   /  125  /  200
2862e705c121SKalle Valo  *   HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX     200   /  200  /  400
2863e705c121SKalle Valo  *   HD_MIN_ENERGY_CCK_DET_INDEX                100   /    0  /  100
2864e705c121SKalle Valo  *
2865e705c121SKalle Valo  *   If actual rate of CCK false alarms (+ plcp_errors) is too high
2866e705c121SKalle Valo  *   (greater than 50 for each 204.8 msecs listening), method for reducing
2867e705c121SKalle Valo  *   sensitivity is:
2868e705c121SKalle Valo  *
2869e705c121SKalle Valo  *   1)  *Add* 3 to value in HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX,
2870e705c121SKalle Valo  *       up to max 400.
2871e705c121SKalle Valo  *
2872e705c121SKalle Valo  *   2)  If current value in HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX is < 160,
2873e705c121SKalle Valo  *       sensitivity has been reduced a significant amount; bring it up to
2874e705c121SKalle Valo  *       a moderate 161.  Otherwise, *add* 3, up to max 200.
2875e705c121SKalle Valo  *
2876e705c121SKalle Valo  *   3)  a)  If current value in HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX is > 160,
2877e705c121SKalle Valo  *       sensitivity has been reduced only a moderate or small amount;
2878e705c121SKalle Valo  *       *subtract* 2 from value in HD_MIN_ENERGY_CCK_DET_INDEX,
2879e705c121SKalle Valo  *       down to min 0.  Otherwise (if gain has been significantly reduced),
2880e705c121SKalle Valo  *       don't change the HD_MIN_ENERGY_CCK_DET_INDEX value.
2881e705c121SKalle Valo  *
2882e705c121SKalle Valo  *       b)  Save a snapshot of the "silence reference".
2883e705c121SKalle Valo  *
2884e705c121SKalle Valo  *   If actual rate of CCK false alarms (+ plcp_errors) is too low
2885e705c121SKalle Valo  *   (less than 5 for each 204.8 msecs listening), method for increasing
2886e705c121SKalle Valo  *   sensitivity is used only if:
2887e705c121SKalle Valo  *
2888e705c121SKalle Valo  *   1a)  Previous beacon did not have too many false alarms
2889e705c121SKalle Valo  *   1b)  AND difference between previous "silence reference" and current
2890e705c121SKalle Valo  *        "silence reference" (prev - current) is 2 or more,
2891e705c121SKalle Valo  *   OR 2)  100 or more consecutive beacon periods have had rate of
2892e705c121SKalle Valo  *          less than 5 false alarms per 204.8 milliseconds rx time.
2893e705c121SKalle Valo  *
2894e705c121SKalle Valo  *   Method for increasing sensitivity:
2895e705c121SKalle Valo  *
2896e705c121SKalle Valo  *   1)  *Subtract* 3 from value in HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX,
2897e705c121SKalle Valo  *       down to min 125.
2898e705c121SKalle Valo  *
2899e705c121SKalle Valo  *   2)  *Subtract* 3 from value in HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX,
2900e705c121SKalle Valo  *       down to min 200.
2901e705c121SKalle Valo  *
2902e705c121SKalle Valo  *   3)  *Add* 2 to value in HD_MIN_ENERGY_CCK_DET_INDEX, up to max 100.
2903e705c121SKalle Valo  *
2904e705c121SKalle Valo  *   If actual rate of CCK false alarms (+ plcp_errors) is within good range
2905e705c121SKalle Valo  *   (between 5 and 50 for each 204.8 msecs listening):
2906e705c121SKalle Valo  *
2907e705c121SKalle Valo  *   1)  Save a snapshot of the silence reference.
2908e705c121SKalle Valo  *
2909e705c121SKalle Valo  *   2)  If previous beacon had too many CCK false alarms (+ plcp_errors),
2910e705c121SKalle Valo  *       give some extra margin to energy threshold by *subtracting* 8
2911e705c121SKalle Valo  *       from value in HD_MIN_ENERGY_CCK_DET_INDEX.
2912e705c121SKalle Valo  *
2913e705c121SKalle Valo  *   For all cases (too few, too many, good range), make sure that the CCK
2914e705c121SKalle Valo  *   detection threshold (energy) is below the energy level for robust
2915e705c121SKalle Valo  *   detection over the past 10 beacon periods, the "Max cck energy".
2916e705c121SKalle Valo  *   Lower values mean higher energy; this means making sure that the value
2917e705c121SKalle Valo  *   in HD_MIN_ENERGY_CCK_DET_INDEX is at or *above* "Max cck energy".
2918e705c121SKalle Valo  *
2919e705c121SKalle Valo  */
2920e705c121SKalle Valo 
2921e705c121SKalle Valo /*
2922e705c121SKalle Valo  * Table entries in SENSITIVITY_CMD (struct iwl_sensitivity_cmd)
2923e705c121SKalle Valo  */
2924e705c121SKalle Valo #define HD_TABLE_SIZE  (11)	/* number of entries */
2925e705c121SKalle Valo #define HD_MIN_ENERGY_CCK_DET_INDEX                 (0)	/* table indexes */
2926e705c121SKalle Valo #define HD_MIN_ENERGY_OFDM_DET_INDEX                (1)
2927e705c121SKalle Valo #define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX          (2)
2928e705c121SKalle Valo #define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX      (3)
2929e705c121SKalle Valo #define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX      (4)
2930e705c121SKalle Valo #define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX          (5)
2931e705c121SKalle Valo #define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX      (6)
2932e705c121SKalle Valo #define HD_BARKER_CORR_TH_ADD_MIN_INDEX             (7)
2933e705c121SKalle Valo #define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX         (8)
2934e705c121SKalle Valo #define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX          (9)
2935e705c121SKalle Valo #define HD_OFDM_ENERGY_TH_IN_INDEX                  (10)
2936e705c121SKalle Valo 
2937e705c121SKalle Valo /*
2938e705c121SKalle Valo  * Additional table entries in enhance SENSITIVITY_CMD
2939e705c121SKalle Valo  */
2940e705c121SKalle Valo #define HD_INA_NON_SQUARE_DET_OFDM_INDEX		(11)
2941e705c121SKalle Valo #define HD_INA_NON_SQUARE_DET_CCK_INDEX			(12)
2942e705c121SKalle Valo #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_INDEX		(13)
2943e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_INDEX		(14)
2944e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_INDEX	(15)
2945e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_SLOPE_INDEX		(16)
2946e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_INDEX		(17)
2947e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_INDEX		(18)
2948e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_INDEX	(19)
2949e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_SLOPE_INDEX		(20)
2950e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_INTERCEPT_INDEX		(21)
2951e705c121SKalle Valo #define HD_RESERVED					(22)
2952e705c121SKalle Valo 
2953e705c121SKalle Valo /* number of entries for enhanced tbl */
2954e705c121SKalle Valo #define ENHANCE_HD_TABLE_SIZE  (23)
2955e705c121SKalle Valo 
2956e705c121SKalle Valo /* number of additional entries for enhanced tbl */
2957e705c121SKalle Valo #define ENHANCE_HD_TABLE_ENTRIES  (ENHANCE_HD_TABLE_SIZE - HD_TABLE_SIZE)
2958e705c121SKalle Valo 
2959e705c121SKalle Valo #define HD_INA_NON_SQUARE_DET_OFDM_DATA_V1		cpu_to_le16(0)
2960e705c121SKalle Valo #define HD_INA_NON_SQUARE_DET_CCK_DATA_V1		cpu_to_le16(0)
2961e705c121SKalle Valo #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1		cpu_to_le16(0)
2962e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1	cpu_to_le16(668)
2963e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1	cpu_to_le16(4)
2964e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1		cpu_to_le16(486)
2965e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1	cpu_to_le16(37)
2966e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1		cpu_to_le16(853)
2967e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1	cpu_to_le16(4)
2968e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1		cpu_to_le16(476)
2969e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1		cpu_to_le16(99)
2970e705c121SKalle Valo 
2971e705c121SKalle Valo #define HD_INA_NON_SQUARE_DET_OFDM_DATA_V2		cpu_to_le16(1)
2972e705c121SKalle Valo #define HD_INA_NON_SQUARE_DET_CCK_DATA_V2		cpu_to_le16(1)
2973e705c121SKalle Valo #define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2		cpu_to_le16(1)
2974e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2	cpu_to_le16(600)
2975e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2	cpu_to_le16(40)
2976e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2		cpu_to_le16(486)
2977e705c121SKalle Valo #define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2	cpu_to_le16(45)
2978e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2		cpu_to_le16(853)
2979e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2	cpu_to_le16(60)
2980e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2		cpu_to_le16(476)
2981e705c121SKalle Valo #define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2		cpu_to_le16(99)
2982e705c121SKalle Valo 
2983e705c121SKalle Valo 
2984e705c121SKalle Valo /* Control field in struct iwl_sensitivity_cmd */
2985e705c121SKalle Valo #define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE	cpu_to_le16(0)
2986e705c121SKalle Valo #define SENSITIVITY_CMD_CONTROL_WORK_TABLE	cpu_to_le16(1)
2987e705c121SKalle Valo 
2988e705c121SKalle Valo /**
2989e705c121SKalle Valo  * struct iwl_sensitivity_cmd
2990e705c121SKalle Valo  * @control:  (1) updates working table, (0) updates default table
2991e705c121SKalle Valo  * @table:  energy threshold values, use HD_* as index into table
2992e705c121SKalle Valo  *
2993e705c121SKalle Valo  * Always use "1" in "control" to update uCode's working table and DSP.
2994e705c121SKalle Valo  */
2995e705c121SKalle Valo struct iwl_sensitivity_cmd {
2996e705c121SKalle Valo 	__le16 control;			/* always use "1" */
2997e705c121SKalle Valo 	__le16 table[HD_TABLE_SIZE];	/* use HD_* as index */
2998e705c121SKalle Valo } __packed;
2999e705c121SKalle Valo 
3000e705c121SKalle Valo /*
3001e705c121SKalle Valo  *
3002e705c121SKalle Valo  */
3003e705c121SKalle Valo struct iwl_enhance_sensitivity_cmd {
3004e705c121SKalle Valo 	__le16 control;			/* always use "1" */
3005e705c121SKalle Valo 	__le16 enhance_table[ENHANCE_HD_TABLE_SIZE];	/* use HD_* as index */
3006e705c121SKalle Valo } __packed;
3007e705c121SKalle Valo 
3008e705c121SKalle Valo 
3009e705c121SKalle Valo /**
3010e705c121SKalle Valo  * REPLY_PHY_CALIBRATION_CMD = 0xb0 (command, has simple generic response)
3011e705c121SKalle Valo  *
3012e705c121SKalle Valo  * This command sets the relative gains of agn device's 3 radio receiver chains.
3013e705c121SKalle Valo  *
3014e705c121SKalle Valo  * After the first association, driver should accumulate signal and noise
3015e705c121SKalle Valo  * statistics from the STATISTICS_NOTIFICATIONs that follow the first 20
3016e705c121SKalle Valo  * beacons from the associated network (don't collect statistics that come
3017e705c121SKalle Valo  * in from scanning, or any other non-network source).
3018e705c121SKalle Valo  *
3019e705c121SKalle Valo  * DISCONNECTED ANTENNA:
3020e705c121SKalle Valo  *
3021e705c121SKalle Valo  * Driver should determine which antennas are actually connected, by comparing
3022e705c121SKalle Valo  * average beacon signal levels for the 3 Rx chains.  Accumulate (add) the
3023e705c121SKalle Valo  * following values over 20 beacons, one accumulator for each of the chains
3024e705c121SKalle Valo  * a/b/c, from struct statistics_rx_non_phy:
3025e705c121SKalle Valo  *
3026e705c121SKalle Valo  * beacon_rssi_[abc] & 0x0FF (unsigned, units in dB)
3027e705c121SKalle Valo  *
3028e705c121SKalle Valo  * Find the strongest signal from among a/b/c.  Compare the other two to the
3029e705c121SKalle Valo  * strongest.  If any signal is more than 15 dB (times 20, unless you
3030e705c121SKalle Valo  * divide the accumulated values by 20) below the strongest, the driver
3031e705c121SKalle Valo  * considers that antenna to be disconnected, and should not try to use that
3032e705c121SKalle Valo  * antenna/chain for Rx or Tx.  If both A and B seem to be disconnected,
3033e705c121SKalle Valo  * driver should declare the stronger one as connected, and attempt to use it
3034e705c121SKalle Valo  * (A and B are the only 2 Tx chains!).
3035e705c121SKalle Valo  *
3036e705c121SKalle Valo  *
3037e705c121SKalle Valo  * RX BALANCE:
3038e705c121SKalle Valo  *
3039e705c121SKalle Valo  * Driver should balance the 3 receivers (but just the ones that are connected
3040e705c121SKalle Valo  * to antennas, see above) for gain, by comparing the average signal levels
3041e705c121SKalle Valo  * detected during the silence after each beacon (background noise).
3042e705c121SKalle Valo  * Accumulate (add) the following values over 20 beacons, one accumulator for
3043e705c121SKalle Valo  * each of the chains a/b/c, from struct statistics_rx_non_phy:
3044e705c121SKalle Valo  *
3045e705c121SKalle Valo  * beacon_silence_rssi_[abc] & 0x0FF (unsigned, units in dB)
3046e705c121SKalle Valo  *
3047e705c121SKalle Valo  * Find the weakest background noise level from among a/b/c.  This Rx chain
3048e705c121SKalle Valo  * will be the reference, with 0 gain adjustment.  Attenuate other channels by
3049e705c121SKalle Valo  * finding noise difference:
3050e705c121SKalle Valo  *
3051e705c121SKalle Valo  * (accum_noise[i] - accum_noise[reference]) / 30
3052e705c121SKalle Valo  *
3053e705c121SKalle Valo  * The "30" adjusts the dB in the 20 accumulated samples to units of 1.5 dB.
3054e705c121SKalle Valo  * For use in diff_gain_[abc] fields of struct iwl_calibration_cmd, the
3055e705c121SKalle Valo  * driver should limit the difference results to a range of 0-3 (0-4.5 dB),
3056e705c121SKalle Valo  * and set bit 2 to indicate "reduce gain".  The value for the reference
3057e705c121SKalle Valo  * (weakest) chain should be "0".
3058e705c121SKalle Valo  *
3059e705c121SKalle Valo  * diff_gain_[abc] bit fields:
3060e705c121SKalle Valo  *   2: (1) reduce gain, (0) increase gain
3061e705c121SKalle Valo  * 1-0: amount of gain, units of 1.5 dB
3062e705c121SKalle Valo  */
3063e705c121SKalle Valo 
3064e705c121SKalle Valo /* Phy calibration command for series */
3065e705c121SKalle Valo enum {
3066e705c121SKalle Valo 	IWL_PHY_CALIBRATE_DC_CMD		= 8,
3067e705c121SKalle Valo 	IWL_PHY_CALIBRATE_LO_CMD		= 9,
3068e705c121SKalle Valo 	IWL_PHY_CALIBRATE_TX_IQ_CMD		= 11,
3069e705c121SKalle Valo 	IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD	= 15,
3070e705c121SKalle Valo 	IWL_PHY_CALIBRATE_BASE_BAND_CMD		= 16,
3071e705c121SKalle Valo 	IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD	= 17,
3072e705c121SKalle Valo 	IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD	= 18,
3073e705c121SKalle Valo };
3074e705c121SKalle Valo 
3075e705c121SKalle Valo /* This enum defines the bitmap of various calibrations to enable in both
3076e705c121SKalle Valo  * init ucode and runtime ucode through CALIBRATION_CFG_CMD.
3077e705c121SKalle Valo  */
3078e705c121SKalle Valo enum iwl_ucode_calib_cfg {
3079e705c121SKalle Valo 	IWL_CALIB_CFG_RX_BB_IDX			= BIT(0),
3080e705c121SKalle Valo 	IWL_CALIB_CFG_DC_IDX			= BIT(1),
3081e705c121SKalle Valo 	IWL_CALIB_CFG_LO_IDX			= BIT(2),
3082e705c121SKalle Valo 	IWL_CALIB_CFG_TX_IQ_IDX			= BIT(3),
3083e705c121SKalle Valo 	IWL_CALIB_CFG_RX_IQ_IDX			= BIT(4),
3084e705c121SKalle Valo 	IWL_CALIB_CFG_NOISE_IDX			= BIT(5),
3085e705c121SKalle Valo 	IWL_CALIB_CFG_CRYSTAL_IDX		= BIT(6),
3086e705c121SKalle Valo 	IWL_CALIB_CFG_TEMPERATURE_IDX		= BIT(7),
3087e705c121SKalle Valo 	IWL_CALIB_CFG_PAPD_IDX			= BIT(8),
3088e705c121SKalle Valo 	IWL_CALIB_CFG_SENSITIVITY_IDX		= BIT(9),
3089e705c121SKalle Valo 	IWL_CALIB_CFG_TX_PWR_IDX		= BIT(10),
3090e705c121SKalle Valo };
3091e705c121SKalle Valo 
3092e705c121SKalle Valo #define IWL_CALIB_INIT_CFG_ALL	cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX |	\
3093e705c121SKalle Valo 					IWL_CALIB_CFG_DC_IDX |		\
3094e705c121SKalle Valo 					IWL_CALIB_CFG_LO_IDX |		\
3095e705c121SKalle Valo 					IWL_CALIB_CFG_TX_IQ_IDX |	\
3096e705c121SKalle Valo 					IWL_CALIB_CFG_RX_IQ_IDX |	\
3097e705c121SKalle Valo 					IWL_CALIB_CFG_CRYSTAL_IDX)
3098e705c121SKalle Valo 
3099e705c121SKalle Valo #define IWL_CALIB_RT_CFG_ALL	cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX |	\
3100e705c121SKalle Valo 					IWL_CALIB_CFG_DC_IDX |		\
3101e705c121SKalle Valo 					IWL_CALIB_CFG_LO_IDX |		\
3102e705c121SKalle Valo 					IWL_CALIB_CFG_TX_IQ_IDX |	\
3103e705c121SKalle Valo 					IWL_CALIB_CFG_RX_IQ_IDX |	\
3104e705c121SKalle Valo 					IWL_CALIB_CFG_TEMPERATURE_IDX |	\
3105e705c121SKalle Valo 					IWL_CALIB_CFG_PAPD_IDX |	\
3106e705c121SKalle Valo 					IWL_CALIB_CFG_TX_PWR_IDX |	\
3107e705c121SKalle Valo 					IWL_CALIB_CFG_CRYSTAL_IDX)
3108e705c121SKalle Valo 
3109e705c121SKalle Valo #define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK	cpu_to_le32(BIT(0))
3110e705c121SKalle Valo 
3111e705c121SKalle Valo struct iwl_calib_cfg_elmnt_s {
3112e705c121SKalle Valo 	__le32 is_enable;
3113e705c121SKalle Valo 	__le32 start;
3114e705c121SKalle Valo 	__le32 send_res;
3115e705c121SKalle Valo 	__le32 apply_res;
3116e705c121SKalle Valo 	__le32 reserved;
3117e705c121SKalle Valo } __packed;
3118e705c121SKalle Valo 
3119e705c121SKalle Valo struct iwl_calib_cfg_status_s {
3120e705c121SKalle Valo 	struct iwl_calib_cfg_elmnt_s once;
3121e705c121SKalle Valo 	struct iwl_calib_cfg_elmnt_s perd;
3122e705c121SKalle Valo 	__le32 flags;
3123e705c121SKalle Valo } __packed;
3124e705c121SKalle Valo 
3125e705c121SKalle Valo struct iwl_calib_cfg_cmd {
3126e705c121SKalle Valo 	struct iwl_calib_cfg_status_s ucd_calib_cfg;
3127e705c121SKalle Valo 	struct iwl_calib_cfg_status_s drv_calib_cfg;
3128e705c121SKalle Valo 	__le32 reserved1;
3129e705c121SKalle Valo } __packed;
3130e705c121SKalle Valo 
3131e705c121SKalle Valo struct iwl_calib_hdr {
3132e705c121SKalle Valo 	u8 op_code;
3133e705c121SKalle Valo 	u8 first_group;
3134e705c121SKalle Valo 	u8 groups_num;
3135e705c121SKalle Valo 	u8 data_valid;
3136e705c121SKalle Valo } __packed;
3137e705c121SKalle Valo 
3138e705c121SKalle Valo struct iwl_calib_cmd {
3139e705c121SKalle Valo 	struct iwl_calib_hdr hdr;
314045c21a0eSGustavo A. R. Silva 	u8 data[];
3141e705c121SKalle Valo } __packed;
3142e705c121SKalle Valo 
3143e705c121SKalle Valo struct iwl_calib_xtal_freq_cmd {
3144e705c121SKalle Valo 	struct iwl_calib_hdr hdr;
3145e705c121SKalle Valo 	u8 cap_pin1;
3146e705c121SKalle Valo 	u8 cap_pin2;
3147e705c121SKalle Valo 	u8 pad[2];
3148e705c121SKalle Valo } __packed;
3149e705c121SKalle Valo 
3150e705c121SKalle Valo #define DEFAULT_RADIO_SENSOR_OFFSET    cpu_to_le16(2700)
3151e705c121SKalle Valo struct iwl_calib_temperature_offset_cmd {
3152e705c121SKalle Valo 	struct iwl_calib_hdr hdr;
3153e705c121SKalle Valo 	__le16 radio_sensor_offset;
3154e705c121SKalle Valo 	__le16 reserved;
3155e705c121SKalle Valo } __packed;
3156e705c121SKalle Valo 
3157e705c121SKalle Valo struct iwl_calib_temperature_offset_v2_cmd {
3158e705c121SKalle Valo 	struct iwl_calib_hdr hdr;
3159e705c121SKalle Valo 	__le16 radio_sensor_offset_high;
3160e705c121SKalle Valo 	__le16 radio_sensor_offset_low;
3161e705c121SKalle Valo 	__le16 burntVoltageRef;
3162e705c121SKalle Valo 	__le16 reserved;
3163e705c121SKalle Valo } __packed;
3164e705c121SKalle Valo 
3165e705c121SKalle Valo /* IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD */
3166e705c121SKalle Valo struct iwl_calib_chain_noise_reset_cmd {
3167e705c121SKalle Valo 	struct iwl_calib_hdr hdr;
316845c21a0eSGustavo A. R. Silva 	u8 data[];
3169e705c121SKalle Valo };
3170e705c121SKalle Valo 
3171e705c121SKalle Valo /* IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD */
3172e705c121SKalle Valo struct iwl_calib_chain_noise_gain_cmd {
3173e705c121SKalle Valo 	struct iwl_calib_hdr hdr;
3174e705c121SKalle Valo 	u8 delta_gain_1;
3175e705c121SKalle Valo 	u8 delta_gain_2;
3176e705c121SKalle Valo 	u8 pad[2];
3177e705c121SKalle Valo } __packed;
3178e705c121SKalle Valo 
3179e705c121SKalle Valo /******************************************************************************
3180e705c121SKalle Valo  * (12)
3181e705c121SKalle Valo  * Miscellaneous Commands:
3182e705c121SKalle Valo  *
3183e705c121SKalle Valo  *****************************************************************************/
3184e705c121SKalle Valo 
3185e705c121SKalle Valo /*
3186e705c121SKalle Valo  * LEDs Command & Response
3187e705c121SKalle Valo  * REPLY_LEDS_CMD = 0x48 (command, has simple generic response)
3188e705c121SKalle Valo  *
3189e705c121SKalle Valo  * For each of 3 possible LEDs (Activity/Link/Tech, selected by "id" field),
3190e705c121SKalle Valo  * this command turns it on or off, or sets up a periodic blinking cycle.
3191e705c121SKalle Valo  */
3192e705c121SKalle Valo struct iwl_led_cmd {
3193e705c121SKalle Valo 	__le32 interval;	/* "interval" in uSec */
3194e705c121SKalle Valo 	u8 id;			/* 1: Activity, 2: Link, 3: Tech */
3195e705c121SKalle Valo 	u8 off;			/* # intervals off while blinking;
3196e705c121SKalle Valo 				 * "0", with >0 "on" value, turns LED on */
3197e705c121SKalle Valo 	u8 on;			/* # intervals on while blinking;
3198e705c121SKalle Valo 				 * "0", regardless of "off", turns LED off */
3199e705c121SKalle Valo 	u8 reserved;
3200e705c121SKalle Valo } __packed;
3201e705c121SKalle Valo 
3202e705c121SKalle Valo /*
3203e705c121SKalle Valo  * station priority table entries
3204e705c121SKalle Valo  * also used as potential "events" value for both
3205e705c121SKalle Valo  * COEX_MEDIUM_NOTIFICATION and COEX_EVENT_CMD
3206e705c121SKalle Valo  */
3207e705c121SKalle Valo 
3208e705c121SKalle Valo /*
3209e705c121SKalle Valo  * COEX events entry flag masks
3210e705c121SKalle Valo  * RP - Requested Priority
3211e705c121SKalle Valo  * WP - Win Medium Priority: priority assigned when the contention has been won
3212e705c121SKalle Valo  */
3213e705c121SKalle Valo #define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG        (0x1)
3214e705c121SKalle Valo #define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG        (0x2)
3215e705c121SKalle Valo #define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG  (0x4)
3216e705c121SKalle Valo 
3217e705c121SKalle Valo #define COEX_CU_UNASSOC_IDLE_RP               4
3218e705c121SKalle Valo #define COEX_CU_UNASSOC_MANUAL_SCAN_RP        4
3219e705c121SKalle Valo #define COEX_CU_UNASSOC_AUTO_SCAN_RP          4
3220e705c121SKalle Valo #define COEX_CU_CALIBRATION_RP                4
3221e705c121SKalle Valo #define COEX_CU_PERIODIC_CALIBRATION_RP       4
3222e705c121SKalle Valo #define COEX_CU_CONNECTION_ESTAB_RP           4
3223e705c121SKalle Valo #define COEX_CU_ASSOCIATED_IDLE_RP            4
3224e705c121SKalle Valo #define COEX_CU_ASSOC_MANUAL_SCAN_RP          4
3225e705c121SKalle Valo #define COEX_CU_ASSOC_AUTO_SCAN_RP            4
3226e705c121SKalle Valo #define COEX_CU_ASSOC_ACTIVE_LEVEL_RP         4
3227e705c121SKalle Valo #define COEX_CU_RF_ON_RP                      6
3228e705c121SKalle Valo #define COEX_CU_RF_OFF_RP                     4
3229e705c121SKalle Valo #define COEX_CU_STAND_ALONE_DEBUG_RP          6
3230e705c121SKalle Valo #define COEX_CU_IPAN_ASSOC_LEVEL_RP           4
3231e705c121SKalle Valo #define COEX_CU_RSRVD1_RP                     4
3232e705c121SKalle Valo #define COEX_CU_RSRVD2_RP                     4
3233e705c121SKalle Valo 
3234e705c121SKalle Valo #define COEX_CU_UNASSOC_IDLE_WP               3
3235e705c121SKalle Valo #define COEX_CU_UNASSOC_MANUAL_SCAN_WP        3
3236e705c121SKalle Valo #define COEX_CU_UNASSOC_AUTO_SCAN_WP          3
3237e705c121SKalle Valo #define COEX_CU_CALIBRATION_WP                3
3238e705c121SKalle Valo #define COEX_CU_PERIODIC_CALIBRATION_WP       3
3239e705c121SKalle Valo #define COEX_CU_CONNECTION_ESTAB_WP           3
3240e705c121SKalle Valo #define COEX_CU_ASSOCIATED_IDLE_WP            3
3241e705c121SKalle Valo #define COEX_CU_ASSOC_MANUAL_SCAN_WP          3
3242e705c121SKalle Valo #define COEX_CU_ASSOC_AUTO_SCAN_WP            3
3243e705c121SKalle Valo #define COEX_CU_ASSOC_ACTIVE_LEVEL_WP         3
3244e705c121SKalle Valo #define COEX_CU_RF_ON_WP                      3
3245e705c121SKalle Valo #define COEX_CU_RF_OFF_WP                     3
3246e705c121SKalle Valo #define COEX_CU_STAND_ALONE_DEBUG_WP          6
3247e705c121SKalle Valo #define COEX_CU_IPAN_ASSOC_LEVEL_WP           3
3248e705c121SKalle Valo #define COEX_CU_RSRVD1_WP                     3
3249e705c121SKalle Valo #define COEX_CU_RSRVD2_WP                     3
3250e705c121SKalle Valo 
3251e705c121SKalle Valo #define COEX_UNASSOC_IDLE_FLAGS                     0
3252e705c121SKalle Valo #define COEX_UNASSOC_MANUAL_SCAN_FLAGS		\
3253e705c121SKalle Valo 	(COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG |	\
3254e705c121SKalle Valo 	COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3255e705c121SKalle Valo #define COEX_UNASSOC_AUTO_SCAN_FLAGS		\
3256e705c121SKalle Valo 	(COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG |	\
3257e705c121SKalle Valo 	COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3258e705c121SKalle Valo #define COEX_CALIBRATION_FLAGS			\
3259e705c121SKalle Valo 	(COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG |	\
3260e705c121SKalle Valo 	COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3261e705c121SKalle Valo #define COEX_PERIODIC_CALIBRATION_FLAGS             0
3262e705c121SKalle Valo /*
3263e705c121SKalle Valo  * COEX_CONNECTION_ESTAB:
3264e705c121SKalle Valo  * we need DELAY_MEDIUM_FREE_NTFY to let WiMAX disconnect from network.
3265e705c121SKalle Valo  */
3266e705c121SKalle Valo #define COEX_CONNECTION_ESTAB_FLAGS		\
3267e705c121SKalle Valo 	(COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG |	\
3268e705c121SKalle Valo 	COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG |	\
3269e705c121SKalle Valo 	COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3270e705c121SKalle Valo #define COEX_ASSOCIATED_IDLE_FLAGS                  0
3271e705c121SKalle Valo #define COEX_ASSOC_MANUAL_SCAN_FLAGS		\
3272e705c121SKalle Valo 	(COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG |	\
3273e705c121SKalle Valo 	COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3274e705c121SKalle Valo #define COEX_ASSOC_AUTO_SCAN_FLAGS		\
3275e705c121SKalle Valo 	(COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG |	\
3276e705c121SKalle Valo 	 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3277e705c121SKalle Valo #define COEX_ASSOC_ACTIVE_LEVEL_FLAGS               0
3278e705c121SKalle Valo #define COEX_RF_ON_FLAGS                            0
3279e705c121SKalle Valo #define COEX_RF_OFF_FLAGS                           0
3280e705c121SKalle Valo #define COEX_STAND_ALONE_DEBUG_FLAGS		\
3281e705c121SKalle Valo 	(COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG |	\
3282e705c121SKalle Valo 	 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3283e705c121SKalle Valo #define COEX_IPAN_ASSOC_LEVEL_FLAGS		\
3284e705c121SKalle Valo 	(COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG |	\
3285e705c121SKalle Valo 	 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG |	\
3286e705c121SKalle Valo 	 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3287e705c121SKalle Valo #define COEX_RSRVD1_FLAGS                           0
3288e705c121SKalle Valo #define COEX_RSRVD2_FLAGS                           0
3289e705c121SKalle Valo /*
3290e705c121SKalle Valo  * COEX_CU_RF_ON is the event wrapping all radio ownership.
3291e705c121SKalle Valo  * We need DELAY_MEDIUM_FREE_NTFY to let WiMAX disconnect from network.
3292e705c121SKalle Valo  */
3293e705c121SKalle Valo #define COEX_CU_RF_ON_FLAGS			\
3294e705c121SKalle Valo 	(COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG |	\
3295e705c121SKalle Valo 	 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG |	\
3296e705c121SKalle Valo 	 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3297e705c121SKalle Valo 
3298e705c121SKalle Valo 
3299e705c121SKalle Valo enum {
3300e705c121SKalle Valo 	/* un-association part */
3301e705c121SKalle Valo 	COEX_UNASSOC_IDLE		= 0,
3302e705c121SKalle Valo 	COEX_UNASSOC_MANUAL_SCAN	= 1,
3303e705c121SKalle Valo 	COEX_UNASSOC_AUTO_SCAN		= 2,
3304e705c121SKalle Valo 	/* calibration */
3305e705c121SKalle Valo 	COEX_CALIBRATION		= 3,
3306e705c121SKalle Valo 	COEX_PERIODIC_CALIBRATION	= 4,
3307e705c121SKalle Valo 	/* connection */
3308e705c121SKalle Valo 	COEX_CONNECTION_ESTAB		= 5,
3309e705c121SKalle Valo 	/* association part */
3310e705c121SKalle Valo 	COEX_ASSOCIATED_IDLE		= 6,
3311e705c121SKalle Valo 	COEX_ASSOC_MANUAL_SCAN		= 7,
3312e705c121SKalle Valo 	COEX_ASSOC_AUTO_SCAN		= 8,
3313e705c121SKalle Valo 	COEX_ASSOC_ACTIVE_LEVEL		= 9,
3314e705c121SKalle Valo 	/* RF ON/OFF */
3315e705c121SKalle Valo 	COEX_RF_ON			= 10,
3316e705c121SKalle Valo 	COEX_RF_OFF			= 11,
3317e705c121SKalle Valo 	COEX_STAND_ALONE_DEBUG		= 12,
3318e705c121SKalle Valo 	/* IPAN */
3319e705c121SKalle Valo 	COEX_IPAN_ASSOC_LEVEL		= 13,
3320e705c121SKalle Valo 	/* reserved */
3321e705c121SKalle Valo 	COEX_RSRVD1			= 14,
3322e705c121SKalle Valo 	COEX_RSRVD2			= 15,
3323e705c121SKalle Valo 	COEX_NUM_OF_EVENTS		= 16
3324e705c121SKalle Valo };
3325e705c121SKalle Valo 
3326e705c121SKalle Valo /*
3327e705c121SKalle Valo  * Coexistence WIFI/WIMAX  Command
3328e705c121SKalle Valo  * COEX_PRIORITY_TABLE_CMD = 0x5a
3329e705c121SKalle Valo  *
3330e705c121SKalle Valo  */
3331e705c121SKalle Valo struct iwl_wimax_coex_event_entry {
3332e705c121SKalle Valo 	u8 request_prio;
3333e705c121SKalle Valo 	u8 win_medium_prio;
3334e705c121SKalle Valo 	u8 reserved;
3335e705c121SKalle Valo 	u8 flags;
3336e705c121SKalle Valo } __packed;
3337e705c121SKalle Valo 
3338e705c121SKalle Valo /* COEX flag masks */
3339e705c121SKalle Valo 
3340e705c121SKalle Valo /* Station table is valid */
3341e705c121SKalle Valo #define COEX_FLAGS_STA_TABLE_VALID_MSK      (0x1)
3342e705c121SKalle Valo /* UnMask wake up src at unassociated sleep */
3343e705c121SKalle Valo #define COEX_FLAGS_UNASSOC_WA_UNMASK_MSK    (0x4)
3344e705c121SKalle Valo /* UnMask wake up src at associated sleep */
3345e705c121SKalle Valo #define COEX_FLAGS_ASSOC_WA_UNMASK_MSK      (0x8)
3346e705c121SKalle Valo /* Enable CoEx feature. */
3347e705c121SKalle Valo #define COEX_FLAGS_COEX_ENABLE_MSK          (0x80)
3348e705c121SKalle Valo 
3349e705c121SKalle Valo struct iwl_wimax_coex_cmd {
3350e705c121SKalle Valo 	u8 flags;
3351e705c121SKalle Valo 	u8 reserved[3];
3352e705c121SKalle Valo 	struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS];
3353e705c121SKalle Valo } __packed;
3354e705c121SKalle Valo 
3355e705c121SKalle Valo /*
3356e705c121SKalle Valo  * Coexistence MEDIUM NOTIFICATION
3357e705c121SKalle Valo  * COEX_MEDIUM_NOTIFICATION = 0x5b
3358e705c121SKalle Valo  *
3359e705c121SKalle Valo  * notification from uCode to host to indicate medium changes
3360e705c121SKalle Valo  *
3361e705c121SKalle Valo  */
3362e705c121SKalle Valo /*
3363e705c121SKalle Valo  * status field
3364e705c121SKalle Valo  * bit 0 - 2: medium status
3365e705c121SKalle Valo  * bit 3: medium change indication
3366e705c121SKalle Valo  * bit 4 - 31: reserved
3367e705c121SKalle Valo  */
3368e705c121SKalle Valo /* status option values, (0 - 2 bits) */
3369e705c121SKalle Valo #define COEX_MEDIUM_BUSY	(0x0) /* radio belongs to WiMAX */
3370e705c121SKalle Valo #define COEX_MEDIUM_ACTIVE	(0x1) /* radio belongs to WiFi */
3371e705c121SKalle Valo #define COEX_MEDIUM_PRE_RELEASE	(0x2) /* received radio release */
3372e705c121SKalle Valo #define COEX_MEDIUM_MSK		(0x7)
3373e705c121SKalle Valo 
3374e705c121SKalle Valo /* send notification status (1 bit) */
3375e705c121SKalle Valo #define COEX_MEDIUM_CHANGED	(0x8)
3376e705c121SKalle Valo #define COEX_MEDIUM_CHANGED_MSK	(0x8)
3377e705c121SKalle Valo #define COEX_MEDIUM_SHIFT	(3)
3378e705c121SKalle Valo 
3379e705c121SKalle Valo struct iwl_coex_medium_notification {
3380e705c121SKalle Valo 	__le32 status;
3381e705c121SKalle Valo 	__le32 events;
3382e705c121SKalle Valo } __packed;
3383e705c121SKalle Valo 
3384e705c121SKalle Valo /*
3385e705c121SKalle Valo  * Coexistence EVENT  Command
3386e705c121SKalle Valo  * COEX_EVENT_CMD = 0x5c
3387e705c121SKalle Valo  *
3388e705c121SKalle Valo  * send from host to uCode for coex event request.
3389e705c121SKalle Valo  */
3390e705c121SKalle Valo /* flags options */
3391e705c121SKalle Valo #define COEX_EVENT_REQUEST_MSK	(0x1)
3392e705c121SKalle Valo 
3393e705c121SKalle Valo struct iwl_coex_event_cmd {
3394e705c121SKalle Valo 	u8 flags;
3395e705c121SKalle Valo 	u8 event;
3396e705c121SKalle Valo 	__le16 reserved;
3397e705c121SKalle Valo } __packed;
3398e705c121SKalle Valo 
3399e705c121SKalle Valo struct iwl_coex_event_resp {
3400e705c121SKalle Valo 	__le32 status;
3401e705c121SKalle Valo } __packed;
3402e705c121SKalle Valo 
3403e705c121SKalle Valo 
3404e705c121SKalle Valo /******************************************************************************
3405e705c121SKalle Valo  * Bluetooth Coexistence commands
3406e705c121SKalle Valo  *
3407e705c121SKalle Valo  *****************************************************************************/
3408e705c121SKalle Valo 
3409e705c121SKalle Valo /*
3410e705c121SKalle Valo  * BT Status notification
3411e705c121SKalle Valo  * REPLY_BT_COEX_PROFILE_NOTIF = 0xce
3412e705c121SKalle Valo  */
3413e705c121SKalle Valo enum iwl_bt_coex_profile_traffic_load {
3414e705c121SKalle Valo 	IWL_BT_COEX_TRAFFIC_LOAD_NONE = 	0,
3415e705c121SKalle Valo 	IWL_BT_COEX_TRAFFIC_LOAD_LOW =		1,
3416e705c121SKalle Valo 	IWL_BT_COEX_TRAFFIC_LOAD_HIGH = 	2,
3417e705c121SKalle Valo 	IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS =	3,
3418e705c121SKalle Valo /*
3419e705c121SKalle Valo  * There are no more even though below is a u8, the
3420e705c121SKalle Valo  * indication from the BT device only has two bits.
3421e705c121SKalle Valo  */
3422e705c121SKalle Valo };
3423e705c121SKalle Valo 
3424e705c121SKalle Valo #define BT_SESSION_ACTIVITY_1_UART_MSG		0x1
3425e705c121SKalle Valo #define BT_SESSION_ACTIVITY_2_UART_MSG		0x2
3426e705c121SKalle Valo 
3427e705c121SKalle Valo /* BT UART message - Share Part (BT -> WiFi) */
3428e705c121SKalle Valo #define BT_UART_MSG_FRAME1MSGTYPE_POS		(0)
3429e705c121SKalle Valo #define BT_UART_MSG_FRAME1MSGTYPE_MSK		\
3430e705c121SKalle Valo 		(0x7 << BT_UART_MSG_FRAME1MSGTYPE_POS)
3431e705c121SKalle Valo #define BT_UART_MSG_FRAME1SSN_POS		(3)
3432e705c121SKalle Valo #define BT_UART_MSG_FRAME1SSN_MSK		\
3433e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME1SSN_POS)
3434e705c121SKalle Valo #define BT_UART_MSG_FRAME1UPDATEREQ_POS		(5)
3435e705c121SKalle Valo #define BT_UART_MSG_FRAME1UPDATEREQ_MSK		\
3436e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME1UPDATEREQ_POS)
3437e705c121SKalle Valo #define BT_UART_MSG_FRAME1RESERVED_POS		(6)
3438e705c121SKalle Valo #define BT_UART_MSG_FRAME1RESERVED_MSK		\
3439e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME1RESERVED_POS)
3440e705c121SKalle Valo 
3441e705c121SKalle Valo #define BT_UART_MSG_FRAME2OPENCONNECTIONS_POS	(0)
3442e705c121SKalle Valo #define BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK	\
3443e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME2OPENCONNECTIONS_POS)
3444e705c121SKalle Valo #define BT_UART_MSG_FRAME2TRAFFICLOAD_POS	(2)
3445e705c121SKalle Valo #define BT_UART_MSG_FRAME2TRAFFICLOAD_MSK	\
3446e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME2TRAFFICLOAD_POS)
3447e705c121SKalle Valo #define BT_UART_MSG_FRAME2CHLSEQN_POS		(4)
3448e705c121SKalle Valo #define BT_UART_MSG_FRAME2CHLSEQN_MSK		\
3449e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME2CHLSEQN_POS)
3450e705c121SKalle Valo #define BT_UART_MSG_FRAME2INBAND_POS		(5)
3451e705c121SKalle Valo #define BT_UART_MSG_FRAME2INBAND_MSK		\
3452e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME2INBAND_POS)
3453e705c121SKalle Valo #define BT_UART_MSG_FRAME2RESERVED_POS		(6)
3454e705c121SKalle Valo #define BT_UART_MSG_FRAME2RESERVED_MSK		\
3455e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME2RESERVED_POS)
3456e705c121SKalle Valo 
3457e705c121SKalle Valo #define BT_UART_MSG_FRAME3SCOESCO_POS		(0)
3458e705c121SKalle Valo #define BT_UART_MSG_FRAME3SCOESCO_MSK		\
3459e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME3SCOESCO_POS)
3460e705c121SKalle Valo #define BT_UART_MSG_FRAME3SNIFF_POS		(1)
3461e705c121SKalle Valo #define BT_UART_MSG_FRAME3SNIFF_MSK		\
3462e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME3SNIFF_POS)
3463e705c121SKalle Valo #define BT_UART_MSG_FRAME3A2DP_POS		(2)
3464e705c121SKalle Valo #define BT_UART_MSG_FRAME3A2DP_MSK		\
3465e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME3A2DP_POS)
3466e705c121SKalle Valo #define BT_UART_MSG_FRAME3ACL_POS		(3)
3467e705c121SKalle Valo #define BT_UART_MSG_FRAME3ACL_MSK		\
3468e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME3ACL_POS)
3469e705c121SKalle Valo #define BT_UART_MSG_FRAME3MASTER_POS		(4)
3470e705c121SKalle Valo #define BT_UART_MSG_FRAME3MASTER_MSK		\
3471e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME3MASTER_POS)
3472e705c121SKalle Valo #define BT_UART_MSG_FRAME3OBEX_POS		(5)
3473e705c121SKalle Valo #define BT_UART_MSG_FRAME3OBEX_MSK		\
3474e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME3OBEX_POS)
3475e705c121SKalle Valo #define BT_UART_MSG_FRAME3RESERVED_POS		(6)
3476e705c121SKalle Valo #define BT_UART_MSG_FRAME3RESERVED_MSK		\
3477e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME3RESERVED_POS)
3478e705c121SKalle Valo 
3479e705c121SKalle Valo #define BT_UART_MSG_FRAME4IDLEDURATION_POS	(0)
3480e705c121SKalle Valo #define BT_UART_MSG_FRAME4IDLEDURATION_MSK	\
3481e705c121SKalle Valo 		(0x3F << BT_UART_MSG_FRAME4IDLEDURATION_POS)
3482e705c121SKalle Valo #define BT_UART_MSG_FRAME4RESERVED_POS		(6)
3483e705c121SKalle Valo #define BT_UART_MSG_FRAME4RESERVED_MSK		\
3484e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME4RESERVED_POS)
3485e705c121SKalle Valo 
3486e705c121SKalle Valo #define BT_UART_MSG_FRAME5TXACTIVITY_POS	(0)
3487e705c121SKalle Valo #define BT_UART_MSG_FRAME5TXACTIVITY_MSK	\
3488e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME5TXACTIVITY_POS)
3489e705c121SKalle Valo #define BT_UART_MSG_FRAME5RXACTIVITY_POS	(2)
3490e705c121SKalle Valo #define BT_UART_MSG_FRAME5RXACTIVITY_MSK	\
3491e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME5RXACTIVITY_POS)
3492e705c121SKalle Valo #define BT_UART_MSG_FRAME5ESCORETRANSMIT_POS	(4)
3493e705c121SKalle Valo #define BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK	\
3494e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME5ESCORETRANSMIT_POS)
3495e705c121SKalle Valo #define BT_UART_MSG_FRAME5RESERVED_POS		(6)
3496e705c121SKalle Valo #define BT_UART_MSG_FRAME5RESERVED_MSK		\
3497e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME5RESERVED_POS)
3498e705c121SKalle Valo 
3499e705c121SKalle Valo #define BT_UART_MSG_FRAME6SNIFFINTERVAL_POS	(0)
3500e705c121SKalle Valo #define BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK	\
3501e705c121SKalle Valo 		(0x1F << BT_UART_MSG_FRAME6SNIFFINTERVAL_POS)
3502e705c121SKalle Valo #define BT_UART_MSG_FRAME6DISCOVERABLE_POS	(5)
3503e705c121SKalle Valo #define BT_UART_MSG_FRAME6DISCOVERABLE_MSK	\
3504e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME6DISCOVERABLE_POS)
3505e705c121SKalle Valo #define BT_UART_MSG_FRAME6RESERVED_POS		(6)
3506e705c121SKalle Valo #define BT_UART_MSG_FRAME6RESERVED_MSK		\
3507e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME6RESERVED_POS)
3508e705c121SKalle Valo 
3509e705c121SKalle Valo #define BT_UART_MSG_FRAME7SNIFFACTIVITY_POS	(0)
3510e705c121SKalle Valo #define BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK	\
3511e705c121SKalle Valo 		(0x7 << BT_UART_MSG_FRAME7SNIFFACTIVITY_POS)
3512e705c121SKalle Valo #define BT_UART_MSG_FRAME7PAGE_POS		(3)
3513e705c121SKalle Valo #define BT_UART_MSG_FRAME7PAGE_MSK		\
3514e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME7PAGE_POS)
3515e705c121SKalle Valo #define BT_UART_MSG_FRAME7INQUIRY_POS		(4)
3516e705c121SKalle Valo #define BT_UART_MSG_FRAME7INQUIRY_MSK		\
3517e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME7INQUIRY_POS)
3518e705c121SKalle Valo #define BT_UART_MSG_FRAME7CONNECTABLE_POS	(5)
3519e705c121SKalle Valo #define BT_UART_MSG_FRAME7CONNECTABLE_MSK	\
3520e705c121SKalle Valo 		(0x1 << BT_UART_MSG_FRAME7CONNECTABLE_POS)
3521e705c121SKalle Valo #define BT_UART_MSG_FRAME7RESERVED_POS		(6)
3522e705c121SKalle Valo #define BT_UART_MSG_FRAME7RESERVED_MSK		\
3523e705c121SKalle Valo 		(0x3 << BT_UART_MSG_FRAME7RESERVED_POS)
3524e705c121SKalle Valo 
3525e705c121SKalle Valo /* BT Session Activity 2 UART message (BT -> WiFi) */
3526e705c121SKalle Valo #define BT_UART_MSG_2_FRAME1RESERVED1_POS	(5)
3527e705c121SKalle Valo #define BT_UART_MSG_2_FRAME1RESERVED1_MSK	\
3528e705c121SKalle Valo 		(0x1<<BT_UART_MSG_2_FRAME1RESERVED1_POS)
3529e705c121SKalle Valo #define BT_UART_MSG_2_FRAME1RESERVED2_POS	(6)
3530e705c121SKalle Valo #define BT_UART_MSG_2_FRAME1RESERVED2_MSK	\
3531e705c121SKalle Valo 		(0x3<<BT_UART_MSG_2_FRAME1RESERVED2_POS)
3532e705c121SKalle Valo 
3533e705c121SKalle Valo #define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS	(0)
3534e705c121SKalle Valo #define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_MSK	\
3535e705c121SKalle Valo 		(0x3F<<BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS)
3536e705c121SKalle Valo #define BT_UART_MSG_2_FRAME2RESERVED_POS	(6)
3537e705c121SKalle Valo #define BT_UART_MSG_2_FRAME2RESERVED_MSK	\
3538e705c121SKalle Valo 		(0x3<<BT_UART_MSG_2_FRAME2RESERVED_POS)
3539e705c121SKalle Valo 
3540e705c121SKalle Valo #define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS	(0)
3541e705c121SKalle Valo #define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_MSK	\
3542e705c121SKalle Valo 		(0xF<<BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS)
3543e705c121SKalle Valo #define BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS	(4)
3544e705c121SKalle Valo #define BT_UART_MSG_2_FRAME3INQPAGESRMODE_MSK	\
3545e705c121SKalle Valo 		(0x1<<BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS)
3546e705c121SKalle Valo #define BT_UART_MSG_2_FRAME3LEMASTER_POS	(5)
3547e705c121SKalle Valo #define BT_UART_MSG_2_FRAME3LEMASTER_MSK	\
3548e705c121SKalle Valo 		(0x1<<BT_UART_MSG_2_FRAME3LEMASTER_POS)
3549e705c121SKalle Valo #define BT_UART_MSG_2_FRAME3RESERVED_POS	(6)
3550e705c121SKalle Valo #define BT_UART_MSG_2_FRAME3RESERVED_MSK	\
3551e705c121SKalle Valo 		(0x3<<BT_UART_MSG_2_FRAME3RESERVED_POS)
3552e705c121SKalle Valo 
3553e705c121SKalle Valo #define BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS	(0)
3554e705c121SKalle Valo #define BT_UART_MSG_2_FRAME4LELASTTXPOWER_MSK	\
3555e705c121SKalle Valo 		(0xF<<BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS)
3556e705c121SKalle Valo #define BT_UART_MSG_2_FRAME4NUMLECONN_POS	(4)
3557e705c121SKalle Valo #define BT_UART_MSG_2_FRAME4NUMLECONN_MSK	\
3558e705c121SKalle Valo 		(0x3<<BT_UART_MSG_2_FRAME4NUMLECONN_POS)
3559e705c121SKalle Valo #define BT_UART_MSG_2_FRAME4RESERVED_POS	(6)
3560e705c121SKalle Valo #define BT_UART_MSG_2_FRAME4RESERVED_MSK	\
3561e705c121SKalle Valo 		(0x3<<BT_UART_MSG_2_FRAME4RESERVED_POS)
3562e705c121SKalle Valo 
3563e705c121SKalle Valo #define BT_UART_MSG_2_FRAME5BTMINRSSI_POS	(0)
3564e705c121SKalle Valo #define BT_UART_MSG_2_FRAME5BTMINRSSI_MSK	\
3565e705c121SKalle Valo 		(0xF<<BT_UART_MSG_2_FRAME5BTMINRSSI_POS)
3566e705c121SKalle Valo #define BT_UART_MSG_2_FRAME5LESCANINITMODE_POS	(4)
3567e705c121SKalle Valo #define BT_UART_MSG_2_FRAME5LESCANINITMODE_MSK	\
3568e705c121SKalle Valo 		(0x1<<BT_UART_MSG_2_FRAME5LESCANINITMODE_POS)
3569e705c121SKalle Valo #define BT_UART_MSG_2_FRAME5LEADVERMODE_POS	(5)
3570e705c121SKalle Valo #define BT_UART_MSG_2_FRAME5LEADVERMODE_MSK	\
3571e705c121SKalle Valo 		(0x1<<BT_UART_MSG_2_FRAME5LEADVERMODE_POS)
3572e705c121SKalle Valo #define BT_UART_MSG_2_FRAME5RESERVED_POS	(6)
3573e705c121SKalle Valo #define BT_UART_MSG_2_FRAME5RESERVED_MSK	\
3574e705c121SKalle Valo 		(0x3<<BT_UART_MSG_2_FRAME5RESERVED_POS)
3575e705c121SKalle Valo 
3576e705c121SKalle Valo #define BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS	(0)
3577e705c121SKalle Valo #define BT_UART_MSG_2_FRAME6LECONNINTERVAL_MSK	\
3578e705c121SKalle Valo 		(0x1F<<BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS)
3579e705c121SKalle Valo #define BT_UART_MSG_2_FRAME6RFU_POS		(5)
3580e705c121SKalle Valo #define BT_UART_MSG_2_FRAME6RFU_MSK		\
3581e705c121SKalle Valo 		(0x1<<BT_UART_MSG_2_FRAME6RFU_POS)
3582e705c121SKalle Valo #define BT_UART_MSG_2_FRAME6RESERVED_POS	(6)
3583e705c121SKalle Valo #define BT_UART_MSG_2_FRAME6RESERVED_MSK	\
3584e705c121SKalle Valo 		(0x3<<BT_UART_MSG_2_FRAME6RESERVED_POS)
3585e705c121SKalle Valo 
3586e705c121SKalle Valo #define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS	(0)
3587e705c121SKalle Valo #define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_MSK	\
3588e705c121SKalle Valo 		(0x7<<BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS)
3589e705c121SKalle Valo #define BT_UART_MSG_2_FRAME7LEPROFILE1_POS	(3)
3590e705c121SKalle Valo #define BT_UART_MSG_2_FRAME7LEPROFILE1_MSK	\
3591e705c121SKalle Valo 		(0x1<<BT_UART_MSG_2_FRAME7LEPROFILE1_POS)
3592e705c121SKalle Valo #define BT_UART_MSG_2_FRAME7LEPROFILE2_POS	(4)
3593e705c121SKalle Valo #define BT_UART_MSG_2_FRAME7LEPROFILE2_MSK	\
3594e705c121SKalle Valo 		(0x1<<BT_UART_MSG_2_FRAME7LEPROFILE2_POS)
3595e705c121SKalle Valo #define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS	(5)
3596e705c121SKalle Valo #define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_MSK	\
3597e705c121SKalle Valo 		(0x1<<BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS)
3598e705c121SKalle Valo #define BT_UART_MSG_2_FRAME7RESERVED_POS	(6)
3599e705c121SKalle Valo #define BT_UART_MSG_2_FRAME7RESERVED_MSK	\
3600e705c121SKalle Valo 		(0x3<<BT_UART_MSG_2_FRAME7RESERVED_POS)
3601e705c121SKalle Valo 
3602e705c121SKalle Valo 
3603e705c121SKalle Valo #define BT_ENABLE_REDUCED_TXPOWER_THRESHOLD	(-62)
3604e705c121SKalle Valo #define BT_DISABLE_REDUCED_TXPOWER_THRESHOLD	(-65)
3605e705c121SKalle Valo 
3606e705c121SKalle Valo struct iwl_bt_uart_msg {
3607e705c121SKalle Valo 	u8 header;
3608e705c121SKalle Valo 	u8 frame1;
3609e705c121SKalle Valo 	u8 frame2;
3610e705c121SKalle Valo 	u8 frame3;
3611e705c121SKalle Valo 	u8 frame4;
3612e705c121SKalle Valo 	u8 frame5;
3613e705c121SKalle Valo 	u8 frame6;
3614e705c121SKalle Valo 	u8 frame7;
3615e705c121SKalle Valo } __packed;
3616e705c121SKalle Valo 
3617e705c121SKalle Valo struct iwl_bt_coex_profile_notif {
3618e705c121SKalle Valo 	struct iwl_bt_uart_msg last_bt_uart_msg;
3619e705c121SKalle Valo 	u8 bt_status; /* 0 - off, 1 - on */
3620e705c121SKalle Valo 	u8 bt_traffic_load; /* 0 .. 3? */
3621e705c121SKalle Valo 	u8 bt_ci_compliance; /* 0 - not complied, 1 - complied */
3622e705c121SKalle Valo 	u8 reserved;
3623e705c121SKalle Valo } __packed;
3624e705c121SKalle Valo 
3625e705c121SKalle Valo #define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS	0
3626e705c121SKalle Valo #define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_MSK	0x1
3627e705c121SKalle Valo #define IWL_BT_COEX_PRIO_TBL_PRIO_POS		1
3628e705c121SKalle Valo #define IWL_BT_COEX_PRIO_TBL_PRIO_MASK		0x0e
3629e705c121SKalle Valo #define IWL_BT_COEX_PRIO_TBL_RESERVED_POS	4
3630e705c121SKalle Valo #define IWL_BT_COEX_PRIO_TBL_RESERVED_MASK	0xf0
3631e705c121SKalle Valo #define IWL_BT_COEX_PRIO_TBL_PRIO_SHIFT		1
3632e705c121SKalle Valo 
3633e705c121SKalle Valo /*
3634e705c121SKalle Valo  * BT Coexistence Priority table
3635e705c121SKalle Valo  * REPLY_BT_COEX_PRIO_TABLE = 0xcc
3636e705c121SKalle Valo  */
3637e705c121SKalle Valo enum bt_coex_prio_table_events {
3638e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_INIT_CALIB1 = 0,
3639e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_INIT_CALIB2 = 1,
3640e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW1 = 2,
3641e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW2 = 3, /* DC calib */
3642e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH1 = 4,
3643e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH2 = 5,
3644e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_DTIM = 6,
3645e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_SCAN52 = 7,
3646e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_SCAN24 = 8,
3647e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_RESERVED0 = 9,
3648e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_RESERVED1 = 10,
3649e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_RESERVED2 = 11,
3650e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_RESERVED3 = 12,
3651e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_RESERVED4 = 13,
3652e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_RESERVED5 = 14,
3653e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_RESERVED6 = 15,
3654e705c121SKalle Valo 	/* BT_COEX_PRIO_TBL_EVT_MAX should always be last */
3655e705c121SKalle Valo 	BT_COEX_PRIO_TBL_EVT_MAX,
3656e705c121SKalle Valo };
3657e705c121SKalle Valo 
3658e705c121SKalle Valo enum bt_coex_prio_table_priorities {
3659e705c121SKalle Valo 	BT_COEX_PRIO_TBL_DISABLED = 0,
3660e705c121SKalle Valo 	BT_COEX_PRIO_TBL_PRIO_LOW = 1,
3661e705c121SKalle Valo 	BT_COEX_PRIO_TBL_PRIO_HIGH = 2,
3662e705c121SKalle Valo 	BT_COEX_PRIO_TBL_PRIO_BYPASS = 3,
3663e705c121SKalle Valo 	BT_COEX_PRIO_TBL_PRIO_COEX_OFF = 4,
3664e705c121SKalle Valo 	BT_COEX_PRIO_TBL_PRIO_COEX_ON = 5,
3665e705c121SKalle Valo 	BT_COEX_PRIO_TBL_PRIO_RSRVD1 = 6,
3666e705c121SKalle Valo 	BT_COEX_PRIO_TBL_PRIO_RSRVD2 = 7,
3667e705c121SKalle Valo 	BT_COEX_PRIO_TBL_MAX,
3668e705c121SKalle Valo };
3669e705c121SKalle Valo 
3670e705c121SKalle Valo struct iwl_bt_coex_prio_table_cmd {
3671e705c121SKalle Valo 	u8 prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX];
3672e705c121SKalle Valo } __packed;
3673e705c121SKalle Valo 
3674e705c121SKalle Valo #define IWL_BT_COEX_ENV_CLOSE	0
3675e705c121SKalle Valo #define IWL_BT_COEX_ENV_OPEN	1
3676e705c121SKalle Valo /*
3677e705c121SKalle Valo  * BT Protection Envelope
3678e705c121SKalle Valo  * REPLY_BT_COEX_PROT_ENV = 0xcd
3679e705c121SKalle Valo  */
3680e705c121SKalle Valo struct iwl_bt_coex_prot_env_cmd {
3681e705c121SKalle Valo 	u8 action; /* 0 = closed, 1 = open */
3682e705c121SKalle Valo 	u8 type; /* 0 .. 15 */
3683e705c121SKalle Valo 	u8 reserved[2];
3684e705c121SKalle Valo } __packed;
3685e705c121SKalle Valo 
3686e705c121SKalle Valo /*
3687e705c121SKalle Valo  * REPLY_D3_CONFIG
3688e705c121SKalle Valo  */
3689e705c121SKalle Valo enum iwlagn_d3_wakeup_filters {
3690e705c121SKalle Valo 	IWLAGN_D3_WAKEUP_RFKILL		= BIT(0),
3691e705c121SKalle Valo 	IWLAGN_D3_WAKEUP_SYSASSERT	= BIT(1),
3692e705c121SKalle Valo };
3693e705c121SKalle Valo 
3694e705c121SKalle Valo struct iwlagn_d3_config_cmd {
3695e705c121SKalle Valo 	__le32 min_sleep_time;
3696e705c121SKalle Valo 	__le32 wakeup_flags;
3697e705c121SKalle Valo } __packed;
3698e705c121SKalle Valo 
3699e705c121SKalle Valo /*
3700e705c121SKalle Valo  * REPLY_WOWLAN_PATTERNS
3701e705c121SKalle Valo  */
3702e705c121SKalle Valo #define IWLAGN_WOWLAN_MIN_PATTERN_LEN	16
3703e705c121SKalle Valo #define IWLAGN_WOWLAN_MAX_PATTERN_LEN	128
3704e705c121SKalle Valo 
3705e705c121SKalle Valo struct iwlagn_wowlan_pattern {
3706e705c121SKalle Valo 	u8 mask[IWLAGN_WOWLAN_MAX_PATTERN_LEN / 8];
3707e705c121SKalle Valo 	u8 pattern[IWLAGN_WOWLAN_MAX_PATTERN_LEN];
3708e705c121SKalle Valo 	u8 mask_size;
3709e705c121SKalle Valo 	u8 pattern_size;
3710e705c121SKalle Valo 	__le16 reserved;
3711e705c121SKalle Valo } __packed;
3712e705c121SKalle Valo 
3713e705c121SKalle Valo #define IWLAGN_WOWLAN_MAX_PATTERNS	20
3714e705c121SKalle Valo 
3715e705c121SKalle Valo struct iwlagn_wowlan_patterns_cmd {
3716e705c121SKalle Valo 	__le32 n_patterns;
3717e705c121SKalle Valo 	struct iwlagn_wowlan_pattern patterns[];
3718e705c121SKalle Valo } __packed;
3719e705c121SKalle Valo 
3720e705c121SKalle Valo /*
3721e705c121SKalle Valo  * REPLY_WOWLAN_WAKEUP_FILTER
3722e705c121SKalle Valo  */
3723e705c121SKalle Valo enum iwlagn_wowlan_wakeup_filters {
3724e705c121SKalle Valo 	IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET	= BIT(0),
3725e705c121SKalle Valo 	IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH	= BIT(1),
3726e705c121SKalle Valo 	IWLAGN_WOWLAN_WAKEUP_BEACON_MISS	= BIT(2),
3727e705c121SKalle Valo 	IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE	= BIT(3),
3728e705c121SKalle Valo 	IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL	= BIT(4),
3729e705c121SKalle Valo 	IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ	= BIT(5),
3730e705c121SKalle Valo 	IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE	= BIT(6),
3731e705c121SKalle Valo 	IWLAGN_WOWLAN_WAKEUP_ALWAYS		= BIT(7),
3732e705c121SKalle Valo 	IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT	= BIT(8),
3733e705c121SKalle Valo };
3734e705c121SKalle Valo 
3735e705c121SKalle Valo struct iwlagn_wowlan_wakeup_filter_cmd {
3736e705c121SKalle Valo 	__le32 enabled;
3737e705c121SKalle Valo 	__le16 non_qos_seq;
3738e705c121SKalle Valo 	__le16 reserved;
3739e705c121SKalle Valo 	__le16 qos_seq[8];
3740e705c121SKalle Valo };
3741e705c121SKalle Valo 
3742e705c121SKalle Valo /*
3743e705c121SKalle Valo  * REPLY_WOWLAN_TSC_RSC_PARAMS
3744e705c121SKalle Valo  */
3745e705c121SKalle Valo #define IWLAGN_NUM_RSC	16
3746e705c121SKalle Valo 
3747e705c121SKalle Valo struct tkip_sc {
3748e705c121SKalle Valo 	__le16 iv16;
3749e705c121SKalle Valo 	__le16 pad;
3750e705c121SKalle Valo 	__le32 iv32;
3751e705c121SKalle Valo } __packed;
3752e705c121SKalle Valo 
3753e705c121SKalle Valo struct iwlagn_tkip_rsc_tsc {
3754e705c121SKalle Valo 	struct tkip_sc unicast_rsc[IWLAGN_NUM_RSC];
3755e705c121SKalle Valo 	struct tkip_sc multicast_rsc[IWLAGN_NUM_RSC];
3756e705c121SKalle Valo 	struct tkip_sc tsc;
3757e705c121SKalle Valo } __packed;
3758e705c121SKalle Valo 
3759e705c121SKalle Valo struct aes_sc {
3760e705c121SKalle Valo 	__le64 pn;
3761e705c121SKalle Valo } __packed;
3762e705c121SKalle Valo 
3763e705c121SKalle Valo struct iwlagn_aes_rsc_tsc {
3764e705c121SKalle Valo 	struct aes_sc unicast_rsc[IWLAGN_NUM_RSC];
3765e705c121SKalle Valo 	struct aes_sc multicast_rsc[IWLAGN_NUM_RSC];
3766e705c121SKalle Valo 	struct aes_sc tsc;
3767e705c121SKalle Valo } __packed;
3768e705c121SKalle Valo 
3769e705c121SKalle Valo union iwlagn_all_tsc_rsc {
3770e705c121SKalle Valo 	struct iwlagn_tkip_rsc_tsc tkip;
3771e705c121SKalle Valo 	struct iwlagn_aes_rsc_tsc aes;
3772e705c121SKalle Valo };
3773e705c121SKalle Valo 
3774e705c121SKalle Valo struct iwlagn_wowlan_rsc_tsc_params_cmd {
3775e705c121SKalle Valo 	union iwlagn_all_tsc_rsc all_tsc_rsc;
3776e705c121SKalle Valo } __packed;
3777e705c121SKalle Valo 
3778e705c121SKalle Valo /*
3779e705c121SKalle Valo  * REPLY_WOWLAN_TKIP_PARAMS
3780e705c121SKalle Valo  */
3781e705c121SKalle Valo #define IWLAGN_MIC_KEY_SIZE	8
3782e705c121SKalle Valo #define IWLAGN_P1K_SIZE		5
3783e705c121SKalle Valo struct iwlagn_mic_keys {
3784e705c121SKalle Valo 	u8 tx[IWLAGN_MIC_KEY_SIZE];
3785e705c121SKalle Valo 	u8 rx_unicast[IWLAGN_MIC_KEY_SIZE];
3786e705c121SKalle Valo 	u8 rx_mcast[IWLAGN_MIC_KEY_SIZE];
3787e705c121SKalle Valo } __packed;
3788e705c121SKalle Valo 
3789e705c121SKalle Valo struct iwlagn_p1k_cache {
3790e705c121SKalle Valo 	__le16 p1k[IWLAGN_P1K_SIZE];
3791e705c121SKalle Valo } __packed;
3792e705c121SKalle Valo 
3793e705c121SKalle Valo #define IWLAGN_NUM_RX_P1K_CACHE	2
3794e705c121SKalle Valo 
3795e705c121SKalle Valo struct iwlagn_wowlan_tkip_params_cmd {
3796e705c121SKalle Valo 	struct iwlagn_mic_keys mic_keys;
3797e705c121SKalle Valo 	struct iwlagn_p1k_cache tx;
3798e705c121SKalle Valo 	struct iwlagn_p1k_cache rx_uni[IWLAGN_NUM_RX_P1K_CACHE];
3799e705c121SKalle Valo 	struct iwlagn_p1k_cache rx_multi[IWLAGN_NUM_RX_P1K_CACHE];
3800e705c121SKalle Valo } __packed;
3801e705c121SKalle Valo 
3802e705c121SKalle Valo /*
3803e705c121SKalle Valo  * REPLY_WOWLAN_KEK_KCK_MATERIAL
3804e705c121SKalle Valo  */
3805e705c121SKalle Valo 
3806e705c121SKalle Valo #define IWLAGN_KCK_MAX_SIZE	32
3807e705c121SKalle Valo #define IWLAGN_KEK_MAX_SIZE	32
3808e705c121SKalle Valo 
3809e705c121SKalle Valo struct iwlagn_wowlan_kek_kck_material_cmd {
3810e705c121SKalle Valo 	u8	kck[IWLAGN_KCK_MAX_SIZE];
3811e705c121SKalle Valo 	u8	kek[IWLAGN_KEK_MAX_SIZE];
3812e705c121SKalle Valo 	__le16	kck_len;
3813e705c121SKalle Valo 	__le16	kek_len;
3814e705c121SKalle Valo 	__le64	replay_ctr;
3815e705c121SKalle Valo } __packed;
3816e705c121SKalle Valo 
3817e705c121SKalle Valo #define RF_KILL_INDICATOR_FOR_WOWLAN	0x87
3818e705c121SKalle Valo 
3819e705c121SKalle Valo /*
3820e705c121SKalle Valo  * REPLY_WOWLAN_GET_STATUS = 0xe5
3821e705c121SKalle Valo  */
3822e705c121SKalle Valo struct iwlagn_wowlan_status {
3823e705c121SKalle Valo 	__le64 replay_ctr;
3824e705c121SKalle Valo 	__le32 rekey_status;
3825e705c121SKalle Valo 	__le32 wakeup_reason;
3826e705c121SKalle Valo 	u8 pattern_number;
3827e705c121SKalle Valo 	u8 reserved1;
3828e705c121SKalle Valo 	__le16 qos_seq_ctr[8];
3829e705c121SKalle Valo 	__le16 non_qos_seq_ctr;
3830e705c121SKalle Valo 	__le16 reserved2;
3831e705c121SKalle Valo 	union iwlagn_all_tsc_rsc tsc_rsc;
3832e705c121SKalle Valo 	__le16 reserved3;
3833e705c121SKalle Valo } __packed;
3834e705c121SKalle Valo 
3835e705c121SKalle Valo /*
3836e705c121SKalle Valo  * REPLY_WIPAN_PARAMS = 0xb2 (Commands and Notification)
3837e705c121SKalle Valo  */
3838e705c121SKalle Valo 
3839e705c121SKalle Valo /*
3840e705c121SKalle Valo  * Minimum slot time in TU
3841e705c121SKalle Valo  */
3842e705c121SKalle Valo #define IWL_MIN_SLOT_TIME	20
3843e705c121SKalle Valo 
3844e705c121SKalle Valo /**
3845e705c121SKalle Valo  * struct iwl_wipan_slot
3846e705c121SKalle Valo  * @width: Time in TU
3847e705c121SKalle Valo  * @type:
3848e705c121SKalle Valo  *   0 - BSS
3849e705c121SKalle Valo  *   1 - PAN
3850e705c121SKalle Valo  */
3851e705c121SKalle Valo struct iwl_wipan_slot {
3852e705c121SKalle Valo 	__le16 width;
3853e705c121SKalle Valo 	u8 type;
3854e705c121SKalle Valo 	u8 reserved;
3855e705c121SKalle Valo } __packed;
3856e705c121SKalle Valo 
3857e705c121SKalle Valo #define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS		BIT(1)	/* reserved */
3858e705c121SKalle Valo #define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET	BIT(2)	/* reserved */
3859e705c121SKalle Valo #define IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE		BIT(3)	/* reserved */
3860e705c121SKalle Valo #define IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF	BIT(4)
3861e705c121SKalle Valo #define IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE		BIT(5)
3862e705c121SKalle Valo 
3863e705c121SKalle Valo /**
3864e705c121SKalle Valo  * struct iwl_wipan_params_cmd
3865e705c121SKalle Valo  * @flags:
3866e705c121SKalle Valo  *   bit0: reserved
3867e705c121SKalle Valo  *   bit1: CP leave channel with CTS
3868e705c121SKalle Valo  *   bit2: CP leave channel qith Quiet
3869e705c121SKalle Valo  *   bit3: slotted mode
3870e705c121SKalle Valo  *     1 - work in slotted mode
3871e705c121SKalle Valo  *     0 - work in non slotted mode
3872e705c121SKalle Valo  *   bit4: filter beacon notification
3873e705c121SKalle Valo  *   bit5: full tx slotted mode. if this flag is set,
3874e705c121SKalle Valo  *         uCode will perform leaving channel methods in context switch
3875e705c121SKalle Valo  *         also when working in same channel mode
3876e705c121SKalle Valo  * @num_slots: 1 - 10
3877e705c121SKalle Valo  */
3878e705c121SKalle Valo struct iwl_wipan_params_cmd {
3879e705c121SKalle Valo 	__le16 flags;
3880e705c121SKalle Valo 	u8 reserved;
3881e705c121SKalle Valo 	u8 num_slots;
3882e705c121SKalle Valo 	struct iwl_wipan_slot slots[10];
3883e705c121SKalle Valo } __packed;
3884e705c121SKalle Valo 
3885e705c121SKalle Valo /*
3886e705c121SKalle Valo  * REPLY_WIPAN_P2P_CHANNEL_SWITCH = 0xb9
3887e705c121SKalle Valo  *
3888e705c121SKalle Valo  * TODO: Figure out what this is used for,
3889e705c121SKalle Valo  *	 it can only switch between 2.4 GHz
3890e705c121SKalle Valo  *	 channels!!
3891e705c121SKalle Valo  */
3892e705c121SKalle Valo 
3893e705c121SKalle Valo struct iwl_wipan_p2p_channel_switch_cmd {
3894e705c121SKalle Valo 	__le16 channel;
3895e705c121SKalle Valo 	__le16 reserved;
3896e705c121SKalle Valo };
3897e705c121SKalle Valo 
3898e705c121SKalle Valo /*
3899e705c121SKalle Valo  * REPLY_WIPAN_NOA_NOTIFICATION = 0xbc
3900e705c121SKalle Valo  *
3901e705c121SKalle Valo  * This is used by the device to notify us of the
3902e705c121SKalle Valo  * NoA schedule it determined so we can forward it
3903e705c121SKalle Valo  * to userspace for inclusion in probe responses.
3904e705c121SKalle Valo  *
3905e705c121SKalle Valo  * In beacons, the NoA schedule is simply appended
3906e705c121SKalle Valo  * to the frame we give the device.
3907e705c121SKalle Valo  */
3908e705c121SKalle Valo 
3909e705c121SKalle Valo struct iwl_wipan_noa_descriptor {
3910e705c121SKalle Valo 	u8 count;
3911e705c121SKalle Valo 	__le32 duration;
3912e705c121SKalle Valo 	__le32 interval;
3913e705c121SKalle Valo 	__le32 starttime;
3914e705c121SKalle Valo } __packed;
3915e705c121SKalle Valo 
3916e705c121SKalle Valo struct iwl_wipan_noa_attribute {
3917e705c121SKalle Valo 	u8 id;
3918e705c121SKalle Valo 	__le16 length;
3919e705c121SKalle Valo 	u8 index;
3920e705c121SKalle Valo 	u8 ct_window;
3921e705c121SKalle Valo 	struct iwl_wipan_noa_descriptor descr0, descr1;
3922e705c121SKalle Valo 	u8 reserved;
3923e705c121SKalle Valo } __packed;
3924e705c121SKalle Valo 
3925e705c121SKalle Valo struct iwl_wipan_noa_notification {
3926e705c121SKalle Valo 	u32 noa_active;
3927e705c121SKalle Valo 	struct iwl_wipan_noa_attribute noa_attribute;
3928e705c121SKalle Valo } __packed;
3929e705c121SKalle Valo 
3930e705c121SKalle Valo #endif				/* __iwl_commands_h__ */
3931