xref: /openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/rate.c (revision 9938b04472d5c59f8bd8152a548533a8599596a2)
1*05491d2cSKalle Valo /*
2*05491d2cSKalle Valo  * Copyright (c) 2010 Broadcom Corporation
3*05491d2cSKalle Valo  *
4*05491d2cSKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
5*05491d2cSKalle Valo  * purpose with or without fee is hereby granted, provided that the above
6*05491d2cSKalle Valo  * copyright notice and this permission notice appear in all copies.
7*05491d2cSKalle Valo  *
8*05491d2cSKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*05491d2cSKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*05491d2cSKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11*05491d2cSKalle Valo  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*05491d2cSKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13*05491d2cSKalle Valo  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14*05491d2cSKalle Valo  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*05491d2cSKalle Valo  */
16*05491d2cSKalle Valo 
17*05491d2cSKalle Valo #include <brcmu_wifi.h>
18*05491d2cSKalle Valo #include <brcmu_utils.h>
19*05491d2cSKalle Valo 
20*05491d2cSKalle Valo #include "d11.h"
21*05491d2cSKalle Valo #include "pub.h"
22*05491d2cSKalle Valo #include "rate.h"
23*05491d2cSKalle Valo 
24*05491d2cSKalle Valo /*
25*05491d2cSKalle Valo  * Rate info per rate: It tells whether a rate is ofdm or not and its phy_rate
26*05491d2cSKalle Valo  * value
27*05491d2cSKalle Valo  */
28*05491d2cSKalle Valo const u8 rate_info[BRCM_MAXRATE + 1] = {
29*05491d2cSKalle Valo 	/*  0     1     2     3     4     5     6     7     8     9 */
30*05491d2cSKalle Valo /*   0 */ 0x00, 0x00, 0x0a, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
31*05491d2cSKalle Valo /*  10 */ 0x00, 0x37, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x00,
32*05491d2cSKalle Valo /*  20 */ 0x00, 0x00, 0x6e, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x00, 0x00,
33*05491d2cSKalle Valo /*  30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00, 0x00, 0x00,
34*05491d2cSKalle Valo /*  40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x00,
35*05491d2cSKalle Valo /*  50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
36*05491d2cSKalle Valo /*  60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
37*05491d2cSKalle Valo /*  70 */ 0x00, 0x00, 0x8d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
38*05491d2cSKalle Valo /*  80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
39*05491d2cSKalle Valo /*  90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00,
40*05491d2cSKalle Valo /* 100 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8c
41*05491d2cSKalle Valo };
42*05491d2cSKalle Valo 
43*05491d2cSKalle Valo /* rates are in units of Kbps */
44*05491d2cSKalle Valo const struct brcms_mcs_info mcs_table[MCS_TABLE_SIZE] = {
45*05491d2cSKalle Valo 	/* MCS  0: SS 1, MOD: BPSK,  CR 1/2 */
46*05491d2cSKalle Valo 	{6500, 13500, CEIL(6500 * 10, 9), CEIL(13500 * 10, 9), 0x00,
47*05491d2cSKalle Valo 	 BRCM_RATE_6M},
48*05491d2cSKalle Valo 	/* MCS  1: SS 1, MOD: QPSK,  CR 1/2 */
49*05491d2cSKalle Valo 	{13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x08,
50*05491d2cSKalle Valo 	 BRCM_RATE_12M},
51*05491d2cSKalle Valo 	/* MCS  2: SS 1, MOD: QPSK,  CR 3/4 */
52*05491d2cSKalle Valo 	{19500, 40500, CEIL(19500 * 10, 9), CEIL(40500 * 10, 9), 0x0A,
53*05491d2cSKalle Valo 	 BRCM_RATE_18M},
54*05491d2cSKalle Valo 	/* MCS  3: SS 1, MOD: 16QAM, CR 1/2 */
55*05491d2cSKalle Valo 	{26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x10,
56*05491d2cSKalle Valo 	 BRCM_RATE_24M},
57*05491d2cSKalle Valo 	/* MCS  4: SS 1, MOD: 16QAM, CR 3/4 */
58*05491d2cSKalle Valo 	{39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x12,
59*05491d2cSKalle Valo 	 BRCM_RATE_36M},
60*05491d2cSKalle Valo 	/* MCS  5: SS 1, MOD: 64QAM, CR 2/3 */
61*05491d2cSKalle Valo 	{52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0x19,
62*05491d2cSKalle Valo 	 BRCM_RATE_48M},
63*05491d2cSKalle Valo 	/* MCS  6: SS 1, MOD: 64QAM, CR 3/4 */
64*05491d2cSKalle Valo 	{58500, 121500, CEIL(58500 * 10, 9), CEIL(121500 * 10, 9), 0x1A,
65*05491d2cSKalle Valo 	 BRCM_RATE_54M},
66*05491d2cSKalle Valo 	/* MCS  7: SS 1, MOD: 64QAM, CR 5/6 */
67*05491d2cSKalle Valo 	{65000, 135000, CEIL(65000 * 10, 9), CEIL(135000 * 10, 9), 0x1C,
68*05491d2cSKalle Valo 	 BRCM_RATE_54M},
69*05491d2cSKalle Valo 	/* MCS  8: SS 2, MOD: BPSK,  CR 1/2 */
70*05491d2cSKalle Valo 	{13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x40,
71*05491d2cSKalle Valo 	 BRCM_RATE_6M},
72*05491d2cSKalle Valo 	/* MCS  9: SS 2, MOD: QPSK,  CR 1/2 */
73*05491d2cSKalle Valo 	{26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x48,
74*05491d2cSKalle Valo 	 BRCM_RATE_12M},
75*05491d2cSKalle Valo 	/* MCS 10: SS 2, MOD: QPSK,  CR 3/4 */
76*05491d2cSKalle Valo 	{39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x4A,
77*05491d2cSKalle Valo 	 BRCM_RATE_18M},
78*05491d2cSKalle Valo 	/* MCS 11: SS 2, MOD: 16QAM, CR 1/2 */
79*05491d2cSKalle Valo 	{52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0x50,
80*05491d2cSKalle Valo 	 BRCM_RATE_24M},
81*05491d2cSKalle Valo 	/* MCS 12: SS 2, MOD: 16QAM, CR 3/4 */
82*05491d2cSKalle Valo 	{78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0x52,
83*05491d2cSKalle Valo 	 BRCM_RATE_36M},
84*05491d2cSKalle Valo 	/* MCS 13: SS 2, MOD: 64QAM, CR 2/3 */
85*05491d2cSKalle Valo 	{104000, 216000, CEIL(104000 * 10, 9), CEIL(216000 * 10, 9), 0x59,
86*05491d2cSKalle Valo 	 BRCM_RATE_48M},
87*05491d2cSKalle Valo 	/* MCS 14: SS 2, MOD: 64QAM, CR 3/4 */
88*05491d2cSKalle Valo 	{117000, 243000, CEIL(117000 * 10, 9), CEIL(243000 * 10, 9), 0x5A,
89*05491d2cSKalle Valo 	 BRCM_RATE_54M},
90*05491d2cSKalle Valo 	/* MCS 15: SS 2, MOD: 64QAM, CR 5/6 */
91*05491d2cSKalle Valo 	{130000, 270000, CEIL(130000 * 10, 9), CEIL(270000 * 10, 9), 0x5C,
92*05491d2cSKalle Valo 	 BRCM_RATE_54M},
93*05491d2cSKalle Valo 	/* MCS 16: SS 3, MOD: BPSK,  CR 1/2 */
94*05491d2cSKalle Valo 	{19500, 40500, CEIL(19500 * 10, 9), CEIL(40500 * 10, 9), 0x80,
95*05491d2cSKalle Valo 	 BRCM_RATE_6M},
96*05491d2cSKalle Valo 	/* MCS 17: SS 3, MOD: QPSK,  CR 1/2 */
97*05491d2cSKalle Valo 	{39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x88,
98*05491d2cSKalle Valo 	 BRCM_RATE_12M},
99*05491d2cSKalle Valo 	/* MCS 18: SS 3, MOD: QPSK,  CR 3/4 */
100*05491d2cSKalle Valo 	{58500, 121500, CEIL(58500 * 10, 9), CEIL(121500 * 10, 9), 0x8A,
101*05491d2cSKalle Valo 	 BRCM_RATE_18M},
102*05491d2cSKalle Valo 	/* MCS 19: SS 3, MOD: 16QAM, CR 1/2 */
103*05491d2cSKalle Valo 	{78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0x90,
104*05491d2cSKalle Valo 	 BRCM_RATE_24M},
105*05491d2cSKalle Valo 	/* MCS 20: SS 3, MOD: 16QAM, CR 3/4 */
106*05491d2cSKalle Valo 	{117000, 243000, CEIL(117000 * 10, 9), CEIL(243000 * 10, 9), 0x92,
107*05491d2cSKalle Valo 	 BRCM_RATE_36M},
108*05491d2cSKalle Valo 	/* MCS 21: SS 3, MOD: 64QAM, CR 2/3 */
109*05491d2cSKalle Valo 	{156000, 324000, CEIL(156000 * 10, 9), CEIL(324000 * 10, 9), 0x99,
110*05491d2cSKalle Valo 	 BRCM_RATE_48M},
111*05491d2cSKalle Valo 	/* MCS 22: SS 3, MOD: 64QAM, CR 3/4 */
112*05491d2cSKalle Valo 	{175500, 364500, CEIL(175500 * 10, 9), CEIL(364500 * 10, 9), 0x9A,
113*05491d2cSKalle Valo 	 BRCM_RATE_54M},
114*05491d2cSKalle Valo 	/* MCS 23: SS 3, MOD: 64QAM, CR 5/6 */
115*05491d2cSKalle Valo 	{195000, 405000, CEIL(195000 * 10, 9), CEIL(405000 * 10, 9), 0x9B,
116*05491d2cSKalle Valo 	 BRCM_RATE_54M},
117*05491d2cSKalle Valo 	/* MCS 24: SS 4, MOD: BPSK,  CR 1/2 */
118*05491d2cSKalle Valo 	{26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0xC0,
119*05491d2cSKalle Valo 	 BRCM_RATE_6M},
120*05491d2cSKalle Valo 	/* MCS 25: SS 4, MOD: QPSK,  CR 1/2 */
121*05491d2cSKalle Valo 	{52000, 108000, CEIL(52000 * 10, 9), CEIL(108000 * 10, 9), 0xC8,
122*05491d2cSKalle Valo 	 BRCM_RATE_12M},
123*05491d2cSKalle Valo 	/* MCS 26: SS 4, MOD: QPSK,  CR 3/4 */
124*05491d2cSKalle Valo 	{78000, 162000, CEIL(78000 * 10, 9), CEIL(162000 * 10, 9), 0xCA,
125*05491d2cSKalle Valo 	 BRCM_RATE_18M},
126*05491d2cSKalle Valo 	/* MCS 27: SS 4, MOD: 16QAM, CR 1/2 */
127*05491d2cSKalle Valo 	{104000, 216000, CEIL(104000 * 10, 9), CEIL(216000 * 10, 9), 0xD0,
128*05491d2cSKalle Valo 	 BRCM_RATE_24M},
129*05491d2cSKalle Valo 	/* MCS 28: SS 4, MOD: 16QAM, CR 3/4 */
130*05491d2cSKalle Valo 	{156000, 324000, CEIL(156000 * 10, 9), CEIL(324000 * 10, 9), 0xD2,
131*05491d2cSKalle Valo 	 BRCM_RATE_36M},
132*05491d2cSKalle Valo 	/* MCS 29: SS 4, MOD: 64QAM, CR 2/3 */
133*05491d2cSKalle Valo 	{208000, 432000, CEIL(208000 * 10, 9), CEIL(432000 * 10, 9), 0xD9,
134*05491d2cSKalle Valo 	 BRCM_RATE_48M},
135*05491d2cSKalle Valo 	/* MCS 30: SS 4, MOD: 64QAM, CR 3/4 */
136*05491d2cSKalle Valo 	{234000, 486000, CEIL(234000 * 10, 9), CEIL(486000 * 10, 9), 0xDA,
137*05491d2cSKalle Valo 	 BRCM_RATE_54M},
138*05491d2cSKalle Valo 	/* MCS 31: SS 4, MOD: 64QAM, CR 5/6 */
139*05491d2cSKalle Valo 	{260000, 540000, CEIL(260000 * 10, 9), CEIL(540000 * 10, 9), 0xDB,
140*05491d2cSKalle Valo 	 BRCM_RATE_54M},
141*05491d2cSKalle Valo 	/* MCS 32: SS 1, MOD: BPSK,  CR 1/2 */
142*05491d2cSKalle Valo 	{0, 6000, 0, CEIL(6000 * 10, 9), 0x00, BRCM_RATE_6M},
143*05491d2cSKalle Valo };
144*05491d2cSKalle Valo 
145*05491d2cSKalle Valo /*
146*05491d2cSKalle Valo  * phycfg for legacy OFDM frames: code rate, modulation scheme, spatial streams
147*05491d2cSKalle Valo  * Number of spatial streams: always 1 other fields: refer to table 78 of
148*05491d2cSKalle Valo  * section 17.3.2.2 of the original .11a standard
149*05491d2cSKalle Valo  */
150*05491d2cSKalle Valo struct legacy_phycfg {
151*05491d2cSKalle Valo 	u32 rate_ofdm;	/* ofdm mac rate */
152*05491d2cSKalle Valo 	/* phy ctl byte 3, code rate, modulation type, # of streams */
153*05491d2cSKalle Valo 	u8 tx_phy_ctl3;
154*05491d2cSKalle Valo };
155*05491d2cSKalle Valo 
156*05491d2cSKalle Valo /* Number of legacy_rate_cfg entries in the table */
157*05491d2cSKalle Valo #define LEGACY_PHYCFG_TABLE_SIZE	12
158*05491d2cSKalle Valo 
159*05491d2cSKalle Valo /*
160*05491d2cSKalle Valo  * In CCK mode LPPHY overloads OFDM Modulation bits with CCK Data Rate
161*05491d2cSKalle Valo  * Eventually MIMOPHY would also be converted to this format
162*05491d2cSKalle Valo  * 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps
163*05491d2cSKalle Valo  */
164*05491d2cSKalle Valo static const struct
165*05491d2cSKalle Valo legacy_phycfg legacy_phycfg_table[LEGACY_PHYCFG_TABLE_SIZE] = {
166*05491d2cSKalle Valo 	{BRCM_RATE_1M, 0x00},	/* CCK  1Mbps,  data rate  0 */
167*05491d2cSKalle Valo 	{BRCM_RATE_2M, 0x08},	/* CCK  2Mbps,  data rate  1 */
168*05491d2cSKalle Valo 	{BRCM_RATE_5M5, 0x10},	/* CCK  5.5Mbps,  data rate  2 */
169*05491d2cSKalle Valo 	{BRCM_RATE_11M, 0x18},	/* CCK  11Mbps,  data rate   3 */
170*05491d2cSKalle Valo 	/* OFDM  6Mbps,  code rate 1/2, BPSK,   1 spatial stream */
171*05491d2cSKalle Valo 	{BRCM_RATE_6M, 0x00},
172*05491d2cSKalle Valo 	/* OFDM  9Mbps,  code rate 3/4, BPSK,   1 spatial stream */
173*05491d2cSKalle Valo 	{BRCM_RATE_9M, 0x02},
174*05491d2cSKalle Valo 	/* OFDM  12Mbps, code rate 1/2, QPSK,   1 spatial stream */
175*05491d2cSKalle Valo 	{BRCM_RATE_12M, 0x08},
176*05491d2cSKalle Valo 	/* OFDM  18Mbps, code rate 3/4, QPSK,   1 spatial stream */
177*05491d2cSKalle Valo 	{BRCM_RATE_18M, 0x0A},
178*05491d2cSKalle Valo 	/* OFDM  24Mbps, code rate 1/2, 16-QAM, 1 spatial stream */
179*05491d2cSKalle Valo 	{BRCM_RATE_24M, 0x10},
180*05491d2cSKalle Valo 	/* OFDM  36Mbps, code rate 3/4, 16-QAM, 1 spatial stream */
181*05491d2cSKalle Valo 	{BRCM_RATE_36M, 0x12},
182*05491d2cSKalle Valo 	/* OFDM  48Mbps, code rate 2/3, 64-QAM, 1 spatial stream */
183*05491d2cSKalle Valo 	{BRCM_RATE_48M, 0x19},
184*05491d2cSKalle Valo 	/* OFDM  54Mbps, code rate 3/4, 64-QAM, 1 spatial stream */
185*05491d2cSKalle Valo 	{BRCM_RATE_54M, 0x1A},
186*05491d2cSKalle Valo };
187*05491d2cSKalle Valo 
188*05491d2cSKalle Valo /* Hardware rates (also encodes default basic rates) */
189*05491d2cSKalle Valo 
190*05491d2cSKalle Valo const struct brcms_c_rateset cck_ofdm_mimo_rates = {
191*05491d2cSKalle Valo 	12,
192*05491d2cSKalle Valo 	/*  1b,   2b,   5.5b, 6,    9,    11b,  12,   18,   24,   36,   48, */
193*05491d2cSKalle Valo 	{ 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
194*05491d2cSKalle Valo 	/* 54 Mbps */
195*05491d2cSKalle Valo 	  0x6c},
196*05491d2cSKalle Valo 	0x00,
197*05491d2cSKalle Valo 	{ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
198*05491d2cSKalle Valo 	  0x00, 0x00, 0x00, 0x00, 0x00}
199*05491d2cSKalle Valo };
200*05491d2cSKalle Valo 
201*05491d2cSKalle Valo const struct brcms_c_rateset ofdm_mimo_rates = {
202*05491d2cSKalle Valo 	8,
203*05491d2cSKalle Valo 	/*  6b,   9,    12b,  18,   24b,  36,   48,   54 Mbps */
204*05491d2cSKalle Valo 	{ 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
205*05491d2cSKalle Valo 	0x00,
206*05491d2cSKalle Valo 	{ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
207*05491d2cSKalle Valo 	  0x00, 0x00, 0x00, 0x00, 0x00}
208*05491d2cSKalle Valo };
209*05491d2cSKalle Valo 
210*05491d2cSKalle Valo /* Default ratesets that include MCS32 for 40BW channels */
211*05491d2cSKalle Valo static const struct brcms_c_rateset cck_ofdm_40bw_mimo_rates = {
212*05491d2cSKalle Valo 	12,
213*05491d2cSKalle Valo 	/*  1b,   2b,   5.5b, 6,    9,    11b,  12,   18,   24,   36,   48 */
214*05491d2cSKalle Valo 	{ 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
215*05491d2cSKalle Valo 	/* 54 Mbps */
216*05491d2cSKalle Valo 	  0x6c},
217*05491d2cSKalle Valo 	0x00,
218*05491d2cSKalle Valo 	{ 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
219*05491d2cSKalle Valo 	  0x00, 0x00, 0x00, 0x00, 0x00}
220*05491d2cSKalle Valo };
221*05491d2cSKalle Valo 
222*05491d2cSKalle Valo static const struct brcms_c_rateset ofdm_40bw_mimo_rates = {
223*05491d2cSKalle Valo 	8,
224*05491d2cSKalle Valo 	/*  6b,   9,    12b,  18,   24b,  36,   48,   54 Mbps */
225*05491d2cSKalle Valo 	{ 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
226*05491d2cSKalle Valo 	0x00,
227*05491d2cSKalle Valo 	{ 0xff, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
228*05491d2cSKalle Valo 	  0x00, 0x00, 0x00, 0x00, 0x00}
229*05491d2cSKalle Valo };
230*05491d2cSKalle Valo 
231*05491d2cSKalle Valo const struct brcms_c_rateset cck_ofdm_rates = {
232*05491d2cSKalle Valo 	12,
233*05491d2cSKalle Valo 	/*  1b,   2b, 5.5b, 6,    9,    11b,  12,   18,   24,   36,   48,*/
234*05491d2cSKalle Valo 	{ 0x82, 0x84, 0x8b, 0x0c, 0x12, 0x96, 0x18, 0x24, 0x30, 0x48, 0x60,
235*05491d2cSKalle Valo 	/*54 Mbps */
236*05491d2cSKalle Valo 	  0x6c},
237*05491d2cSKalle Valo 	0x00,
238*05491d2cSKalle Valo 	{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
239*05491d2cSKalle Valo 	  0x00, 0x00, 0x00, 0x00, 0x00}
240*05491d2cSKalle Valo };
241*05491d2cSKalle Valo 
242*05491d2cSKalle Valo const struct brcms_c_rateset gphy_legacy_rates = {
243*05491d2cSKalle Valo 	4,
244*05491d2cSKalle Valo 	/*  1b,   2b,   5.5b, 11b Mbps */
245*05491d2cSKalle Valo 	{ 0x82, 0x84, 0x8b, 0x96},
246*05491d2cSKalle Valo 	0x00,
247*05491d2cSKalle Valo 	{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
248*05491d2cSKalle Valo 	  0x00, 0x00, 0x00, 0x00, 0x00}
249*05491d2cSKalle Valo };
250*05491d2cSKalle Valo 
251*05491d2cSKalle Valo const struct brcms_c_rateset ofdm_rates = {
252*05491d2cSKalle Valo 	8,
253*05491d2cSKalle Valo 	/*  6b,   9,    12b,  18,   24b,  36,   48,   54 Mbps */
254*05491d2cSKalle Valo 	{ 0x8c, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6c},
255*05491d2cSKalle Valo 	0x00,
256*05491d2cSKalle Valo 	{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
257*05491d2cSKalle Valo 	  0x00, 0x00, 0x00, 0x00, 0x00}
258*05491d2cSKalle Valo };
259*05491d2cSKalle Valo 
260*05491d2cSKalle Valo const struct brcms_c_rateset cck_rates = {
261*05491d2cSKalle Valo 	4,
262*05491d2cSKalle Valo 	/*  1b,   2b,   5.5,  11 Mbps */
263*05491d2cSKalle Valo 	{ 0x82, 0x84, 0x0b, 0x16},
264*05491d2cSKalle Valo 	0x00,
265*05491d2cSKalle Valo 	{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
266*05491d2cSKalle Valo 	  0x00, 0x00, 0x00, 0x00, 0x00}
267*05491d2cSKalle Valo };
268*05491d2cSKalle Valo 
269*05491d2cSKalle Valo /* check if rateset is valid.
270*05491d2cSKalle Valo  * if check_brate is true, rateset without a basic rate is considered NOT valid.
271*05491d2cSKalle Valo  */
brcms_c_rateset_valid(struct brcms_c_rateset * rs,bool check_brate)272*05491d2cSKalle Valo static bool brcms_c_rateset_valid(struct brcms_c_rateset *rs, bool check_brate)
273*05491d2cSKalle Valo {
274*05491d2cSKalle Valo 	uint idx;
275*05491d2cSKalle Valo 
276*05491d2cSKalle Valo 	if (!rs->count)
277*05491d2cSKalle Valo 		return false;
278*05491d2cSKalle Valo 
279*05491d2cSKalle Valo 	if (!check_brate)
280*05491d2cSKalle Valo 		return true;
281*05491d2cSKalle Valo 
282*05491d2cSKalle Valo 	/* error if no basic rates */
283*05491d2cSKalle Valo 	for (idx = 0; idx < rs->count; idx++) {
284*05491d2cSKalle Valo 		if (rs->rates[idx] & BRCMS_RATE_FLAG)
285*05491d2cSKalle Valo 			return true;
286*05491d2cSKalle Valo 	}
287*05491d2cSKalle Valo 	return false;
288*05491d2cSKalle Valo }
289*05491d2cSKalle Valo 
brcms_c_rateset_mcs_upd(struct brcms_c_rateset * rs,u8 txstreams)290*05491d2cSKalle Valo void brcms_c_rateset_mcs_upd(struct brcms_c_rateset *rs, u8 txstreams)
291*05491d2cSKalle Valo {
292*05491d2cSKalle Valo 	int i;
293*05491d2cSKalle Valo 	for (i = txstreams; i < MAX_STREAMS_SUPPORTED; i++)
294*05491d2cSKalle Valo 		rs->mcs[i] = 0;
295*05491d2cSKalle Valo }
296*05491d2cSKalle Valo 
297*05491d2cSKalle Valo /*
298*05491d2cSKalle Valo  * filter based on hardware rateset, and sort filtered rateset with basic
299*05491d2cSKalle Valo  * bit(s) preserved, and check if resulting rateset is valid.
300*05491d2cSKalle Valo */
301*05491d2cSKalle Valo bool
brcms_c_rate_hwrs_filter_sort_validate(struct brcms_c_rateset * rs,const struct brcms_c_rateset * hw_rs,bool check_brate,u8 txstreams)302*05491d2cSKalle Valo brcms_c_rate_hwrs_filter_sort_validate(struct brcms_c_rateset *rs,
303*05491d2cSKalle Valo 				   const struct brcms_c_rateset *hw_rs,
304*05491d2cSKalle Valo 				   bool check_brate, u8 txstreams)
305*05491d2cSKalle Valo {
306*05491d2cSKalle Valo 	u8 rateset[BRCM_MAXRATE + 1];
307*05491d2cSKalle Valo 	u8 r;
308*05491d2cSKalle Valo 	uint count;
309*05491d2cSKalle Valo 	uint i;
310*05491d2cSKalle Valo 
311*05491d2cSKalle Valo 	memset(rateset, 0, sizeof(rateset));
312*05491d2cSKalle Valo 	count = rs->count;
313*05491d2cSKalle Valo 
314*05491d2cSKalle Valo 	for (i = 0; i < count; i++) {
315*05491d2cSKalle Valo 		/* mask off "basic rate" bit, BRCMS_RATE_FLAG */
316*05491d2cSKalle Valo 		r = (int)rs->rates[i] & BRCMS_RATE_MASK;
317*05491d2cSKalle Valo 		if ((r > BRCM_MAXRATE) || (rate_info[r] == 0))
318*05491d2cSKalle Valo 			continue;
319*05491d2cSKalle Valo 		rateset[r] = rs->rates[i];	/* preserve basic bit! */
320*05491d2cSKalle Valo 	}
321*05491d2cSKalle Valo 
322*05491d2cSKalle Valo 	/* fill out the rates in order, looking at only supported rates */
323*05491d2cSKalle Valo 	count = 0;
324*05491d2cSKalle Valo 	for (i = 0; i < hw_rs->count; i++) {
325*05491d2cSKalle Valo 		r = hw_rs->rates[i] & BRCMS_RATE_MASK;
326*05491d2cSKalle Valo 		if (rateset[r])
327*05491d2cSKalle Valo 			rs->rates[count++] = rateset[r];
328*05491d2cSKalle Valo 	}
329*05491d2cSKalle Valo 
330*05491d2cSKalle Valo 	rs->count = count;
331*05491d2cSKalle Valo 
332*05491d2cSKalle Valo 	/* only set the mcs rate bit if the equivalent hw mcs bit is set */
333*05491d2cSKalle Valo 	for (i = 0; i < MCSSET_LEN; i++)
334*05491d2cSKalle Valo 		rs->mcs[i] = (rs->mcs[i] & hw_rs->mcs[i]);
335*05491d2cSKalle Valo 
336*05491d2cSKalle Valo 	if (brcms_c_rateset_valid(rs, check_brate))
337*05491d2cSKalle Valo 		return true;
338*05491d2cSKalle Valo 	else
339*05491d2cSKalle Valo 		return false;
340*05491d2cSKalle Valo }
341*05491d2cSKalle Valo 
342*05491d2cSKalle Valo /* calculate the rate of a rx'd frame and return it as a ratespec */
brcms_c_compute_rspec(struct d11rxhdr * rxh,u8 * plcp)343*05491d2cSKalle Valo u32 brcms_c_compute_rspec(struct d11rxhdr *rxh, u8 *plcp)
344*05491d2cSKalle Valo {
345*05491d2cSKalle Valo 	int phy_type;
346*05491d2cSKalle Valo 	u32 rspec = PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT;
347*05491d2cSKalle Valo 
348*05491d2cSKalle Valo 	phy_type =
349*05491d2cSKalle Valo 	    ((rxh->RxChan & RXS_CHAN_PHYTYPE_MASK) >> RXS_CHAN_PHYTYPE_SHIFT);
350*05491d2cSKalle Valo 
351*05491d2cSKalle Valo 	if ((phy_type == PHY_TYPE_N) || (phy_type == PHY_TYPE_SSN) ||
352*05491d2cSKalle Valo 	    (phy_type == PHY_TYPE_LCN) || (phy_type == PHY_TYPE_HT)) {
353*05491d2cSKalle Valo 		switch (rxh->PhyRxStatus_0 & PRXS0_FT_MASK) {
354*05491d2cSKalle Valo 		case PRXS0_CCK:
355*05491d2cSKalle Valo 			rspec =
356*05491d2cSKalle Valo 				cck_phy2mac_rate(
357*05491d2cSKalle Valo 				((struct cck_phy_hdr *) plcp)->signal);
358*05491d2cSKalle Valo 			break;
359*05491d2cSKalle Valo 		case PRXS0_OFDM:
360*05491d2cSKalle Valo 			rspec =
361*05491d2cSKalle Valo 			    ofdm_phy2mac_rate(
362*05491d2cSKalle Valo 				((struct ofdm_phy_hdr *) plcp)->rlpt[0]);
363*05491d2cSKalle Valo 			break;
364*05491d2cSKalle Valo 		case PRXS0_PREN:
365*05491d2cSKalle Valo 			rspec = (plcp[0] & MIMO_PLCP_MCS_MASK) | RSPEC_MIMORATE;
366*05491d2cSKalle Valo 			if (plcp[0] & MIMO_PLCP_40MHZ) {
367*05491d2cSKalle Valo 				/* indicate rspec is for 40 MHz mode */
368*05491d2cSKalle Valo 				rspec &= ~RSPEC_BW_MASK;
369*05491d2cSKalle Valo 				rspec |= (PHY_TXC1_BW_40MHZ << RSPEC_BW_SHIFT);
370*05491d2cSKalle Valo 			}
371*05491d2cSKalle Valo 			break;
372*05491d2cSKalle Valo 		case PRXS0_STDN:
373*05491d2cSKalle Valo 			/* fallthru */
374*05491d2cSKalle Valo 		default:
375*05491d2cSKalle Valo 			/* not supported, error condition */
376*05491d2cSKalle Valo 			break;
377*05491d2cSKalle Valo 		}
378*05491d2cSKalle Valo 		if (plcp3_issgi(plcp[3]))
379*05491d2cSKalle Valo 			rspec |= RSPEC_SHORT_GI;
380*05491d2cSKalle Valo 	} else
381*05491d2cSKalle Valo 	    if ((phy_type == PHY_TYPE_A) || (rxh->PhyRxStatus_0 & PRXS0_OFDM))
382*05491d2cSKalle Valo 		rspec = ofdm_phy2mac_rate(
383*05491d2cSKalle Valo 				((struct ofdm_phy_hdr *) plcp)->rlpt[0]);
384*05491d2cSKalle Valo 	else
385*05491d2cSKalle Valo 		rspec = cck_phy2mac_rate(
386*05491d2cSKalle Valo 				((struct cck_phy_hdr *) plcp)->signal);
387*05491d2cSKalle Valo 
388*05491d2cSKalle Valo 	return rspec;
389*05491d2cSKalle Valo }
390*05491d2cSKalle Valo 
391*05491d2cSKalle Valo /* copy rateset src to dst as-is (no masking or sorting) */
brcms_c_rateset_copy(const struct brcms_c_rateset * src,struct brcms_c_rateset * dst)392*05491d2cSKalle Valo void brcms_c_rateset_copy(const struct brcms_c_rateset *src,
393*05491d2cSKalle Valo 			  struct brcms_c_rateset *dst)
394*05491d2cSKalle Valo {
395*05491d2cSKalle Valo 	memcpy(dst, src, sizeof(struct brcms_c_rateset));
396*05491d2cSKalle Valo }
397*05491d2cSKalle Valo 
398*05491d2cSKalle Valo /*
399*05491d2cSKalle Valo  * Copy and selectively filter one rateset to another.
400*05491d2cSKalle Valo  * 'basic_only' means only copy basic rates.
401*05491d2cSKalle Valo  * 'rates' indicates cck (11b) and ofdm rates combinations.
402*05491d2cSKalle Valo  *    - 0: cck and ofdm
403*05491d2cSKalle Valo  *    - 1: cck only
404*05491d2cSKalle Valo  *    - 2: ofdm only
405*05491d2cSKalle Valo  * 'xmask' is the copy mask (typically 0x7f or 0xff).
406*05491d2cSKalle Valo  */
407*05491d2cSKalle Valo void
brcms_c_rateset_filter(struct brcms_c_rateset * src,struct brcms_c_rateset * dst,bool basic_only,u8 rates,uint xmask,bool mcsallow)408*05491d2cSKalle Valo brcms_c_rateset_filter(struct brcms_c_rateset *src, struct brcms_c_rateset *dst,
409*05491d2cSKalle Valo 		       bool basic_only, u8 rates, uint xmask, bool mcsallow)
410*05491d2cSKalle Valo {
411*05491d2cSKalle Valo 	uint i;
412*05491d2cSKalle Valo 	uint r;
413*05491d2cSKalle Valo 	uint count;
414*05491d2cSKalle Valo 
415*05491d2cSKalle Valo 	count = 0;
416*05491d2cSKalle Valo 	for (i = 0; i < src->count; i++) {
417*05491d2cSKalle Valo 		r = src->rates[i];
418*05491d2cSKalle Valo 		if (basic_only && !(r & BRCMS_RATE_FLAG))
419*05491d2cSKalle Valo 			continue;
420*05491d2cSKalle Valo 		if (rates == BRCMS_RATES_CCK &&
421*05491d2cSKalle Valo 		    is_ofdm_rate((r & BRCMS_RATE_MASK)))
422*05491d2cSKalle Valo 			continue;
423*05491d2cSKalle Valo 		if (rates == BRCMS_RATES_OFDM &&
424*05491d2cSKalle Valo 		    is_cck_rate((r & BRCMS_RATE_MASK)))
425*05491d2cSKalle Valo 			continue;
426*05491d2cSKalle Valo 		dst->rates[count++] = r & xmask;
427*05491d2cSKalle Valo 	}
428*05491d2cSKalle Valo 	dst->count = count;
429*05491d2cSKalle Valo 	dst->htphy_membership = src->htphy_membership;
430*05491d2cSKalle Valo 
431*05491d2cSKalle Valo 	if (mcsallow && rates != BRCMS_RATES_CCK)
432*05491d2cSKalle Valo 		memcpy(&dst->mcs[0], &src->mcs[0], MCSSET_LEN);
433*05491d2cSKalle Valo 	else
434*05491d2cSKalle Valo 		brcms_c_rateset_mcs_clear(dst);
435*05491d2cSKalle Valo }
436*05491d2cSKalle Valo 
437*05491d2cSKalle Valo /* select rateset for a given phy_type and bandtype and filter it, sort it
438*05491d2cSKalle Valo  * and fill rs_tgt with result
439*05491d2cSKalle Valo  */
440*05491d2cSKalle Valo void
brcms_c_rateset_default(struct brcms_c_rateset * rs_tgt,const struct brcms_c_rateset * rs_hw,uint phy_type,int bandtype,bool cck_only,uint rate_mask,bool mcsallow,u8 bw,u8 txstreams)441*05491d2cSKalle Valo brcms_c_rateset_default(struct brcms_c_rateset *rs_tgt,
442*05491d2cSKalle Valo 			const struct brcms_c_rateset *rs_hw,
443*05491d2cSKalle Valo 			uint phy_type, int bandtype, bool cck_only,
444*05491d2cSKalle Valo 			uint rate_mask, bool mcsallow, u8 bw, u8 txstreams)
445*05491d2cSKalle Valo {
446*05491d2cSKalle Valo 	const struct brcms_c_rateset *rs_dflt;
447*05491d2cSKalle Valo 	struct brcms_c_rateset rs_sel;
448*05491d2cSKalle Valo 	if ((PHYTYPE_IS(phy_type, PHY_TYPE_HT)) ||
449*05491d2cSKalle Valo 	    (PHYTYPE_IS(phy_type, PHY_TYPE_N)) ||
450*05491d2cSKalle Valo 	    (PHYTYPE_IS(phy_type, PHY_TYPE_LCN)) ||
451*05491d2cSKalle Valo 	    (PHYTYPE_IS(phy_type, PHY_TYPE_SSN))) {
452*05491d2cSKalle Valo 		if (bandtype == BRCM_BAND_5G)
453*05491d2cSKalle Valo 			rs_dflt = (bw == BRCMS_20_MHZ ?
454*05491d2cSKalle Valo 				   &ofdm_mimo_rates : &ofdm_40bw_mimo_rates);
455*05491d2cSKalle Valo 		else
456*05491d2cSKalle Valo 			rs_dflt = (bw == BRCMS_20_MHZ ?
457*05491d2cSKalle Valo 				   &cck_ofdm_mimo_rates :
458*05491d2cSKalle Valo 				   &cck_ofdm_40bw_mimo_rates);
459*05491d2cSKalle Valo 	} else if (PHYTYPE_IS(phy_type, PHY_TYPE_LP)) {
460*05491d2cSKalle Valo 		rs_dflt = (bandtype == BRCM_BAND_5G) ?
461*05491d2cSKalle Valo 			  &ofdm_rates : &cck_ofdm_rates;
462*05491d2cSKalle Valo 	} else if (PHYTYPE_IS(phy_type, PHY_TYPE_A)) {
463*05491d2cSKalle Valo 		rs_dflt = &ofdm_rates;
464*05491d2cSKalle Valo 	} else if (PHYTYPE_IS(phy_type, PHY_TYPE_G)) {
465*05491d2cSKalle Valo 		rs_dflt = &cck_ofdm_rates;
466*05491d2cSKalle Valo 	} else {
467*05491d2cSKalle Valo 		/* should not happen, error condition */
468*05491d2cSKalle Valo 		rs_dflt = &cck_rates;	/* force cck */
469*05491d2cSKalle Valo 	}
470*05491d2cSKalle Valo 
471*05491d2cSKalle Valo 	/* if hw rateset is not supplied, assign selected rateset to it */
472*05491d2cSKalle Valo 	if (!rs_hw)
473*05491d2cSKalle Valo 		rs_hw = rs_dflt;
474*05491d2cSKalle Valo 
475*05491d2cSKalle Valo 	brcms_c_rateset_copy(rs_dflt, &rs_sel);
476*05491d2cSKalle Valo 	brcms_c_rateset_mcs_upd(&rs_sel, txstreams);
477*05491d2cSKalle Valo 	brcms_c_rateset_filter(&rs_sel, rs_tgt, false,
478*05491d2cSKalle Valo 			   cck_only ? BRCMS_RATES_CCK : BRCMS_RATES_CCK_OFDM,
479*05491d2cSKalle Valo 			   rate_mask, mcsallow);
480*05491d2cSKalle Valo 	brcms_c_rate_hwrs_filter_sort_validate(rs_tgt, rs_hw, false,
481*05491d2cSKalle Valo 					   mcsallow ? txstreams : 1);
482*05491d2cSKalle Valo }
483*05491d2cSKalle Valo 
brcms_c_rate_legacy_phyctl(uint rate)484*05491d2cSKalle Valo s16 brcms_c_rate_legacy_phyctl(uint rate)
485*05491d2cSKalle Valo {
486*05491d2cSKalle Valo 	uint i;
487*05491d2cSKalle Valo 	for (i = 0; i < LEGACY_PHYCFG_TABLE_SIZE; i++)
488*05491d2cSKalle Valo 		if (rate == legacy_phycfg_table[i].rate_ofdm)
489*05491d2cSKalle Valo 			return legacy_phycfg_table[i].tx_phy_ctl3;
490*05491d2cSKalle Valo 
491*05491d2cSKalle Valo 	return -1;
492*05491d2cSKalle Valo }
493*05491d2cSKalle Valo 
brcms_c_rateset_mcs_clear(struct brcms_c_rateset * rateset)494*05491d2cSKalle Valo void brcms_c_rateset_mcs_clear(struct brcms_c_rateset *rateset)
495*05491d2cSKalle Valo {
496*05491d2cSKalle Valo 	uint i;
497*05491d2cSKalle Valo 	for (i = 0; i < MCSSET_LEN; i++)
498*05491d2cSKalle Valo 		rateset->mcs[i] = 0;
499*05491d2cSKalle Valo }
500*05491d2cSKalle Valo 
brcms_c_rateset_mcs_build(struct brcms_c_rateset * rateset,u8 txstreams)501*05491d2cSKalle Valo void brcms_c_rateset_mcs_build(struct brcms_c_rateset *rateset, u8 txstreams)
502*05491d2cSKalle Valo {
503*05491d2cSKalle Valo 	memcpy(&rateset->mcs[0], &cck_ofdm_mimo_rates.mcs[0], MCSSET_LEN);
504*05491d2cSKalle Valo 	brcms_c_rateset_mcs_upd(rateset, txstreams);
505*05491d2cSKalle Valo }
506*05491d2cSKalle Valo 
507*05491d2cSKalle Valo /* Based on bandwidth passed, allow/disallow MCS 32 in the rateset */
brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset * rateset,u8 bw)508*05491d2cSKalle Valo void brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset *rateset, u8 bw)
509*05491d2cSKalle Valo {
510*05491d2cSKalle Valo 	if (bw == BRCMS_40_MHZ)
511*05491d2cSKalle Valo 		setbit(rateset->mcs, 32);
512*05491d2cSKalle Valo 	else
513*05491d2cSKalle Valo 		clrbit(rateset->mcs, 32);
514*05491d2cSKalle Valo }
515