1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2423e3ce3SKalle Valo #ifndef B43legacy_XMIT_H_
3423e3ce3SKalle Valo #define B43legacy_XMIT_H_
4423e3ce3SKalle Valo
5423e3ce3SKalle Valo #include "main.h"
6423e3ce3SKalle Valo
7423e3ce3SKalle Valo
8423e3ce3SKalle Valo #define _b43legacy_declare_plcp_hdr(size) \
9423e3ce3SKalle Valo struct b43legacy_plcp_hdr##size { \
10423e3ce3SKalle Valo union { \
11423e3ce3SKalle Valo __le32 data; \
12423e3ce3SKalle Valo __u8 raw[size]; \
13423e3ce3SKalle Valo } __packed; \
14423e3ce3SKalle Valo } __packed
15423e3ce3SKalle Valo
16423e3ce3SKalle Valo /* struct b43legacy_plcp_hdr4 */
17423e3ce3SKalle Valo _b43legacy_declare_plcp_hdr(4);
18423e3ce3SKalle Valo /* struct b43legacy_plcp_hdr6 */
19423e3ce3SKalle Valo _b43legacy_declare_plcp_hdr(6);
20423e3ce3SKalle Valo
21423e3ce3SKalle Valo #undef _b43legacy_declare_plcp_hdr
22423e3ce3SKalle Valo
23423e3ce3SKalle Valo
24423e3ce3SKalle Valo /* TX header for v3 firmware */
25423e3ce3SKalle Valo struct b43legacy_txhdr_fw3 {
26423e3ce3SKalle Valo __le32 mac_ctl; /* MAC TX control */
27423e3ce3SKalle Valo __le16 mac_frame_ctl; /* Copy of the FrameControl */
28423e3ce3SKalle Valo __le16 tx_fes_time_norm; /* TX FES Time Normal */
29423e3ce3SKalle Valo __le16 phy_ctl; /* PHY TX control */
30423e3ce3SKalle Valo __u8 iv[16]; /* Encryption IV */
31423e3ce3SKalle Valo __u8 tx_receiver[6]; /* TX Frame Receiver address */
32423e3ce3SKalle Valo __le16 tx_fes_time_fb; /* TX FES Time Fallback */
33423e3ce3SKalle Valo struct b43legacy_plcp_hdr4 rts_plcp_fb; /* RTS fallback PLCP */
34423e3ce3SKalle Valo __le16 rts_dur_fb; /* RTS fallback duration */
35423e3ce3SKalle Valo struct b43legacy_plcp_hdr4 plcp_fb; /* Fallback PLCP */
36423e3ce3SKalle Valo __le16 dur_fb; /* Fallback duration */
37423e3ce3SKalle Valo PAD_BYTES(2);
38423e3ce3SKalle Valo __le16 cookie;
39423e3ce3SKalle Valo __le16 unknown_scb_stuff;
40423e3ce3SKalle Valo struct b43legacy_plcp_hdr6 rts_plcp; /* RTS PLCP */
41423e3ce3SKalle Valo __u8 rts_frame[18]; /* The RTS frame (if used) */
42423e3ce3SKalle Valo struct b43legacy_plcp_hdr6 plcp;
43423e3ce3SKalle Valo } __packed;
44423e3ce3SKalle Valo
45423e3ce3SKalle Valo /* MAC TX control */
46423e3ce3SKalle Valo #define B43legacy_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
47423e3ce3SKalle Valo #define B43legacy_TX4_MAC_KEYIDX_SHIFT 20
48423e3ce3SKalle Valo #define B43legacy_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
49423e3ce3SKalle Valo #define B43legacy_TX4_MAC_KEYALG_SHIFT 16
50423e3ce3SKalle Valo #define B43legacy_TX4_MAC_LIFETIME 0x00001000
51423e3ce3SKalle Valo #define B43legacy_TX4_MAC_FRAMEBURST 0x00000800
52423e3ce3SKalle Valo #define B43legacy_TX4_MAC_SENDCTS 0x00000400
53423e3ce3SKalle Valo #define B43legacy_TX4_MAC_AMPDU 0x00000300
54423e3ce3SKalle Valo #define B43legacy_TX4_MAC_AMPDU_SHIFT 8
55423e3ce3SKalle Valo #define B43legacy_TX4_MAC_CTSFALLBACKOFDM 0x00000200
56423e3ce3SKalle Valo #define B43legacy_TX4_MAC_FALLBACKOFDM 0x00000100
57423e3ce3SKalle Valo #define B43legacy_TX4_MAC_5GHZ 0x00000080
58423e3ce3SKalle Valo #define B43legacy_TX4_MAC_IGNPMQ 0x00000020
59423e3ce3SKalle Valo #define B43legacy_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Seq No */
60423e3ce3SKalle Valo #define B43legacy_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */
61423e3ce3SKalle Valo #define B43legacy_TX4_MAC_SENDRTS 0x00000004
62423e3ce3SKalle Valo #define B43legacy_TX4_MAC_LONGFRAME 0x00000002
63423e3ce3SKalle Valo #define B43legacy_TX4_MAC_ACK 0x00000001
64423e3ce3SKalle Valo
65423e3ce3SKalle Valo /* Extra Frame Types */
66423e3ce3SKalle Valo #define B43legacy_TX4_EFT_FBOFDM 0x0001 /* Data frame fb rate type */
67423e3ce3SKalle Valo #define B43legacy_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */
68423e3ce3SKalle Valo #define B43legacy_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */
69423e3ce3SKalle Valo
70423e3ce3SKalle Valo /* PHY TX control word */
71423e3ce3SKalle Valo #define B43legacy_TX4_PHY_ENC 0x0003 /* Data frame encoding */
72423e3ce3SKalle Valo #define B43legacy_TX4_PHY_ENC_CCK 0x0000 /* CCK */
73423e3ce3SKalle Valo #define B43legacy_TX4_PHY_ENC_OFDM 0x0001 /* Data frame rate type */
74423e3ce3SKalle Valo #define B43legacy_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
75423e3ce3SKalle Valo #define B43legacy_TX4_PHY_ANT 0x03C0 /* Antenna selection */
76423e3ce3SKalle Valo #define B43legacy_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */
77423e3ce3SKalle Valo #define B43legacy_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */
78423e3ce3SKalle Valo #define B43legacy_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */
79423e3ce3SKalle Valo
80423e3ce3SKalle Valo
81423e3ce3SKalle Valo
82423e3ce3SKalle Valo int b43legacy_generate_txhdr(struct b43legacy_wldev *dev,
83423e3ce3SKalle Valo u8 *txhdr,
84423e3ce3SKalle Valo const unsigned char *fragment_data,
85423e3ce3SKalle Valo unsigned int fragment_len,
86423e3ce3SKalle Valo struct ieee80211_tx_info *info,
87423e3ce3SKalle Valo u16 cookie);
88423e3ce3SKalle Valo
89423e3ce3SKalle Valo
90423e3ce3SKalle Valo /* Transmit Status */
91423e3ce3SKalle Valo struct b43legacy_txstatus {
92423e3ce3SKalle Valo u16 cookie; /* The cookie from the txhdr */
93423e3ce3SKalle Valo u16 seq; /* Sequence number */
94423e3ce3SKalle Valo u8 phy_stat; /* PHY TX status */
95423e3ce3SKalle Valo u8 frame_count; /* Frame transmit count */
96423e3ce3SKalle Valo u8 rts_count; /* RTS transmit count */
97423e3ce3SKalle Valo u8 supp_reason; /* Suppression reason */
98423e3ce3SKalle Valo /* flags */
99423e3ce3SKalle Valo u8 pm_indicated;/* PM mode indicated to AP */
100423e3ce3SKalle Valo u8 intermediate;/* Intermediate status notification */
101423e3ce3SKalle Valo u8 for_ampdu; /* Status is for an AMPDU (afterburner) */
102423e3ce3SKalle Valo u8 acked; /* Wireless ACK received */
103423e3ce3SKalle Valo };
104423e3ce3SKalle Valo
105423e3ce3SKalle Valo /* txstatus supp_reason values */
106423e3ce3SKalle Valo enum {
107423e3ce3SKalle Valo B43legacy_TXST_SUPP_NONE, /* Not suppressed */
108423e3ce3SKalle Valo B43legacy_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */
109423e3ce3SKalle Valo B43legacy_TXST_SUPP_FLUSH, /* Suppressed due to flush request */
110423e3ce3SKalle Valo B43legacy_TXST_SUPP_PREV, /* Previous fragment failed */
111423e3ce3SKalle Valo B43legacy_TXST_SUPP_CHAN, /* Channel mismatch */
112423e3ce3SKalle Valo B43legacy_TXST_SUPP_LIFE, /* Lifetime expired */
113423e3ce3SKalle Valo B43legacy_TXST_SUPP_UNDER, /* Buffer underflow */
114423e3ce3SKalle Valo B43legacy_TXST_SUPP_ABNACK, /* Afterburner NACK */
115423e3ce3SKalle Valo };
116423e3ce3SKalle Valo
117423e3ce3SKalle Valo /* Transmit Status as received through DMA/PIO on old chips */
118423e3ce3SKalle Valo struct b43legacy_hwtxstatus {
119423e3ce3SKalle Valo PAD_BYTES(4);
120423e3ce3SKalle Valo __le16 cookie;
121423e3ce3SKalle Valo u8 flags;
122423e3ce3SKalle Valo u8 count;
123423e3ce3SKalle Valo PAD_BYTES(2);
124423e3ce3SKalle Valo __le16 seq;
125423e3ce3SKalle Valo u8 phy_stat;
126423e3ce3SKalle Valo PAD_BYTES(1);
127423e3ce3SKalle Valo } __packed;
128423e3ce3SKalle Valo
129423e3ce3SKalle Valo
130423e3ce3SKalle Valo /* Receive header for v3 firmware. */
131423e3ce3SKalle Valo struct b43legacy_rxhdr_fw3 {
132423e3ce3SKalle Valo __le16 frame_len; /* Frame length */
133423e3ce3SKalle Valo PAD_BYTES(2);
134423e3ce3SKalle Valo __le16 phy_status0; /* PHY RX Status 0 */
135423e3ce3SKalle Valo __u8 jssi; /* PHY RX Status 1: JSSI */
136423e3ce3SKalle Valo __u8 sig_qual; /* PHY RX Status 1: Signal Quality */
137423e3ce3SKalle Valo PAD_BYTES(2); /* PHY RX Status 2 */
138423e3ce3SKalle Valo __le16 phy_status3; /* PHY RX Status 3 */
139423e3ce3SKalle Valo __le16 mac_status; /* MAC RX status */
140423e3ce3SKalle Valo __le16 mac_time;
141423e3ce3SKalle Valo __le16 channel;
142423e3ce3SKalle Valo } __packed;
143423e3ce3SKalle Valo
144423e3ce3SKalle Valo
145423e3ce3SKalle Valo /* PHY RX Status 0 */
146423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
147423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_PLCPHCF 0x0200
148423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_PLCPFV 0x0100
149423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_SHORTPRMBL 0x0080 /* Recvd with Short Preamble */
150423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_LCRS 0x0040
151423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_ANT 0x0020 /* Antenna */
152423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_UNSRATE 0x0010
153423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_CLIP 0x000C
154423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_CLIP_SHIFT 2
155423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_FTYPE 0x0003 /* Frame type */
156423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
157423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
158423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
159423e3ce3SKalle Valo #define B43legacy_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
160423e3ce3SKalle Valo
161423e3ce3SKalle Valo /* PHY RX Status 2 */
162423e3ce3SKalle Valo #define B43legacy_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
163423e3ce3SKalle Valo #define B43legacy_RX_PHYST2_LNAG_SHIFT 14
164423e3ce3SKalle Valo #define B43legacy_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
165423e3ce3SKalle Valo #define B43legacy_RX_PHYST2_PNAG_SHIFT 10
166423e3ce3SKalle Valo #define B43legacy_RX_PHYST2_FOFF 0x03FF /* F offset */
167423e3ce3SKalle Valo
168423e3ce3SKalle Valo /* PHY RX Status 3 */
169423e3ce3SKalle Valo #define B43legacy_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
170423e3ce3SKalle Valo #define B43legacy_RX_PHYST3_DIGG_SHIFT 11
171423e3ce3SKalle Valo #define B43legacy_RX_PHYST3_TRSTATE 0x0400 /* TR state */
172423e3ce3SKalle Valo
173423e3ce3SKalle Valo /* MAC RX Status */
174423e3ce3SKalle Valo #define B43legacy_RX_MAC_BEACONSENT 0x00008000 /* Beacon send flag */
175423e3ce3SKalle Valo #define B43legacy_RX_MAC_KEYIDX 0x000007E0 /* Key index */
176423e3ce3SKalle Valo #define B43legacy_RX_MAC_KEYIDX_SHIFT 5
177423e3ce3SKalle Valo #define B43legacy_RX_MAC_DECERR 0x00000010 /* Decrypt error */
178423e3ce3SKalle Valo #define B43legacy_RX_MAC_DEC 0x00000008 /* Decryption attempted */
179423e3ce3SKalle Valo #define B43legacy_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
180423e3ce3SKalle Valo #define B43legacy_RX_MAC_RESP 0x00000002 /* Response frame xmitted */
181423e3ce3SKalle Valo #define B43legacy_RX_MAC_FCSERR 0x00000001 /* FCS error */
182423e3ce3SKalle Valo
183423e3ce3SKalle Valo /* RX channel */
184423e3ce3SKalle Valo #define B43legacy_RX_CHAN_GAIN 0xFC00 /* Gain */
185423e3ce3SKalle Valo #define B43legacy_RX_CHAN_GAIN_SHIFT 10
186423e3ce3SKalle Valo #define B43legacy_RX_CHAN_ID 0x03FC /* Channel ID */
187423e3ce3SKalle Valo #define B43legacy_RX_CHAN_ID_SHIFT 2
188423e3ce3SKalle Valo #define B43legacy_RX_CHAN_PHYTYPE 0x0003 /* PHY type */
189423e3ce3SKalle Valo
190423e3ce3SKalle Valo
191423e3ce3SKalle Valo
192423e3ce3SKalle Valo u8 b43legacy_plcp_get_ratecode_cck(const u8 bitrate);
193423e3ce3SKalle Valo u8 b43legacy_plcp_get_ratecode_ofdm(const u8 bitrate);
194423e3ce3SKalle Valo
195423e3ce3SKalle Valo void b43legacy_generate_plcp_hdr(struct b43legacy_plcp_hdr4 *plcp,
196423e3ce3SKalle Valo const u16 octets, const u8 bitrate);
197423e3ce3SKalle Valo
198423e3ce3SKalle Valo void b43legacy_rx(struct b43legacy_wldev *dev,
199423e3ce3SKalle Valo struct sk_buff *skb,
200423e3ce3SKalle Valo const void *_rxhdr);
201423e3ce3SKalle Valo
202423e3ce3SKalle Valo void b43legacy_handle_txstatus(struct b43legacy_wldev *dev,
203423e3ce3SKalle Valo const struct b43legacy_txstatus *status);
204423e3ce3SKalle Valo
205423e3ce3SKalle Valo void b43legacy_handle_hwtxstatus(struct b43legacy_wldev *dev,
206423e3ce3SKalle Valo const struct b43legacy_hwtxstatus *hw);
207423e3ce3SKalle Valo
208423e3ce3SKalle Valo void b43legacy_tx_suspend(struct b43legacy_wldev *dev);
209423e3ce3SKalle Valo void b43legacy_tx_resume(struct b43legacy_wldev *dev);
210423e3ce3SKalle Valo
211423e3ce3SKalle Valo
212423e3ce3SKalle Valo #define B43legacy_NR_QOSPARMS 22
213423e3ce3SKalle Valo enum {
214423e3ce3SKalle Valo B43legacy_QOSPARM_TXOP = 0,
215423e3ce3SKalle Valo B43legacy_QOSPARM_CWMIN,
216423e3ce3SKalle Valo B43legacy_QOSPARM_CWMAX,
217423e3ce3SKalle Valo B43legacy_QOSPARM_CWCUR,
218423e3ce3SKalle Valo B43legacy_QOSPARM_AIFS,
219423e3ce3SKalle Valo B43legacy_QOSPARM_BSLOTS,
220423e3ce3SKalle Valo B43legacy_QOSPARM_REGGAP,
221423e3ce3SKalle Valo B43legacy_QOSPARM_STATUS,
222423e3ce3SKalle Valo };
223423e3ce3SKalle Valo
224423e3ce3SKalle Valo void b43legacy_qos_init(struct b43legacy_wldev *dev);
225423e3ce3SKalle Valo
226423e3ce3SKalle Valo
227423e3ce3SKalle Valo /* Helper functions for converting the key-table index from "firmware-format"
228423e3ce3SKalle Valo * to "raw-format" and back. The firmware API changed for this at some revision.
229423e3ce3SKalle Valo * We need to account for that here. */
230423e3ce3SKalle Valo static inline
b43legacy_new_kidx_api(struct b43legacy_wldev * dev)231423e3ce3SKalle Valo int b43legacy_new_kidx_api(struct b43legacy_wldev *dev)
232423e3ce3SKalle Valo {
233423e3ce3SKalle Valo /* FIXME: Not sure the change was at rev 351 */
234423e3ce3SKalle Valo return (dev->fw.rev >= 351);
235423e3ce3SKalle Valo }
236423e3ce3SKalle Valo static inline
b43legacy_kidx_to_fw(struct b43legacy_wldev * dev,u8 raw_kidx)237423e3ce3SKalle Valo u8 b43legacy_kidx_to_fw(struct b43legacy_wldev *dev, u8 raw_kidx)
238423e3ce3SKalle Valo {
239423e3ce3SKalle Valo u8 firmware_kidx;
240423e3ce3SKalle Valo if (b43legacy_new_kidx_api(dev))
241423e3ce3SKalle Valo firmware_kidx = raw_kidx;
242423e3ce3SKalle Valo else {
243423e3ce3SKalle Valo if (raw_kidx >= 4) /* Is per STA key? */
244423e3ce3SKalle Valo firmware_kidx = raw_kidx - 4;
245423e3ce3SKalle Valo else
246423e3ce3SKalle Valo firmware_kidx = raw_kidx; /* TX default key */
247423e3ce3SKalle Valo }
248423e3ce3SKalle Valo return firmware_kidx;
249423e3ce3SKalle Valo }
250423e3ce3SKalle Valo static inline
b43legacy_kidx_to_raw(struct b43legacy_wldev * dev,u8 firmware_kidx)251423e3ce3SKalle Valo u8 b43legacy_kidx_to_raw(struct b43legacy_wldev *dev, u8 firmware_kidx)
252423e3ce3SKalle Valo {
253423e3ce3SKalle Valo u8 raw_kidx;
254423e3ce3SKalle Valo if (b43legacy_new_kidx_api(dev))
255423e3ce3SKalle Valo raw_kidx = firmware_kidx;
256423e3ce3SKalle Valo else
257423e3ce3SKalle Valo /* RX default keys or per STA keys */
258423e3ce3SKalle Valo raw_kidx = firmware_kidx + 4;
259423e3ce3SKalle Valo return raw_kidx;
260423e3ce3SKalle Valo }
261423e3ce3SKalle Valo
262423e3ce3SKalle Valo #endif /* B43legacy_XMIT_H_ */
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