1 /* 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __WIL6210_H__ 19 #define __WIL6210_H__ 20 21 #include <linux/etherdevice.h> 22 #include <linux/netdevice.h> 23 #include <linux/wireless.h> 24 #include <net/cfg80211.h> 25 #include <linux/timex.h> 26 #include <linux/types.h> 27 #include <linux/irqreturn.h> 28 #include "wmi.h" 29 #include "wil_platform.h" 30 #include "fw.h" 31 32 extern bool no_fw_recovery; 33 extern unsigned int mtu_max; 34 extern unsigned short rx_ring_overflow_thrsh; 35 extern int agg_wsize; 36 extern bool rx_align_2; 37 extern bool rx_large_buf; 38 extern bool debug_fw; 39 extern bool disable_ap_sme; 40 41 struct wil6210_priv; 42 struct wil6210_vif; 43 union wil_tx_desc; 44 45 #define WIL_NAME "wil6210" 46 47 #define WIL_FW_NAME_DEFAULT "wil6210.fw" 48 #define WIL_FW_NAME_FTM_DEFAULT "wil6210_ftm.fw" 49 50 #define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw" 51 #define WIL_FW_NAME_FTM_SPARROW_PLUS "wil6210_sparrow_plus_ftm.fw" 52 53 #define WIL_FW_NAME_TALYN "wil6436.fw" 54 #define WIL_FW_NAME_FTM_TALYN "wil6436_ftm.fw" 55 56 #define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */ 57 58 #define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */ 59 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 60 61 #define WIL_NUM_LATENCY_BINS 200 62 63 /* maximum number of virtual interfaces the driver supports 64 * (including the main interface) 65 */ 66 #define WIL_MAX_VIFS 4 67 68 /** 69 * extract bits [@b0:@b1] (inclusive) from the value @x 70 * it should be @b0 <= @b1, or result is incorrect 71 */ 72 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 73 { 74 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 75 } 76 77 #define WIL6210_MIN_MEM_SIZE (2 * 1024 * 1024UL) 78 #define WIL6210_MAX_MEM_SIZE (4 * 1024 * 1024UL) 79 80 #define WIL_TX_Q_LEN_DEFAULT (4000) 81 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 82 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12) 83 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 84 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 85 /* limit ring size in range [32..32k] */ 86 #define WIL_RING_SIZE_ORDER_MIN (5) 87 #define WIL_RING_SIZE_ORDER_MAX (15) 88 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 89 #define WIL6210_MAX_CID (8) /* HW limit */ 90 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 91 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 92 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 93 #define WIL6210_MAX_STATUS_RINGS (8) 94 95 /* Hardware offload block adds the following: 96 * 26 bytes - 3-address QoS data header 97 * 8 bytes - IV + EIV (for GCMP) 98 * 8 bytes - SNAP 99 * 16 bytes - MIC (for GCMP) 100 * 4 bytes - CRC 101 */ 102 #define WIL_MAX_MPDU_OVERHEAD (62) 103 104 struct wil_suspend_count_stats { 105 unsigned long successful_suspends; 106 unsigned long successful_resumes; 107 unsigned long failed_suspends; 108 unsigned long failed_resumes; 109 }; 110 111 struct wil_suspend_stats { 112 struct wil_suspend_count_stats r_off; 113 struct wil_suspend_count_stats r_on; 114 unsigned long rejected_by_device; /* only radio on */ 115 unsigned long rejected_by_host; 116 }; 117 118 /* Calculate MAC buffer size for the firmware. It includes all overhead, 119 * as it will go over the air, and need to be 8 byte aligned 120 */ 121 static inline u32 wil_mtu2macbuf(u32 mtu) 122 { 123 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 124 } 125 126 /* MTU for Ethernet need to take into account 8-byte SNAP header 127 * to be added when encapsulating Ethernet frame into 802.11 128 */ 129 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 130 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 131 #define WIL6210_ITR_TRSH_MAX (5000000) 132 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 133 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 134 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 135 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 136 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 137 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 138 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 139 #define WIL6210_DISCONNECT_TO_MS (2000) 140 #define WIL6210_RX_HIGH_TRSH_INIT (0) 141 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 142 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 143 #define WIL_MAX_DMG_AID 254 /* for DMG only 1-254 allowed (see 144 * 802.11REVmc/D5.0, section 9.4.1.8) 145 */ 146 /* Hardware definitions begin */ 147 148 /* 149 * Mapping 150 * RGF File | Host addr | FW addr 151 * | | 152 * user_rgf | 0x000000 | 0x880000 153 * dma_rgf | 0x001000 | 0x881000 154 * pcie_rgf | 0x002000 | 0x882000 155 * | | 156 */ 157 158 /* Where various structures placed in host address space */ 159 #define WIL6210_FW_HOST_OFF (0x880000UL) 160 161 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 162 163 /* 164 * Interrupt control registers block 165 * 166 * each interrupt controlled by the same bit in all registers 167 */ 168 struct RGF_ICR { 169 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 170 u32 ICR; /* Cause, W1C/COR depending on ICC */ 171 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 172 u32 ICS; /* Cause Set, WO */ 173 u32 IMV; /* Mask, RW+S/C */ 174 u32 IMS; /* Mask Set, write 1 to set */ 175 u32 IMC; /* Mask Clear, write 1 to clear */ 176 } __packed; 177 178 /* registers - FW addresses */ 179 #define RGF_USER_USAGE_1 (0x880004) 180 #define RGF_USER_USAGE_6 (0x880018) 181 #define BIT_USER_OOB_MODE BIT(31) 182 #define BIT_USER_OOB_R2_MODE BIT(30) 183 #define RGF_USER_USAGE_8 (0x880020) 184 #define BIT_USER_PREVENT_DEEP_SLEEP BIT(0) 185 #define BIT_USER_SUPPORT_T_POWER_ON_0 BIT(1) 186 #define BIT_USER_EXT_CLK BIT(2) 187 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 188 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 189 #define RGF_USER_USER_CPU_0 (0x8801e0) 190 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 191 #define RGF_USER_CPU_PC (0x8801e8) 192 #define RGF_USER_MAC_CPU_0 (0x8801fc) 193 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 194 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 195 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 196 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 197 #define RGF_USER_FW_CALIB_RESULT (0x880a90) /* b0-7:result 198 * b8-15:signature 199 */ 200 #define CALIB_RESULT_SIGNATURE (0x11) 201 #define RGF_USER_CLKS_CTL_0 (0x880abc) 202 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 203 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 204 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 205 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 206 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 207 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 208 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 209 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 210 #define BIT_CAR_PERST_RST BIT(7) 211 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 212 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 213 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 214 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 215 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 216 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 217 #define RGF_USER_OTP_HW_RD_MACHINE_1 (0x880ce0) 218 #define BIT_OTP_SIGNATURE_ERR_TALYN_MB BIT(0) 219 #define BIT_OTP_HW_SECTION_DONE_TALYN_MB BIT(2) 220 #define BIT_NO_FLASH_INDICATION BIT(8) 221 #define RGF_USER_XPM_IFC_RD_TIME1 (0x880cec) 222 #define RGF_USER_XPM_IFC_RD_TIME2 (0x880cf0) 223 #define RGF_USER_XPM_IFC_RD_TIME3 (0x880cf4) 224 #define RGF_USER_XPM_IFC_RD_TIME4 (0x880cf8) 225 #define RGF_USER_XPM_IFC_RD_TIME5 (0x880cfc) 226 #define RGF_USER_XPM_IFC_RD_TIME6 (0x880d00) 227 #define RGF_USER_XPM_IFC_RD_TIME7 (0x880d04) 228 #define RGF_USER_XPM_IFC_RD_TIME8 (0x880d08) 229 #define RGF_USER_XPM_IFC_RD_TIME9 (0x880d0c) 230 #define RGF_USER_XPM_IFC_RD_TIME10 (0x880d10) 231 #define RGF_USER_XPM_RD_DOUT_SAMPLE_TIME (0x880d64) 232 233 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 234 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 235 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 236 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 237 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 238 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 239 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 240 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 241 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 242 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) 243 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 244 245 /* Legacy interrupt moderation control (before Sparrow v2)*/ 246 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 247 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 248 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 249 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 250 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 251 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 252 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 253 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 254 255 /* Offload control (Sparrow B0+) */ 256 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 257 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 258 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 259 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 260 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 261 262 /* New (sparrow v2+) interrupt moderation control */ 263 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 264 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 265 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 266 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 267 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 268 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 269 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 270 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 271 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 272 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 273 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 274 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 275 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 276 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 277 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 278 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 279 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 280 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 281 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 282 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 283 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 284 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 285 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 286 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 287 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 288 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 289 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 290 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 291 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 292 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 293 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 294 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 295 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 296 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 297 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 298 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 299 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 300 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 301 302 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 303 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 304 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 305 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 306 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 307 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 308 309 #define RGF_HP_CTRL (0x88265c) 310 #define RGF_PAL_UNIT_ICR (0x88266c) /* struct RGF_ICR */ 311 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 312 313 /* MAC timer, usec, for packet lifetime */ 314 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 315 316 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 317 #define RGF_CAF_OSC_CONTROL (0x88afa4) 318 #define BIT_CAF_OSC_XTAL_EN BIT(0) 319 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 320 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 321 322 #define RGF_OTP_QC_SECURED (0x8a0038) 323 #define BIT_BOOT_FROM_ROM BIT(31) 324 325 /* eDMA */ 326 #define RGF_INT_COUNT_ON_SPECIAL_EVT (0x8b62d8) 327 328 #define RGF_INT_CTRL_INT_GEN_CFG_0 (0x8bc000) 329 #define RGF_INT_CTRL_INT_GEN_CFG_1 (0x8bc004) 330 #define RGF_INT_GEN_TIME_UNIT_LIMIT (0x8bc0c8) 331 332 #define RGF_INT_GEN_CTRL (0x8bc0ec) 333 #define BIT_CONTROL_0 BIT(0) 334 335 /* eDMA status interrupts */ 336 #define RGF_INT_GEN_RX_ICR (0x8bc0f4) 337 #define BIT_RX_STATUS_IRQ BIT(WIL_RX_STATUS_IRQ_IDX) 338 #define RGF_INT_GEN_TX_ICR (0x8bc110) 339 #define BIT_TX_STATUS_IRQ BIT(WIL_TX_STATUS_IRQ_IDX) 340 #define RGF_INT_CTRL_RX_INT_MASK (0x8bc12c) 341 #define RGF_INT_CTRL_TX_INT_MASK (0x8bc130) 342 343 #define RGF_INT_GEN_IDLE_TIME_LIMIT (0x8bc134) 344 345 #define USER_EXT_USER_PMU_3 (0x88d00c) 346 #define BIT_PMU_DEVICE_RDY BIT(0) 347 348 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 349 #define JTAG_DEV_ID_SPARROW (0x2632072f) 350 #define JTAG_DEV_ID_TALYN (0x7e0e1) 351 #define JTAG_DEV_ID_TALYN_MB (0x1007e0e1) 352 353 #define RGF_USER_REVISION_ID (0x88afe4) 354 #define RGF_USER_REVISION_ID_MASK (3) 355 #define REVISION_ID_SPARROW_B0 (0x0) 356 #define REVISION_ID_SPARROW_D0 (0x3) 357 358 #define RGF_OTP_MAC_TALYN_MB (0x8a0304) 359 #define RGF_OTP_MAC (0x8a0620) 360 361 /* Talyn-MB */ 362 #define RGF_USER_USER_CPU_0_TALYN_MB (0x8c0138) 363 #define RGF_USER_MAC_CPU_0_TALYN_MB (0x8c0154) 364 365 /* crash codes for FW/Ucode stored here */ 366 367 /* ASSERT RGFs */ 368 #define SPARROW_RGF_FW_ASSERT_CODE (0x91f020) 369 #define SPARROW_RGF_UCODE_ASSERT_CODE (0x91f028) 370 #define TALYN_RGF_FW_ASSERT_CODE (0xa37020) 371 #define TALYN_RGF_UCODE_ASSERT_CODE (0xa37028) 372 373 enum { 374 HW_VER_UNKNOWN, 375 HW_VER_SPARROW_B0, /* REVISION_ID_SPARROW_B0 */ 376 HW_VER_SPARROW_D0, /* REVISION_ID_SPARROW_D0 */ 377 HW_VER_TALYN, /* JTAG_DEV_ID_TALYN */ 378 HW_VER_TALYN_MB /* JTAG_DEV_ID_TALYN_MB */ 379 }; 380 381 /* popular locations */ 382 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 383 #define HOST_MBOX HOSTADDR(RGF_MBOX) 384 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 385 386 /* ISR register bits */ 387 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 388 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 389 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 390 391 #define WIL_DATA_COMPLETION_TO_MS 200 392 393 /* Hardware definitions end */ 394 #define SPARROW_FW_MAPPING_TABLE_SIZE 10 395 #define TALYN_FW_MAPPING_TABLE_SIZE 13 396 #define TALYN_MB_FW_MAPPING_TABLE_SIZE 19 397 #define MAX_FW_MAPPING_TABLE_SIZE 19 398 399 /* Common representation of physical address in wil ring */ 400 struct wil_ring_dma_addr { 401 __le32 addr_low; 402 __le16 addr_high; 403 } __packed; 404 405 struct fw_map { 406 u32 from; /* linker address - from, inclusive */ 407 u32 to; /* linker address - to, exclusive */ 408 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 409 const char *name; /* for debugfs */ 410 bool fw; /* true if FW mapping, false if UCODE mapping */ 411 bool crash_dump; /* true if should be dumped during crash dump */ 412 }; 413 414 /* array size should be in sync with actual definition in the wmi.c */ 415 extern const struct fw_map sparrow_fw_mapping[SPARROW_FW_MAPPING_TABLE_SIZE]; 416 extern const struct fw_map sparrow_d0_mac_rgf_ext; 417 extern const struct fw_map talyn_fw_mapping[TALYN_FW_MAPPING_TABLE_SIZE]; 418 extern const struct fw_map talyn_mb_fw_mapping[TALYN_MB_FW_MAPPING_TABLE_SIZE]; 419 extern struct fw_map fw_mapping[MAX_FW_MAPPING_TABLE_SIZE]; 420 421 /** 422 * mk_cidxtid - construct @cidxtid field 423 * @cid: CID value 424 * @tid: TID value 425 * 426 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 427 */ 428 static inline u8 mk_cidxtid(u8 cid, u8 tid) 429 { 430 return ((tid & 0xf) << 4) | (cid & 0xf); 431 } 432 433 /** 434 * parse_cidxtid - parse @cidxtid field 435 * @cid: store CID value here 436 * @tid: store TID value here 437 * 438 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 439 */ 440 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 441 { 442 *cid = cidxtid & 0xf; 443 *tid = (cidxtid >> 4) & 0xf; 444 } 445 446 struct wil6210_mbox_ring { 447 u32 base; 448 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 449 u16 size; 450 u32 tail; 451 u32 head; 452 } __packed; 453 454 struct wil6210_mbox_ring_desc { 455 __le32 sync; 456 __le32 addr; 457 } __packed; 458 459 /* at HOST_OFF_WIL6210_MBOX_CTL */ 460 struct wil6210_mbox_ctl { 461 struct wil6210_mbox_ring tx; 462 struct wil6210_mbox_ring rx; 463 } __packed; 464 465 struct wil6210_mbox_hdr { 466 __le16 seq; 467 __le16 len; /* payload, bytes after this header */ 468 __le16 type; 469 u8 flags; 470 u8 reserved; 471 } __packed; 472 473 #define WIL_MBOX_HDR_TYPE_WMI (0) 474 475 /* max. value for wil6210_mbox_hdr.len */ 476 #define MAX_MBOXITEM_SIZE (240) 477 478 struct pending_wmi_event { 479 struct list_head list; 480 struct { 481 struct wil6210_mbox_hdr hdr; 482 struct wmi_cmd_hdr wmi; 483 u8 data[0]; 484 } __packed event; 485 }; 486 487 enum { /* for wil_ctx.mapped_as */ 488 wil_mapped_as_none = 0, 489 wil_mapped_as_single = 1, 490 wil_mapped_as_page = 2, 491 }; 492 493 /** 494 * struct wil_ctx - software context for ring descriptor 495 */ 496 struct wil_ctx { 497 struct sk_buff *skb; 498 u8 nr_frags; 499 u8 mapped_as; 500 }; 501 502 struct wil_desc_ring_rx_swtail { /* relevant for enhanced DMA only */ 503 u32 *va; 504 dma_addr_t pa; 505 }; 506 507 /** 508 * A general ring structure, used for RX and TX. 509 * In legacy DMA it represents the vring, 510 * In enahnced DMA it represents the descriptor ring (vrings are handled by FW) 511 */ 512 struct wil_ring { 513 dma_addr_t pa; 514 volatile union wil_ring_desc *va; 515 u16 size; /* number of wil_ring_desc elements */ 516 u32 swtail; 517 u32 swhead; 518 u32 hwtail; /* write here to inform hw */ 519 struct wil_ctx *ctx; /* ctx[size] - software context */ 520 struct wil_desc_ring_rx_swtail edma_rx_swtail; 521 bool is_rx; 522 }; 523 524 /** 525 * Additional data for Rx ring. 526 * Used for enhanced DMA RX chaining. 527 */ 528 struct wil_ring_rx_data { 529 /* the skb being assembled */ 530 struct sk_buff *skb; 531 /* true if we are skipping a bad fragmented packet */ 532 bool skipping; 533 u16 buff_size; 534 }; 535 536 /** 537 * Status ring structure, used for enhanced DMA completions for RX and TX. 538 */ 539 struct wil_status_ring { 540 dma_addr_t pa; 541 void *va; /* pointer to ring_[tr]x_status elements */ 542 u16 size; /* number of status elements */ 543 size_t elem_size; /* status element size in bytes */ 544 u32 swhead; 545 u32 hwtail; /* write here to inform hw */ 546 bool is_rx; 547 u8 desc_rdy_pol; /* Expected descriptor ready bit polarity */ 548 struct wil_ring_rx_data rx_data; 549 }; 550 551 #define WIL_STA_TID_NUM (16) 552 #define WIL_MCS_MAX (12) /* Maximum MCS supported */ 553 554 struct wil_net_stats { 555 unsigned long rx_packets; 556 unsigned long tx_packets; 557 unsigned long rx_bytes; 558 unsigned long tx_bytes; 559 unsigned long tx_errors; 560 u32 tx_latency_min_us; 561 u32 tx_latency_max_us; 562 u64 tx_latency_total_us; 563 unsigned long rx_dropped; 564 unsigned long rx_non_data_frame; 565 unsigned long rx_short_frame; 566 unsigned long rx_large_frame; 567 unsigned long rx_replay; 568 unsigned long rx_mic_error; 569 unsigned long rx_key_error; /* eDMA specific */ 570 unsigned long rx_amsdu_error; /* eDMA specific */ 571 unsigned long rx_csum_err; 572 u16 last_mcs_rx; 573 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 574 }; 575 576 /** 577 * struct tx_rx_ops - different TX/RX ops for legacy and enhanced 578 * DMA flow 579 */ 580 struct wil_txrx_ops { 581 void (*configure_interrupt_moderation)(struct wil6210_priv *wil); 582 /* TX ops */ 583 int (*ring_init_tx)(struct wil6210_vif *vif, int ring_id, 584 int size, int cid, int tid); 585 void (*ring_fini_tx)(struct wil6210_priv *wil, struct wil_ring *ring); 586 int (*ring_init_bcast)(struct wil6210_vif *vif, int id, int size); 587 int (*tx_init)(struct wil6210_priv *wil); 588 void (*tx_fini)(struct wil6210_priv *wil); 589 int (*tx_desc_map)(union wil_tx_desc *desc, dma_addr_t pa, 590 u32 len, int ring_index); 591 void (*tx_desc_unmap)(struct device *dev, 592 union wil_tx_desc *desc, 593 struct wil_ctx *ctx); 594 int (*tx_ring_tso)(struct wil6210_priv *wil, struct wil6210_vif *vif, 595 struct wil_ring *ring, struct sk_buff *skb); 596 irqreturn_t (*irq_tx)(int irq, void *cookie); 597 /* RX ops */ 598 int (*rx_init)(struct wil6210_priv *wil, u16 ring_size); 599 void (*rx_fini)(struct wil6210_priv *wil); 600 int (*wmi_addba_rx_resp)(struct wil6210_priv *wil, u8 mid, u8 cid, 601 u8 tid, u8 token, u16 status, bool amsdu, 602 u16 agg_wsize, u16 timeout); 603 void (*get_reorder_params)(struct wil6210_priv *wil, 604 struct sk_buff *skb, int *tid, int *cid, 605 int *mid, u16 *seq, int *mcast, int *retry); 606 void (*get_netif_rx_params)(struct sk_buff *skb, 607 int *cid, int *security); 608 int (*rx_crypto_check)(struct wil6210_priv *wil, struct sk_buff *skb); 609 int (*rx_error_check)(struct wil6210_priv *wil, struct sk_buff *skb, 610 struct wil_net_stats *stats); 611 bool (*is_rx_idle)(struct wil6210_priv *wil); 612 irqreturn_t (*irq_rx)(int irq, void *cookie); 613 }; 614 615 /** 616 * Additional data for Tx ring 617 */ 618 struct wil_ring_tx_data { 619 bool dot1x_open; 620 int enabled; 621 cycles_t idle, last_idle, begin; 622 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 623 u16 agg_timeout; 624 u8 agg_amsdu; 625 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 626 u8 mid; 627 spinlock_t lock; 628 }; 629 630 enum { /* for wil6210_priv.status */ 631 wil_status_fwready = 0, /* FW operational */ 632 wil_status_dontscan, 633 wil_status_mbox_ready, /* MBOX structures ready */ 634 wil_status_irqen, /* interrupts enabled - for debug */ 635 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 636 wil_status_resetting, /* reset in progress */ 637 wil_status_suspending, /* suspend in progress */ 638 wil_status_suspended, /* suspend completed, device is suspended */ 639 wil_status_resuming, /* resume in progress */ 640 wil_status_collecting_dumps, /* crashdump collection in progress */ 641 wil_status_last /* keep last */ 642 }; 643 644 struct pci_dev; 645 646 /** 647 * struct tid_ampdu_rx - TID aggregation information (Rx). 648 * 649 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 650 * @last_rx: jiffies of last rx activity 651 * @head_seq_num: head sequence number in reordering buffer. 652 * @stored_mpdu_num: number of MPDUs in reordering buffer 653 * @ssn: Starting Sequence Number expected to be aggregated. 654 * @buf_size: buffer size for incoming A-MPDUs 655 * @ssn_last_drop: SSN of the last dropped frame 656 * @total: total number of processed incoming frames 657 * @drop_dup: duplicate frames dropped for this reorder buffer 658 * @drop_old: old frames dropped for this reorder buffer 659 * @first_time: true when this buffer used 1-st time 660 * @mcast_last_seq: sequence number (SN) of last received multicast packet 661 * @drop_dup_mcast: duplicate multicast frames dropped for this reorder buffer 662 */ 663 struct wil_tid_ampdu_rx { 664 struct sk_buff **reorder_buf; 665 unsigned long last_rx; 666 u16 head_seq_num; 667 u16 stored_mpdu_num; 668 u16 ssn; 669 u16 buf_size; 670 u16 ssn_last_drop; 671 unsigned long long total; /* frames processed */ 672 unsigned long long drop_dup; 673 unsigned long long drop_old; 674 bool first_time; /* is it 1-st time this buffer used? */ 675 u16 mcast_last_seq; /* multicast dup detection */ 676 unsigned long long drop_dup_mcast; 677 }; 678 679 /** 680 * struct wil_tid_crypto_rx_single - TID crypto information (Rx). 681 * 682 * @pn: GCMP PN for the session 683 * @key_set: valid key present 684 */ 685 struct wil_tid_crypto_rx_single { 686 u8 pn[IEEE80211_GCMP_PN_LEN]; 687 bool key_set; 688 }; 689 690 struct wil_tid_crypto_rx { 691 struct wil_tid_crypto_rx_single key_id[4]; 692 }; 693 694 struct wil_p2p_info { 695 struct ieee80211_channel listen_chan; 696 u8 discovery_started; 697 u64 cookie; 698 struct wireless_dev *pending_listen_wdev; 699 unsigned int listen_duration; 700 struct timer_list discovery_timer; /* listen/search duration */ 701 struct work_struct discovery_expired_work; /* listen/search expire */ 702 struct work_struct delayed_listen_work; /* listen after scan done */ 703 }; 704 705 enum wil_sta_status { 706 wil_sta_unused = 0, 707 wil_sta_conn_pending = 1, 708 wil_sta_connected = 2, 709 }; 710 711 /** 712 * struct wil_sta_info - data for peer 713 * 714 * Peer identified by its CID (connection ID) 715 * NIC performs beam forming for each peer; 716 * if no beam forming done, frame exchange is not 717 * possible. 718 */ 719 struct wil_sta_info { 720 u8 addr[ETH_ALEN]; 721 u8 mid; 722 enum wil_sta_status status; 723 struct wil_net_stats stats; 724 /** 725 * 20 latency bins. 1st bin counts packets with latency 726 * of 0..tx_latency_res, last bin counts packets with latency 727 * of 19*tx_latency_res and above. 728 * tx_latency_res is configured from "tx_latency" debug-fs. 729 */ 730 u64 *tx_latency_bins; 731 /* Rx BACK */ 732 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 733 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 734 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 735 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 736 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM]; 737 struct wil_tid_crypto_rx group_crypto_rx; 738 u8 aid; /* 1-254; 0 if unknown/not reported */ 739 }; 740 741 enum { 742 fw_recovery_idle = 0, 743 fw_recovery_pending = 1, 744 fw_recovery_running = 2, 745 }; 746 747 enum { 748 hw_capa_no_flash, 749 hw_capa_last 750 }; 751 752 struct wil_probe_client_req { 753 struct list_head list; 754 u64 cookie; 755 u8 cid; 756 }; 757 758 struct pmc_ctx { 759 /* alloc, free, and read operations must own the lock */ 760 struct mutex lock; 761 struct vring_tx_desc *pring_va; 762 dma_addr_t pring_pa; 763 struct desc_alloc_info *descriptors; 764 int last_cmd_status; 765 int num_descriptors; 766 int descriptor_size; 767 }; 768 769 struct wil_halp { 770 struct mutex lock; /* protect halp ref_cnt */ 771 unsigned int ref_cnt; 772 struct completion comp; 773 }; 774 775 struct wil_blob_wrapper { 776 struct wil6210_priv *wil; 777 struct debugfs_blob_wrapper blob; 778 }; 779 780 #define WIL_LED_MAX_ID (2) 781 #define WIL_LED_INVALID_ID (0xF) 782 #define WIL_LED_BLINK_ON_SLOW_MS (300) 783 #define WIL_LED_BLINK_OFF_SLOW_MS (300) 784 #define WIL_LED_BLINK_ON_MED_MS (200) 785 #define WIL_LED_BLINK_OFF_MED_MS (200) 786 #define WIL_LED_BLINK_ON_FAST_MS (100) 787 #define WIL_LED_BLINK_OFF_FAST_MS (100) 788 enum { 789 WIL_LED_TIME_SLOW = 0, 790 WIL_LED_TIME_MED, 791 WIL_LED_TIME_FAST, 792 WIL_LED_TIME_LAST, 793 }; 794 795 struct blink_on_off_time { 796 u32 on_ms; 797 u32 off_ms; 798 }; 799 800 struct wil_debugfs_iomem_data { 801 void *offset; 802 struct wil6210_priv *wil; 803 }; 804 805 struct wil_debugfs_data { 806 struct wil_debugfs_iomem_data *data_arr; 807 int iomem_data_count; 808 }; 809 810 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST]; 811 extern u8 led_id; 812 extern u8 led_polarity; 813 814 enum wil6210_vif_status { 815 wil_vif_fwconnecting, 816 wil_vif_fwconnected, 817 wil_vif_status_last /* keep last */ 818 }; 819 820 struct wil6210_vif { 821 struct wireless_dev wdev; 822 struct net_device *ndev; 823 struct wil6210_priv *wil; 824 u8 mid; 825 DECLARE_BITMAP(status, wil_vif_status_last); 826 u32 privacy; /* secure connection? */ 827 u16 channel; /* relevant in AP mode */ 828 u8 hidden_ssid; /* relevant in AP mode */ 829 u32 ap_isolate; /* no intra-BSS communication */ 830 bool pbss; 831 int bcast_ring; 832 struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */ 833 int locally_generated_disc; /* relevant in STA mode */ 834 struct timer_list connect_timer; 835 struct work_struct disconnect_worker; 836 /* scan */ 837 struct cfg80211_scan_request *scan_request; 838 struct timer_list scan_timer; /* detect scan timeout */ 839 struct wil_p2p_info p2p; 840 /* keep alive */ 841 struct list_head probe_client_pending; 842 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 843 struct work_struct probe_client_worker; 844 int net_queue_stopped; /* netif_tx_stop_all_queues invoked */ 845 }; 846 847 /** 848 * RX buffer allocated for enhanced DMA RX descriptors 849 */ 850 struct wil_rx_buff { 851 struct sk_buff *skb; 852 struct list_head list; 853 int id; 854 }; 855 856 /** 857 * During Rx completion processing, the driver extracts a buffer ID which 858 * is used as an index to the rx_buff_mgmt.buff_arr array and then the SKB 859 * is given to the network stack and the buffer is moved from the 'active' 860 * list to the 'free' list. 861 * During Rx refill, SKBs are attached to free buffers and moved to the 862 * 'active' list. 863 */ 864 struct wil_rx_buff_mgmt { 865 struct wil_rx_buff *buff_arr; 866 size_t size; /* number of items in buff_arr */ 867 struct list_head active; 868 struct list_head free; 869 unsigned long free_list_empty_cnt; /* statistics */ 870 }; 871 872 struct wil6210_priv { 873 struct pci_dev *pdev; 874 u32 bar_size; 875 struct wiphy *wiphy; 876 struct net_device *main_ndev; 877 int n_msi; 878 void __iomem *csr; 879 DECLARE_BITMAP(status, wil_status_last); 880 u8 fw_version[ETHTOOL_FWVERS_LEN]; 881 u32 hw_version; 882 u8 chip_revision; 883 const char *hw_name; 884 const char *wil_fw_name; 885 char *board_file; 886 u32 brd_file_addr; 887 u32 brd_file_max_size; 888 DECLARE_BITMAP(hw_capa, hw_capa_last); 889 DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX); 890 DECLARE_BITMAP(platform_capa, WIL_PLATFORM_CAPA_MAX); 891 u32 recovery_count; /* num of FW recovery attempts in a short time */ 892 u32 recovery_state; /* FW recovery state machine */ 893 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 894 wait_queue_head_t wq; /* for all wait_event() use */ 895 u8 max_vifs; /* maximum number of interfaces, including main */ 896 struct wil6210_vif *vifs[WIL_MAX_VIFS]; 897 struct mutex vif_mutex; /* protects access to VIF entries */ 898 atomic_t connected_vifs; 899 /* profile */ 900 struct cfg80211_chan_def monitor_chandef; 901 u32 monitor_flags; 902 int sinfo_gen; 903 /* interrupt moderation */ 904 u32 tx_max_burst_duration; 905 u32 tx_interframe_timeout; 906 u32 rx_max_burst_duration; 907 u32 rx_interframe_timeout; 908 /* cached ISR registers */ 909 u32 isr_misc; 910 /* mailbox related */ 911 struct mutex wmi_mutex; 912 struct wil6210_mbox_ctl mbox_ctl; 913 struct completion wmi_ready; 914 struct completion wmi_call; 915 u16 wmi_seq; 916 u16 reply_id; /**< wait for this WMI event */ 917 u8 reply_mid; 918 void *reply_buf; 919 u16 reply_size; 920 struct workqueue_struct *wmi_wq; /* for deferred calls */ 921 struct work_struct wmi_event_worker; 922 struct workqueue_struct *wq_service; 923 struct work_struct fw_error_worker; /* for FW error recovery */ 924 struct list_head pending_wmi_ev; 925 /* 926 * protect pending_wmi_ev 927 * - fill in IRQ from wil6210_irq_misc, 928 * - consumed in thread by wmi_event_worker 929 */ 930 spinlock_t wmi_ev_lock; 931 spinlock_t net_queue_lock; /* guarding stop/wake netif queue */ 932 struct napi_struct napi_rx; 933 struct napi_struct napi_tx; 934 struct net_device napi_ndev; /* dummy net_device serving all VIFs */ 935 936 /* DMA related */ 937 struct wil_ring ring_rx; 938 unsigned int rx_buf_len; 939 struct wil_ring ring_tx[WIL6210_MAX_TX_RINGS]; 940 struct wil_ring_tx_data ring_tx_data[WIL6210_MAX_TX_RINGS]; 941 struct wil_status_ring srings[WIL6210_MAX_STATUS_RINGS]; 942 u8 num_rx_status_rings; 943 int tx_sring_idx; 944 u8 ring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 945 struct wil_sta_info sta[WIL6210_MAX_CID]; 946 u32 ring_idle_trsh; /* HW fetches up to 16 descriptors at once */ 947 u32 dma_addr_size; /* indicates dma addr size */ 948 struct wil_rx_buff_mgmt rx_buff_mgmt; 949 bool use_enhanced_dma_hw; 950 struct wil_txrx_ops txrx_ops; 951 952 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 953 /* statistics */ 954 atomic_t isr_count_rx, isr_count_tx; 955 /* debugfs */ 956 struct dentry *debug; 957 struct wil_blob_wrapper blobs[MAX_FW_MAPPING_TABLE_SIZE]; 958 u8 discovery_mode; 959 u8 abft_len; 960 u8 wakeup_trigger; 961 struct wil_suspend_stats suspend_stats; 962 struct wil_debugfs_data dbg_data; 963 bool tx_latency; /* collect TX latency measurements */ 964 size_t tx_latency_res; /* bin resolution in usec */ 965 966 void *platform_handle; 967 struct wil_platform_ops platform_ops; 968 bool keep_radio_on_during_sleep; 969 970 struct pmc_ctx pmc; 971 972 u8 p2p_dev_started; 973 974 /* P2P_DEVICE vif */ 975 struct wireless_dev *p2p_wdev; 976 struct wireless_dev *radio_wdev; 977 978 /* High Access Latency Policy voting */ 979 struct wil_halp halp; 980 981 enum wmi_ps_profile_type ps_profile; 982 983 int fw_calib_result; 984 985 struct notifier_block pm_notify; 986 987 bool suspend_resp_rcvd; 988 bool suspend_resp_comp; 989 u32 bus_request_kbps; 990 u32 bus_request_kbps_pre_suspend; 991 992 u32 rgf_fw_assert_code_addr; 993 u32 rgf_ucode_assert_code_addr; 994 u32 iccm_base; 995 996 /* relevant only for eDMA */ 997 bool use_compressed_rx_status; 998 u32 rx_status_ring_order; 999 u32 tx_status_ring_order; 1000 u32 rx_buff_id_count; 1001 bool amsdu_en; 1002 bool use_rx_hw_reordering; 1003 bool secured_boot; 1004 u8 boot_config; 1005 }; 1006 1007 #define wil_to_wiphy(i) (i->wiphy) 1008 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 1009 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 1010 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 1011 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 1012 #define ndev_to_vif(n) (struct wil6210_vif *)(netdev_priv(n)) 1013 #define vif_to_wil(v) (v->wil) 1014 #define vif_to_ndev(v) (v->ndev) 1015 #define vif_to_wdev(v) (&v->wdev) 1016 1017 static inline struct wil6210_vif *wdev_to_vif(struct wil6210_priv *wil, 1018 struct wireless_dev *wdev) 1019 { 1020 /* main interface is shared with P2P device */ 1021 if (wdev == wil->p2p_wdev) 1022 return ndev_to_vif(wil->main_ndev); 1023 else 1024 return container_of(wdev, struct wil6210_vif, wdev); 1025 } 1026 1027 static inline struct wireless_dev * 1028 vif_to_radio_wdev(struct wil6210_priv *wil, struct wil6210_vif *vif) 1029 { 1030 /* main interface is shared with P2P device */ 1031 if (vif->mid) 1032 return vif_to_wdev(vif); 1033 else 1034 return wil->radio_wdev; 1035 } 1036 1037 __printf(2, 3) 1038 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 1039 __printf(2, 3) 1040 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...); 1041 __printf(2, 3) 1042 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 1043 __printf(2, 3) 1044 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...); 1045 __printf(2, 3) 1046 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...); 1047 #define wil_dbg(wil, fmt, arg...) do { \ 1048 netdev_dbg(wil->main_ndev, fmt, ##arg); \ 1049 wil_dbg_trace(wil, fmt, ##arg); \ 1050 } while (0) 1051 1052 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 1053 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 1054 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 1055 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 1056 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 1057 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg) 1058 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg) 1059 #define wil_err_ratelimited(wil, fmt, arg...) \ 1060 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg) 1061 1062 /* target operations */ 1063 /* register read */ 1064 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 1065 { 1066 return readl(wil->csr + HOSTADDR(reg)); 1067 } 1068 1069 /* register write. wmb() to make sure it is completed */ 1070 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 1071 { 1072 writel(val, wil->csr + HOSTADDR(reg)); 1073 wmb(); /* wait for write to propagate to the HW */ 1074 } 1075 1076 /* register set = read, OR, write */ 1077 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 1078 { 1079 wil_w(wil, reg, wil_r(wil, reg) | val); 1080 } 1081 1082 /* register clear = read, AND with inverted, write */ 1083 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 1084 { 1085 wil_w(wil, reg, wil_r(wil, reg) & ~val); 1086 } 1087 1088 #if defined(CONFIG_DYNAMIC_DEBUG) 1089 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 1090 groupsize, buf, len, ascii) \ 1091 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 1092 prefix_type, rowsize, \ 1093 groupsize, buf, len, ascii) 1094 1095 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 1096 groupsize, buf, len, ascii) \ 1097 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 1098 prefix_type, rowsize, \ 1099 groupsize, buf, len, ascii) 1100 1101 #define wil_hex_dump_misc(prefix_str, prefix_type, rowsize, \ 1102 groupsize, buf, len, ascii) \ 1103 print_hex_dump_debug("DBG[MISC]" prefix_str,\ 1104 prefix_type, rowsize, \ 1105 groupsize, buf, len, ascii) 1106 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 1107 static inline 1108 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 1109 int groupsize, const void *buf, size_t len, bool ascii) 1110 { 1111 } 1112 1113 static inline 1114 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 1115 int groupsize, const void *buf, size_t len, bool ascii) 1116 { 1117 } 1118 1119 static inline 1120 void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize, 1121 int groupsize, const void *buf, size_t len, bool ascii) 1122 { 1123 } 1124 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 1125 1126 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 1127 size_t count); 1128 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 1129 size_t count); 1130 1131 struct wil6210_vif * 1132 wil_vif_alloc(struct wil6210_priv *wil, const char *name, 1133 unsigned char name_assign_type, enum nl80211_iftype iftype); 1134 void wil_vif_free(struct wil6210_vif *vif); 1135 void *wil_if_alloc(struct device *dev); 1136 bool wil_has_other_active_ifaces(struct wil6210_priv *wil, 1137 struct net_device *ndev, bool up, bool ok); 1138 bool wil_has_active_ifaces(struct wil6210_priv *wil, bool up, bool ok); 1139 void wil_if_free(struct wil6210_priv *wil); 1140 int wil_vif_add(struct wil6210_priv *wil, struct wil6210_vif *vif); 1141 int wil_if_add(struct wil6210_priv *wil); 1142 void wil_vif_remove(struct wil6210_priv *wil, u8 mid); 1143 void wil_if_remove(struct wil6210_priv *wil); 1144 int wil_priv_init(struct wil6210_priv *wil); 1145 void wil_priv_deinit(struct wil6210_priv *wil); 1146 int wil_ps_update(struct wil6210_priv *wil, 1147 enum wmi_ps_profile_type ps_profile); 1148 int wil_reset(struct wil6210_priv *wil, bool no_fw); 1149 void wil_fw_error_recovery(struct wil6210_priv *wil); 1150 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 1151 bool wil_is_recovery_blocked(struct wil6210_priv *wil); 1152 int wil_up(struct wil6210_priv *wil); 1153 int __wil_up(struct wil6210_priv *wil); 1154 int wil_down(struct wil6210_priv *wil); 1155 int __wil_down(struct wil6210_priv *wil); 1156 void wil_refresh_fw_capabilities(struct wil6210_priv *wil); 1157 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 1158 int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac); 1159 void wil_set_ethtoolops(struct net_device *ndev); 1160 1161 struct fw_map *wil_find_fw_mapping(const char *section); 1162 void __iomem *wmi_buffer_block(struct wil6210_priv *wil, __le32 ptr, u32 size); 1163 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 1164 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 1165 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 1166 struct wil6210_mbox_hdr *hdr); 1167 int wmi_send(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len); 1168 void wmi_recv_cmd(struct wil6210_priv *wil); 1169 int wmi_call(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len, 1170 u16 reply_id, void *reply, u16 reply_size, int to_msec); 1171 void wmi_event_worker(struct work_struct *work); 1172 void wmi_event_flush(struct wil6210_priv *wil); 1173 int wmi_set_ssid(struct wil6210_vif *vif, u8 ssid_len, const void *ssid); 1174 int wmi_get_ssid(struct wil6210_vif *vif, u8 *ssid_len, void *ssid); 1175 int wmi_set_channel(struct wil6210_priv *wil, int channel); 1176 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 1177 int wmi_del_cipher_key(struct wil6210_vif *vif, u8 key_index, 1178 const void *mac_addr, int key_usage); 1179 int wmi_add_cipher_key(struct wil6210_vif *vif, u8 key_index, 1180 const void *mac_addr, int key_len, const void *key, 1181 int key_usage); 1182 int wmi_echo(struct wil6210_priv *wil); 1183 int wmi_set_ie(struct wil6210_vif *vif, u8 type, u16 ie_len, const void *ie); 1184 int wmi_rx_chain_add(struct wil6210_priv *wil, struct wil_ring *vring); 1185 int wmi_rxon(struct wil6210_priv *wil, bool on); 1186 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 1187 int wmi_disconnect_sta(struct wil6210_vif *vif, const u8 *mac, 1188 u16 reason, bool full_disconnect, bool del_sta); 1189 int wmi_addba(struct wil6210_priv *wil, u8 mid, 1190 u8 ringid, u8 size, u16 timeout); 1191 int wmi_delba_tx(struct wil6210_priv *wil, u8 mid, u8 ringid, u16 reason); 1192 int wmi_delba_rx(struct wil6210_priv *wil, u8 mid, u8 cidxtid, u16 reason); 1193 int wmi_addba_rx_resp(struct wil6210_priv *wil, 1194 u8 mid, u8 cid, u8 tid, u8 token, 1195 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 1196 int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, 1197 enum wmi_ps_profile_type ps_profile); 1198 int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short); 1199 int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short); 1200 int wmi_new_sta(struct wil6210_vif *vif, const u8 *mac, u8 aid); 1201 int wmi_port_allocate(struct wil6210_priv *wil, u8 mid, 1202 const u8 *mac, enum nl80211_iftype iftype); 1203 int wmi_port_delete(struct wil6210_priv *wil, u8 mid); 1204 int wil_addba_rx_request(struct wil6210_priv *wil, u8 mid, 1205 u8 cidxtid, u8 dialog_token, __le16 ba_param_set, 1206 __le16 ba_timeout, __le16 ba_seq_ctrl); 1207 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 1208 1209 void wil6210_clear_irq(struct wil6210_priv *wil); 1210 int wil6210_init_irq(struct wil6210_priv *wil, int irq); 1211 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 1212 void wil_mask_irq(struct wil6210_priv *wil); 1213 void wil_unmask_irq(struct wil6210_priv *wil); 1214 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 1215 void wil_disable_irq(struct wil6210_priv *wil); 1216 void wil_enable_irq(struct wil6210_priv *wil); 1217 void wil6210_mask_halp(struct wil6210_priv *wil); 1218 1219 /* P2P */ 1220 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); 1221 int wil_p2p_search(struct wil6210_vif *vif, 1222 struct cfg80211_scan_request *request); 1223 int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, 1224 unsigned int duration, struct ieee80211_channel *chan, 1225 u64 *cookie); 1226 u8 wil_p2p_stop_discovery(struct wil6210_vif *vif); 1227 int wil_p2p_cancel_listen(struct wil6210_vif *vif, u64 cookie); 1228 void wil_p2p_listen_expired(struct work_struct *work); 1229 void wil_p2p_search_expired(struct work_struct *work); 1230 void wil_p2p_stop_radio_operations(struct wil6210_priv *wil); 1231 void wil_p2p_delayed_listen_work(struct work_struct *work); 1232 1233 /* WMI for P2P */ 1234 int wmi_p2p_cfg(struct wil6210_vif *vif, int channel, int bi); 1235 int wmi_start_listen(struct wil6210_vif *vif); 1236 int wmi_start_search(struct wil6210_vif *vif); 1237 int wmi_stop_discovery(struct wil6210_vif *vif); 1238 1239 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 1240 struct cfg80211_mgmt_tx_params *params, 1241 u64 *cookie); 1242 int wil_cfg80211_iface_combinations_from_fw( 1243 struct wil6210_priv *wil, 1244 const struct wil_fw_record_concurrency *conc); 1245 int wil_vif_prepare_stop(struct wil6210_vif *vif); 1246 1247 #if defined(CONFIG_WIL6210_DEBUGFS) 1248 int wil6210_debugfs_init(struct wil6210_priv *wil); 1249 void wil6210_debugfs_remove(struct wil6210_priv *wil); 1250 #else 1251 static inline int wil6210_debugfs_init(struct wil6210_priv *wil) { return 0; } 1252 static inline void wil6210_debugfs_remove(struct wil6210_priv *wil) {} 1253 #endif 1254 1255 int wil_cid_fill_sinfo(struct wil6210_vif *vif, int cid, 1256 struct station_info *sinfo); 1257 1258 struct wil6210_priv *wil_cfg80211_init(struct device *dev); 1259 void wil_cfg80211_deinit(struct wil6210_priv *wil); 1260 void wil_p2p_wdev_free(struct wil6210_priv *wil); 1261 1262 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 1263 int wmi_pcp_start(struct wil6210_vif *vif, int bi, u8 wmi_nettype, u8 chan, 1264 u8 hidden_ssid, u8 is_go); 1265 int wmi_pcp_stop(struct wil6210_vif *vif); 1266 int wmi_led_cfg(struct wil6210_priv *wil, bool enable); 1267 int wmi_abort_scan(struct wil6210_vif *vif); 1268 void wil_abort_scan(struct wil6210_vif *vif, bool sync); 1269 void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync); 1270 void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps); 1271 void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid, 1272 u16 reason_code, bool from_event); 1273 void wil_probe_client_flush(struct wil6210_vif *vif); 1274 void wil_probe_client_worker(struct work_struct *work); 1275 void wil_disconnect_worker(struct work_struct *work); 1276 1277 void wil_init_txrx_ops(struct wil6210_priv *wil); 1278 1279 /* TX API */ 1280 int wil_ring_init_tx(struct wil6210_vif *vif, int cid); 1281 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size); 1282 int wil_bcast_init(struct wil6210_vif *vif); 1283 void wil_bcast_fini(struct wil6210_vif *vif); 1284 void wil_bcast_fini_all(struct wil6210_priv *wil); 1285 1286 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif, 1287 struct wil_ring *ring, bool should_stop); 1288 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif, 1289 struct wil_ring *ring, bool check_stop); 1290 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 1291 int wil_tx_complete(struct wil6210_vif *vif, int ringid); 1292 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 1293 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil); 1294 1295 /* RX API */ 1296 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 1297 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 1298 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil); 1299 1300 int wil_iftype_nl2wmi(enum nl80211_iftype type); 1301 1302 int wil_request_firmware(struct wil6210_priv *wil, const char *name, 1303 bool load); 1304 int wil_request_board(struct wil6210_priv *wil, const char *name); 1305 bool wil_fw_verify_file_exists(struct wil6210_priv *wil, const char *name); 1306 1307 void wil_pm_runtime_allow(struct wil6210_priv *wil); 1308 void wil_pm_runtime_forbid(struct wil6210_priv *wil); 1309 int wil_pm_runtime_get(struct wil6210_priv *wil); 1310 void wil_pm_runtime_put(struct wil6210_priv *wil); 1311 1312 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 1313 int wil_suspend(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1314 int wil_resume(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1315 bool wil_is_wmi_idle(struct wil6210_priv *wil); 1316 int wmi_resume(struct wil6210_priv *wil); 1317 int wmi_suspend(struct wil6210_priv *wil); 1318 bool wil_is_tx_idle(struct wil6210_priv *wil); 1319 1320 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size); 1321 void wil_fw_core_dump(struct wil6210_priv *wil); 1322 1323 void wil_halp_vote(struct wil6210_priv *wil); 1324 void wil_halp_unvote(struct wil6210_priv *wil); 1325 void wil6210_set_halp(struct wil6210_priv *wil); 1326 void wil6210_clear_halp(struct wil6210_priv *wil); 1327 1328 int wmi_start_sched_scan(struct wil6210_priv *wil, 1329 struct cfg80211_sched_scan_request *request); 1330 int wmi_stop_sched_scan(struct wil6210_priv *wil); 1331 int wmi_mgmt_tx(struct wil6210_vif *vif, const u8 *buf, size_t len); 1332 1333 int reverse_memcmp(const void *cs, const void *ct, size_t count); 1334 1335 /* WMI for enhanced DMA */ 1336 int wil_wmi_tx_sring_cfg(struct wil6210_priv *wil, int ring_id); 1337 int wil_wmi_cfg_def_rx_offload(struct wil6210_priv *wil, 1338 u16 max_rx_pl_per_desc); 1339 int wil_wmi_rx_sring_add(struct wil6210_priv *wil, u16 ring_id); 1340 int wil_wmi_rx_desc_ring_add(struct wil6210_priv *wil, int status_ring_id); 1341 int wil_wmi_tx_desc_ring_add(struct wil6210_vif *vif, int ring_id, int cid, 1342 int tid); 1343 int wil_wmi_bcast_desc_ring_add(struct wil6210_vif *vif, int ring_id); 1344 int wmi_addba_rx_resp_edma(struct wil6210_priv *wil, u8 mid, u8 cid, 1345 u8 tid, u8 token, u16 status, bool amsdu, 1346 u16 agg_wsize, u16 timeout); 1347 1348 #endif /* __WIL6210_H__ */ 1349