1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 23 { 24 /* 25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 26 * 0 for no restriction 27 * 1 for 1/4 us 28 * 2 for 1/2 us 29 * 3 for 1 us 30 * 4 for 2 us 31 * 5 for 4 us 32 * 6 for 8 us 33 * 7 for 16 us 34 */ 35 switch (mpdudensity) { 36 case 0: 37 return 0; 38 case 1: 39 case 2: 40 case 3: 41 /* Our lower layer calculations limit our precision to 42 1 microsecond */ 43 return 1; 44 case 4: 45 return 2; 46 case 5: 47 return 4; 48 case 6: 49 return 8; 50 case 7: 51 return 16; 52 default: 53 return 0; 54 } 55 } 56 57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 58 { 59 bool pending = false; 60 61 spin_lock_bh(&txq->axq_lock); 62 63 if (txq->axq_depth) 64 pending = true; 65 66 if (txq->mac80211_qnum >= 0) { 67 struct list_head *list; 68 69 list = &sc->cur_chan->acq[txq->mac80211_qnum]; 70 if (!list_empty(list)) 71 pending = true; 72 } 73 spin_unlock_bh(&txq->axq_lock); 74 return pending; 75 } 76 77 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 78 { 79 unsigned long flags; 80 bool ret; 81 82 spin_lock_irqsave(&sc->sc_pm_lock, flags); 83 ret = ath9k_hw_setpower(sc->sc_ah, mode); 84 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 85 86 return ret; 87 } 88 89 void ath_ps_full_sleep(unsigned long data) 90 { 91 struct ath_softc *sc = (struct ath_softc *) data; 92 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 93 bool reset; 94 95 spin_lock(&common->cc_lock); 96 ath_hw_cycle_counters_update(common); 97 spin_unlock(&common->cc_lock); 98 99 ath9k_hw_setrxabort(sc->sc_ah, 1); 100 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 101 102 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 103 } 104 105 void ath9k_ps_wakeup(struct ath_softc *sc) 106 { 107 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 108 unsigned long flags; 109 enum ath9k_power_mode power_mode; 110 111 spin_lock_irqsave(&sc->sc_pm_lock, flags); 112 if (++sc->ps_usecount != 1) 113 goto unlock; 114 115 del_timer_sync(&sc->sleep_timer); 116 power_mode = sc->sc_ah->power_mode; 117 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 118 119 /* 120 * While the hardware is asleep, the cycle counters contain no 121 * useful data. Better clear them now so that they don't mess up 122 * survey data results. 123 */ 124 if (power_mode != ATH9K_PM_AWAKE) { 125 spin_lock(&common->cc_lock); 126 ath_hw_cycle_counters_update(common); 127 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 128 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 129 spin_unlock(&common->cc_lock); 130 } 131 132 unlock: 133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 134 } 135 136 void ath9k_ps_restore(struct ath_softc *sc) 137 { 138 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 139 enum ath9k_power_mode mode; 140 unsigned long flags; 141 142 spin_lock_irqsave(&sc->sc_pm_lock, flags); 143 if (--sc->ps_usecount != 0) 144 goto unlock; 145 146 if (sc->ps_idle) { 147 mod_timer(&sc->sleep_timer, jiffies + HZ / 10); 148 goto unlock; 149 } 150 151 if (sc->ps_enabled && 152 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 153 PS_WAIT_FOR_CAB | 154 PS_WAIT_FOR_PSPOLL_DATA | 155 PS_WAIT_FOR_TX_ACK | 156 PS_WAIT_FOR_ANI))) { 157 mode = ATH9K_PM_NETWORK_SLEEP; 158 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 159 ath9k_btcoex_stop_gen_timer(sc); 160 } else { 161 goto unlock; 162 } 163 164 spin_lock(&common->cc_lock); 165 ath_hw_cycle_counters_update(common); 166 spin_unlock(&common->cc_lock); 167 168 ath9k_hw_setpower(sc->sc_ah, mode); 169 170 unlock: 171 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 172 } 173 174 static void __ath_cancel_work(struct ath_softc *sc) 175 { 176 cancel_work_sync(&sc->paprd_work); 177 cancel_delayed_work_sync(&sc->tx_complete_work); 178 cancel_delayed_work_sync(&sc->hw_pll_work); 179 180 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 181 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 182 cancel_work_sync(&sc->mci_work); 183 #endif 184 } 185 186 void ath_cancel_work(struct ath_softc *sc) 187 { 188 __ath_cancel_work(sc); 189 cancel_work_sync(&sc->hw_reset_work); 190 } 191 192 void ath_restart_work(struct ath_softc *sc) 193 { 194 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 195 196 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 197 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 198 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 199 200 ath_start_ani(sc); 201 } 202 203 static bool ath_prepare_reset(struct ath_softc *sc) 204 { 205 struct ath_hw *ah = sc->sc_ah; 206 bool ret = true; 207 208 ieee80211_stop_queues(sc->hw); 209 ath_stop_ani(sc); 210 ath9k_hw_disable_interrupts(ah); 211 212 if (!ath_drain_all_txq(sc)) 213 ret = false; 214 215 if (!ath_stoprecv(sc)) 216 ret = false; 217 218 return ret; 219 } 220 221 static bool ath_complete_reset(struct ath_softc *sc, bool start) 222 { 223 struct ath_hw *ah = sc->sc_ah; 224 struct ath_common *common = ath9k_hw_common(ah); 225 unsigned long flags; 226 int i; 227 228 if (ath_startrecv(sc) != 0) { 229 ath_err(common, "Unable to restart recv logic\n"); 230 return false; 231 } 232 233 ath9k_cmn_update_txpow(ah, sc->curtxpow, 234 sc->cur_chan->txpower, &sc->curtxpow); 235 236 clear_bit(ATH_OP_HW_RESET, &common->op_flags); 237 ath9k_calculate_summary_state(sc, sc->cur_chan); 238 239 if (!sc->cur_chan->offchannel && start) { 240 /* restore per chanctx TSF timer */ 241 if (sc->cur_chan->tsf_val) { 242 u32 offset; 243 244 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, 245 NULL); 246 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); 247 } 248 249 250 if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) 251 goto work; 252 253 if (ah->opmode == NL80211_IFTYPE_STATION && 254 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { 255 spin_lock_irqsave(&sc->sc_pm_lock, flags); 256 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 257 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 258 } else { 259 ath9k_set_beacon(sc); 260 } 261 work: 262 ath_restart_work(sc); 263 ath_txq_schedule_all(sc); 264 } 265 266 sc->gtt_cnt = 0; 267 268 ath9k_hw_set_interrupts(ah); 269 ath9k_hw_enable_interrupts(ah); 270 271 if (!ath9k_use_chanctx) 272 ieee80211_wake_queues(sc->hw); 273 else { 274 if (sc->cur_chan == &sc->offchannel.chan) 275 ieee80211_wake_queue(sc->hw, 276 sc->hw->offchannel_tx_hw_queue); 277 else { 278 for (i = 0; i < IEEE80211_NUM_ACS; i++) 279 ieee80211_wake_queue(sc->hw, 280 sc->cur_chan->hw_queue_base + i); 281 } 282 if (ah->opmode == NL80211_IFTYPE_AP) 283 ieee80211_wake_queue(sc->hw, sc->hw->queues - 2); 284 } 285 286 ath9k_p2p_ps_timer(sc); 287 288 return true; 289 } 290 291 int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 292 { 293 struct ath_hw *ah = sc->sc_ah; 294 struct ath_common *common = ath9k_hw_common(ah); 295 struct ath9k_hw_cal_data *caldata = NULL; 296 bool fastcc = true; 297 int r; 298 299 __ath_cancel_work(sc); 300 301 tasklet_disable(&sc->intr_tq); 302 spin_lock_bh(&sc->sc_pcu_lock); 303 304 if (!sc->cur_chan->offchannel) { 305 fastcc = false; 306 caldata = &sc->cur_chan->caldata; 307 } 308 309 if (!hchan) { 310 fastcc = false; 311 hchan = ah->curchan; 312 } 313 314 if (!ath_prepare_reset(sc)) 315 fastcc = false; 316 317 spin_lock_bh(&sc->chan_lock); 318 sc->cur_chandef = sc->cur_chan->chandef; 319 spin_unlock_bh(&sc->chan_lock); 320 321 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 322 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 323 324 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 325 if (r) { 326 ath_err(common, 327 "Unable to reset channel, reset status %d\n", r); 328 329 ath9k_hw_enable_interrupts(ah); 330 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 331 332 goto out; 333 } 334 335 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 336 sc->cur_chan->offchannel) 337 ath9k_mci_set_txpower(sc, true, false); 338 339 if (!ath_complete_reset(sc, true)) 340 r = -EIO; 341 342 out: 343 spin_unlock_bh(&sc->sc_pcu_lock); 344 tasklet_enable(&sc->intr_tq); 345 346 return r; 347 } 348 349 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 350 struct ieee80211_vif *vif) 351 { 352 struct ath_node *an; 353 an = (struct ath_node *)sta->drv_priv; 354 355 an->sc = sc; 356 an->sta = sta; 357 an->vif = vif; 358 memset(&an->key_idx, 0, sizeof(an->key_idx)); 359 360 ath_tx_node_init(sc, an); 361 } 362 363 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 364 { 365 struct ath_node *an = (struct ath_node *)sta->drv_priv; 366 ath_tx_node_cleanup(sc, an); 367 } 368 369 void ath9k_tasklet(unsigned long data) 370 { 371 struct ath_softc *sc = (struct ath_softc *)data; 372 struct ath_hw *ah = sc->sc_ah; 373 struct ath_common *common = ath9k_hw_common(ah); 374 enum ath_reset_type type; 375 unsigned long flags; 376 u32 status = sc->intrstatus; 377 u32 rxmask; 378 379 ath9k_ps_wakeup(sc); 380 spin_lock(&sc->sc_pcu_lock); 381 382 if (status & ATH9K_INT_FATAL) { 383 type = RESET_TYPE_FATAL_INT; 384 ath9k_queue_reset(sc, type); 385 386 /* 387 * Increment the ref. counter here so that 388 * interrupts are enabled in the reset routine. 389 */ 390 atomic_inc(&ah->intr_ref_cnt); 391 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); 392 goto out; 393 } 394 395 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 396 (status & ATH9K_INT_BB_WATCHDOG)) { 397 spin_lock(&common->cc_lock); 398 ath_hw_cycle_counters_update(common); 399 ar9003_hw_bb_watchdog_dbg_info(ah); 400 spin_unlock(&common->cc_lock); 401 402 if (ar9003_hw_bb_watchdog_check(ah)) { 403 type = RESET_TYPE_BB_WATCHDOG; 404 ath9k_queue_reset(sc, type); 405 406 /* 407 * Increment the ref. counter here so that 408 * interrupts are enabled in the reset routine. 409 */ 410 atomic_inc(&ah->intr_ref_cnt); 411 ath_dbg(common, RESET, 412 "BB_WATCHDOG: Skipping interrupts\n"); 413 goto out; 414 } 415 } 416 417 if (status & ATH9K_INT_GTT) { 418 sc->gtt_cnt++; 419 420 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { 421 type = RESET_TYPE_TX_GTT; 422 ath9k_queue_reset(sc, type); 423 atomic_inc(&ah->intr_ref_cnt); 424 ath_dbg(common, RESET, 425 "GTT: Skipping interrupts\n"); 426 goto out; 427 } 428 } 429 430 spin_lock_irqsave(&sc->sc_pm_lock, flags); 431 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 432 /* 433 * TSF sync does not look correct; remain awake to sync with 434 * the next Beacon. 435 */ 436 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 437 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 438 } 439 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 440 441 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 442 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 443 ATH9K_INT_RXORN); 444 else 445 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 446 447 if (status & rxmask) { 448 /* Check for high priority Rx first */ 449 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 450 (status & ATH9K_INT_RXHP)) 451 ath_rx_tasklet(sc, 0, true); 452 453 ath_rx_tasklet(sc, 0, false); 454 } 455 456 if (status & ATH9K_INT_TX) { 457 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 458 /* 459 * For EDMA chips, TX completion is enabled for the 460 * beacon queue, so if a beacon has been transmitted 461 * successfully after a GTT interrupt, the GTT counter 462 * gets reset to zero here. 463 */ 464 sc->gtt_cnt = 0; 465 466 ath_tx_edma_tasklet(sc); 467 } else { 468 ath_tx_tasklet(sc); 469 } 470 471 wake_up(&sc->tx_wait); 472 } 473 474 if (status & ATH9K_INT_GENTIMER) 475 ath_gen_timer_isr(sc->sc_ah); 476 477 ath9k_btcoex_handle_interrupt(sc, status); 478 479 /* re-enable hardware interrupt */ 480 ath9k_hw_enable_interrupts(ah); 481 out: 482 spin_unlock(&sc->sc_pcu_lock); 483 ath9k_ps_restore(sc); 484 } 485 486 irqreturn_t ath_isr(int irq, void *dev) 487 { 488 #define SCHED_INTR ( \ 489 ATH9K_INT_FATAL | \ 490 ATH9K_INT_BB_WATCHDOG | \ 491 ATH9K_INT_RXORN | \ 492 ATH9K_INT_RXEOL | \ 493 ATH9K_INT_RX | \ 494 ATH9K_INT_RXLP | \ 495 ATH9K_INT_RXHP | \ 496 ATH9K_INT_TX | \ 497 ATH9K_INT_BMISS | \ 498 ATH9K_INT_CST | \ 499 ATH9K_INT_GTT | \ 500 ATH9K_INT_TSFOOR | \ 501 ATH9K_INT_GENTIMER | \ 502 ATH9K_INT_MCI) 503 504 struct ath_softc *sc = dev; 505 struct ath_hw *ah = sc->sc_ah; 506 struct ath_common *common = ath9k_hw_common(ah); 507 enum ath9k_int status; 508 u32 sync_cause = 0; 509 bool sched = false; 510 511 /* 512 * The hardware is not ready/present, don't 513 * touch anything. Note this can happen early 514 * on if the IRQ is shared. 515 */ 516 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 517 return IRQ_NONE; 518 519 /* shared irq, not for us */ 520 521 if (!ath9k_hw_intrpend(ah)) 522 return IRQ_NONE; 523 524 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) { 525 ath9k_hw_kill_interrupts(ah); 526 return IRQ_HANDLED; 527 } 528 529 /* 530 * Figure out the reason(s) for the interrupt. Note 531 * that the hal returns a pseudo-ISR that may include 532 * bits we haven't explicitly enabled so we mask the 533 * value to insure we only process bits we requested. 534 */ 535 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ 536 ath9k_debug_sync_cause(sc, sync_cause); 537 status &= ah->imask; /* discard unasked-for bits */ 538 539 /* 540 * If there are no status bits set, then this interrupt was not 541 * for me (should have been caught above). 542 */ 543 if (!status) 544 return IRQ_NONE; 545 546 /* Cache the status */ 547 sc->intrstatus = status; 548 549 if (status & SCHED_INTR) 550 sched = true; 551 552 /* 553 * If a FATAL or RXORN interrupt is received, we have to reset the 554 * chip immediately. 555 */ 556 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 557 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 558 goto chip_reset; 559 560 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 561 (status & ATH9K_INT_BB_WATCHDOG)) 562 goto chip_reset; 563 564 #ifdef CONFIG_ATH9K_WOW 565 if (status & ATH9K_INT_BMISS) { 566 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 567 atomic_inc(&sc->wow_got_bmiss_intr); 568 atomic_dec(&sc->wow_sleep_proc_intr); 569 } 570 } 571 #endif 572 573 if (status & ATH9K_INT_SWBA) 574 tasklet_schedule(&sc->bcon_tasklet); 575 576 if (status & ATH9K_INT_TXURN) 577 ath9k_hw_updatetxtriglevel(ah, true); 578 579 if (status & ATH9K_INT_RXEOL) { 580 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 581 ath9k_hw_set_interrupts(ah); 582 } 583 584 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 585 if (status & ATH9K_INT_TIM_TIMER) { 586 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 587 goto chip_reset; 588 /* Clear RxAbort bit so that we can 589 * receive frames */ 590 ath9k_setpower(sc, ATH9K_PM_AWAKE); 591 spin_lock(&sc->sc_pm_lock); 592 ath9k_hw_setrxabort(sc->sc_ah, 0); 593 sc->ps_flags |= PS_WAIT_FOR_BEACON; 594 spin_unlock(&sc->sc_pm_lock); 595 } 596 597 chip_reset: 598 599 ath_debug_stat_interrupt(sc, status); 600 601 if (sched) { 602 /* turn off every interrupt */ 603 ath9k_hw_disable_interrupts(ah); 604 tasklet_schedule(&sc->intr_tq); 605 } 606 607 return IRQ_HANDLED; 608 609 #undef SCHED_INTR 610 } 611 612 int ath_reset(struct ath_softc *sc) 613 { 614 int r; 615 616 ath9k_ps_wakeup(sc); 617 r = ath_reset_internal(sc, NULL); 618 ath9k_ps_restore(sc); 619 620 return r; 621 } 622 623 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 624 { 625 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 626 #ifdef CONFIG_ATH9K_DEBUGFS 627 RESET_STAT_INC(sc, type); 628 #endif 629 set_bit(ATH_OP_HW_RESET, &common->op_flags); 630 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 631 } 632 633 void ath_reset_work(struct work_struct *work) 634 { 635 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 636 637 ath_reset(sc); 638 } 639 640 /**********************/ 641 /* mac80211 callbacks */ 642 /**********************/ 643 644 static int ath9k_start(struct ieee80211_hw *hw) 645 { 646 struct ath_softc *sc = hw->priv; 647 struct ath_hw *ah = sc->sc_ah; 648 struct ath_common *common = ath9k_hw_common(ah); 649 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; 650 struct ath_chanctx *ctx = sc->cur_chan; 651 struct ath9k_channel *init_channel; 652 int r; 653 654 ath_dbg(common, CONFIG, 655 "Starting driver with initial channel: %d MHz\n", 656 curchan->center_freq); 657 658 ath9k_ps_wakeup(sc); 659 mutex_lock(&sc->mutex); 660 661 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); 662 sc->cur_chandef = hw->conf.chandef; 663 664 /* Reset SERDES registers */ 665 ath9k_hw_configpcipowersave(ah, false); 666 667 /* 668 * The basic interface to setting the hardware in a good 669 * state is ``reset''. On return the hardware is known to 670 * be powered up and with interrupts disabled. This must 671 * be followed by initialization of the appropriate bits 672 * and then setup of the interrupt mask. 673 */ 674 spin_lock_bh(&sc->sc_pcu_lock); 675 676 atomic_set(&ah->intr_ref_cnt, -1); 677 678 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 679 if (r) { 680 ath_err(common, 681 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 682 r, curchan->center_freq); 683 ah->reset_power_on = false; 684 } 685 686 /* Setup our intr mask. */ 687 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 688 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 689 ATH9K_INT_GLOBAL; 690 691 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 692 ah->imask |= ATH9K_INT_RXHP | 693 ATH9K_INT_RXLP; 694 else 695 ah->imask |= ATH9K_INT_RX; 696 697 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) 698 ah->imask |= ATH9K_INT_BB_WATCHDOG; 699 700 /* 701 * Enable GTT interrupts only for AR9003/AR9004 chips 702 * for now. 703 */ 704 if (AR_SREV_9300_20_OR_LATER(ah)) 705 ah->imask |= ATH9K_INT_GTT; 706 707 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 708 ah->imask |= ATH9K_INT_CST; 709 710 ath_mci_enable(sc); 711 712 clear_bit(ATH_OP_INVALID, &common->op_flags); 713 sc->sc_ah->is_monitoring = false; 714 715 if (!ath_complete_reset(sc, false)) 716 ah->reset_power_on = false; 717 718 if (ah->led_pin >= 0) { 719 ath9k_hw_cfg_output(ah, ah->led_pin, 720 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 721 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 722 } 723 724 /* 725 * Reset key cache to sane defaults (all entries cleared) instead of 726 * semi-random values after suspend/resume. 727 */ 728 ath9k_cmn_init_crypto(sc->sc_ah); 729 730 ath9k_hw_reset_tsf(ah); 731 732 spin_unlock_bh(&sc->sc_pcu_lock); 733 734 mutex_unlock(&sc->mutex); 735 736 ath9k_ps_restore(sc); 737 738 return 0; 739 } 740 741 static void ath9k_tx(struct ieee80211_hw *hw, 742 struct ieee80211_tx_control *control, 743 struct sk_buff *skb) 744 { 745 struct ath_softc *sc = hw->priv; 746 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 747 struct ath_tx_control txctl; 748 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 749 unsigned long flags; 750 751 if (sc->ps_enabled) { 752 /* 753 * mac80211 does not set PM field for normal data frames, so we 754 * need to update that based on the current PS mode. 755 */ 756 if (ieee80211_is_data(hdr->frame_control) && 757 !ieee80211_is_nullfunc(hdr->frame_control) && 758 !ieee80211_has_pm(hdr->frame_control)) { 759 ath_dbg(common, PS, 760 "Add PM=1 for a TX frame while in PS mode\n"); 761 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 762 } 763 } 764 765 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 766 /* 767 * We are using PS-Poll and mac80211 can request TX while in 768 * power save mode. Need to wake up hardware for the TX to be 769 * completed and if needed, also for RX of buffered frames. 770 */ 771 ath9k_ps_wakeup(sc); 772 spin_lock_irqsave(&sc->sc_pm_lock, flags); 773 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 774 ath9k_hw_setrxabort(sc->sc_ah, 0); 775 if (ieee80211_is_pspoll(hdr->frame_control)) { 776 ath_dbg(common, PS, 777 "Sending PS-Poll to pick a buffered frame\n"); 778 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 779 } else { 780 ath_dbg(common, PS, "Wake up to complete TX\n"); 781 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 782 } 783 /* 784 * The actual restore operation will happen only after 785 * the ps_flags bit is cleared. We are just dropping 786 * the ps_usecount here. 787 */ 788 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 789 ath9k_ps_restore(sc); 790 } 791 792 /* 793 * Cannot tx while the hardware is in full sleep, it first needs a full 794 * chip reset to recover from that 795 */ 796 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 797 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 798 goto exit; 799 } 800 801 memset(&txctl, 0, sizeof(struct ath_tx_control)); 802 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 803 txctl.sta = control->sta; 804 805 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 806 807 if (ath_tx_start(hw, skb, &txctl) != 0) { 808 ath_dbg(common, XMIT, "TX failed\n"); 809 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 810 goto exit; 811 } 812 813 return; 814 exit: 815 ieee80211_free_txskb(hw, skb); 816 } 817 818 static void ath9k_stop(struct ieee80211_hw *hw) 819 { 820 struct ath_softc *sc = hw->priv; 821 struct ath_hw *ah = sc->sc_ah; 822 struct ath_common *common = ath9k_hw_common(ah); 823 bool prev_idle; 824 825 cancel_work_sync(&sc->chanctx_work); 826 mutex_lock(&sc->mutex); 827 828 ath_cancel_work(sc); 829 830 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 831 ath_dbg(common, ANY, "Device not present\n"); 832 mutex_unlock(&sc->mutex); 833 return; 834 } 835 836 /* Ensure HW is awake when we try to shut it down. */ 837 ath9k_ps_wakeup(sc); 838 839 spin_lock_bh(&sc->sc_pcu_lock); 840 841 /* prevent tasklets to enable interrupts once we disable them */ 842 ah->imask &= ~ATH9K_INT_GLOBAL; 843 844 /* make sure h/w will not generate any interrupt 845 * before setting the invalid flag. */ 846 ath9k_hw_disable_interrupts(ah); 847 848 spin_unlock_bh(&sc->sc_pcu_lock); 849 850 /* we can now sync irq and kill any running tasklets, since we already 851 * disabled interrupts and not holding a spin lock */ 852 synchronize_irq(sc->irq); 853 tasklet_kill(&sc->intr_tq); 854 tasklet_kill(&sc->bcon_tasklet); 855 856 prev_idle = sc->ps_idle; 857 sc->ps_idle = true; 858 859 spin_lock_bh(&sc->sc_pcu_lock); 860 861 if (ah->led_pin >= 0) { 862 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 863 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 864 } 865 866 ath_prepare_reset(sc); 867 868 if (sc->rx.frag) { 869 dev_kfree_skb_any(sc->rx.frag); 870 sc->rx.frag = NULL; 871 } 872 873 if (!ah->curchan) 874 ah->curchan = ath9k_cmn_get_channel(hw, ah, 875 &sc->cur_chan->chandef); 876 877 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 878 ath9k_hw_phy_disable(ah); 879 880 ath9k_hw_configpcipowersave(ah, true); 881 882 spin_unlock_bh(&sc->sc_pcu_lock); 883 884 ath9k_ps_restore(sc); 885 886 set_bit(ATH_OP_INVALID, &common->op_flags); 887 sc->ps_idle = prev_idle; 888 889 mutex_unlock(&sc->mutex); 890 891 ath_dbg(common, CONFIG, "Driver halt\n"); 892 } 893 894 static bool ath9k_uses_beacons(int type) 895 { 896 switch (type) { 897 case NL80211_IFTYPE_AP: 898 case NL80211_IFTYPE_ADHOC: 899 case NL80211_IFTYPE_MESH_POINT: 900 return true; 901 default: 902 return false; 903 } 904 } 905 906 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 907 { 908 struct ath9k_vif_iter_data *iter_data = data; 909 int i; 910 911 if (iter_data->has_hw_macaddr) { 912 for (i = 0; i < ETH_ALEN; i++) 913 iter_data->mask[i] &= 914 ~(iter_data->hw_macaddr[i] ^ mac[i]); 915 } else { 916 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 917 iter_data->has_hw_macaddr = true; 918 } 919 920 if (!vif->bss_conf.use_short_slot) 921 iter_data->slottime = ATH9K_SLOT_TIME_20; 922 923 switch (vif->type) { 924 case NL80211_IFTYPE_AP: 925 iter_data->naps++; 926 if (vif->bss_conf.enable_beacon) 927 iter_data->beacons = true; 928 break; 929 case NL80211_IFTYPE_STATION: 930 iter_data->nstations++; 931 if (vif->bss_conf.assoc && !iter_data->primary_sta) 932 iter_data->primary_sta = vif; 933 break; 934 case NL80211_IFTYPE_ADHOC: 935 iter_data->nadhocs++; 936 if (vif->bss_conf.enable_beacon) 937 iter_data->beacons = true; 938 break; 939 case NL80211_IFTYPE_MESH_POINT: 940 iter_data->nmeshes++; 941 if (vif->bss_conf.enable_beacon) 942 iter_data->beacons = true; 943 break; 944 case NL80211_IFTYPE_WDS: 945 iter_data->nwds++; 946 break; 947 default: 948 break; 949 } 950 } 951 952 /* Called with sc->mutex held. */ 953 void ath9k_calculate_iter_data(struct ath_softc *sc, 954 struct ath_chanctx *ctx, 955 struct ath9k_vif_iter_data *iter_data) 956 { 957 struct ath_vif *avp; 958 959 /* 960 * Pick the MAC address of the first interface as the new hardware 961 * MAC address. The hardware will use it together with the BSSID mask 962 * when matching addresses. 963 */ 964 memset(iter_data, 0, sizeof(*iter_data)); 965 memset(&iter_data->mask, 0xff, ETH_ALEN); 966 iter_data->slottime = ATH9K_SLOT_TIME_9; 967 968 list_for_each_entry(avp, &ctx->vifs, list) 969 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); 970 971 if (ctx == &sc->offchannel.chan) { 972 struct ieee80211_vif *vif; 973 974 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) 975 vif = sc->offchannel.scan_vif; 976 else 977 vif = sc->offchannel.roc_vif; 978 979 if (vif) 980 ath9k_vif_iter(iter_data, vif->addr, vif); 981 iter_data->beacons = false; 982 } 983 } 984 985 static void ath9k_set_assoc_state(struct ath_softc *sc, 986 struct ieee80211_vif *vif, bool changed) 987 { 988 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 989 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 990 unsigned long flags; 991 992 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 993 /* Set the AID, BSSID and do beacon-sync only when 994 * the HW opmode is STATION. 995 * 996 * But the primary bit is set above in any case. 997 */ 998 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) 999 return; 1000 1001 ether_addr_copy(common->curbssid, bss_conf->bssid); 1002 common->curaid = bss_conf->aid; 1003 ath9k_hw_write_associd(sc->sc_ah); 1004 1005 if (changed) { 1006 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 1007 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1008 1009 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1010 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1011 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1012 } 1013 1014 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1015 ath9k_mci_update_wlan_channels(sc, false); 1016 1017 ath_dbg(common, CONFIG, 1018 "Primary Station interface: %pM, BSSID: %pM\n", 1019 vif->addr, common->curbssid); 1020 } 1021 1022 /* Called with sc->mutex held. */ 1023 void ath9k_calculate_summary_state(struct ath_softc *sc, 1024 struct ath_chanctx *ctx) 1025 { 1026 struct ath_hw *ah = sc->sc_ah; 1027 struct ath_common *common = ath9k_hw_common(ah); 1028 struct ath9k_vif_iter_data iter_data; 1029 1030 ath_chanctx_check_active(sc, ctx); 1031 1032 if (ctx != sc->cur_chan) 1033 return; 1034 1035 ath9k_ps_wakeup(sc); 1036 ath9k_calculate_iter_data(sc, ctx, &iter_data); 1037 1038 if (iter_data.has_hw_macaddr) 1039 ether_addr_copy(common->macaddr, iter_data.hw_macaddr); 1040 1041 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1042 ath_hw_setbssidmask(common); 1043 1044 if (iter_data.naps > 0) { 1045 ath9k_hw_set_tsfadjust(ah, true); 1046 ah->opmode = NL80211_IFTYPE_AP; 1047 } else { 1048 ath9k_hw_set_tsfadjust(ah, false); 1049 1050 if (iter_data.nmeshes) 1051 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1052 else if (iter_data.nwds) 1053 ah->opmode = NL80211_IFTYPE_AP; 1054 else if (iter_data.nadhocs) 1055 ah->opmode = NL80211_IFTYPE_ADHOC; 1056 else 1057 ah->opmode = NL80211_IFTYPE_STATION; 1058 } 1059 1060 ath9k_hw_setopmode(ah); 1061 1062 ctx->switch_after_beacon = false; 1063 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1064 ah->imask |= ATH9K_INT_TSFOOR; 1065 else { 1066 ah->imask &= ~ATH9K_INT_TSFOOR; 1067 if (iter_data.naps == 1 && iter_data.beacons) 1068 ctx->switch_after_beacon = true; 1069 } 1070 1071 ah->imask &= ~ATH9K_INT_SWBA; 1072 if (ah->opmode == NL80211_IFTYPE_STATION) { 1073 bool changed = (iter_data.primary_sta != ctx->primary_sta); 1074 1075 iter_data.beacons = true; 1076 if (iter_data.primary_sta) { 1077 ath9k_set_assoc_state(sc, iter_data.primary_sta, 1078 changed); 1079 if (!ctx->primary_sta || 1080 !ctx->primary_sta->bss_conf.assoc) 1081 ctx->primary_sta = iter_data.primary_sta; 1082 } else { 1083 ctx->primary_sta = NULL; 1084 memset(common->curbssid, 0, ETH_ALEN); 1085 common->curaid = 0; 1086 ath9k_hw_write_associd(sc->sc_ah); 1087 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1088 ath9k_mci_update_wlan_channels(sc, true); 1089 } 1090 } else if (iter_data.beacons) { 1091 ah->imask |= ATH9K_INT_SWBA; 1092 } 1093 ath9k_hw_set_interrupts(ah); 1094 1095 if (iter_data.beacons) 1096 set_bit(ATH_OP_BEACONS, &common->op_flags); 1097 else 1098 clear_bit(ATH_OP_BEACONS, &common->op_flags); 1099 1100 if (ah->slottime != iter_data.slottime) { 1101 ah->slottime = iter_data.slottime; 1102 ath9k_hw_init_global_settings(ah); 1103 } 1104 1105 if (iter_data.primary_sta) 1106 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1107 else 1108 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1109 1110 ctx->primary_sta = iter_data.primary_sta; 1111 1112 ath9k_ps_restore(sc); 1113 } 1114 1115 static int ath9k_add_interface(struct ieee80211_hw *hw, 1116 struct ieee80211_vif *vif) 1117 { 1118 struct ath_softc *sc = hw->priv; 1119 struct ath_hw *ah = sc->sc_ah; 1120 struct ath_common *common = ath9k_hw_common(ah); 1121 struct ath_vif *avp = (void *)vif->drv_priv; 1122 struct ath_node *an = &avp->mcast_node; 1123 int i; 1124 1125 mutex_lock(&sc->mutex); 1126 1127 if (config_enabled(CONFIG_ATH9K_TX99)) { 1128 if (sc->nvifs >= 1) { 1129 mutex_unlock(&sc->mutex); 1130 return -EOPNOTSUPP; 1131 } 1132 sc->tx99_vif = vif; 1133 } 1134 1135 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1136 sc->nvifs++; 1137 1138 if (ath9k_uses_beacons(vif->type)) 1139 ath9k_beacon_assign_slot(sc, vif); 1140 1141 avp->vif = vif; 1142 if (!ath9k_use_chanctx) { 1143 avp->chanctx = sc->cur_chan; 1144 list_add_tail(&avp->list, &avp->chanctx->vifs); 1145 } 1146 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1147 vif->hw_queue[i] = i; 1148 if (vif->type == NL80211_IFTYPE_AP) 1149 vif->cab_queue = hw->queues - 2; 1150 else 1151 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; 1152 1153 an->sc = sc; 1154 an->sta = NULL; 1155 an->vif = vif; 1156 an->no_ps_filter = true; 1157 ath_tx_node_init(sc, an); 1158 1159 mutex_unlock(&sc->mutex); 1160 return 0; 1161 } 1162 1163 static int ath9k_change_interface(struct ieee80211_hw *hw, 1164 struct ieee80211_vif *vif, 1165 enum nl80211_iftype new_type, 1166 bool p2p) 1167 { 1168 struct ath_softc *sc = hw->priv; 1169 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1170 struct ath_vif *avp = (void *)vif->drv_priv; 1171 int i; 1172 1173 mutex_lock(&sc->mutex); 1174 1175 if (config_enabled(CONFIG_ATH9K_TX99)) { 1176 mutex_unlock(&sc->mutex); 1177 return -EOPNOTSUPP; 1178 } 1179 1180 ath_dbg(common, CONFIG, "Change Interface\n"); 1181 1182 if (ath9k_uses_beacons(vif->type)) 1183 ath9k_beacon_remove_slot(sc, vif); 1184 1185 vif->type = new_type; 1186 vif->p2p = p2p; 1187 1188 if (ath9k_uses_beacons(vif->type)) 1189 ath9k_beacon_assign_slot(sc, vif); 1190 1191 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1192 vif->hw_queue[i] = i; 1193 1194 if (vif->type == NL80211_IFTYPE_AP) 1195 vif->cab_queue = hw->queues - 2; 1196 else 1197 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; 1198 1199 ath9k_calculate_summary_state(sc, avp->chanctx); 1200 1201 mutex_unlock(&sc->mutex); 1202 return 0; 1203 } 1204 1205 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1206 struct ieee80211_vif *vif) 1207 { 1208 struct ath_softc *sc = hw->priv; 1209 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1210 struct ath_vif *avp = (void *)vif->drv_priv; 1211 1212 ath_dbg(common, CONFIG, "Detach Interface\n"); 1213 1214 mutex_lock(&sc->mutex); 1215 1216 ath9k_p2p_remove_vif(sc, vif); 1217 1218 sc->nvifs--; 1219 sc->tx99_vif = NULL; 1220 if (!ath9k_use_chanctx) 1221 list_del(&avp->list); 1222 1223 if (ath9k_uses_beacons(vif->type)) 1224 ath9k_beacon_remove_slot(sc, vif); 1225 1226 ath_tx_node_cleanup(sc, &avp->mcast_node); 1227 1228 mutex_unlock(&sc->mutex); 1229 } 1230 1231 static void ath9k_enable_ps(struct ath_softc *sc) 1232 { 1233 struct ath_hw *ah = sc->sc_ah; 1234 struct ath_common *common = ath9k_hw_common(ah); 1235 1236 if (config_enabled(CONFIG_ATH9K_TX99)) 1237 return; 1238 1239 sc->ps_enabled = true; 1240 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1241 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1242 ah->imask |= ATH9K_INT_TIM_TIMER; 1243 ath9k_hw_set_interrupts(ah); 1244 } 1245 ath9k_hw_setrxabort(ah, 1); 1246 } 1247 ath_dbg(common, PS, "PowerSave enabled\n"); 1248 } 1249 1250 static void ath9k_disable_ps(struct ath_softc *sc) 1251 { 1252 struct ath_hw *ah = sc->sc_ah; 1253 struct ath_common *common = ath9k_hw_common(ah); 1254 1255 if (config_enabled(CONFIG_ATH9K_TX99)) 1256 return; 1257 1258 sc->ps_enabled = false; 1259 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1260 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1261 ath9k_hw_setrxabort(ah, 0); 1262 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1263 PS_WAIT_FOR_CAB | 1264 PS_WAIT_FOR_PSPOLL_DATA | 1265 PS_WAIT_FOR_TX_ACK); 1266 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1267 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1268 ath9k_hw_set_interrupts(ah); 1269 } 1270 } 1271 ath_dbg(common, PS, "PowerSave disabled\n"); 1272 } 1273 1274 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) 1275 { 1276 struct ath_softc *sc = hw->priv; 1277 struct ath_hw *ah = sc->sc_ah; 1278 struct ath_common *common = ath9k_hw_common(ah); 1279 u32 rxfilter; 1280 1281 if (config_enabled(CONFIG_ATH9K_TX99)) 1282 return; 1283 1284 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1285 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1286 return; 1287 } 1288 1289 ath9k_ps_wakeup(sc); 1290 rxfilter = ath9k_hw_getrxfilter(ah); 1291 ath9k_hw_setrxfilter(ah, rxfilter | 1292 ATH9K_RX_FILTER_PHYRADAR | 1293 ATH9K_RX_FILTER_PHYERR); 1294 1295 /* TODO: usually this should not be neccesary, but for some reason 1296 * (or in some mode?) the trigger must be called after the 1297 * configuration, otherwise the register will have its values reset 1298 * (on my ar9220 to value 0x01002310) 1299 */ 1300 ath9k_spectral_scan_config(hw, sc->spectral_mode); 1301 ath9k_hw_ops(ah)->spectral_scan_trigger(ah); 1302 ath9k_ps_restore(sc); 1303 } 1304 1305 int ath9k_spectral_scan_config(struct ieee80211_hw *hw, 1306 enum spectral_mode spectral_mode) 1307 { 1308 struct ath_softc *sc = hw->priv; 1309 struct ath_hw *ah = sc->sc_ah; 1310 struct ath_common *common = ath9k_hw_common(ah); 1311 1312 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1313 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1314 return -1; 1315 } 1316 1317 switch (spectral_mode) { 1318 case SPECTRAL_DISABLED: 1319 sc->spec_config.enabled = 0; 1320 break; 1321 case SPECTRAL_BACKGROUND: 1322 /* send endless samples. 1323 * TODO: is this really useful for "background"? 1324 */ 1325 sc->spec_config.endless = 1; 1326 sc->spec_config.enabled = 1; 1327 break; 1328 case SPECTRAL_CHANSCAN: 1329 case SPECTRAL_MANUAL: 1330 sc->spec_config.endless = 0; 1331 sc->spec_config.enabled = 1; 1332 break; 1333 default: 1334 return -1; 1335 } 1336 1337 ath9k_ps_wakeup(sc); 1338 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); 1339 ath9k_ps_restore(sc); 1340 1341 sc->spectral_mode = spectral_mode; 1342 1343 return 0; 1344 } 1345 1346 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1347 { 1348 struct ath_softc *sc = hw->priv; 1349 struct ath_hw *ah = sc->sc_ah; 1350 struct ath_common *common = ath9k_hw_common(ah); 1351 struct ieee80211_conf *conf = &hw->conf; 1352 struct ath_chanctx *ctx = sc->cur_chan; 1353 1354 ath9k_ps_wakeup(sc); 1355 mutex_lock(&sc->mutex); 1356 1357 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1358 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1359 if (sc->ps_idle) { 1360 ath_cancel_work(sc); 1361 ath9k_stop_btcoex(sc); 1362 } else { 1363 ath9k_start_btcoex(sc); 1364 /* 1365 * The chip needs a reset to properly wake up from 1366 * full sleep 1367 */ 1368 ath_chanctx_set_channel(sc, ctx, &ctx->chandef); 1369 } 1370 } 1371 1372 /* 1373 * We just prepare to enable PS. We have to wait until our AP has 1374 * ACK'd our null data frame to disable RX otherwise we'll ignore 1375 * those ACKs and end up retransmitting the same null data frames. 1376 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1377 */ 1378 if (changed & IEEE80211_CONF_CHANGE_PS) { 1379 unsigned long flags; 1380 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1381 if (conf->flags & IEEE80211_CONF_PS) 1382 ath9k_enable_ps(sc); 1383 else 1384 ath9k_disable_ps(sc); 1385 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1386 } 1387 1388 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1389 if (conf->flags & IEEE80211_CONF_MONITOR) { 1390 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1391 sc->sc_ah->is_monitoring = true; 1392 } else { 1393 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1394 sc->sc_ah->is_monitoring = false; 1395 } 1396 } 1397 1398 if (!ath9k_use_chanctx && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { 1399 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); 1400 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); 1401 } 1402 1403 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1404 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1405 sc->cur_chan->txpower = 2 * conf->power_level; 1406 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1407 sc->cur_chan->txpower, &sc->curtxpow); 1408 } 1409 1410 mutex_unlock(&sc->mutex); 1411 ath9k_ps_restore(sc); 1412 1413 return 0; 1414 } 1415 1416 #define SUPPORTED_FILTERS \ 1417 (FIF_PROMISC_IN_BSS | \ 1418 FIF_ALLMULTI | \ 1419 FIF_CONTROL | \ 1420 FIF_PSPOLL | \ 1421 FIF_OTHER_BSS | \ 1422 FIF_BCN_PRBRESP_PROMISC | \ 1423 FIF_PROBE_REQ | \ 1424 FIF_FCSFAIL) 1425 1426 /* FIXME: sc->sc_full_reset ? */ 1427 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1428 unsigned int changed_flags, 1429 unsigned int *total_flags, 1430 u64 multicast) 1431 { 1432 struct ath_softc *sc = hw->priv; 1433 u32 rfilt; 1434 1435 changed_flags &= SUPPORTED_FILTERS; 1436 *total_flags &= SUPPORTED_FILTERS; 1437 1438 sc->rx.rxfilter = *total_flags; 1439 ath9k_ps_wakeup(sc); 1440 rfilt = ath_calcrxfilter(sc); 1441 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1442 ath9k_ps_restore(sc); 1443 1444 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1445 rfilt); 1446 } 1447 1448 static int ath9k_sta_add(struct ieee80211_hw *hw, 1449 struct ieee80211_vif *vif, 1450 struct ieee80211_sta *sta) 1451 { 1452 struct ath_softc *sc = hw->priv; 1453 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1454 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1455 struct ieee80211_key_conf ps_key = { }; 1456 int key; 1457 1458 ath_node_attach(sc, sta, vif); 1459 1460 if (vif->type != NL80211_IFTYPE_AP && 1461 vif->type != NL80211_IFTYPE_AP_VLAN) 1462 return 0; 1463 1464 key = ath_key_config(common, vif, sta, &ps_key); 1465 if (key > 0) { 1466 an->ps_key = key; 1467 an->key_idx[0] = key; 1468 } 1469 1470 return 0; 1471 } 1472 1473 static void ath9k_del_ps_key(struct ath_softc *sc, 1474 struct ieee80211_vif *vif, 1475 struct ieee80211_sta *sta) 1476 { 1477 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1478 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1479 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1480 1481 if (!an->ps_key) 1482 return; 1483 1484 ath_key_delete(common, &ps_key); 1485 an->ps_key = 0; 1486 an->key_idx[0] = 0; 1487 } 1488 1489 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1490 struct ieee80211_vif *vif, 1491 struct ieee80211_sta *sta) 1492 { 1493 struct ath_softc *sc = hw->priv; 1494 1495 ath9k_del_ps_key(sc, vif, sta); 1496 ath_node_detach(sc, sta); 1497 1498 return 0; 1499 } 1500 1501 static void ath9k_sta_set_tx_filter(struct ath_hw *ah, 1502 struct ath_node *an, 1503 bool set) 1504 { 1505 int i; 1506 1507 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1508 if (!an->key_idx[i]) 1509 continue; 1510 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); 1511 } 1512 } 1513 1514 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1515 struct ieee80211_vif *vif, 1516 enum sta_notify_cmd cmd, 1517 struct ieee80211_sta *sta) 1518 { 1519 struct ath_softc *sc = hw->priv; 1520 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1521 1522 switch (cmd) { 1523 case STA_NOTIFY_SLEEP: 1524 an->sleeping = true; 1525 ath_tx_aggr_sleep(sta, sc, an); 1526 ath9k_sta_set_tx_filter(sc->sc_ah, an, true); 1527 break; 1528 case STA_NOTIFY_AWAKE: 1529 ath9k_sta_set_tx_filter(sc->sc_ah, an, false); 1530 an->sleeping = false; 1531 ath_tx_aggr_wakeup(sc, an); 1532 break; 1533 } 1534 } 1535 1536 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1537 struct ieee80211_vif *vif, u16 queue, 1538 const struct ieee80211_tx_queue_params *params) 1539 { 1540 struct ath_softc *sc = hw->priv; 1541 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1542 struct ath_txq *txq; 1543 struct ath9k_tx_queue_info qi; 1544 int ret = 0; 1545 1546 if (queue >= IEEE80211_NUM_ACS) 1547 return 0; 1548 1549 txq = sc->tx.txq_map[queue]; 1550 1551 ath9k_ps_wakeup(sc); 1552 mutex_lock(&sc->mutex); 1553 1554 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1555 1556 qi.tqi_aifs = params->aifs; 1557 qi.tqi_cwmin = params->cw_min; 1558 qi.tqi_cwmax = params->cw_max; 1559 qi.tqi_burstTime = params->txop * 32; 1560 1561 ath_dbg(common, CONFIG, 1562 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1563 queue, txq->axq_qnum, params->aifs, params->cw_min, 1564 params->cw_max, params->txop); 1565 1566 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1567 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1568 if (ret) 1569 ath_err(common, "TXQ Update failed\n"); 1570 1571 mutex_unlock(&sc->mutex); 1572 ath9k_ps_restore(sc); 1573 1574 return ret; 1575 } 1576 1577 static int ath9k_set_key(struct ieee80211_hw *hw, 1578 enum set_key_cmd cmd, 1579 struct ieee80211_vif *vif, 1580 struct ieee80211_sta *sta, 1581 struct ieee80211_key_conf *key) 1582 { 1583 struct ath_softc *sc = hw->priv; 1584 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1585 struct ath_node *an = NULL; 1586 int ret = 0, i; 1587 1588 if (ath9k_modparam_nohwcrypt) 1589 return -ENOSPC; 1590 1591 if ((vif->type == NL80211_IFTYPE_ADHOC || 1592 vif->type == NL80211_IFTYPE_MESH_POINT) && 1593 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1594 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1595 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1596 /* 1597 * For now, disable hw crypto for the RSN IBSS group keys. This 1598 * could be optimized in the future to use a modified key cache 1599 * design to support per-STA RX GTK, but until that gets 1600 * implemented, use of software crypto for group addressed 1601 * frames is a acceptable to allow RSN IBSS to be used. 1602 */ 1603 return -EOPNOTSUPP; 1604 } 1605 1606 mutex_lock(&sc->mutex); 1607 ath9k_ps_wakeup(sc); 1608 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); 1609 if (sta) 1610 an = (struct ath_node *)sta->drv_priv; 1611 1612 switch (cmd) { 1613 case SET_KEY: 1614 if (sta) 1615 ath9k_del_ps_key(sc, vif, sta); 1616 1617 key->hw_key_idx = 0; 1618 ret = ath_key_config(common, vif, sta, key); 1619 if (ret >= 0) { 1620 key->hw_key_idx = ret; 1621 /* push IV and Michael MIC generation to stack */ 1622 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1623 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1624 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1625 if (sc->sc_ah->sw_mgmt_crypto && 1626 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1627 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1628 ret = 0; 1629 } 1630 if (an && key->hw_key_idx) { 1631 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1632 if (an->key_idx[i]) 1633 continue; 1634 an->key_idx[i] = key->hw_key_idx; 1635 break; 1636 } 1637 WARN_ON(i == ARRAY_SIZE(an->key_idx)); 1638 } 1639 break; 1640 case DISABLE_KEY: 1641 ath_key_delete(common, key); 1642 if (an) { 1643 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1644 if (an->key_idx[i] != key->hw_key_idx) 1645 continue; 1646 an->key_idx[i] = 0; 1647 break; 1648 } 1649 } 1650 key->hw_key_idx = 0; 1651 break; 1652 default: 1653 ret = -EINVAL; 1654 } 1655 1656 ath9k_ps_restore(sc); 1657 mutex_unlock(&sc->mutex); 1658 1659 return ret; 1660 } 1661 1662 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1663 struct ieee80211_vif *vif, 1664 struct ieee80211_bss_conf *bss_conf, 1665 u32 changed) 1666 { 1667 #define CHECK_ANI \ 1668 (BSS_CHANGED_ASSOC | \ 1669 BSS_CHANGED_IBSS | \ 1670 BSS_CHANGED_BEACON_ENABLED) 1671 1672 struct ath_softc *sc = hw->priv; 1673 struct ath_hw *ah = sc->sc_ah; 1674 struct ath_common *common = ath9k_hw_common(ah); 1675 struct ath_vif *avp = (void *)vif->drv_priv; 1676 int slottime; 1677 1678 ath9k_ps_wakeup(sc); 1679 mutex_lock(&sc->mutex); 1680 1681 if (changed & BSS_CHANGED_ASSOC) { 1682 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1683 bss_conf->bssid, bss_conf->assoc); 1684 1685 ath9k_calculate_summary_state(sc, avp->chanctx); 1686 if (bss_conf->assoc) 1687 ath_chanctx_event(sc, vif, ATH_CHANCTX_EVENT_ASSOC); 1688 } 1689 1690 if (changed & BSS_CHANGED_IBSS) { 1691 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1692 common->curaid = bss_conf->aid; 1693 ath9k_hw_write_associd(sc->sc_ah); 1694 } 1695 1696 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1697 (changed & BSS_CHANGED_BEACON_INT) || 1698 (changed & BSS_CHANGED_BEACON_INFO)) { 1699 if (changed & BSS_CHANGED_BEACON_ENABLED) 1700 ath9k_calculate_summary_state(sc, avp->chanctx); 1701 ath9k_beacon_config(sc, vif, changed); 1702 } 1703 1704 if ((avp->chanctx == sc->cur_chan) && 1705 (changed & BSS_CHANGED_ERP_SLOT)) { 1706 if (bss_conf->use_short_slot) 1707 slottime = 9; 1708 else 1709 slottime = 20; 1710 if (vif->type == NL80211_IFTYPE_AP) { 1711 /* 1712 * Defer update, so that connected stations can adjust 1713 * their settings at the same time. 1714 * See beacon.c for more details 1715 */ 1716 sc->beacon.slottime = slottime; 1717 sc->beacon.updateslot = UPDATE; 1718 } else { 1719 ah->slottime = slottime; 1720 ath9k_hw_init_global_settings(ah); 1721 } 1722 } 1723 1724 if (changed & BSS_CHANGED_P2P_PS) 1725 ath9k_p2p_bss_info_changed(sc, vif); 1726 1727 if (changed & CHECK_ANI) 1728 ath_check_ani(sc); 1729 1730 mutex_unlock(&sc->mutex); 1731 ath9k_ps_restore(sc); 1732 1733 #undef CHECK_ANI 1734 } 1735 1736 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1737 { 1738 struct ath_softc *sc = hw->priv; 1739 u64 tsf; 1740 1741 mutex_lock(&sc->mutex); 1742 ath9k_ps_wakeup(sc); 1743 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1744 ath9k_ps_restore(sc); 1745 mutex_unlock(&sc->mutex); 1746 1747 return tsf; 1748 } 1749 1750 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1751 struct ieee80211_vif *vif, 1752 u64 tsf) 1753 { 1754 struct ath_softc *sc = hw->priv; 1755 1756 mutex_lock(&sc->mutex); 1757 ath9k_ps_wakeup(sc); 1758 ath9k_hw_settsf64(sc->sc_ah, tsf); 1759 ath9k_ps_restore(sc); 1760 mutex_unlock(&sc->mutex); 1761 } 1762 1763 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1764 { 1765 struct ath_softc *sc = hw->priv; 1766 1767 mutex_lock(&sc->mutex); 1768 1769 ath9k_ps_wakeup(sc); 1770 ath9k_hw_reset_tsf(sc->sc_ah); 1771 ath9k_ps_restore(sc); 1772 1773 mutex_unlock(&sc->mutex); 1774 } 1775 1776 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1777 struct ieee80211_vif *vif, 1778 enum ieee80211_ampdu_mlme_action action, 1779 struct ieee80211_sta *sta, 1780 u16 tid, u16 *ssn, u8 buf_size) 1781 { 1782 struct ath_softc *sc = hw->priv; 1783 bool flush = false; 1784 int ret = 0; 1785 1786 mutex_lock(&sc->mutex); 1787 1788 switch (action) { 1789 case IEEE80211_AMPDU_RX_START: 1790 break; 1791 case IEEE80211_AMPDU_RX_STOP: 1792 break; 1793 case IEEE80211_AMPDU_TX_START: 1794 ath9k_ps_wakeup(sc); 1795 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1796 if (!ret) 1797 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1798 ath9k_ps_restore(sc); 1799 break; 1800 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1801 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1802 flush = true; 1803 case IEEE80211_AMPDU_TX_STOP_CONT: 1804 ath9k_ps_wakeup(sc); 1805 ath_tx_aggr_stop(sc, sta, tid); 1806 if (!flush) 1807 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1808 ath9k_ps_restore(sc); 1809 break; 1810 case IEEE80211_AMPDU_TX_OPERATIONAL: 1811 ath9k_ps_wakeup(sc); 1812 ath_tx_aggr_resume(sc, sta, tid); 1813 ath9k_ps_restore(sc); 1814 break; 1815 default: 1816 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1817 } 1818 1819 mutex_unlock(&sc->mutex); 1820 1821 return ret; 1822 } 1823 1824 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1825 struct survey_info *survey) 1826 { 1827 struct ath_softc *sc = hw->priv; 1828 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1829 struct ieee80211_supported_band *sband; 1830 struct ieee80211_channel *chan; 1831 int pos; 1832 1833 if (config_enabled(CONFIG_ATH9K_TX99)) 1834 return -EOPNOTSUPP; 1835 1836 spin_lock_bh(&common->cc_lock); 1837 if (idx == 0) 1838 ath_update_survey_stats(sc); 1839 1840 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1841 if (sband && idx >= sband->n_channels) { 1842 idx -= sband->n_channels; 1843 sband = NULL; 1844 } 1845 1846 if (!sband) 1847 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1848 1849 if (!sband || idx >= sband->n_channels) { 1850 spin_unlock_bh(&common->cc_lock); 1851 return -ENOENT; 1852 } 1853 1854 chan = &sband->channels[idx]; 1855 pos = chan->hw_value; 1856 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1857 survey->channel = chan; 1858 spin_unlock_bh(&common->cc_lock); 1859 1860 return 0; 1861 } 1862 1863 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 1864 { 1865 struct ath_softc *sc = hw->priv; 1866 struct ath_hw *ah = sc->sc_ah; 1867 1868 if (config_enabled(CONFIG_ATH9K_TX99)) 1869 return; 1870 1871 mutex_lock(&sc->mutex); 1872 ah->coverage_class = coverage_class; 1873 1874 ath9k_ps_wakeup(sc); 1875 ath9k_hw_init_global_settings(ah); 1876 ath9k_ps_restore(sc); 1877 1878 mutex_unlock(&sc->mutex); 1879 } 1880 1881 static bool ath9k_has_tx_pending(struct ath_softc *sc) 1882 { 1883 int i, npend = 0; 1884 1885 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1886 if (!ATH_TXQ_SETUP(sc, i)) 1887 continue; 1888 1889 if (!sc->tx.txq[i].axq_depth) 1890 continue; 1891 1892 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1893 if (npend) 1894 break; 1895 } 1896 1897 return !!npend; 1898 } 1899 1900 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1901 u32 queues, bool drop) 1902 { 1903 struct ath_softc *sc = hw->priv; 1904 1905 mutex_lock(&sc->mutex); 1906 __ath9k_flush(hw, queues, drop); 1907 mutex_unlock(&sc->mutex); 1908 } 1909 1910 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1911 { 1912 struct ath_softc *sc = hw->priv; 1913 struct ath_hw *ah = sc->sc_ah; 1914 struct ath_common *common = ath9k_hw_common(ah); 1915 int timeout = HZ / 5; /* 200 ms */ 1916 bool drain_txq; 1917 int i; 1918 1919 cancel_delayed_work_sync(&sc->tx_complete_work); 1920 1921 if (ah->ah_flags & AH_UNPLUGGED) { 1922 ath_dbg(common, ANY, "Device has been unplugged!\n"); 1923 return; 1924 } 1925 1926 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 1927 ath_dbg(common, ANY, "Device not present\n"); 1928 return; 1929 } 1930 1931 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc), 1932 timeout) > 0) 1933 drop = false; 1934 1935 if (drop) { 1936 ath9k_ps_wakeup(sc); 1937 spin_lock_bh(&sc->sc_pcu_lock); 1938 drain_txq = ath_drain_all_txq(sc); 1939 spin_unlock_bh(&sc->sc_pcu_lock); 1940 1941 if (!drain_txq) 1942 ath_reset(sc); 1943 1944 ath9k_ps_restore(sc); 1945 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 1946 ieee80211_wake_queue(sc->hw, 1947 sc->cur_chan->hw_queue_base + i); 1948 } 1949 } 1950 1951 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 1952 } 1953 1954 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 1955 { 1956 struct ath_softc *sc = hw->priv; 1957 int i; 1958 1959 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1960 if (!ATH_TXQ_SETUP(sc, i)) 1961 continue; 1962 1963 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) 1964 return true; 1965 } 1966 return false; 1967 } 1968 1969 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 1970 { 1971 struct ath_softc *sc = hw->priv; 1972 struct ath_hw *ah = sc->sc_ah; 1973 struct ieee80211_vif *vif; 1974 struct ath_vif *avp; 1975 struct ath_buf *bf; 1976 struct ath_tx_status ts; 1977 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1978 int status; 1979 1980 vif = sc->beacon.bslot[0]; 1981 if (!vif) 1982 return 0; 1983 1984 if (!vif->bss_conf.enable_beacon) 1985 return 0; 1986 1987 avp = (void *)vif->drv_priv; 1988 1989 if (!sc->beacon.tx_processed && !edma) { 1990 tasklet_disable(&sc->bcon_tasklet); 1991 1992 bf = avp->av_bcbuf; 1993 if (!bf || !bf->bf_mpdu) 1994 goto skip; 1995 1996 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 1997 if (status == -EINPROGRESS) 1998 goto skip; 1999 2000 sc->beacon.tx_processed = true; 2001 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2002 2003 skip: 2004 tasklet_enable(&sc->bcon_tasklet); 2005 } 2006 2007 return sc->beacon.tx_last; 2008 } 2009 2010 static int ath9k_get_stats(struct ieee80211_hw *hw, 2011 struct ieee80211_low_level_stats *stats) 2012 { 2013 struct ath_softc *sc = hw->priv; 2014 struct ath_hw *ah = sc->sc_ah; 2015 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 2016 2017 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 2018 stats->dot11RTSFailureCount = mib_stats->rts_bad; 2019 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 2020 stats->dot11RTSSuccessCount = mib_stats->rts_good; 2021 return 0; 2022 } 2023 2024 static u32 fill_chainmask(u32 cap, u32 new) 2025 { 2026 u32 filled = 0; 2027 int i; 2028 2029 for (i = 0; cap && new; i++, cap >>= 1) { 2030 if (!(cap & BIT(0))) 2031 continue; 2032 2033 if (new & BIT(0)) 2034 filled |= BIT(i); 2035 2036 new >>= 1; 2037 } 2038 2039 return filled; 2040 } 2041 2042 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 2043 { 2044 if (AR_SREV_9300_20_OR_LATER(ah)) 2045 return true; 2046 2047 switch (val & 0x7) { 2048 case 0x1: 2049 case 0x3: 2050 case 0x7: 2051 return true; 2052 case 0x2: 2053 return (ah->caps.rx_chainmask == 1); 2054 default: 2055 return false; 2056 } 2057 } 2058 2059 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2060 { 2061 struct ath_softc *sc = hw->priv; 2062 struct ath_hw *ah = sc->sc_ah; 2063 2064 if (ah->caps.rx_chainmask != 1) 2065 rx_ant |= tx_ant; 2066 2067 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 2068 return -EINVAL; 2069 2070 sc->ant_rx = rx_ant; 2071 sc->ant_tx = tx_ant; 2072 2073 if (ah->caps.rx_chainmask == 1) 2074 return 0; 2075 2076 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2077 if (AR_SREV_9100(ah)) 2078 ah->rxchainmask = 0x7; 2079 else 2080 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2081 2082 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2083 ath9k_cmn_reload_chainmask(ah); 2084 2085 return 0; 2086 } 2087 2088 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2089 { 2090 struct ath_softc *sc = hw->priv; 2091 2092 *tx_ant = sc->ant_tx; 2093 *rx_ant = sc->ant_rx; 2094 return 0; 2095 } 2096 2097 static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2098 { 2099 struct ath_softc *sc = hw->priv; 2100 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2101 set_bit(ATH_OP_SCANNING, &common->op_flags); 2102 } 2103 2104 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) 2105 { 2106 struct ath_softc *sc = hw->priv; 2107 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2108 clear_bit(ATH_OP_SCANNING, &common->op_flags); 2109 } 2110 2111 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2112 struct ieee80211_scan_request *hw_req) 2113 { 2114 struct cfg80211_scan_request *req = &hw_req->req; 2115 struct ath_softc *sc = hw->priv; 2116 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2117 int ret = 0; 2118 2119 mutex_lock(&sc->mutex); 2120 2121 if (WARN_ON(sc->offchannel.scan_req)) { 2122 ret = -EBUSY; 2123 goto out; 2124 } 2125 2126 ath9k_ps_wakeup(sc); 2127 set_bit(ATH_OP_SCANNING, &common->op_flags); 2128 sc->offchannel.scan_vif = vif; 2129 sc->offchannel.scan_req = req; 2130 sc->offchannel.scan_idx = 0; 2131 2132 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n", 2133 vif->addr); 2134 2135 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2136 ath_dbg(common, CHAN_CTX, "Starting HW scan\n"); 2137 ath_offchannel_next(sc); 2138 } 2139 2140 out: 2141 mutex_unlock(&sc->mutex); 2142 2143 return ret; 2144 } 2145 2146 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, 2147 struct ieee80211_vif *vif) 2148 { 2149 struct ath_softc *sc = hw->priv; 2150 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2151 2152 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr); 2153 2154 mutex_lock(&sc->mutex); 2155 del_timer_sync(&sc->offchannel.timer); 2156 ath_scan_complete(sc, true); 2157 mutex_unlock(&sc->mutex); 2158 } 2159 2160 static int ath9k_remain_on_channel(struct ieee80211_hw *hw, 2161 struct ieee80211_vif *vif, 2162 struct ieee80211_channel *chan, int duration, 2163 enum ieee80211_roc_type type) 2164 { 2165 struct ath_softc *sc = hw->priv; 2166 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2167 int ret = 0; 2168 2169 mutex_lock(&sc->mutex); 2170 2171 if (WARN_ON(sc->offchannel.roc_vif)) { 2172 ret = -EBUSY; 2173 goto out; 2174 } 2175 2176 ath9k_ps_wakeup(sc); 2177 sc->offchannel.roc_vif = vif; 2178 sc->offchannel.roc_chan = chan; 2179 sc->offchannel.roc_duration = duration; 2180 2181 ath_dbg(common, CHAN_CTX, 2182 "RoC request on vif: %pM, type: %d duration: %d\n", 2183 vif->addr, type, duration); 2184 2185 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2186 ath_dbg(common, CHAN_CTX, "Starting RoC period\n"); 2187 ath_offchannel_next(sc); 2188 } 2189 2190 out: 2191 mutex_unlock(&sc->mutex); 2192 2193 return ret; 2194 } 2195 2196 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw) 2197 { 2198 struct ath_softc *sc = hw->priv; 2199 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2200 2201 mutex_lock(&sc->mutex); 2202 2203 ath_dbg(common, CHAN_CTX, "Cancel RoC\n"); 2204 del_timer_sync(&sc->offchannel.timer); 2205 2206 if (sc->offchannel.roc_vif) { 2207 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2208 ath_roc_complete(sc, true); 2209 } 2210 2211 mutex_unlock(&sc->mutex); 2212 2213 return 0; 2214 } 2215 2216 static int ath9k_add_chanctx(struct ieee80211_hw *hw, 2217 struct ieee80211_chanctx_conf *conf) 2218 { 2219 struct ath_softc *sc = hw->priv; 2220 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2221 struct ath_chanctx *ctx, **ptr; 2222 int pos; 2223 2224 mutex_lock(&sc->mutex); 2225 2226 ath_for_each_chanctx(sc, ctx) { 2227 if (ctx->assigned) 2228 continue; 2229 2230 ptr = (void *) conf->drv_priv; 2231 *ptr = ctx; 2232 ctx->assigned = true; 2233 pos = ctx - &sc->chanctx[0]; 2234 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; 2235 2236 ath_dbg(common, CHAN_CTX, 2237 "Add channel context: %d MHz\n", 2238 conf->def.chan->center_freq); 2239 2240 ath_chanctx_set_channel(sc, ctx, &conf->def); 2241 mutex_unlock(&sc->mutex); 2242 return 0; 2243 } 2244 2245 mutex_unlock(&sc->mutex); 2246 return -ENOSPC; 2247 } 2248 2249 2250 static void ath9k_remove_chanctx(struct ieee80211_hw *hw, 2251 struct ieee80211_chanctx_conf *conf) 2252 { 2253 struct ath_softc *sc = hw->priv; 2254 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2255 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2256 2257 mutex_lock(&sc->mutex); 2258 2259 ath_dbg(common, CHAN_CTX, 2260 "Remove channel context: %d MHz\n", 2261 conf->def.chan->center_freq); 2262 2263 ctx->assigned = false; 2264 ctx->hw_queue_base = -1; 2265 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); 2266 2267 mutex_unlock(&sc->mutex); 2268 } 2269 2270 static void ath9k_change_chanctx(struct ieee80211_hw *hw, 2271 struct ieee80211_chanctx_conf *conf, 2272 u32 changed) 2273 { 2274 struct ath_softc *sc = hw->priv; 2275 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2276 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2277 2278 mutex_lock(&sc->mutex); 2279 ath_dbg(common, CHAN_CTX, 2280 "Change channel context: %d MHz\n", 2281 conf->def.chan->center_freq); 2282 ath_chanctx_set_channel(sc, ctx, &conf->def); 2283 mutex_unlock(&sc->mutex); 2284 } 2285 2286 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, 2287 struct ieee80211_vif *vif, 2288 struct ieee80211_chanctx_conf *conf) 2289 { 2290 struct ath_softc *sc = hw->priv; 2291 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2292 struct ath_vif *avp = (void *)vif->drv_priv; 2293 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2294 int i; 2295 2296 mutex_lock(&sc->mutex); 2297 2298 ath_dbg(common, CHAN_CTX, 2299 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n", 2300 vif->addr, vif->type, vif->p2p, 2301 conf->def.chan->center_freq); 2302 2303 avp->chanctx = ctx; 2304 list_add_tail(&avp->list, &ctx->vifs); 2305 ath9k_calculate_summary_state(sc, ctx); 2306 for (i = 0; i < IEEE80211_NUM_ACS; i++) 2307 vif->hw_queue[i] = ctx->hw_queue_base + i; 2308 2309 mutex_unlock(&sc->mutex); 2310 2311 return 0; 2312 } 2313 2314 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, 2315 struct ieee80211_vif *vif, 2316 struct ieee80211_chanctx_conf *conf) 2317 { 2318 struct ath_softc *sc = hw->priv; 2319 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2320 struct ath_vif *avp = (void *)vif->drv_priv; 2321 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2322 int ac; 2323 2324 mutex_lock(&sc->mutex); 2325 2326 ath_dbg(common, CHAN_CTX, 2327 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n", 2328 vif->addr, vif->type, vif->p2p, 2329 conf->def.chan->center_freq); 2330 2331 avp->chanctx = NULL; 2332 list_del(&avp->list); 2333 ath9k_calculate_summary_state(sc, ctx); 2334 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2335 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; 2336 2337 mutex_unlock(&sc->mutex); 2338 } 2339 2340 void ath9k_fill_chanctx_ops(void) 2341 { 2342 if (!ath9k_use_chanctx) 2343 return; 2344 2345 ath9k_ops.hw_scan = ath9k_hw_scan; 2346 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; 2347 ath9k_ops.remain_on_channel = ath9k_remain_on_channel; 2348 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; 2349 ath9k_ops.add_chanctx = ath9k_add_chanctx; 2350 ath9k_ops.remove_chanctx = ath9k_remove_chanctx; 2351 ath9k_ops.change_chanctx = ath9k_change_chanctx; 2352 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; 2353 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; 2354 ath9k_ops.mgd_prepare_tx = ath9k_chanctx_force_active; 2355 } 2356 2357 struct ieee80211_ops ath9k_ops = { 2358 .tx = ath9k_tx, 2359 .start = ath9k_start, 2360 .stop = ath9k_stop, 2361 .add_interface = ath9k_add_interface, 2362 .change_interface = ath9k_change_interface, 2363 .remove_interface = ath9k_remove_interface, 2364 .config = ath9k_config, 2365 .configure_filter = ath9k_configure_filter, 2366 .sta_add = ath9k_sta_add, 2367 .sta_remove = ath9k_sta_remove, 2368 .sta_notify = ath9k_sta_notify, 2369 .conf_tx = ath9k_conf_tx, 2370 .bss_info_changed = ath9k_bss_info_changed, 2371 .set_key = ath9k_set_key, 2372 .get_tsf = ath9k_get_tsf, 2373 .set_tsf = ath9k_set_tsf, 2374 .reset_tsf = ath9k_reset_tsf, 2375 .ampdu_action = ath9k_ampdu_action, 2376 .get_survey = ath9k_get_survey, 2377 .rfkill_poll = ath9k_rfkill_poll_state, 2378 .set_coverage_class = ath9k_set_coverage_class, 2379 .flush = ath9k_flush, 2380 .tx_frames_pending = ath9k_tx_frames_pending, 2381 .tx_last_beacon = ath9k_tx_last_beacon, 2382 .release_buffered_frames = ath9k_release_buffered_frames, 2383 .get_stats = ath9k_get_stats, 2384 .set_antenna = ath9k_set_antenna, 2385 .get_antenna = ath9k_get_antenna, 2386 2387 #ifdef CONFIG_ATH9K_WOW 2388 .suspend = ath9k_suspend, 2389 .resume = ath9k_resume, 2390 .set_wakeup = ath9k_set_wakeup, 2391 #endif 2392 2393 #ifdef CONFIG_ATH9K_DEBUGFS 2394 .get_et_sset_count = ath9k_get_et_sset_count, 2395 .get_et_stats = ath9k_get_et_stats, 2396 .get_et_strings = ath9k_get_et_strings, 2397 #endif 2398 2399 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) 2400 .sta_add_debugfs = ath9k_sta_add_debugfs, 2401 #endif 2402 .sw_scan_start = ath9k_sw_scan_start, 2403 .sw_scan_complete = ath9k_sw_scan_complete, 2404 }; 2405