1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/delay.h> 19 #include "ath9k.h" 20 #include "btcoex.h" 21 22 u8 ath9k_parse_mpdudensity(u8 mpdudensity) 23 { 24 /* 25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": 26 * 0 for no restriction 27 * 1 for 1/4 us 28 * 2 for 1/2 us 29 * 3 for 1 us 30 * 4 for 2 us 31 * 5 for 4 us 32 * 6 for 8 us 33 * 7 for 16 us 34 */ 35 switch (mpdudensity) { 36 case 0: 37 return 0; 38 case 1: 39 case 2: 40 case 3: 41 /* Our lower layer calculations limit our precision to 42 1 microsecond */ 43 return 1; 44 case 4: 45 return 2; 46 case 5: 47 return 4; 48 case 6: 49 return 8; 50 case 7: 51 return 16; 52 default: 53 return 0; 54 } 55 } 56 57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) 58 { 59 bool pending = false; 60 61 spin_lock_bh(&txq->axq_lock); 62 63 if (txq->axq_depth) { 64 pending = true; 65 goto out; 66 } 67 68 if (txq->mac80211_qnum >= 0) { 69 struct list_head *list; 70 71 list = &sc->cur_chan->acq[txq->mac80211_qnum]; 72 if (!list_empty(list)) 73 pending = true; 74 } 75 out: 76 spin_unlock_bh(&txq->axq_lock); 77 return pending; 78 } 79 80 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 81 { 82 unsigned long flags; 83 bool ret; 84 85 spin_lock_irqsave(&sc->sc_pm_lock, flags); 86 ret = ath9k_hw_setpower(sc->sc_ah, mode); 87 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 88 89 return ret; 90 } 91 92 void ath_ps_full_sleep(unsigned long data) 93 { 94 struct ath_softc *sc = (struct ath_softc *) data; 95 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 96 bool reset; 97 98 spin_lock(&common->cc_lock); 99 ath_hw_cycle_counters_update(common); 100 spin_unlock(&common->cc_lock); 101 102 ath9k_hw_setrxabort(sc->sc_ah, 1); 103 ath9k_hw_stopdmarecv(sc->sc_ah, &reset); 104 105 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 106 } 107 108 void ath9k_ps_wakeup(struct ath_softc *sc) 109 { 110 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 111 unsigned long flags; 112 enum ath9k_power_mode power_mode; 113 114 spin_lock_irqsave(&sc->sc_pm_lock, flags); 115 if (++sc->ps_usecount != 1) 116 goto unlock; 117 118 del_timer_sync(&sc->sleep_timer); 119 power_mode = sc->sc_ah->power_mode; 120 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 121 122 /* 123 * While the hardware is asleep, the cycle counters contain no 124 * useful data. Better clear them now so that they don't mess up 125 * survey data results. 126 */ 127 if (power_mode != ATH9K_PM_AWAKE) { 128 spin_lock(&common->cc_lock); 129 ath_hw_cycle_counters_update(common); 130 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 131 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 132 spin_unlock(&common->cc_lock); 133 } 134 135 unlock: 136 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 137 } 138 139 void ath9k_ps_restore(struct ath_softc *sc) 140 { 141 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 142 enum ath9k_power_mode mode; 143 unsigned long flags; 144 145 spin_lock_irqsave(&sc->sc_pm_lock, flags); 146 if (--sc->ps_usecount != 0) 147 goto unlock; 148 149 if (sc->ps_idle) { 150 mod_timer(&sc->sleep_timer, jiffies + HZ / 10); 151 goto unlock; 152 } 153 154 if (sc->ps_enabled && 155 !(sc->ps_flags & (PS_WAIT_FOR_BEACON | 156 PS_WAIT_FOR_CAB | 157 PS_WAIT_FOR_PSPOLL_DATA | 158 PS_WAIT_FOR_TX_ACK | 159 PS_WAIT_FOR_ANI))) { 160 mode = ATH9K_PM_NETWORK_SLEEP; 161 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) 162 ath9k_btcoex_stop_gen_timer(sc); 163 } else { 164 goto unlock; 165 } 166 167 spin_lock(&common->cc_lock); 168 ath_hw_cycle_counters_update(common); 169 spin_unlock(&common->cc_lock); 170 171 ath9k_hw_setpower(sc->sc_ah, mode); 172 173 unlock: 174 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 175 } 176 177 static void __ath_cancel_work(struct ath_softc *sc) 178 { 179 cancel_work_sync(&sc->paprd_work); 180 cancel_delayed_work_sync(&sc->tx_complete_work); 181 cancel_delayed_work_sync(&sc->hw_pll_work); 182 183 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 184 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 185 cancel_work_sync(&sc->mci_work); 186 #endif 187 } 188 189 void ath_cancel_work(struct ath_softc *sc) 190 { 191 __ath_cancel_work(sc); 192 cancel_work_sync(&sc->hw_reset_work); 193 } 194 195 void ath_restart_work(struct ath_softc *sc) 196 { 197 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 198 199 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) 200 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, 201 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); 202 203 ath_start_ani(sc); 204 } 205 206 static bool ath_prepare_reset(struct ath_softc *sc) 207 { 208 struct ath_hw *ah = sc->sc_ah; 209 bool ret = true; 210 211 ieee80211_stop_queues(sc->hw); 212 ath_stop_ani(sc); 213 ath9k_hw_disable_interrupts(ah); 214 215 if (!ath_drain_all_txq(sc)) 216 ret = false; 217 218 if (!ath_stoprecv(sc)) 219 ret = false; 220 221 return ret; 222 } 223 224 static bool ath_complete_reset(struct ath_softc *sc, bool start) 225 { 226 struct ath_hw *ah = sc->sc_ah; 227 struct ath_common *common = ath9k_hw_common(ah); 228 unsigned long flags; 229 230 ath9k_calculate_summary_state(sc, sc->cur_chan); 231 ath_startrecv(sc); 232 ath9k_cmn_update_txpow(ah, sc->curtxpow, 233 sc->cur_chan->txpower, &sc->curtxpow); 234 clear_bit(ATH_OP_HW_RESET, &common->op_flags); 235 236 if (!sc->cur_chan->offchannel && start) { 237 /* restore per chanctx TSF timer */ 238 if (sc->cur_chan->tsf_val) { 239 u32 offset; 240 241 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, 242 NULL); 243 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); 244 } 245 246 247 if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) 248 goto work; 249 250 if (ah->opmode == NL80211_IFTYPE_STATION && 251 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { 252 spin_lock_irqsave(&sc->sc_pm_lock, flags); 253 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 254 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 255 } else { 256 ath9k_set_beacon(sc); 257 } 258 work: 259 ath_restart_work(sc); 260 ath_txq_schedule_all(sc); 261 } 262 263 sc->gtt_cnt = 0; 264 265 ath9k_hw_set_interrupts(ah); 266 ath9k_hw_enable_interrupts(ah); 267 ieee80211_wake_queues(sc->hw); 268 ath9k_p2p_ps_timer(sc); 269 270 return true; 271 } 272 273 int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) 274 { 275 struct ath_hw *ah = sc->sc_ah; 276 struct ath_common *common = ath9k_hw_common(ah); 277 struct ath9k_hw_cal_data *caldata = NULL; 278 bool fastcc = true; 279 int r; 280 281 __ath_cancel_work(sc); 282 283 tasklet_disable(&sc->intr_tq); 284 spin_lock_bh(&sc->sc_pcu_lock); 285 286 if (!sc->cur_chan->offchannel) { 287 fastcc = false; 288 caldata = &sc->cur_chan->caldata; 289 } 290 291 if (!hchan) { 292 fastcc = false; 293 hchan = ah->curchan; 294 } 295 296 if (!ath_prepare_reset(sc)) 297 fastcc = false; 298 299 if (ath9k_is_chanctx_enabled()) 300 fastcc = false; 301 302 spin_lock_bh(&sc->chan_lock); 303 sc->cur_chandef = sc->cur_chan->chandef; 304 spin_unlock_bh(&sc->chan_lock); 305 306 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", 307 hchan->channel, IS_CHAN_HT40(hchan), fastcc); 308 309 r = ath9k_hw_reset(ah, hchan, caldata, fastcc); 310 if (r) { 311 ath_err(common, 312 "Unable to reset channel, reset status %d\n", r); 313 314 ath9k_hw_enable_interrupts(ah); 315 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); 316 317 goto out; 318 } 319 320 if (ath9k_hw_mci_is_enabled(sc->sc_ah) && 321 sc->cur_chan->offchannel) 322 ath9k_mci_set_txpower(sc, true, false); 323 324 if (!ath_complete_reset(sc, true)) 325 r = -EIO; 326 327 out: 328 spin_unlock_bh(&sc->sc_pcu_lock); 329 tasklet_enable(&sc->intr_tq); 330 331 return r; 332 } 333 334 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, 335 struct ieee80211_vif *vif) 336 { 337 struct ath_node *an; 338 an = (struct ath_node *)sta->drv_priv; 339 340 an->sc = sc; 341 an->sta = sta; 342 an->vif = vif; 343 memset(&an->key_idx, 0, sizeof(an->key_idx)); 344 345 ath_tx_node_init(sc, an); 346 347 ath_dynack_node_init(sc->sc_ah, an); 348 } 349 350 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) 351 { 352 struct ath_node *an = (struct ath_node *)sta->drv_priv; 353 ath_tx_node_cleanup(sc, an); 354 355 ath_dynack_node_deinit(sc->sc_ah, an); 356 } 357 358 void ath9k_tasklet(unsigned long data) 359 { 360 struct ath_softc *sc = (struct ath_softc *)data; 361 struct ath_hw *ah = sc->sc_ah; 362 struct ath_common *common = ath9k_hw_common(ah); 363 enum ath_reset_type type; 364 unsigned long flags; 365 u32 status = sc->intrstatus; 366 u32 rxmask; 367 368 ath9k_ps_wakeup(sc); 369 spin_lock(&sc->sc_pcu_lock); 370 371 if (status & ATH9K_INT_FATAL) { 372 type = RESET_TYPE_FATAL_INT; 373 ath9k_queue_reset(sc, type); 374 375 /* 376 * Increment the ref. counter here so that 377 * interrupts are enabled in the reset routine. 378 */ 379 atomic_inc(&ah->intr_ref_cnt); 380 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); 381 goto out; 382 } 383 384 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 385 (status & ATH9K_INT_BB_WATCHDOG)) { 386 spin_lock(&common->cc_lock); 387 ath_hw_cycle_counters_update(common); 388 ar9003_hw_bb_watchdog_dbg_info(ah); 389 spin_unlock(&common->cc_lock); 390 391 if (ar9003_hw_bb_watchdog_check(ah)) { 392 type = RESET_TYPE_BB_WATCHDOG; 393 ath9k_queue_reset(sc, type); 394 395 /* 396 * Increment the ref. counter here so that 397 * interrupts are enabled in the reset routine. 398 */ 399 atomic_inc(&ah->intr_ref_cnt); 400 ath_dbg(common, RESET, 401 "BB_WATCHDOG: Skipping interrupts\n"); 402 goto out; 403 } 404 } 405 406 if (status & ATH9K_INT_GTT) { 407 sc->gtt_cnt++; 408 409 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { 410 type = RESET_TYPE_TX_GTT; 411 ath9k_queue_reset(sc, type); 412 atomic_inc(&ah->intr_ref_cnt); 413 ath_dbg(common, RESET, 414 "GTT: Skipping interrupts\n"); 415 goto out; 416 } 417 } 418 419 spin_lock_irqsave(&sc->sc_pm_lock, flags); 420 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { 421 /* 422 * TSF sync does not look correct; remain awake to sync with 423 * the next Beacon. 424 */ 425 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); 426 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; 427 } 428 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 429 430 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 431 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | 432 ATH9K_INT_RXORN); 433 else 434 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 435 436 if (status & rxmask) { 437 /* Check for high priority Rx first */ 438 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 439 (status & ATH9K_INT_RXHP)) 440 ath_rx_tasklet(sc, 0, true); 441 442 ath_rx_tasklet(sc, 0, false); 443 } 444 445 if (status & ATH9K_INT_TX) { 446 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 447 /* 448 * For EDMA chips, TX completion is enabled for the 449 * beacon queue, so if a beacon has been transmitted 450 * successfully after a GTT interrupt, the GTT counter 451 * gets reset to zero here. 452 */ 453 sc->gtt_cnt = 0; 454 455 ath_tx_edma_tasklet(sc); 456 } else { 457 ath_tx_tasklet(sc); 458 } 459 460 wake_up(&sc->tx_wait); 461 } 462 463 if (status & ATH9K_INT_GENTIMER) 464 ath_gen_timer_isr(sc->sc_ah); 465 466 ath9k_btcoex_handle_interrupt(sc, status); 467 468 /* re-enable hardware interrupt */ 469 ath9k_hw_enable_interrupts(ah); 470 out: 471 spin_unlock(&sc->sc_pcu_lock); 472 ath9k_ps_restore(sc); 473 } 474 475 irqreturn_t ath_isr(int irq, void *dev) 476 { 477 #define SCHED_INTR ( \ 478 ATH9K_INT_FATAL | \ 479 ATH9K_INT_BB_WATCHDOG | \ 480 ATH9K_INT_RXORN | \ 481 ATH9K_INT_RXEOL | \ 482 ATH9K_INT_RX | \ 483 ATH9K_INT_RXLP | \ 484 ATH9K_INT_RXHP | \ 485 ATH9K_INT_TX | \ 486 ATH9K_INT_BMISS | \ 487 ATH9K_INT_CST | \ 488 ATH9K_INT_GTT | \ 489 ATH9K_INT_TSFOOR | \ 490 ATH9K_INT_GENTIMER | \ 491 ATH9K_INT_MCI) 492 493 struct ath_softc *sc = dev; 494 struct ath_hw *ah = sc->sc_ah; 495 struct ath_common *common = ath9k_hw_common(ah); 496 enum ath9k_int status; 497 u32 sync_cause = 0; 498 bool sched = false; 499 500 /* 501 * The hardware is not ready/present, don't 502 * touch anything. Note this can happen early 503 * on if the IRQ is shared. 504 */ 505 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags)) 506 return IRQ_NONE; 507 508 /* shared irq, not for us */ 509 510 if (!ath9k_hw_intrpend(ah)) 511 return IRQ_NONE; 512 513 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) { 514 ath9k_hw_kill_interrupts(ah); 515 return IRQ_HANDLED; 516 } 517 518 /* 519 * Figure out the reason(s) for the interrupt. Note 520 * that the hal returns a pseudo-ISR that may include 521 * bits we haven't explicitly enabled so we mask the 522 * value to insure we only process bits we requested. 523 */ 524 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ 525 ath9k_debug_sync_cause(sc, sync_cause); 526 status &= ah->imask; /* discard unasked-for bits */ 527 528 /* 529 * If there are no status bits set, then this interrupt was not 530 * for me (should have been caught above). 531 */ 532 if (!status) 533 return IRQ_NONE; 534 535 /* Cache the status */ 536 sc->intrstatus = status; 537 538 if (status & SCHED_INTR) 539 sched = true; 540 541 /* 542 * If a FATAL or RXORN interrupt is received, we have to reset the 543 * chip immediately. 544 */ 545 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && 546 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) 547 goto chip_reset; 548 549 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && 550 (status & ATH9K_INT_BB_WATCHDOG)) 551 goto chip_reset; 552 553 #ifdef CONFIG_ATH9K_WOW 554 if (status & ATH9K_INT_BMISS) { 555 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { 556 atomic_inc(&sc->wow_got_bmiss_intr); 557 atomic_dec(&sc->wow_sleep_proc_intr); 558 } 559 } 560 #endif 561 562 if (status & ATH9K_INT_SWBA) 563 tasklet_schedule(&sc->bcon_tasklet); 564 565 if (status & ATH9K_INT_TXURN) 566 ath9k_hw_updatetxtriglevel(ah, true); 567 568 if (status & ATH9K_INT_RXEOL) { 569 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 570 ath9k_hw_set_interrupts(ah); 571 } 572 573 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 574 if (status & ATH9K_INT_TIM_TIMER) { 575 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) 576 goto chip_reset; 577 /* Clear RxAbort bit so that we can 578 * receive frames */ 579 ath9k_setpower(sc, ATH9K_PM_AWAKE); 580 spin_lock(&sc->sc_pm_lock); 581 ath9k_hw_setrxabort(sc->sc_ah, 0); 582 sc->ps_flags |= PS_WAIT_FOR_BEACON; 583 spin_unlock(&sc->sc_pm_lock); 584 } 585 586 chip_reset: 587 588 ath_debug_stat_interrupt(sc, status); 589 590 if (sched) { 591 /* turn off every interrupt */ 592 ath9k_hw_disable_interrupts(ah); 593 tasklet_schedule(&sc->intr_tq); 594 } 595 596 return IRQ_HANDLED; 597 598 #undef SCHED_INTR 599 } 600 601 int ath_reset(struct ath_softc *sc) 602 { 603 int r; 604 605 ath9k_ps_wakeup(sc); 606 r = ath_reset_internal(sc, NULL); 607 ath9k_ps_restore(sc); 608 609 return r; 610 } 611 612 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) 613 { 614 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 615 #ifdef CONFIG_ATH9K_DEBUGFS 616 RESET_STAT_INC(sc, type); 617 #endif 618 set_bit(ATH_OP_HW_RESET, &common->op_flags); 619 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 620 } 621 622 void ath_reset_work(struct work_struct *work) 623 { 624 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); 625 626 ath_reset(sc); 627 } 628 629 /**********************/ 630 /* mac80211 callbacks */ 631 /**********************/ 632 633 static int ath9k_start(struct ieee80211_hw *hw) 634 { 635 struct ath_softc *sc = hw->priv; 636 struct ath_hw *ah = sc->sc_ah; 637 struct ath_common *common = ath9k_hw_common(ah); 638 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; 639 struct ath_chanctx *ctx = sc->cur_chan; 640 struct ath9k_channel *init_channel; 641 int r; 642 643 ath_dbg(common, CONFIG, 644 "Starting driver with initial channel: %d MHz\n", 645 curchan->center_freq); 646 647 ath9k_ps_wakeup(sc); 648 mutex_lock(&sc->mutex); 649 650 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); 651 sc->cur_chandef = hw->conf.chandef; 652 653 /* Reset SERDES registers */ 654 ath9k_hw_configpcipowersave(ah, false); 655 656 /* 657 * The basic interface to setting the hardware in a good 658 * state is ``reset''. On return the hardware is known to 659 * be powered up and with interrupts disabled. This must 660 * be followed by initialization of the appropriate bits 661 * and then setup of the interrupt mask. 662 */ 663 spin_lock_bh(&sc->sc_pcu_lock); 664 665 atomic_set(&ah->intr_ref_cnt, -1); 666 667 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); 668 if (r) { 669 ath_err(common, 670 "Unable to reset hardware; reset status %d (freq %u MHz)\n", 671 r, curchan->center_freq); 672 ah->reset_power_on = false; 673 } 674 675 /* Setup our intr mask. */ 676 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | 677 ATH9K_INT_RXORN | ATH9K_INT_FATAL | 678 ATH9K_INT_GLOBAL; 679 680 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 681 ah->imask |= ATH9K_INT_RXHP | 682 ATH9K_INT_RXLP; 683 else 684 ah->imask |= ATH9K_INT_RX; 685 686 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) 687 ah->imask |= ATH9K_INT_BB_WATCHDOG; 688 689 /* 690 * Enable GTT interrupts only for AR9003/AR9004 chips 691 * for now. 692 */ 693 if (AR_SREV_9300_20_OR_LATER(ah)) 694 ah->imask |= ATH9K_INT_GTT; 695 696 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) 697 ah->imask |= ATH9K_INT_CST; 698 699 ath_mci_enable(sc); 700 701 clear_bit(ATH_OP_INVALID, &common->op_flags); 702 sc->sc_ah->is_monitoring = false; 703 704 if (!ath_complete_reset(sc, false)) 705 ah->reset_power_on = false; 706 707 if (ah->led_pin >= 0) { 708 ath9k_hw_cfg_output(ah, ah->led_pin, 709 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 710 ath9k_hw_set_gpio(ah, ah->led_pin, 0); 711 } 712 713 /* 714 * Reset key cache to sane defaults (all entries cleared) instead of 715 * semi-random values after suspend/resume. 716 */ 717 ath9k_cmn_init_crypto(sc->sc_ah); 718 719 ath9k_hw_reset_tsf(ah); 720 721 spin_unlock_bh(&sc->sc_pcu_lock); 722 723 mutex_unlock(&sc->mutex); 724 725 ath9k_ps_restore(sc); 726 727 return 0; 728 } 729 730 static void ath9k_tx(struct ieee80211_hw *hw, 731 struct ieee80211_tx_control *control, 732 struct sk_buff *skb) 733 { 734 struct ath_softc *sc = hw->priv; 735 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 736 struct ath_tx_control txctl; 737 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 738 unsigned long flags; 739 740 if (sc->ps_enabled) { 741 /* 742 * mac80211 does not set PM field for normal data frames, so we 743 * need to update that based on the current PS mode. 744 */ 745 if (ieee80211_is_data(hdr->frame_control) && 746 !ieee80211_is_nullfunc(hdr->frame_control) && 747 !ieee80211_has_pm(hdr->frame_control)) { 748 ath_dbg(common, PS, 749 "Add PM=1 for a TX frame while in PS mode\n"); 750 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 751 } 752 } 753 754 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { 755 /* 756 * We are using PS-Poll and mac80211 can request TX while in 757 * power save mode. Need to wake up hardware for the TX to be 758 * completed and if needed, also for RX of buffered frames. 759 */ 760 ath9k_ps_wakeup(sc); 761 spin_lock_irqsave(&sc->sc_pm_lock, flags); 762 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) 763 ath9k_hw_setrxabort(sc->sc_ah, 0); 764 if (ieee80211_is_pspoll(hdr->frame_control)) { 765 ath_dbg(common, PS, 766 "Sending PS-Poll to pick a buffered frame\n"); 767 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; 768 } else { 769 ath_dbg(common, PS, "Wake up to complete TX\n"); 770 sc->ps_flags |= PS_WAIT_FOR_TX_ACK; 771 } 772 /* 773 * The actual restore operation will happen only after 774 * the ps_flags bit is cleared. We are just dropping 775 * the ps_usecount here. 776 */ 777 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 778 ath9k_ps_restore(sc); 779 } 780 781 /* 782 * Cannot tx while the hardware is in full sleep, it first needs a full 783 * chip reset to recover from that 784 */ 785 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { 786 ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); 787 goto exit; 788 } 789 790 memset(&txctl, 0, sizeof(struct ath_tx_control)); 791 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; 792 txctl.sta = control->sta; 793 794 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); 795 796 if (ath_tx_start(hw, skb, &txctl) != 0) { 797 ath_dbg(common, XMIT, "TX failed\n"); 798 TX_STAT_INC(txctl.txq->axq_qnum, txfailed); 799 goto exit; 800 } 801 802 return; 803 exit: 804 ieee80211_free_txskb(hw, skb); 805 } 806 807 static void ath9k_stop(struct ieee80211_hw *hw) 808 { 809 struct ath_softc *sc = hw->priv; 810 struct ath_hw *ah = sc->sc_ah; 811 struct ath_common *common = ath9k_hw_common(ah); 812 bool prev_idle; 813 814 ath9k_deinit_channel_context(sc); 815 816 mutex_lock(&sc->mutex); 817 818 ath_cancel_work(sc); 819 820 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 821 ath_dbg(common, ANY, "Device not present\n"); 822 mutex_unlock(&sc->mutex); 823 return; 824 } 825 826 /* Ensure HW is awake when we try to shut it down. */ 827 ath9k_ps_wakeup(sc); 828 829 spin_lock_bh(&sc->sc_pcu_lock); 830 831 /* prevent tasklets to enable interrupts once we disable them */ 832 ah->imask &= ~ATH9K_INT_GLOBAL; 833 834 /* make sure h/w will not generate any interrupt 835 * before setting the invalid flag. */ 836 ath9k_hw_disable_interrupts(ah); 837 838 spin_unlock_bh(&sc->sc_pcu_lock); 839 840 /* we can now sync irq and kill any running tasklets, since we already 841 * disabled interrupts and not holding a spin lock */ 842 synchronize_irq(sc->irq); 843 tasklet_kill(&sc->intr_tq); 844 tasklet_kill(&sc->bcon_tasklet); 845 846 prev_idle = sc->ps_idle; 847 sc->ps_idle = true; 848 849 spin_lock_bh(&sc->sc_pcu_lock); 850 851 if (ah->led_pin >= 0) { 852 ath9k_hw_set_gpio(ah, ah->led_pin, 1); 853 ath9k_hw_cfg_gpio_input(ah, ah->led_pin); 854 } 855 856 ath_prepare_reset(sc); 857 858 if (sc->rx.frag) { 859 dev_kfree_skb_any(sc->rx.frag); 860 sc->rx.frag = NULL; 861 } 862 863 if (!ah->curchan) 864 ah->curchan = ath9k_cmn_get_channel(hw, ah, 865 &sc->cur_chan->chandef); 866 867 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); 868 ath9k_hw_phy_disable(ah); 869 870 ath9k_hw_configpcipowersave(ah, true); 871 872 spin_unlock_bh(&sc->sc_pcu_lock); 873 874 ath9k_ps_restore(sc); 875 876 set_bit(ATH_OP_INVALID, &common->op_flags); 877 sc->ps_idle = prev_idle; 878 879 mutex_unlock(&sc->mutex); 880 881 ath_dbg(common, CONFIG, "Driver halt\n"); 882 } 883 884 static bool ath9k_uses_beacons(int type) 885 { 886 switch (type) { 887 case NL80211_IFTYPE_AP: 888 case NL80211_IFTYPE_ADHOC: 889 case NL80211_IFTYPE_MESH_POINT: 890 return true; 891 default: 892 return false; 893 } 894 } 895 896 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data, 897 u8 *mac, struct ieee80211_vif *vif) 898 { 899 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 900 int i; 901 902 if (iter_data->has_hw_macaddr) { 903 for (i = 0; i < ETH_ALEN; i++) 904 iter_data->mask[i] &= 905 ~(iter_data->hw_macaddr[i] ^ mac[i]); 906 } else { 907 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); 908 iter_data->has_hw_macaddr = true; 909 } 910 911 if (!vif->bss_conf.use_short_slot) 912 iter_data->slottime = ATH9K_SLOT_TIME_20; 913 914 switch (vif->type) { 915 case NL80211_IFTYPE_AP: 916 iter_data->naps++; 917 break; 918 case NL80211_IFTYPE_STATION: 919 iter_data->nstations++; 920 if (avp->assoc && !iter_data->primary_sta) 921 iter_data->primary_sta = vif; 922 break; 923 case NL80211_IFTYPE_ADHOC: 924 iter_data->nadhocs++; 925 if (vif->bss_conf.enable_beacon) 926 iter_data->beacons = true; 927 break; 928 case NL80211_IFTYPE_MESH_POINT: 929 iter_data->nmeshes++; 930 if (vif->bss_conf.enable_beacon) 931 iter_data->beacons = true; 932 break; 933 case NL80211_IFTYPE_WDS: 934 iter_data->nwds++; 935 break; 936 default: 937 break; 938 } 939 } 940 941 static void ath9k_update_bssid_mask(struct ath_softc *sc, 942 struct ath_chanctx *ctx, 943 struct ath9k_vif_iter_data *iter_data) 944 { 945 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 946 struct ath_vif *avp; 947 int i; 948 949 if (!ath9k_is_chanctx_enabled()) 950 return; 951 952 list_for_each_entry(avp, &ctx->vifs, list) { 953 if (ctx->nvifs_assigned != 1) 954 continue; 955 956 if (!avp->vif->p2p || !iter_data->has_hw_macaddr) 957 continue; 958 959 ether_addr_copy(common->curbssid, avp->bssid); 960 961 /* perm_addr will be used as the p2p device address. */ 962 for (i = 0; i < ETH_ALEN; i++) 963 iter_data->mask[i] &= 964 ~(iter_data->hw_macaddr[i] ^ 965 sc->hw->wiphy->perm_addr[i]); 966 } 967 } 968 969 /* Called with sc->mutex held. */ 970 void ath9k_calculate_iter_data(struct ath_softc *sc, 971 struct ath_chanctx *ctx, 972 struct ath9k_vif_iter_data *iter_data) 973 { 974 struct ath_vif *avp; 975 976 /* 977 * Pick the MAC address of the first interface as the new hardware 978 * MAC address. The hardware will use it together with the BSSID mask 979 * when matching addresses. 980 */ 981 memset(iter_data, 0, sizeof(*iter_data)); 982 memset(&iter_data->mask, 0xff, ETH_ALEN); 983 iter_data->slottime = ATH9K_SLOT_TIME_9; 984 985 list_for_each_entry(avp, &ctx->vifs, list) 986 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); 987 988 ath9k_update_bssid_mask(sc, ctx, iter_data); 989 } 990 991 static void ath9k_set_assoc_state(struct ath_softc *sc, 992 struct ieee80211_vif *vif, bool changed) 993 { 994 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 995 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; 996 unsigned long flags; 997 998 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 999 1000 ether_addr_copy(common->curbssid, avp->bssid); 1001 common->curaid = avp->aid; 1002 ath9k_hw_write_associd(sc->sc_ah); 1003 1004 if (changed) { 1005 common->last_rssi = ATH_RSSI_DUMMY_MARKER; 1006 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1007 1008 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1009 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1010 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1011 } 1012 1013 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1014 ath9k_mci_update_wlan_channels(sc, false); 1015 1016 ath_dbg(common, CONFIG, 1017 "Primary Station interface: %pM, BSSID: %pM\n", 1018 vif->addr, common->curbssid); 1019 } 1020 1021 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1022 static void ath9k_set_offchannel_state(struct ath_softc *sc) 1023 { 1024 struct ath_hw *ah = sc->sc_ah; 1025 struct ath_common *common = ath9k_hw_common(ah); 1026 struct ieee80211_vif *vif = NULL; 1027 1028 ath9k_ps_wakeup(sc); 1029 1030 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) 1031 vif = sc->offchannel.scan_vif; 1032 else 1033 vif = sc->offchannel.roc_vif; 1034 1035 if (WARN_ON(!vif)) 1036 goto exit; 1037 1038 eth_zero_addr(common->curbssid); 1039 eth_broadcast_addr(common->bssidmask); 1040 ether_addr_copy(common->macaddr, vif->addr); 1041 common->curaid = 0; 1042 ah->opmode = vif->type; 1043 ah->imask &= ~ATH9K_INT_SWBA; 1044 ah->imask &= ~ATH9K_INT_TSFOOR; 1045 ah->slottime = ATH9K_SLOT_TIME_9; 1046 1047 ath_hw_setbssidmask(common); 1048 ath9k_hw_setopmode(ah); 1049 ath9k_hw_write_associd(sc->sc_ah); 1050 ath9k_hw_set_interrupts(ah); 1051 ath9k_hw_init_global_settings(ah); 1052 1053 exit: 1054 ath9k_ps_restore(sc); 1055 } 1056 #endif 1057 1058 /* Called with sc->mutex held. */ 1059 void ath9k_calculate_summary_state(struct ath_softc *sc, 1060 struct ath_chanctx *ctx) 1061 { 1062 struct ath_hw *ah = sc->sc_ah; 1063 struct ath_common *common = ath9k_hw_common(ah); 1064 struct ath9k_vif_iter_data iter_data; 1065 struct ath_beacon_config *cur_conf; 1066 1067 ath_chanctx_check_active(sc, ctx); 1068 1069 if (ctx != sc->cur_chan) 1070 return; 1071 1072 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 1073 if (ctx == &sc->offchannel.chan) 1074 return ath9k_set_offchannel_state(sc); 1075 #endif 1076 1077 ath9k_ps_wakeup(sc); 1078 ath9k_calculate_iter_data(sc, ctx, &iter_data); 1079 1080 if (iter_data.has_hw_macaddr) 1081 ether_addr_copy(common->macaddr, iter_data.hw_macaddr); 1082 1083 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); 1084 ath_hw_setbssidmask(common); 1085 1086 if (iter_data.naps > 0) { 1087 cur_conf = &ctx->beacon; 1088 ath9k_hw_set_tsfadjust(ah, true); 1089 ah->opmode = NL80211_IFTYPE_AP; 1090 if (cur_conf->enable_beacon) 1091 iter_data.beacons = true; 1092 } else { 1093 ath9k_hw_set_tsfadjust(ah, false); 1094 1095 if (iter_data.nmeshes) 1096 ah->opmode = NL80211_IFTYPE_MESH_POINT; 1097 else if (iter_data.nwds) 1098 ah->opmode = NL80211_IFTYPE_AP; 1099 else if (iter_data.nadhocs) 1100 ah->opmode = NL80211_IFTYPE_ADHOC; 1101 else 1102 ah->opmode = NL80211_IFTYPE_STATION; 1103 } 1104 1105 ath9k_hw_setopmode(ah); 1106 1107 ctx->switch_after_beacon = false; 1108 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) 1109 ah->imask |= ATH9K_INT_TSFOOR; 1110 else { 1111 ah->imask &= ~ATH9K_INT_TSFOOR; 1112 if (iter_data.naps == 1 && iter_data.beacons) 1113 ctx->switch_after_beacon = true; 1114 } 1115 1116 ah->imask &= ~ATH9K_INT_SWBA; 1117 if (ah->opmode == NL80211_IFTYPE_STATION) { 1118 bool changed = (iter_data.primary_sta != ctx->primary_sta); 1119 1120 if (iter_data.primary_sta) { 1121 iter_data.beacons = true; 1122 ath9k_set_assoc_state(sc, iter_data.primary_sta, 1123 changed); 1124 ctx->primary_sta = iter_data.primary_sta; 1125 } else { 1126 ctx->primary_sta = NULL; 1127 memset(common->curbssid, 0, ETH_ALEN); 1128 common->curaid = 0; 1129 ath9k_hw_write_associd(sc->sc_ah); 1130 if (ath9k_hw_mci_is_enabled(sc->sc_ah)) 1131 ath9k_mci_update_wlan_channels(sc, true); 1132 } 1133 } else if (iter_data.beacons) { 1134 ah->imask |= ATH9K_INT_SWBA; 1135 } 1136 ath9k_hw_set_interrupts(ah); 1137 1138 if (iter_data.beacons) 1139 set_bit(ATH_OP_BEACONS, &common->op_flags); 1140 else 1141 clear_bit(ATH_OP_BEACONS, &common->op_flags); 1142 1143 if (ah->slottime != iter_data.slottime) { 1144 ah->slottime = iter_data.slottime; 1145 ath9k_hw_init_global_settings(ah); 1146 } 1147 1148 if (iter_data.primary_sta) 1149 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1150 else 1151 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); 1152 1153 ath_dbg(common, CONFIG, 1154 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n", 1155 common->macaddr, common->curbssid, common->bssidmask); 1156 1157 ath9k_ps_restore(sc); 1158 } 1159 1160 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw, 1161 struct ieee80211_vif *vif) 1162 { 1163 int i; 1164 1165 if (!ath9k_is_chanctx_enabled()) 1166 return; 1167 1168 for (i = 0; i < IEEE80211_NUM_ACS; i++) 1169 vif->hw_queue[i] = i; 1170 1171 if (vif->type == NL80211_IFTYPE_AP) 1172 vif->cab_queue = hw->queues - 2; 1173 else 1174 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; 1175 } 1176 1177 static int ath9k_add_interface(struct ieee80211_hw *hw, 1178 struct ieee80211_vif *vif) 1179 { 1180 struct ath_softc *sc = hw->priv; 1181 struct ath_hw *ah = sc->sc_ah; 1182 struct ath_common *common = ath9k_hw_common(ah); 1183 struct ath_vif *avp = (void *)vif->drv_priv; 1184 struct ath_node *an = &avp->mcast_node; 1185 1186 mutex_lock(&sc->mutex); 1187 1188 if (config_enabled(CONFIG_ATH9K_TX99)) { 1189 if (sc->cur_chan->nvifs >= 1) { 1190 mutex_unlock(&sc->mutex); 1191 return -EOPNOTSUPP; 1192 } 1193 sc->tx99_vif = vif; 1194 } 1195 1196 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); 1197 sc->cur_chan->nvifs++; 1198 1199 if (ath9k_uses_beacons(vif->type)) 1200 ath9k_beacon_assign_slot(sc, vif); 1201 1202 avp->vif = vif; 1203 if (!ath9k_is_chanctx_enabled()) { 1204 avp->chanctx = sc->cur_chan; 1205 list_add_tail(&avp->list, &avp->chanctx->vifs); 1206 } 1207 1208 ath9k_assign_hw_queues(hw, vif); 1209 1210 an->sc = sc; 1211 an->sta = NULL; 1212 an->vif = vif; 1213 an->no_ps_filter = true; 1214 ath_tx_node_init(sc, an); 1215 1216 mutex_unlock(&sc->mutex); 1217 return 0; 1218 } 1219 1220 static int ath9k_change_interface(struct ieee80211_hw *hw, 1221 struct ieee80211_vif *vif, 1222 enum nl80211_iftype new_type, 1223 bool p2p) 1224 { 1225 struct ath_softc *sc = hw->priv; 1226 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1227 struct ath_vif *avp = (void *)vif->drv_priv; 1228 1229 mutex_lock(&sc->mutex); 1230 1231 if (config_enabled(CONFIG_ATH9K_TX99)) { 1232 mutex_unlock(&sc->mutex); 1233 return -EOPNOTSUPP; 1234 } 1235 1236 ath_dbg(common, CONFIG, "Change Interface\n"); 1237 1238 if (ath9k_uses_beacons(vif->type)) 1239 ath9k_beacon_remove_slot(sc, vif); 1240 1241 vif->type = new_type; 1242 vif->p2p = p2p; 1243 1244 if (ath9k_uses_beacons(vif->type)) 1245 ath9k_beacon_assign_slot(sc, vif); 1246 1247 ath9k_assign_hw_queues(hw, vif); 1248 ath9k_calculate_summary_state(sc, avp->chanctx); 1249 1250 mutex_unlock(&sc->mutex); 1251 return 0; 1252 } 1253 1254 static void ath9k_remove_interface(struct ieee80211_hw *hw, 1255 struct ieee80211_vif *vif) 1256 { 1257 struct ath_softc *sc = hw->priv; 1258 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1259 struct ath_vif *avp = (void *)vif->drv_priv; 1260 1261 ath_dbg(common, CONFIG, "Detach Interface\n"); 1262 1263 mutex_lock(&sc->mutex); 1264 1265 ath9k_p2p_remove_vif(sc, vif); 1266 1267 sc->cur_chan->nvifs--; 1268 sc->tx99_vif = NULL; 1269 if (!ath9k_is_chanctx_enabled()) 1270 list_del(&avp->list); 1271 1272 if (ath9k_uses_beacons(vif->type)) 1273 ath9k_beacon_remove_slot(sc, vif); 1274 1275 ath_tx_node_cleanup(sc, &avp->mcast_node); 1276 1277 mutex_unlock(&sc->mutex); 1278 } 1279 1280 static void ath9k_enable_ps(struct ath_softc *sc) 1281 { 1282 struct ath_hw *ah = sc->sc_ah; 1283 struct ath_common *common = ath9k_hw_common(ah); 1284 1285 if (config_enabled(CONFIG_ATH9K_TX99)) 1286 return; 1287 1288 sc->ps_enabled = true; 1289 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1290 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { 1291 ah->imask |= ATH9K_INT_TIM_TIMER; 1292 ath9k_hw_set_interrupts(ah); 1293 } 1294 ath9k_hw_setrxabort(ah, 1); 1295 } 1296 ath_dbg(common, PS, "PowerSave enabled\n"); 1297 } 1298 1299 static void ath9k_disable_ps(struct ath_softc *sc) 1300 { 1301 struct ath_hw *ah = sc->sc_ah; 1302 struct ath_common *common = ath9k_hw_common(ah); 1303 1304 if (config_enabled(CONFIG_ATH9K_TX99)) 1305 return; 1306 1307 sc->ps_enabled = false; 1308 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); 1309 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1310 ath9k_hw_setrxabort(ah, 0); 1311 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | 1312 PS_WAIT_FOR_CAB | 1313 PS_WAIT_FOR_PSPOLL_DATA | 1314 PS_WAIT_FOR_TX_ACK); 1315 if (ah->imask & ATH9K_INT_TIM_TIMER) { 1316 ah->imask &= ~ATH9K_INT_TIM_TIMER; 1317 ath9k_hw_set_interrupts(ah); 1318 } 1319 } 1320 ath_dbg(common, PS, "PowerSave disabled\n"); 1321 } 1322 1323 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) 1324 { 1325 struct ath_softc *sc = hw->priv; 1326 struct ath_hw *ah = sc->sc_ah; 1327 struct ath_common *common = ath9k_hw_common(ah); 1328 u32 rxfilter; 1329 1330 if (config_enabled(CONFIG_ATH9K_TX99)) 1331 return; 1332 1333 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1334 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1335 return; 1336 } 1337 1338 ath9k_ps_wakeup(sc); 1339 rxfilter = ath9k_hw_getrxfilter(ah); 1340 ath9k_hw_setrxfilter(ah, rxfilter | 1341 ATH9K_RX_FILTER_PHYRADAR | 1342 ATH9K_RX_FILTER_PHYERR); 1343 1344 /* TODO: usually this should not be neccesary, but for some reason 1345 * (or in some mode?) the trigger must be called after the 1346 * configuration, otherwise the register will have its values reset 1347 * (on my ar9220 to value 0x01002310) 1348 */ 1349 ath9k_spectral_scan_config(hw, sc->spectral_mode); 1350 ath9k_hw_ops(ah)->spectral_scan_trigger(ah); 1351 ath9k_ps_restore(sc); 1352 } 1353 1354 int ath9k_spectral_scan_config(struct ieee80211_hw *hw, 1355 enum spectral_mode spectral_mode) 1356 { 1357 struct ath_softc *sc = hw->priv; 1358 struct ath_hw *ah = sc->sc_ah; 1359 struct ath_common *common = ath9k_hw_common(ah); 1360 1361 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { 1362 ath_err(common, "spectrum analyzer not implemented on this hardware\n"); 1363 return -1; 1364 } 1365 1366 switch (spectral_mode) { 1367 case SPECTRAL_DISABLED: 1368 sc->spec_config.enabled = 0; 1369 break; 1370 case SPECTRAL_BACKGROUND: 1371 /* send endless samples. 1372 * TODO: is this really useful for "background"? 1373 */ 1374 sc->spec_config.endless = 1; 1375 sc->spec_config.enabled = 1; 1376 break; 1377 case SPECTRAL_CHANSCAN: 1378 case SPECTRAL_MANUAL: 1379 sc->spec_config.endless = 0; 1380 sc->spec_config.enabled = 1; 1381 break; 1382 default: 1383 return -1; 1384 } 1385 1386 ath9k_ps_wakeup(sc); 1387 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); 1388 ath9k_ps_restore(sc); 1389 1390 sc->spectral_mode = spectral_mode; 1391 1392 return 0; 1393 } 1394 1395 static int ath9k_config(struct ieee80211_hw *hw, u32 changed) 1396 { 1397 struct ath_softc *sc = hw->priv; 1398 struct ath_hw *ah = sc->sc_ah; 1399 struct ath_common *common = ath9k_hw_common(ah); 1400 struct ieee80211_conf *conf = &hw->conf; 1401 struct ath_chanctx *ctx = sc->cur_chan; 1402 1403 ath9k_ps_wakeup(sc); 1404 mutex_lock(&sc->mutex); 1405 1406 if (changed & IEEE80211_CONF_CHANGE_IDLE) { 1407 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); 1408 if (sc->ps_idle) { 1409 ath_cancel_work(sc); 1410 ath9k_stop_btcoex(sc); 1411 } else { 1412 ath9k_start_btcoex(sc); 1413 /* 1414 * The chip needs a reset to properly wake up from 1415 * full sleep 1416 */ 1417 ath_chanctx_set_channel(sc, ctx, &ctx->chandef); 1418 } 1419 } 1420 1421 /* 1422 * We just prepare to enable PS. We have to wait until our AP has 1423 * ACK'd our null data frame to disable RX otherwise we'll ignore 1424 * those ACKs and end up retransmitting the same null data frames. 1425 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. 1426 */ 1427 if (changed & IEEE80211_CONF_CHANGE_PS) { 1428 unsigned long flags; 1429 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1430 if (conf->flags & IEEE80211_CONF_PS) 1431 ath9k_enable_ps(sc); 1432 else 1433 ath9k_disable_ps(sc); 1434 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1435 } 1436 1437 if (changed & IEEE80211_CONF_CHANGE_MONITOR) { 1438 if (conf->flags & IEEE80211_CONF_MONITOR) { 1439 ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); 1440 sc->sc_ah->is_monitoring = true; 1441 } else { 1442 ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); 1443 sc->sc_ah->is_monitoring = false; 1444 } 1445 } 1446 1447 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { 1448 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); 1449 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); 1450 } 1451 1452 if (changed & IEEE80211_CONF_CHANGE_POWER) { 1453 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); 1454 sc->cur_chan->txpower = 2 * conf->power_level; 1455 ath9k_cmn_update_txpow(ah, sc->curtxpow, 1456 sc->cur_chan->txpower, &sc->curtxpow); 1457 } 1458 1459 mutex_unlock(&sc->mutex); 1460 ath9k_ps_restore(sc); 1461 1462 return 0; 1463 } 1464 1465 #define SUPPORTED_FILTERS \ 1466 (FIF_PROMISC_IN_BSS | \ 1467 FIF_ALLMULTI | \ 1468 FIF_CONTROL | \ 1469 FIF_PSPOLL | \ 1470 FIF_OTHER_BSS | \ 1471 FIF_BCN_PRBRESP_PROMISC | \ 1472 FIF_PROBE_REQ | \ 1473 FIF_FCSFAIL) 1474 1475 /* FIXME: sc->sc_full_reset ? */ 1476 static void ath9k_configure_filter(struct ieee80211_hw *hw, 1477 unsigned int changed_flags, 1478 unsigned int *total_flags, 1479 u64 multicast) 1480 { 1481 struct ath_softc *sc = hw->priv; 1482 u32 rfilt; 1483 1484 changed_flags &= SUPPORTED_FILTERS; 1485 *total_flags &= SUPPORTED_FILTERS; 1486 1487 spin_lock_bh(&sc->chan_lock); 1488 sc->cur_chan->rxfilter = *total_flags; 1489 spin_unlock_bh(&sc->chan_lock); 1490 1491 ath9k_ps_wakeup(sc); 1492 rfilt = ath_calcrxfilter(sc); 1493 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 1494 ath9k_ps_restore(sc); 1495 1496 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", 1497 rfilt); 1498 } 1499 1500 static int ath9k_sta_add(struct ieee80211_hw *hw, 1501 struct ieee80211_vif *vif, 1502 struct ieee80211_sta *sta) 1503 { 1504 struct ath_softc *sc = hw->priv; 1505 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1506 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1507 struct ieee80211_key_conf ps_key = { }; 1508 int key; 1509 1510 ath_node_attach(sc, sta, vif); 1511 1512 if (vif->type != NL80211_IFTYPE_AP && 1513 vif->type != NL80211_IFTYPE_AP_VLAN) 1514 return 0; 1515 1516 key = ath_key_config(common, vif, sta, &ps_key); 1517 if (key > 0) { 1518 an->ps_key = key; 1519 an->key_idx[0] = key; 1520 } 1521 1522 return 0; 1523 } 1524 1525 static void ath9k_del_ps_key(struct ath_softc *sc, 1526 struct ieee80211_vif *vif, 1527 struct ieee80211_sta *sta) 1528 { 1529 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1530 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1531 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; 1532 1533 if (!an->ps_key) 1534 return; 1535 1536 ath_key_delete(common, &ps_key); 1537 an->ps_key = 0; 1538 an->key_idx[0] = 0; 1539 } 1540 1541 static int ath9k_sta_remove(struct ieee80211_hw *hw, 1542 struct ieee80211_vif *vif, 1543 struct ieee80211_sta *sta) 1544 { 1545 struct ath_softc *sc = hw->priv; 1546 1547 ath9k_del_ps_key(sc, vif, sta); 1548 ath_node_detach(sc, sta); 1549 1550 return 0; 1551 } 1552 1553 static void ath9k_sta_set_tx_filter(struct ath_hw *ah, 1554 struct ath_node *an, 1555 bool set) 1556 { 1557 int i; 1558 1559 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1560 if (!an->key_idx[i]) 1561 continue; 1562 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); 1563 } 1564 } 1565 1566 static void ath9k_sta_notify(struct ieee80211_hw *hw, 1567 struct ieee80211_vif *vif, 1568 enum sta_notify_cmd cmd, 1569 struct ieee80211_sta *sta) 1570 { 1571 struct ath_softc *sc = hw->priv; 1572 struct ath_node *an = (struct ath_node *) sta->drv_priv; 1573 1574 switch (cmd) { 1575 case STA_NOTIFY_SLEEP: 1576 an->sleeping = true; 1577 ath_tx_aggr_sleep(sta, sc, an); 1578 ath9k_sta_set_tx_filter(sc->sc_ah, an, true); 1579 break; 1580 case STA_NOTIFY_AWAKE: 1581 ath9k_sta_set_tx_filter(sc->sc_ah, an, false); 1582 an->sleeping = false; 1583 ath_tx_aggr_wakeup(sc, an); 1584 break; 1585 } 1586 } 1587 1588 static int ath9k_conf_tx(struct ieee80211_hw *hw, 1589 struct ieee80211_vif *vif, u16 queue, 1590 const struct ieee80211_tx_queue_params *params) 1591 { 1592 struct ath_softc *sc = hw->priv; 1593 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1594 struct ath_txq *txq; 1595 struct ath9k_tx_queue_info qi; 1596 int ret = 0; 1597 1598 if (queue >= IEEE80211_NUM_ACS) 1599 return 0; 1600 1601 txq = sc->tx.txq_map[queue]; 1602 1603 ath9k_ps_wakeup(sc); 1604 mutex_lock(&sc->mutex); 1605 1606 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); 1607 1608 qi.tqi_aifs = params->aifs; 1609 qi.tqi_cwmin = params->cw_min; 1610 qi.tqi_cwmax = params->cw_max; 1611 qi.tqi_burstTime = params->txop * 32; 1612 1613 ath_dbg(common, CONFIG, 1614 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 1615 queue, txq->axq_qnum, params->aifs, params->cw_min, 1616 params->cw_max, params->txop); 1617 1618 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); 1619 ret = ath_txq_update(sc, txq->axq_qnum, &qi); 1620 if (ret) 1621 ath_err(common, "TXQ Update failed\n"); 1622 1623 mutex_unlock(&sc->mutex); 1624 ath9k_ps_restore(sc); 1625 1626 return ret; 1627 } 1628 1629 static int ath9k_set_key(struct ieee80211_hw *hw, 1630 enum set_key_cmd cmd, 1631 struct ieee80211_vif *vif, 1632 struct ieee80211_sta *sta, 1633 struct ieee80211_key_conf *key) 1634 { 1635 struct ath_softc *sc = hw->priv; 1636 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1637 struct ath_node *an = NULL; 1638 int ret = 0, i; 1639 1640 if (ath9k_modparam_nohwcrypt) 1641 return -ENOSPC; 1642 1643 if ((vif->type == NL80211_IFTYPE_ADHOC || 1644 vif->type == NL80211_IFTYPE_MESH_POINT) && 1645 (key->cipher == WLAN_CIPHER_SUITE_TKIP || 1646 key->cipher == WLAN_CIPHER_SUITE_CCMP) && 1647 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 1648 /* 1649 * For now, disable hw crypto for the RSN IBSS group keys. This 1650 * could be optimized in the future to use a modified key cache 1651 * design to support per-STA RX GTK, but until that gets 1652 * implemented, use of software crypto for group addressed 1653 * frames is a acceptable to allow RSN IBSS to be used. 1654 */ 1655 return -EOPNOTSUPP; 1656 } 1657 1658 mutex_lock(&sc->mutex); 1659 ath9k_ps_wakeup(sc); 1660 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); 1661 if (sta) 1662 an = (struct ath_node *)sta->drv_priv; 1663 1664 switch (cmd) { 1665 case SET_KEY: 1666 if (sta) 1667 ath9k_del_ps_key(sc, vif, sta); 1668 1669 key->hw_key_idx = 0; 1670 ret = ath_key_config(common, vif, sta, key); 1671 if (ret >= 0) { 1672 key->hw_key_idx = ret; 1673 /* push IV and Michael MIC generation to stack */ 1674 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 1675 if (key->cipher == WLAN_CIPHER_SUITE_TKIP) 1676 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 1677 if (sc->sc_ah->sw_mgmt_crypto && 1678 key->cipher == WLAN_CIPHER_SUITE_CCMP) 1679 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; 1680 ret = 0; 1681 } 1682 if (an && key->hw_key_idx) { 1683 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1684 if (an->key_idx[i]) 1685 continue; 1686 an->key_idx[i] = key->hw_key_idx; 1687 break; 1688 } 1689 WARN_ON(i == ARRAY_SIZE(an->key_idx)); 1690 } 1691 break; 1692 case DISABLE_KEY: 1693 ath_key_delete(common, key); 1694 if (an) { 1695 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { 1696 if (an->key_idx[i] != key->hw_key_idx) 1697 continue; 1698 an->key_idx[i] = 0; 1699 break; 1700 } 1701 } 1702 key->hw_key_idx = 0; 1703 break; 1704 default: 1705 ret = -EINVAL; 1706 } 1707 1708 ath9k_ps_restore(sc); 1709 mutex_unlock(&sc->mutex); 1710 1711 return ret; 1712 } 1713 1714 static void ath9k_bss_info_changed(struct ieee80211_hw *hw, 1715 struct ieee80211_vif *vif, 1716 struct ieee80211_bss_conf *bss_conf, 1717 u32 changed) 1718 { 1719 #define CHECK_ANI \ 1720 (BSS_CHANGED_ASSOC | \ 1721 BSS_CHANGED_IBSS | \ 1722 BSS_CHANGED_BEACON_ENABLED) 1723 1724 struct ath_softc *sc = hw->priv; 1725 struct ath_hw *ah = sc->sc_ah; 1726 struct ath_common *common = ath9k_hw_common(ah); 1727 struct ath_vif *avp = (void *)vif->drv_priv; 1728 int slottime; 1729 1730 ath9k_ps_wakeup(sc); 1731 mutex_lock(&sc->mutex); 1732 1733 if (changed & BSS_CHANGED_ASSOC) { 1734 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", 1735 bss_conf->bssid, bss_conf->assoc); 1736 1737 ether_addr_copy(avp->bssid, bss_conf->bssid); 1738 avp->aid = bss_conf->aid; 1739 avp->assoc = bss_conf->assoc; 1740 1741 ath9k_calculate_summary_state(sc, avp->chanctx); 1742 1743 if (ath9k_is_chanctx_enabled()) { 1744 if (bss_conf->assoc) 1745 ath_chanctx_event(sc, vif, 1746 ATH_CHANCTX_EVENT_ASSOC); 1747 } 1748 } 1749 1750 if (changed & BSS_CHANGED_IBSS) { 1751 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1752 common->curaid = bss_conf->aid; 1753 ath9k_hw_write_associd(sc->sc_ah); 1754 } 1755 1756 if ((changed & BSS_CHANGED_BEACON_ENABLED) || 1757 (changed & BSS_CHANGED_BEACON_INT) || 1758 (changed & BSS_CHANGED_BEACON_INFO)) { 1759 ath9k_beacon_config(sc, vif, changed); 1760 if (changed & BSS_CHANGED_BEACON_ENABLED) 1761 ath9k_calculate_summary_state(sc, avp->chanctx); 1762 } 1763 1764 if ((avp->chanctx == sc->cur_chan) && 1765 (changed & BSS_CHANGED_ERP_SLOT)) { 1766 if (bss_conf->use_short_slot) 1767 slottime = 9; 1768 else 1769 slottime = 20; 1770 if (vif->type == NL80211_IFTYPE_AP) { 1771 /* 1772 * Defer update, so that connected stations can adjust 1773 * their settings at the same time. 1774 * See beacon.c for more details 1775 */ 1776 sc->beacon.slottime = slottime; 1777 sc->beacon.updateslot = UPDATE; 1778 } else { 1779 ah->slottime = slottime; 1780 ath9k_hw_init_global_settings(ah); 1781 } 1782 } 1783 1784 if (changed & BSS_CHANGED_P2P_PS) 1785 ath9k_p2p_bss_info_changed(sc, vif); 1786 1787 if (changed & CHECK_ANI) 1788 ath_check_ani(sc); 1789 1790 mutex_unlock(&sc->mutex); 1791 ath9k_ps_restore(sc); 1792 1793 #undef CHECK_ANI 1794 } 1795 1796 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1797 { 1798 struct ath_softc *sc = hw->priv; 1799 u64 tsf; 1800 1801 mutex_lock(&sc->mutex); 1802 ath9k_ps_wakeup(sc); 1803 tsf = ath9k_hw_gettsf64(sc->sc_ah); 1804 ath9k_ps_restore(sc); 1805 mutex_unlock(&sc->mutex); 1806 1807 return tsf; 1808 } 1809 1810 static void ath9k_set_tsf(struct ieee80211_hw *hw, 1811 struct ieee80211_vif *vif, 1812 u64 tsf) 1813 { 1814 struct ath_softc *sc = hw->priv; 1815 1816 mutex_lock(&sc->mutex); 1817 ath9k_ps_wakeup(sc); 1818 ath9k_hw_settsf64(sc->sc_ah, tsf); 1819 ath9k_ps_restore(sc); 1820 mutex_unlock(&sc->mutex); 1821 } 1822 1823 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1824 { 1825 struct ath_softc *sc = hw->priv; 1826 1827 mutex_lock(&sc->mutex); 1828 1829 ath9k_ps_wakeup(sc); 1830 ath9k_hw_reset_tsf(sc->sc_ah); 1831 ath9k_ps_restore(sc); 1832 1833 mutex_unlock(&sc->mutex); 1834 } 1835 1836 static int ath9k_ampdu_action(struct ieee80211_hw *hw, 1837 struct ieee80211_vif *vif, 1838 enum ieee80211_ampdu_mlme_action action, 1839 struct ieee80211_sta *sta, 1840 u16 tid, u16 *ssn, u8 buf_size) 1841 { 1842 struct ath_softc *sc = hw->priv; 1843 bool flush = false; 1844 int ret = 0; 1845 1846 mutex_lock(&sc->mutex); 1847 1848 switch (action) { 1849 case IEEE80211_AMPDU_RX_START: 1850 break; 1851 case IEEE80211_AMPDU_RX_STOP: 1852 break; 1853 case IEEE80211_AMPDU_TX_START: 1854 ath9k_ps_wakeup(sc); 1855 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 1856 if (!ret) 1857 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1858 ath9k_ps_restore(sc); 1859 break; 1860 case IEEE80211_AMPDU_TX_STOP_FLUSH: 1861 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 1862 flush = true; 1863 case IEEE80211_AMPDU_TX_STOP_CONT: 1864 ath9k_ps_wakeup(sc); 1865 ath_tx_aggr_stop(sc, sta, tid); 1866 if (!flush) 1867 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 1868 ath9k_ps_restore(sc); 1869 break; 1870 case IEEE80211_AMPDU_TX_OPERATIONAL: 1871 ath9k_ps_wakeup(sc); 1872 ath_tx_aggr_resume(sc, sta, tid); 1873 ath9k_ps_restore(sc); 1874 break; 1875 default: 1876 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); 1877 } 1878 1879 mutex_unlock(&sc->mutex); 1880 1881 return ret; 1882 } 1883 1884 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, 1885 struct survey_info *survey) 1886 { 1887 struct ath_softc *sc = hw->priv; 1888 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1889 struct ieee80211_supported_band *sband; 1890 struct ieee80211_channel *chan; 1891 int pos; 1892 1893 if (config_enabled(CONFIG_ATH9K_TX99)) 1894 return -EOPNOTSUPP; 1895 1896 spin_lock_bh(&common->cc_lock); 1897 if (idx == 0) 1898 ath_update_survey_stats(sc); 1899 1900 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; 1901 if (sband && idx >= sband->n_channels) { 1902 idx -= sband->n_channels; 1903 sband = NULL; 1904 } 1905 1906 if (!sband) 1907 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; 1908 1909 if (!sband || idx >= sband->n_channels) { 1910 spin_unlock_bh(&common->cc_lock); 1911 return -ENOENT; 1912 } 1913 1914 chan = &sband->channels[idx]; 1915 pos = chan->hw_value; 1916 memcpy(survey, &sc->survey[pos], sizeof(*survey)); 1917 survey->channel = chan; 1918 spin_unlock_bh(&common->cc_lock); 1919 1920 return 0; 1921 } 1922 1923 static void ath9k_enable_dynack(struct ath_softc *sc) 1924 { 1925 #ifdef CONFIG_ATH9K_DYNACK 1926 u32 rfilt; 1927 struct ath_hw *ah = sc->sc_ah; 1928 1929 ath_dynack_reset(ah); 1930 1931 ah->dynack.enabled = true; 1932 rfilt = ath_calcrxfilter(sc); 1933 ath9k_hw_setrxfilter(ah, rfilt); 1934 #endif 1935 } 1936 1937 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, 1938 s16 coverage_class) 1939 { 1940 struct ath_softc *sc = hw->priv; 1941 struct ath_hw *ah = sc->sc_ah; 1942 1943 if (config_enabled(CONFIG_ATH9K_TX99)) 1944 return; 1945 1946 mutex_lock(&sc->mutex); 1947 1948 if (coverage_class >= 0) { 1949 ah->coverage_class = coverage_class; 1950 if (ah->dynack.enabled) { 1951 u32 rfilt; 1952 1953 ah->dynack.enabled = false; 1954 rfilt = ath_calcrxfilter(sc); 1955 ath9k_hw_setrxfilter(ah, rfilt); 1956 } 1957 ath9k_ps_wakeup(sc); 1958 ath9k_hw_init_global_settings(ah); 1959 ath9k_ps_restore(sc); 1960 } else if (!ah->dynack.enabled) { 1961 ath9k_enable_dynack(sc); 1962 } 1963 1964 mutex_unlock(&sc->mutex); 1965 } 1966 1967 static bool ath9k_has_tx_pending(struct ath_softc *sc) 1968 { 1969 int i, npend = 0; 1970 1971 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1972 if (!ATH_TXQ_SETUP(sc, i)) 1973 continue; 1974 1975 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); 1976 if (npend) 1977 break; 1978 } 1979 1980 return !!npend; 1981 } 1982 1983 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1984 u32 queues, bool drop) 1985 { 1986 struct ath_softc *sc = hw->priv; 1987 1988 mutex_lock(&sc->mutex); 1989 __ath9k_flush(hw, queues, drop); 1990 mutex_unlock(&sc->mutex); 1991 } 1992 1993 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop) 1994 { 1995 struct ath_softc *sc = hw->priv; 1996 struct ath_hw *ah = sc->sc_ah; 1997 struct ath_common *common = ath9k_hw_common(ah); 1998 int timeout = HZ / 5; /* 200 ms */ 1999 bool drain_txq; 2000 2001 cancel_delayed_work_sync(&sc->tx_complete_work); 2002 2003 if (ah->ah_flags & AH_UNPLUGGED) { 2004 ath_dbg(common, ANY, "Device has been unplugged!\n"); 2005 return; 2006 } 2007 2008 if (test_bit(ATH_OP_INVALID, &common->op_flags)) { 2009 ath_dbg(common, ANY, "Device not present\n"); 2010 return; 2011 } 2012 2013 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc), 2014 timeout) > 0) 2015 drop = false; 2016 2017 if (drop) { 2018 ath9k_ps_wakeup(sc); 2019 spin_lock_bh(&sc->sc_pcu_lock); 2020 drain_txq = ath_drain_all_txq(sc); 2021 spin_unlock_bh(&sc->sc_pcu_lock); 2022 2023 if (!drain_txq) 2024 ath_reset(sc); 2025 2026 ath9k_ps_restore(sc); 2027 } 2028 2029 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); 2030 } 2031 2032 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) 2033 { 2034 struct ath_softc *sc = hw->priv; 2035 2036 return ath9k_has_tx_pending(sc); 2037 } 2038 2039 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 2040 { 2041 struct ath_softc *sc = hw->priv; 2042 struct ath_hw *ah = sc->sc_ah; 2043 struct ieee80211_vif *vif; 2044 struct ath_vif *avp; 2045 struct ath_buf *bf; 2046 struct ath_tx_status ts; 2047 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2048 int status; 2049 2050 vif = sc->beacon.bslot[0]; 2051 if (!vif) 2052 return 0; 2053 2054 if (!vif->bss_conf.enable_beacon) 2055 return 0; 2056 2057 avp = (void *)vif->drv_priv; 2058 2059 if (!sc->beacon.tx_processed && !edma) { 2060 tasklet_disable(&sc->bcon_tasklet); 2061 2062 bf = avp->av_bcbuf; 2063 if (!bf || !bf->bf_mpdu) 2064 goto skip; 2065 2066 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); 2067 if (status == -EINPROGRESS) 2068 goto skip; 2069 2070 sc->beacon.tx_processed = true; 2071 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2072 2073 skip: 2074 tasklet_enable(&sc->bcon_tasklet); 2075 } 2076 2077 return sc->beacon.tx_last; 2078 } 2079 2080 static int ath9k_get_stats(struct ieee80211_hw *hw, 2081 struct ieee80211_low_level_stats *stats) 2082 { 2083 struct ath_softc *sc = hw->priv; 2084 struct ath_hw *ah = sc->sc_ah; 2085 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; 2086 2087 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; 2088 stats->dot11RTSFailureCount = mib_stats->rts_bad; 2089 stats->dot11FCSErrorCount = mib_stats->fcs_bad; 2090 stats->dot11RTSSuccessCount = mib_stats->rts_good; 2091 return 0; 2092 } 2093 2094 static u32 fill_chainmask(u32 cap, u32 new) 2095 { 2096 u32 filled = 0; 2097 int i; 2098 2099 for (i = 0; cap && new; i++, cap >>= 1) { 2100 if (!(cap & BIT(0))) 2101 continue; 2102 2103 if (new & BIT(0)) 2104 filled |= BIT(i); 2105 2106 new >>= 1; 2107 } 2108 2109 return filled; 2110 } 2111 2112 static bool validate_antenna_mask(struct ath_hw *ah, u32 val) 2113 { 2114 if (AR_SREV_9300_20_OR_LATER(ah)) 2115 return true; 2116 2117 switch (val & 0x7) { 2118 case 0x1: 2119 case 0x3: 2120 case 0x7: 2121 return true; 2122 case 0x2: 2123 return (ah->caps.rx_chainmask == 1); 2124 default: 2125 return false; 2126 } 2127 } 2128 2129 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 2130 { 2131 struct ath_softc *sc = hw->priv; 2132 struct ath_hw *ah = sc->sc_ah; 2133 2134 if (ah->caps.rx_chainmask != 1) 2135 rx_ant |= tx_ant; 2136 2137 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) 2138 return -EINVAL; 2139 2140 sc->ant_rx = rx_ant; 2141 sc->ant_tx = tx_ant; 2142 2143 if (ah->caps.rx_chainmask == 1) 2144 return 0; 2145 2146 /* AR9100 runs into calibration issues if not all rx chains are enabled */ 2147 if (AR_SREV_9100(ah)) 2148 ah->rxchainmask = 0x7; 2149 else 2150 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); 2151 2152 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); 2153 ath9k_cmn_reload_chainmask(ah); 2154 2155 return 0; 2156 } 2157 2158 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 2159 { 2160 struct ath_softc *sc = hw->priv; 2161 2162 *tx_ant = sc->ant_tx; 2163 *rx_ant = sc->ant_rx; 2164 return 0; 2165 } 2166 2167 static void ath9k_sw_scan_start(struct ieee80211_hw *hw) 2168 { 2169 struct ath_softc *sc = hw->priv; 2170 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2171 set_bit(ATH_OP_SCANNING, &common->op_flags); 2172 } 2173 2174 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) 2175 { 2176 struct ath_softc *sc = hw->priv; 2177 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2178 clear_bit(ATH_OP_SCANNING, &common->op_flags); 2179 } 2180 2181 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 2182 2183 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2184 struct ieee80211_scan_request *hw_req) 2185 { 2186 struct cfg80211_scan_request *req = &hw_req->req; 2187 struct ath_softc *sc = hw->priv; 2188 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2189 int ret = 0; 2190 2191 mutex_lock(&sc->mutex); 2192 2193 if (WARN_ON(sc->offchannel.scan_req)) { 2194 ret = -EBUSY; 2195 goto out; 2196 } 2197 2198 ath9k_ps_wakeup(sc); 2199 set_bit(ATH_OP_SCANNING, &common->op_flags); 2200 sc->offchannel.scan_vif = vif; 2201 sc->offchannel.scan_req = req; 2202 sc->offchannel.scan_idx = 0; 2203 2204 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n", 2205 vif->addr); 2206 2207 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2208 ath_dbg(common, CHAN_CTX, "Starting HW scan\n"); 2209 ath_offchannel_next(sc); 2210 } 2211 2212 out: 2213 mutex_unlock(&sc->mutex); 2214 2215 return ret; 2216 } 2217 2218 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, 2219 struct ieee80211_vif *vif) 2220 { 2221 struct ath_softc *sc = hw->priv; 2222 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2223 2224 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr); 2225 2226 mutex_lock(&sc->mutex); 2227 del_timer_sync(&sc->offchannel.timer); 2228 ath_scan_complete(sc, true); 2229 mutex_unlock(&sc->mutex); 2230 } 2231 2232 static int ath9k_remain_on_channel(struct ieee80211_hw *hw, 2233 struct ieee80211_vif *vif, 2234 struct ieee80211_channel *chan, int duration, 2235 enum ieee80211_roc_type type) 2236 { 2237 struct ath_softc *sc = hw->priv; 2238 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2239 int ret = 0; 2240 2241 mutex_lock(&sc->mutex); 2242 2243 if (WARN_ON(sc->offchannel.roc_vif)) { 2244 ret = -EBUSY; 2245 goto out; 2246 } 2247 2248 ath9k_ps_wakeup(sc); 2249 sc->offchannel.roc_vif = vif; 2250 sc->offchannel.roc_chan = chan; 2251 sc->offchannel.roc_duration = duration; 2252 2253 ath_dbg(common, CHAN_CTX, 2254 "RoC request on vif: %pM, type: %d duration: %d\n", 2255 vif->addr, type, duration); 2256 2257 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { 2258 ath_dbg(common, CHAN_CTX, "Starting RoC period\n"); 2259 ath_offchannel_next(sc); 2260 } 2261 2262 out: 2263 mutex_unlock(&sc->mutex); 2264 2265 return ret; 2266 } 2267 2268 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw) 2269 { 2270 struct ath_softc *sc = hw->priv; 2271 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2272 2273 mutex_lock(&sc->mutex); 2274 2275 ath_dbg(common, CHAN_CTX, "Cancel RoC\n"); 2276 del_timer_sync(&sc->offchannel.timer); 2277 2278 if (sc->offchannel.roc_vif) { 2279 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) 2280 ath_roc_complete(sc, true); 2281 } 2282 2283 mutex_unlock(&sc->mutex); 2284 2285 return 0; 2286 } 2287 2288 static int ath9k_add_chanctx(struct ieee80211_hw *hw, 2289 struct ieee80211_chanctx_conf *conf) 2290 { 2291 struct ath_softc *sc = hw->priv; 2292 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2293 struct ath_chanctx *ctx, **ptr; 2294 int pos; 2295 2296 mutex_lock(&sc->mutex); 2297 2298 ath_for_each_chanctx(sc, ctx) { 2299 if (ctx->assigned) 2300 continue; 2301 2302 ptr = (void *) conf->drv_priv; 2303 *ptr = ctx; 2304 ctx->assigned = true; 2305 pos = ctx - &sc->chanctx[0]; 2306 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; 2307 2308 ath_dbg(common, CHAN_CTX, 2309 "Add channel context: %d MHz\n", 2310 conf->def.chan->center_freq); 2311 2312 ath_chanctx_set_channel(sc, ctx, &conf->def); 2313 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_ASSIGN); 2314 2315 mutex_unlock(&sc->mutex); 2316 return 0; 2317 } 2318 2319 mutex_unlock(&sc->mutex); 2320 return -ENOSPC; 2321 } 2322 2323 2324 static void ath9k_remove_chanctx(struct ieee80211_hw *hw, 2325 struct ieee80211_chanctx_conf *conf) 2326 { 2327 struct ath_softc *sc = hw->priv; 2328 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2329 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2330 2331 mutex_lock(&sc->mutex); 2332 2333 ath_dbg(common, CHAN_CTX, 2334 "Remove channel context: %d MHz\n", 2335 conf->def.chan->center_freq); 2336 2337 ctx->assigned = false; 2338 ctx->hw_queue_base = 0; 2339 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); 2340 2341 mutex_unlock(&sc->mutex); 2342 } 2343 2344 static void ath9k_change_chanctx(struct ieee80211_hw *hw, 2345 struct ieee80211_chanctx_conf *conf, 2346 u32 changed) 2347 { 2348 struct ath_softc *sc = hw->priv; 2349 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2350 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2351 2352 mutex_lock(&sc->mutex); 2353 ath_dbg(common, CHAN_CTX, 2354 "Change channel context: %d MHz\n", 2355 conf->def.chan->center_freq); 2356 ath_chanctx_set_channel(sc, ctx, &conf->def); 2357 mutex_unlock(&sc->mutex); 2358 } 2359 2360 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, 2361 struct ieee80211_vif *vif, 2362 struct ieee80211_chanctx_conf *conf) 2363 { 2364 struct ath_softc *sc = hw->priv; 2365 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2366 struct ath_vif *avp = (void *)vif->drv_priv; 2367 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2368 int i; 2369 2370 mutex_lock(&sc->mutex); 2371 2372 ath_dbg(common, CHAN_CTX, 2373 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n", 2374 vif->addr, vif->type, vif->p2p, 2375 conf->def.chan->center_freq); 2376 2377 avp->chanctx = ctx; 2378 ctx->nvifs_assigned++; 2379 list_add_tail(&avp->list, &ctx->vifs); 2380 ath9k_calculate_summary_state(sc, ctx); 2381 for (i = 0; i < IEEE80211_NUM_ACS; i++) 2382 vif->hw_queue[i] = ctx->hw_queue_base + i; 2383 2384 mutex_unlock(&sc->mutex); 2385 2386 return 0; 2387 } 2388 2389 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, 2390 struct ieee80211_vif *vif, 2391 struct ieee80211_chanctx_conf *conf) 2392 { 2393 struct ath_softc *sc = hw->priv; 2394 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2395 struct ath_vif *avp = (void *)vif->drv_priv; 2396 struct ath_chanctx *ctx = ath_chanctx_get(conf); 2397 int ac; 2398 2399 mutex_lock(&sc->mutex); 2400 2401 ath_dbg(common, CHAN_CTX, 2402 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n", 2403 vif->addr, vif->type, vif->p2p, 2404 conf->def.chan->center_freq); 2405 2406 avp->chanctx = NULL; 2407 ctx->nvifs_assigned--; 2408 list_del(&avp->list); 2409 ath9k_calculate_summary_state(sc, ctx); 2410 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2411 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; 2412 2413 mutex_unlock(&sc->mutex); 2414 } 2415 2416 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw, 2417 struct ieee80211_vif *vif) 2418 { 2419 struct ath_softc *sc = hw->priv; 2420 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2421 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv; 2422 bool changed = false; 2423 2424 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) 2425 return; 2426 2427 if (!avp->chanctx) 2428 return; 2429 2430 mutex_lock(&sc->mutex); 2431 2432 spin_lock_bh(&sc->chan_lock); 2433 if (sc->next_chan || (sc->cur_chan != avp->chanctx)) { 2434 sc->next_chan = avp->chanctx; 2435 changed = true; 2436 } 2437 ath_dbg(common, CHAN_CTX, 2438 "%s: Set chanctx state to FORCE_ACTIVE, changed: %d\n", 2439 __func__, changed); 2440 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE; 2441 spin_unlock_bh(&sc->chan_lock); 2442 2443 if (changed) 2444 ath_chanctx_set_next(sc, true); 2445 2446 mutex_unlock(&sc->mutex); 2447 } 2448 2449 void ath9k_fill_chanctx_ops(void) 2450 { 2451 if (!ath9k_is_chanctx_enabled()) 2452 return; 2453 2454 ath9k_ops.hw_scan = ath9k_hw_scan; 2455 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; 2456 ath9k_ops.remain_on_channel = ath9k_remain_on_channel; 2457 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; 2458 ath9k_ops.add_chanctx = ath9k_add_chanctx; 2459 ath9k_ops.remove_chanctx = ath9k_remove_chanctx; 2460 ath9k_ops.change_chanctx = ath9k_change_chanctx; 2461 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; 2462 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; 2463 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx; 2464 } 2465 2466 #endif 2467 2468 struct ieee80211_ops ath9k_ops = { 2469 .tx = ath9k_tx, 2470 .start = ath9k_start, 2471 .stop = ath9k_stop, 2472 .add_interface = ath9k_add_interface, 2473 .change_interface = ath9k_change_interface, 2474 .remove_interface = ath9k_remove_interface, 2475 .config = ath9k_config, 2476 .configure_filter = ath9k_configure_filter, 2477 .sta_add = ath9k_sta_add, 2478 .sta_remove = ath9k_sta_remove, 2479 .sta_notify = ath9k_sta_notify, 2480 .conf_tx = ath9k_conf_tx, 2481 .bss_info_changed = ath9k_bss_info_changed, 2482 .set_key = ath9k_set_key, 2483 .get_tsf = ath9k_get_tsf, 2484 .set_tsf = ath9k_set_tsf, 2485 .reset_tsf = ath9k_reset_tsf, 2486 .ampdu_action = ath9k_ampdu_action, 2487 .get_survey = ath9k_get_survey, 2488 .rfkill_poll = ath9k_rfkill_poll_state, 2489 .set_coverage_class = ath9k_set_coverage_class, 2490 .flush = ath9k_flush, 2491 .tx_frames_pending = ath9k_tx_frames_pending, 2492 .tx_last_beacon = ath9k_tx_last_beacon, 2493 .release_buffered_frames = ath9k_release_buffered_frames, 2494 .get_stats = ath9k_get_stats, 2495 .set_antenna = ath9k_set_antenna, 2496 .get_antenna = ath9k_get_antenna, 2497 2498 #ifdef CONFIG_ATH9K_WOW 2499 .suspend = ath9k_suspend, 2500 .resume = ath9k_resume, 2501 .set_wakeup = ath9k_set_wakeup, 2502 #endif 2503 2504 #ifdef CONFIG_ATH9K_DEBUGFS 2505 .get_et_sset_count = ath9k_get_et_sset_count, 2506 .get_et_stats = ath9k_get_et_stats, 2507 .get_et_strings = ath9k_get_et_strings, 2508 #endif 2509 2510 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) 2511 .sta_add_debugfs = ath9k_sta_add_debugfs, 2512 #endif 2513 .sw_scan_start = ath9k_sw_scan_start, 2514 .sw_scan_complete = ath9k_sw_scan_complete, 2515 }; 2516