1 /* 2 * Copyright (c) 2008-2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef HW_H 18 #define HW_H 19 20 #include <linux/if_ether.h> 21 #include <linux/delay.h> 22 #include <linux/io.h> 23 24 #include "mac.h" 25 #include "ani.h" 26 #include "eeprom.h" 27 #include "calib.h" 28 #include "reg.h" 29 #include "phy.h" 30 #include "btcoex.h" 31 32 #include "../regd.h" 33 #include "../debug.h" 34 35 #define ATHEROS_VENDOR_ID 0x168c 36 37 #define AR5416_DEVID_PCI 0x0023 38 #define AR5416_DEVID_PCIE 0x0024 39 #define AR9160_DEVID_PCI 0x0027 40 #define AR9280_DEVID_PCI 0x0029 41 #define AR9280_DEVID_PCIE 0x002a 42 #define AR9285_DEVID_PCIE 0x002b 43 #define AR2427_DEVID_PCIE 0x002c 44 #define AR9287_DEVID_PCI 0x002d 45 #define AR9287_DEVID_PCIE 0x002e 46 #define AR9300_DEVID_PCIE 0x0030 47 48 #define AR5416_AR9100_DEVID 0x000b 49 50 #define AR_SUBVENDOR_ID_NOG 0x0e11 51 #define AR_SUBVENDOR_ID_NEW_A 0x7065 52 #define AR5416_MAGIC 0x19641014 53 54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b 55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa 56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab 57 58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 59 60 #define ATH_DEFAULT_NOISE_FLOOR -95 61 62 #define ATH9K_RSSI_BAD -128 63 64 /* Register read/write primitives */ 65 #define REG_WRITE(_ah, _reg, _val) \ 66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg)) 67 68 #define REG_READ(_ah, _reg) \ 69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg)) 70 71 #define ENABLE_REGWRITE_BUFFER(_ah) \ 72 do { \ 73 if (AR_SREV_9271(_ah)) \ 74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \ 75 } while (0) 76 77 #define DISABLE_REGWRITE_BUFFER(_ah) \ 78 do { \ 79 if (AR_SREV_9271(_ah)) \ 80 ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \ 81 } while (0) 82 83 #define REGWRITE_BUFFER_FLUSH(_ah) \ 84 do { \ 85 if (AR_SREV_9271(_ah)) \ 86 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \ 87 } while (0) 88 89 #define SM(_v, _f) (((_v) << _f##_S) & _f) 90 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 91 #define REG_RMW(_a, _r, _set, _clr) \ 92 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) 93 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 94 REG_WRITE(_a, _r, \ 95 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) 96 #define REG_READ_FIELD(_a, _r, _f) \ 97 (((REG_READ(_a, _r) & _f) >> _f##_S)) 98 #define REG_SET_BIT(_a, _r, _f) \ 99 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) 100 #define REG_CLR_BIT(_a, _r, _f) \ 101 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) 102 103 #define DO_DELAY(x) do { \ 104 if ((++(x) % 64) == 0) \ 105 udelay(1); \ 106 } while (0) 107 108 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ 109 int r; \ 110 for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 111 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ 112 INI_RA((iniarray), r, (column))); \ 113 DO_DELAY(regWr); \ 114 } \ 115 } while (0) 116 117 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 118 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 119 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 120 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 121 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 122 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 123 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 124 125 #define AR_GPIOD_MASK 0x00001FFF 126 #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 127 128 #define BASE_ACTIVATE_DELAY 100 129 #define RTC_PLL_SETTLE_DELAY 100 130 #define COEF_SCALE_S 24 131 #define HT40_CHANNEL_CENTER_SHIFT 10 132 133 #define ATH9K_ANTENNA0_CHAINMASK 0x1 134 #define ATH9K_ANTENNA1_CHAINMASK 0x2 135 136 #define ATH9K_NUM_DMA_DEBUG_REGS 8 137 #define ATH9K_NUM_QUEUES 10 138 139 #define MAX_RATE_POWER 63 140 #define AH_WAIT_TIMEOUT 100000 /* (us) */ 141 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ 142 #define AH_TIME_QUANTUM 10 143 #define AR_KEYTABLE_SIZE 128 144 #define POWER_UP_TIME 10000 145 #define SPUR_RSSI_THRESH 40 146 147 #define CAB_TIMEOUT_VAL 10 148 #define BEACON_TIMEOUT_VAL 10 149 #define MIN_BEACON_TIMEOUT_VAL 1 150 #define SLEEP_SLOP 3 151 152 #define INIT_CONFIG_STATUS 0x00000000 153 #define INIT_RSSI_THR 0x00000700 154 #define INIT_BCON_CNTRL_REG 0x00000000 155 156 #define TU_TO_USEC(_tu) ((_tu) << 10) 157 158 #define ATH9K_HW_RX_HP_QDEPTH 16 159 #define ATH9K_HW_RX_LP_QDEPTH 128 160 161 enum ath_ini_subsys { 162 ATH_INI_PRE = 0, 163 ATH_INI_CORE, 164 ATH_INI_POST, 165 ATH_INI_NUM_SPLIT, 166 }; 167 168 enum wireless_mode { 169 ATH9K_MODE_11A = 0, 170 ATH9K_MODE_11G, 171 ATH9K_MODE_11NA_HT20, 172 ATH9K_MODE_11NG_HT20, 173 ATH9K_MODE_11NA_HT40PLUS, 174 ATH9K_MODE_11NA_HT40MINUS, 175 ATH9K_MODE_11NG_HT40PLUS, 176 ATH9K_MODE_11NG_HT40MINUS, 177 ATH9K_MODE_MAX, 178 }; 179 180 enum ath9k_hw_caps { 181 ATH9K_HW_CAP_MIC_AESCCM = BIT(0), 182 ATH9K_HW_CAP_MIC_CKIP = BIT(1), 183 ATH9K_HW_CAP_MIC_TKIP = BIT(2), 184 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3), 185 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4), 186 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5), 187 ATH9K_HW_CAP_VEOL = BIT(6), 188 ATH9K_HW_CAP_BSSIDMASK = BIT(7), 189 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8), 190 ATH9K_HW_CAP_HT = BIT(9), 191 ATH9K_HW_CAP_GTT = BIT(10), 192 ATH9K_HW_CAP_FASTCC = BIT(11), 193 ATH9K_HW_CAP_RFSILENT = BIT(12), 194 ATH9K_HW_CAP_CST = BIT(13), 195 ATH9K_HW_CAP_ENHANCEDPM = BIT(14), 196 ATH9K_HW_CAP_AUTOSLEEP = BIT(15), 197 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16), 198 ATH9K_HW_CAP_EDMA = BIT(17), 199 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18), 200 ATH9K_HW_CAP_LDPC = BIT(19), 201 ATH9K_HW_CAP_FASTCLOCK = BIT(20), 202 ATH9K_HW_CAP_SGI_20 = BIT(21), 203 }; 204 205 enum ath9k_capability_type { 206 ATH9K_CAP_CIPHER = 0, 207 ATH9K_CAP_TKIP_MIC, 208 ATH9K_CAP_TKIP_SPLIT, 209 ATH9K_CAP_TXPOW, 210 ATH9K_CAP_MCAST_KEYSRCH, 211 ATH9K_CAP_DS 212 }; 213 214 struct ath9k_hw_capabilities { 215 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 216 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ 217 u16 total_queues; 218 u16 keycache_size; 219 u16 low_5ghz_chan, high_5ghz_chan; 220 u16 low_2ghz_chan, high_2ghz_chan; 221 u16 rts_aggr_limit; 222 u8 tx_chainmask; 223 u8 rx_chainmask; 224 u16 tx_triglevel_max; 225 u16 reg_cap; 226 u8 num_gpio_pins; 227 u8 num_antcfg_2ghz; 228 u8 num_antcfg_5ghz; 229 u8 rx_hp_qdepth; 230 u8 rx_lp_qdepth; 231 u8 rx_status_len; 232 u8 tx_desc_len; 233 u8 txs_len; 234 }; 235 236 struct ath9k_ops_config { 237 int dma_beacon_response_time; 238 int sw_beacon_response_time; 239 int additional_swba_backoff; 240 int ack_6mb; 241 int cwm_ignore_extcca; 242 u8 pcie_powersave_enable; 243 u8 pcie_clock_req; 244 u32 pcie_waen; 245 u8 analog_shiftreg; 246 u8 ht_enable; 247 u32 ofdm_trig_low; 248 u32 ofdm_trig_high; 249 u32 cck_trig_high; 250 u32 cck_trig_low; 251 u32 enable_ani; 252 int serialize_regmode; 253 bool rx_intr_mitigation; 254 bool tx_intr_mitigation; 255 #define SPUR_DISABLE 0 256 #define SPUR_ENABLE_IOCTL 1 257 #define SPUR_ENABLE_EEPROM 2 258 #define AR_EEPROM_MODAL_SPURS 5 259 #define AR_SPUR_5413_1 1640 260 #define AR_SPUR_5413_2 1200 261 #define AR_NO_SPUR 0x8000 262 #define AR_BASE_FREQ_2GHZ 2300 263 #define AR_BASE_FREQ_5GHZ 4900 264 #define AR_SPUR_FEEQ_BOUND_HT40 19 265 #define AR_SPUR_FEEQ_BOUND_HT20 10 266 int spurmode; 267 u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; 268 u8 max_txtrig_level; 269 u16 ani_poll_interval; /* ANI poll interval in ms */ 270 }; 271 272 enum ath9k_int { 273 ATH9K_INT_RX = 0x00000001, 274 ATH9K_INT_RXDESC = 0x00000002, 275 ATH9K_INT_RXHP = 0x00000001, 276 ATH9K_INT_RXLP = 0x00000002, 277 ATH9K_INT_RXNOFRM = 0x00000008, 278 ATH9K_INT_RXEOL = 0x00000010, 279 ATH9K_INT_RXORN = 0x00000020, 280 ATH9K_INT_TX = 0x00000040, 281 ATH9K_INT_TXDESC = 0x00000080, 282 ATH9K_INT_TIM_TIMER = 0x00000100, 283 ATH9K_INT_BB_WATCHDOG = 0x00000400, 284 ATH9K_INT_TXURN = 0x00000800, 285 ATH9K_INT_MIB = 0x00001000, 286 ATH9K_INT_RXPHY = 0x00004000, 287 ATH9K_INT_RXKCM = 0x00008000, 288 ATH9K_INT_SWBA = 0x00010000, 289 ATH9K_INT_BMISS = 0x00040000, 290 ATH9K_INT_BNR = 0x00100000, 291 ATH9K_INT_TIM = 0x00200000, 292 ATH9K_INT_DTIM = 0x00400000, 293 ATH9K_INT_DTIMSYNC = 0x00800000, 294 ATH9K_INT_GPIO = 0x01000000, 295 ATH9K_INT_CABEND = 0x02000000, 296 ATH9K_INT_TSFOOR = 0x04000000, 297 ATH9K_INT_GENTIMER = 0x08000000, 298 ATH9K_INT_CST = 0x10000000, 299 ATH9K_INT_GTT = 0x20000000, 300 ATH9K_INT_FATAL = 0x40000000, 301 ATH9K_INT_GLOBAL = 0x80000000, 302 ATH9K_INT_BMISC = ATH9K_INT_TIM | 303 ATH9K_INT_DTIM | 304 ATH9K_INT_DTIMSYNC | 305 ATH9K_INT_TSFOOR | 306 ATH9K_INT_CABEND, 307 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 308 ATH9K_INT_RXDESC | 309 ATH9K_INT_RXEOL | 310 ATH9K_INT_RXORN | 311 ATH9K_INT_TXURN | 312 ATH9K_INT_TXDESC | 313 ATH9K_INT_MIB | 314 ATH9K_INT_RXPHY | 315 ATH9K_INT_RXKCM | 316 ATH9K_INT_SWBA | 317 ATH9K_INT_BMISS | 318 ATH9K_INT_GPIO, 319 ATH9K_INT_NOCARD = 0xffffffff 320 }; 321 322 #define CHANNEL_CW_INT 0x00002 323 #define CHANNEL_CCK 0x00020 324 #define CHANNEL_OFDM 0x00040 325 #define CHANNEL_2GHZ 0x00080 326 #define CHANNEL_5GHZ 0x00100 327 #define CHANNEL_PASSIVE 0x00200 328 #define CHANNEL_DYN 0x00400 329 #define CHANNEL_HALF 0x04000 330 #define CHANNEL_QUARTER 0x08000 331 #define CHANNEL_HT20 0x10000 332 #define CHANNEL_HT40PLUS 0x20000 333 #define CHANNEL_HT40MINUS 0x40000 334 335 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 336 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 337 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 338 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) 339 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) 340 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) 341 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) 342 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) 343 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) 344 #define CHANNEL_ALL \ 345 (CHANNEL_OFDM| \ 346 CHANNEL_CCK| \ 347 CHANNEL_2GHZ | \ 348 CHANNEL_5GHZ | \ 349 CHANNEL_HT20 | \ 350 CHANNEL_HT40PLUS | \ 351 CHANNEL_HT40MINUS) 352 353 struct ath9k_channel { 354 struct ieee80211_channel *chan; 355 u16 channel; 356 u32 channelFlags; 357 u32 chanmode; 358 int32_t CalValid; 359 bool oneTimeCalsDone; 360 int8_t iCoff; 361 int8_t qCoff; 362 int16_t rawNoiseFloor; 363 }; 364 365 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ 366 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ 367 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ 368 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) 369 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 370 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 371 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 372 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 373 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 374 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ 375 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 376 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) 377 378 /* These macros check chanmode and not channelFlags */ 379 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) 380 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ 381 ((_c)->chanmode == CHANNEL_G_HT20)) 382 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ 383 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ 384 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ 385 ((_c)->chanmode == CHANNEL_G_HT40MINUS)) 386 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) 387 388 enum ath9k_power_mode { 389 ATH9K_PM_AWAKE = 0, 390 ATH9K_PM_FULL_SLEEP, 391 ATH9K_PM_NETWORK_SLEEP, 392 ATH9K_PM_UNDEFINED 393 }; 394 395 enum ath9k_tp_scale { 396 ATH9K_TP_SCALE_MAX = 0, 397 ATH9K_TP_SCALE_50, 398 ATH9K_TP_SCALE_25, 399 ATH9K_TP_SCALE_12, 400 ATH9K_TP_SCALE_MIN 401 }; 402 403 enum ser_reg_mode { 404 SER_REG_MODE_OFF = 0, 405 SER_REG_MODE_ON = 1, 406 SER_REG_MODE_AUTO = 2, 407 }; 408 409 enum ath9k_rx_qtype { 410 ATH9K_RX_QUEUE_HP, 411 ATH9K_RX_QUEUE_LP, 412 ATH9K_RX_QUEUE_MAX, 413 }; 414 415 struct ath9k_beacon_state { 416 u32 bs_nexttbtt; 417 u32 bs_nextdtim; 418 u32 bs_intval; 419 #define ATH9K_BEACON_PERIOD 0x0000ffff 420 #define ATH9K_BEACON_ENA 0x00800000 421 #define ATH9K_BEACON_RESET_TSF 0x01000000 422 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 423 u32 bs_dtimperiod; 424 u16 bs_cfpperiod; 425 u16 bs_cfpmaxduration; 426 u32 bs_cfpnext; 427 u16 bs_timoffset; 428 u16 bs_bmissthreshold; 429 u32 bs_sleepduration; 430 u32 bs_tsfoor_threshold; 431 }; 432 433 struct chan_centers { 434 u16 synth_center; 435 u16 ctl_center; 436 u16 ext_center; 437 }; 438 439 enum { 440 ATH9K_RESET_POWER_ON, 441 ATH9K_RESET_WARM, 442 ATH9K_RESET_COLD, 443 }; 444 445 struct ath9k_hw_version { 446 u32 magic; 447 u16 devid; 448 u16 subvendorid; 449 u32 macVersion; 450 u16 macRev; 451 u16 phyRev; 452 u16 analog5GhzRev; 453 u16 analog2GhzRev; 454 u16 subsysid; 455 }; 456 457 /* Generic TSF timer definitions */ 458 459 #define ATH_MAX_GEN_TIMER 16 460 461 #define AR_GENTMR_BIT(_index) (1 << (_index)) 462 463 /* 464 * Using de Bruijin sequence to look up 1's index in a 32 bit number 465 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 466 */ 467 #define debruijn32 0x077CB531U 468 469 struct ath_gen_timer_configuration { 470 u32 next_addr; 471 u32 period_addr; 472 u32 mode_addr; 473 u32 mode_mask; 474 }; 475 476 struct ath_gen_timer { 477 void (*trigger)(void *arg); 478 void (*overflow)(void *arg); 479 void *arg; 480 u8 index; 481 }; 482 483 struct ath_gen_timer_table { 484 u32 gen_timer_index[32]; 485 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; 486 union { 487 unsigned long timer_bits; 488 u16 val; 489 } timer_mask; 490 }; 491 492 /** 493 * struct ath_hw_private_ops - callbacks used internally by hardware code 494 * 495 * This structure contains private callbacks designed to only be used internally 496 * by the hardware core. 497 * 498 * @init_cal_settings: setup types of calibrations supported 499 * @init_cal: starts actual calibration 500 * 501 * @init_mode_regs: Initializes mode registers 502 * @init_mode_gain_regs: Initialize TX/RX gain registers 503 * @macversion_supported: If this specific mac revision is supported 504 * 505 * @rf_set_freq: change frequency 506 * @spur_mitigate_freq: spur mitigation 507 * @rf_alloc_ext_banks: 508 * @rf_free_ext_banks: 509 * @set_rf_regs: 510 * @compute_pll_control: compute the PLL control value to use for 511 * AR_RTC_PLL_CONTROL for a given channel 512 * @setup_calibration: set up calibration 513 * @iscal_supported: used to query if a type of calibration is supported 514 * @loadnf: load noise floor read from each chain on the CCA registers 515 * 516 * @ani_reset: reset ANI parameters to default values 517 * @ani_lower_immunity: lower the noise immunity level. The level controls 518 * the power-based packet detection on hardware. If a power jump is 519 * detected the adapter takes it as an indication that a packet has 520 * arrived. The level ranges from 0-5. Each level corresponds to a 521 * few dB more of noise immunity. If you have a strong time-varying 522 * interference that is causing false detections (OFDM timing errors or 523 * CCK timing errors) the level can be increased. 524 * @ani_cache_ini_regs: cache the values for ANI from the initial 525 * register settings through the register initialization. 526 */ 527 struct ath_hw_private_ops { 528 /* Calibration ops */ 529 void (*init_cal_settings)(struct ath_hw *ah); 530 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); 531 532 void (*init_mode_regs)(struct ath_hw *ah); 533 void (*init_mode_gain_regs)(struct ath_hw *ah); 534 bool (*macversion_supported)(u32 macversion); 535 void (*setup_calibration)(struct ath_hw *ah, 536 struct ath9k_cal_list *currCal); 537 bool (*iscal_supported)(struct ath_hw *ah, 538 enum ath9k_cal_types calType); 539 540 /* PHY ops */ 541 int (*rf_set_freq)(struct ath_hw *ah, 542 struct ath9k_channel *chan); 543 void (*spur_mitigate_freq)(struct ath_hw *ah, 544 struct ath9k_channel *chan); 545 int (*rf_alloc_ext_banks)(struct ath_hw *ah); 546 void (*rf_free_ext_banks)(struct ath_hw *ah); 547 bool (*set_rf_regs)(struct ath_hw *ah, 548 struct ath9k_channel *chan, 549 u16 modesIndex); 550 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); 551 void (*init_bb)(struct ath_hw *ah, 552 struct ath9k_channel *chan); 553 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); 554 void (*olc_init)(struct ath_hw *ah); 555 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); 556 void (*mark_phy_inactive)(struct ath_hw *ah); 557 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); 558 bool (*rfbus_req)(struct ath_hw *ah); 559 void (*rfbus_done)(struct ath_hw *ah); 560 void (*enable_rfkill)(struct ath_hw *ah); 561 void (*restore_chainmask)(struct ath_hw *ah); 562 void (*set_diversity)(struct ath_hw *ah, bool value); 563 u32 (*compute_pll_control)(struct ath_hw *ah, 564 struct ath9k_channel *chan); 565 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, 566 int param); 567 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); 568 void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan); 569 570 /* ANI */ 571 void (*ani_reset)(struct ath_hw *ah, bool is_scanning); 572 void (*ani_lower_immunity)(struct ath_hw *ah); 573 void (*ani_cache_ini_regs)(struct ath_hw *ah); 574 }; 575 576 /** 577 * struct ath_hw_ops - callbacks used by hardware code and driver code 578 * 579 * This structure contains callbacks designed to to be used internally by 580 * hardware code and also by the lower level driver. 581 * 582 * @config_pci_powersave: 583 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC 584 * 585 * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI 586 * thresholds being reached or having overflowed. 587 * @ani_monitor: called periodically by the core driver to collect 588 * MIB stats and adjust ANI if specific thresholds have been reached. 589 */ 590 struct ath_hw_ops { 591 void (*config_pci_powersave)(struct ath_hw *ah, 592 int restore, 593 int power_off); 594 void (*rx_enable)(struct ath_hw *ah); 595 void (*set_desc_link)(void *ds, u32 link); 596 void (*get_desc_link)(void *ds, u32 **link); 597 bool (*calibrate)(struct ath_hw *ah, 598 struct ath9k_channel *chan, 599 u8 rxchainmask, 600 bool longcal); 601 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); 602 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen, 603 bool is_firstseg, bool is_is_lastseg, 604 const void *ds0, dma_addr_t buf_addr, 605 unsigned int qcu); 606 int (*proc_txdesc)(struct ath_hw *ah, void *ds, 607 struct ath_tx_status *ts); 608 void (*set11n_txdesc)(struct ath_hw *ah, void *ds, 609 u32 pktLen, enum ath9k_pkt_type type, 610 u32 txPower, u32 keyIx, 611 enum ath9k_key_type keyType, 612 u32 flags); 613 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds, 614 void *lastds, 615 u32 durUpdateEn, u32 rtsctsRate, 616 u32 rtsctsDuration, 617 struct ath9k_11n_rate_series series[], 618 u32 nseries, u32 flags); 619 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds, 620 u32 aggrLen); 621 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds, 622 u32 numDelims); 623 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds); 624 void (*clr11n_aggr)(struct ath_hw *ah, void *ds); 625 void (*set11n_burstduration)(struct ath_hw *ah, void *ds, 626 u32 burstDuration); 627 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds, 628 u32 vmf); 629 630 void (*ani_proc_mib_event)(struct ath_hw *ah); 631 void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan); 632 }; 633 634 struct ath_hw { 635 struct ieee80211_hw *hw; 636 struct ath_common common; 637 struct ath9k_hw_version hw_version; 638 struct ath9k_ops_config config; 639 struct ath9k_hw_capabilities caps; 640 struct ath9k_channel channels[38]; 641 struct ath9k_channel *curchan; 642 643 union { 644 struct ar5416_eeprom_def def; 645 struct ar5416_eeprom_4k map4k; 646 struct ar9287_eeprom map9287; 647 struct ar9300_eeprom ar9300_eep; 648 } eeprom; 649 const struct eeprom_ops *eep_ops; 650 651 bool sw_mgmt_crypto; 652 bool is_pciexpress; 653 bool need_an_top2_fixup; 654 u16 tx_trig_level; 655 s16 nf_2g_max; 656 s16 nf_2g_min; 657 s16 nf_5g_max; 658 s16 nf_5g_min; 659 u16 rfsilent; 660 u32 rfkill_gpio; 661 u32 rfkill_polarity; 662 u32 ah_flags; 663 664 bool htc_reset_init; 665 666 enum nl80211_iftype opmode; 667 enum ath9k_power_mode power_mode; 668 669 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 670 struct ath9k_pacal_info pacal_info; 671 struct ar5416Stats stats; 672 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; 673 674 int16_t curchan_rad_index; 675 enum ath9k_int imask; 676 u32 imrs2_reg; 677 u32 txok_interrupt_mask; 678 u32 txerr_interrupt_mask; 679 u32 txdesc_interrupt_mask; 680 u32 txeol_interrupt_mask; 681 u32 txurn_interrupt_mask; 682 bool chip_fullsleep; 683 u32 atim_window; 684 685 /* Calibration */ 686 enum ath9k_cal_types supp_cals; 687 struct ath9k_cal_list iq_caldata; 688 struct ath9k_cal_list adcgain_caldata; 689 struct ath9k_cal_list adcdc_calinitdata; 690 struct ath9k_cal_list adcdc_caldata; 691 struct ath9k_cal_list tempCompCalData; 692 struct ath9k_cal_list *cal_list; 693 struct ath9k_cal_list *cal_list_last; 694 struct ath9k_cal_list *cal_list_curr; 695 #define totalPowerMeasI meas0.unsign 696 #define totalPowerMeasQ meas1.unsign 697 #define totalIqCorrMeas meas2.sign 698 #define totalAdcIOddPhase meas0.unsign 699 #define totalAdcIEvenPhase meas1.unsign 700 #define totalAdcQOddPhase meas2.unsign 701 #define totalAdcQEvenPhase meas3.unsign 702 #define totalAdcDcOffsetIOddPhase meas0.sign 703 #define totalAdcDcOffsetIEvenPhase meas1.sign 704 #define totalAdcDcOffsetQOddPhase meas2.sign 705 #define totalAdcDcOffsetQEvenPhase meas3.sign 706 union { 707 u32 unsign[AR5416_MAX_CHAINS]; 708 int32_t sign[AR5416_MAX_CHAINS]; 709 } meas0; 710 union { 711 u32 unsign[AR5416_MAX_CHAINS]; 712 int32_t sign[AR5416_MAX_CHAINS]; 713 } meas1; 714 union { 715 u32 unsign[AR5416_MAX_CHAINS]; 716 int32_t sign[AR5416_MAX_CHAINS]; 717 } meas2; 718 union { 719 u32 unsign[AR5416_MAX_CHAINS]; 720 int32_t sign[AR5416_MAX_CHAINS]; 721 } meas3; 722 u16 cal_samples; 723 724 u32 sta_id1_defaults; 725 u32 misc_mode; 726 enum { 727 AUTO_32KHZ, 728 USE_32KHZ, 729 DONT_USE_32KHZ, 730 } enable_32kHz_clock; 731 732 /* Private to hardware code */ 733 struct ath_hw_private_ops private_ops; 734 /* Accessed by the lower level driver */ 735 struct ath_hw_ops ops; 736 737 /* Used to program the radio on non single-chip devices */ 738 u32 *analogBank0Data; 739 u32 *analogBank1Data; 740 u32 *analogBank2Data; 741 u32 *analogBank3Data; 742 u32 *analogBank6Data; 743 u32 *analogBank6TPCData; 744 u32 *analogBank7Data; 745 u32 *addac5416_21; 746 u32 *bank6Temp; 747 748 u8 txpower_limit; 749 int16_t txpower_indexoffset; 750 int coverage_class; 751 u32 beacon_interval; 752 u32 slottime; 753 u32 globaltxtimeout; 754 755 /* ANI */ 756 u32 proc_phyerr; 757 u32 aniperiod; 758 struct ar5416AniState *curani; 759 struct ar5416AniState ani[255]; 760 int totalSizeDesired[5]; 761 int coarse_high[5]; 762 int coarse_low[5]; 763 int firpwr[5]; 764 enum ath9k_ani_cmd ani_function; 765 766 /* Bluetooth coexistance */ 767 struct ath_btcoex_hw btcoex_hw; 768 769 u32 intr_txqs; 770 u8 txchainmask; 771 u8 rxchainmask; 772 773 u32 originalGain[22]; 774 int initPDADC; 775 int PDADCdelta; 776 u8 led_pin; 777 778 struct ar5416IniArray iniModes; 779 struct ar5416IniArray iniCommon; 780 struct ar5416IniArray iniBank0; 781 struct ar5416IniArray iniBB_RfGain; 782 struct ar5416IniArray iniBank1; 783 struct ar5416IniArray iniBank2; 784 struct ar5416IniArray iniBank3; 785 struct ar5416IniArray iniBank6; 786 struct ar5416IniArray iniBank6TPC; 787 struct ar5416IniArray iniBank7; 788 struct ar5416IniArray iniAddac; 789 struct ar5416IniArray iniPcieSerdes; 790 struct ar5416IniArray iniPcieSerdesLowPower; 791 struct ar5416IniArray iniModesAdditional; 792 struct ar5416IniArray iniModesRxGain; 793 struct ar5416IniArray iniModesTxGain; 794 struct ar5416IniArray iniModes_9271_1_0_only; 795 struct ar5416IniArray iniCckfirNormal; 796 struct ar5416IniArray iniCckfirJapan2484; 797 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; 798 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; 799 struct ar5416IniArray iniModes_9271_ANI_reg; 800 struct ar5416IniArray iniModes_high_power_tx_gain_9271; 801 struct ar5416IniArray iniModes_normal_power_tx_gain_9271; 802 803 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; 804 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; 805 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; 806 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; 807 808 u32 intr_gen_timer_trigger; 809 u32 intr_gen_timer_thresh; 810 struct ath_gen_timer_table hw_gen_timers; 811 812 struct ar9003_txs *ts_ring; 813 void *ts_start; 814 u32 ts_paddr_start; 815 u32 ts_paddr_end; 816 u16 ts_tail; 817 u8 ts_size; 818 819 u32 bb_watchdog_last_status; 820 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ 821 }; 822 823 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) 824 { 825 return &ah->common; 826 } 827 828 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) 829 { 830 return &(ath9k_hw_common(ah)->regulatory); 831 } 832 833 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) 834 { 835 return &ah->private_ops; 836 } 837 838 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) 839 { 840 return &ah->ops; 841 } 842 843 /* Initialization, Detach, Reset */ 844 const char *ath9k_hw_probe(u16 vendorid, u16 devid); 845 void ath9k_hw_deinit(struct ath_hw *ah); 846 int ath9k_hw_init(struct ath_hw *ah); 847 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 848 bool bChannelChange); 849 int ath9k_hw_fill_cap_info(struct ath_hw *ah); 850 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, 851 u32 capability, u32 *result); 852 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 853 u32 capability, u32 setting, int *status); 854 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); 855 856 /* Key Cache Management */ 857 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); 858 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac); 859 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, 860 const struct ath9k_keyval *k, 861 const u8 *mac); 862 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry); 863 864 /* GPIO / RFKILL / Antennae */ 865 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); 866 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); 867 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 868 u32 ah_signal_type); 869 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); 870 u32 ath9k_hw_getdefantenna(struct ath_hw *ah); 871 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); 872 873 /* General Operation */ 874 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); 875 u32 ath9k_hw_reverse_bits(u32 val, u32 n); 876 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); 877 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 878 u8 phy, int kbps, 879 u32 frameLen, u16 rateix, bool shortPreamble); 880 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 881 struct ath9k_channel *chan, 882 struct chan_centers *centers); 883 u32 ath9k_hw_getrxfilter(struct ath_hw *ah); 884 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); 885 bool ath9k_hw_phy_disable(struct ath_hw *ah); 886 bool ath9k_hw_disable(struct ath_hw *ah); 887 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); 888 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); 889 void ath9k_hw_setopmode(struct ath_hw *ah); 890 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); 891 void ath9k_hw_setbssidmask(struct ath_hw *ah); 892 void ath9k_hw_write_associd(struct ath_hw *ah); 893 u64 ath9k_hw_gettsf64(struct ath_hw *ah); 894 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); 895 void ath9k_hw_reset_tsf(struct ath_hw *ah); 896 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); 897 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp); 898 void ath9k_hw_init_global_settings(struct ath_hw *ah); 899 void ath9k_hw_set11nmac2040(struct ath_hw *ah); 900 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); 901 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 902 const struct ath9k_beacon_state *bs); 903 bool ath9k_hw_check_alive(struct ath_hw *ah); 904 905 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); 906 907 /* Generic hw timer primitives */ 908 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 909 void (*trigger)(void *), 910 void (*overflow)(void *), 911 void *arg, 912 u8 timer_index); 913 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 914 struct ath_gen_timer *timer, 915 u32 timer_next, 916 u32 timer_period); 917 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); 918 919 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); 920 void ath_gen_timer_isr(struct ath_hw *hw); 921 u32 ath9k_hw_gettsf32(struct ath_hw *ah); 922 923 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); 924 925 /* HTC */ 926 void ath9k_hw_htc_resetinit(struct ath_hw *ah); 927 928 /* PHY */ 929 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 930 u32 *coef_mantissa, u32 *coef_exponent); 931 932 /* 933 * Code Specific to AR5008, AR9001 or AR9002, 934 * we stuff these here to avoid callbacks for AR9003. 935 */ 936 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); 937 int ar9002_hw_rf_claim(struct ath_hw *ah); 938 void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 939 void ar9002_hw_update_async_fifo(struct ath_hw *ah); 940 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah); 941 942 /* 943 * Code specific to AR9003, we stuff these here to avoid callbacks 944 * for older families 945 */ 946 void ar9003_hw_set_nf_limits(struct ath_hw *ah); 947 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); 948 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); 949 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); 950 951 /* Hardware family op attach helpers */ 952 void ar5008_hw_attach_phy_ops(struct ath_hw *ah); 953 void ar9002_hw_attach_phy_ops(struct ath_hw *ah); 954 void ar9003_hw_attach_phy_ops(struct ath_hw *ah); 955 956 void ar9002_hw_attach_calib_ops(struct ath_hw *ah); 957 void ar9003_hw_attach_calib_ops(struct ath_hw *ah); 958 959 void ar9002_hw_attach_ops(struct ath_hw *ah); 960 void ar9003_hw_attach_ops(struct ath_hw *ah); 961 962 /* 963 * ANI work can be shared between all families but a next 964 * generation implementation of ANI will be used only for AR9003 only 965 * for now as the other families still need to be tested with the same 966 * next generation ANI. Feel free to start testing it though for the 967 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. 968 */ 969 extern int modparam_force_new_ani; 970 void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah); 971 void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah); 972 973 #define ATH_PCIE_CAP_LINK_CTRL 0x70 974 #define ATH_PCIE_CAP_LINK_L0S 1 975 #define ATH_PCIE_CAP_LINK_L1 2 976 977 #define ATH9K_CLOCK_RATE_CCK 22 978 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 979 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 980 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 981 982 #endif 983