xref: /openbmc/linux/drivers/net/wireless/ath/ath9k/hw.h (revision fe12946e66575677879941a14f75b70ca2d2962a)
1203c4805SLuis R. Rodriguez /*
2203c4805SLuis R. Rodriguez  * Copyright (c) 2008-2009 Atheros Communications Inc.
3203c4805SLuis R. Rodriguez  *
4203c4805SLuis R. Rodriguez  * Permission to use, copy, modify, and/or distribute this software for any
5203c4805SLuis R. Rodriguez  * purpose with or without fee is hereby granted, provided that the above
6203c4805SLuis R. Rodriguez  * copyright notice and this permission notice appear in all copies.
7203c4805SLuis R. Rodriguez  *
8203c4805SLuis R. Rodriguez  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9203c4805SLuis R. Rodriguez  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10203c4805SLuis R. Rodriguez  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11203c4805SLuis R. Rodriguez  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12203c4805SLuis R. Rodriguez  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13203c4805SLuis R. Rodriguez  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14203c4805SLuis R. Rodriguez  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15203c4805SLuis R. Rodriguez  */
16203c4805SLuis R. Rodriguez 
17203c4805SLuis R. Rodriguez #ifndef HW_H
18203c4805SLuis R. Rodriguez #define HW_H
19203c4805SLuis R. Rodriguez 
20203c4805SLuis R. Rodriguez #include <linux/if_ether.h>
21203c4805SLuis R. Rodriguez #include <linux/delay.h>
22203c4805SLuis R. Rodriguez #include <linux/io.h>
23203c4805SLuis R. Rodriguez 
24203c4805SLuis R. Rodriguez #include "mac.h"
25203c4805SLuis R. Rodriguez #include "ani.h"
26203c4805SLuis R. Rodriguez #include "eeprom.h"
27203c4805SLuis R. Rodriguez #include "calib.h"
28203c4805SLuis R. Rodriguez #include "reg.h"
29203c4805SLuis R. Rodriguez #include "phy.h"
30203c4805SLuis R. Rodriguez 
31203c4805SLuis R. Rodriguez #include "../regd.h"
32203c4805SLuis R. Rodriguez 
33203c4805SLuis R. Rodriguez #define ATHEROS_VENDOR_ID	0x168c
34203c4805SLuis R. Rodriguez #define AR5416_DEVID_PCI	0x0023
35203c4805SLuis R. Rodriguez #define AR5416_DEVID_PCIE	0x0024
36203c4805SLuis R. Rodriguez #define AR9160_DEVID_PCI	0x0027
37203c4805SLuis R. Rodriguez #define AR9280_DEVID_PCI	0x0029
38203c4805SLuis R. Rodriguez #define AR9280_DEVID_PCIE	0x002a
39203c4805SLuis R. Rodriguez #define AR9285_DEVID_PCIE	0x002b
40203c4805SLuis R. Rodriguez #define AR5416_AR9100_DEVID	0x000b
41203c4805SLuis R. Rodriguez #define	AR_SUBVENDOR_ID_NOG	0x0e11
42203c4805SLuis R. Rodriguez #define AR_SUBVENDOR_ID_NEW_A	0x7065
43203c4805SLuis R. Rodriguez #define AR5416_MAGIC		0x19641014
44203c4805SLuis R. Rodriguez 
45ac88b6ecSVivek Natarajan #define AR5416_DEVID_AR9287_PCI  0x002D
46ac88b6ecSVivek Natarajan #define AR5416_DEVID_AR9287_PCIE 0x002E
47ac88b6ecSVivek Natarajan 
48*fe12946eSVasanthakumar Thiagarajan #define AR9280_COEX2WIRE_SUBSYSID	0x309b
49*fe12946eSVasanthakumar Thiagarajan #define AT9285_COEX3WIRE_SA_SUBSYSID	0x30aa
50*fe12946eSVasanthakumar Thiagarajan #define AT9285_COEX3WIRE_DA_SUBSYSID	0x30ab
51*fe12946eSVasanthakumar Thiagarajan 
52203c4805SLuis R. Rodriguez /* Register read/write primitives */
53203c4805SLuis R. Rodriguez #define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
54203c4805SLuis R. Rodriguez #define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
55203c4805SLuis R. Rodriguez 
56203c4805SLuis R. Rodriguez #define SM(_v, _f)  (((_v) << _f##_S) & _f)
57203c4805SLuis R. Rodriguez #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
58203c4805SLuis R. Rodriguez #define REG_RMW(_a, _r, _set, _clr)    \
59203c4805SLuis R. Rodriguez 	REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
60203c4805SLuis R. Rodriguez #define REG_RMW_FIELD(_a, _r, _f, _v) \
61203c4805SLuis R. Rodriguez 	REG_WRITE(_a, _r, \
62203c4805SLuis R. Rodriguez 	(REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
63203c4805SLuis R. Rodriguez #define REG_SET_BIT(_a, _r, _f) \
64203c4805SLuis R. Rodriguez 	REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
65203c4805SLuis R. Rodriguez #define REG_CLR_BIT(_a, _r, _f) \
66203c4805SLuis R. Rodriguez 	REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
67203c4805SLuis R. Rodriguez 
68203c4805SLuis R. Rodriguez #define DO_DELAY(x) do {			\
69203c4805SLuis R. Rodriguez 		if ((++(x) % 64) == 0)          \
70203c4805SLuis R. Rodriguez 			udelay(1);		\
71203c4805SLuis R. Rodriguez 	} while (0)
72203c4805SLuis R. Rodriguez 
73203c4805SLuis R. Rodriguez #define REG_WRITE_ARRAY(iniarray, column, regWr) do {                   \
74203c4805SLuis R. Rodriguez 		int r;							\
75203c4805SLuis R. Rodriguez 		for (r = 0; r < ((iniarray)->ia_rows); r++) {		\
76203c4805SLuis R. Rodriguez 			REG_WRITE(ah, INI_RA((iniarray), (r), 0),	\
77203c4805SLuis R. Rodriguez 				  INI_RA((iniarray), r, (column)));	\
78203c4805SLuis R. Rodriguez 			DO_DELAY(regWr);				\
79203c4805SLuis R. Rodriguez 		}							\
80203c4805SLuis R. Rodriguez 	} while (0)
81203c4805SLuis R. Rodriguez 
82203c4805SLuis R. Rodriguez #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT             0
83203c4805SLuis R. Rodriguez #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
84203c4805SLuis R. Rodriguez #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED     2
85203c4805SLuis R. Rodriguez #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME           3
861773912bSVasanthakumar Thiagarajan #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL  4
87203c4805SLuis R. Rodriguez #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED    5
88203c4805SLuis R. Rodriguez #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED      6
89203c4805SLuis R. Rodriguez 
90203c4805SLuis R. Rodriguez #define AR_GPIOD_MASK               0x00001FFF
91203c4805SLuis R. Rodriguez #define AR_GPIO_BIT(_gpio)          (1 << (_gpio))
92203c4805SLuis R. Rodriguez 
93203c4805SLuis R. Rodriguez #define BASE_ACTIVATE_DELAY         100
94203c4805SLuis R. Rodriguez #define RTC_PLL_SETTLE_DELAY        1000
95203c4805SLuis R. Rodriguez #define COEF_SCALE_S                24
96203c4805SLuis R. Rodriguez #define HT40_CHANNEL_CENTER_SHIFT   10
97203c4805SLuis R. Rodriguez 
98203c4805SLuis R. Rodriguez #define ATH9K_ANTENNA0_CHAINMASK    0x1
99203c4805SLuis R. Rodriguez #define ATH9K_ANTENNA1_CHAINMASK    0x2
100203c4805SLuis R. Rodriguez 
101203c4805SLuis R. Rodriguez #define ATH9K_NUM_DMA_DEBUG_REGS    8
102203c4805SLuis R. Rodriguez #define ATH9K_NUM_QUEUES            10
103203c4805SLuis R. Rodriguez 
104203c4805SLuis R. Rodriguez #define MAX_RATE_POWER              63
105203c4805SLuis R. Rodriguez #define AH_WAIT_TIMEOUT             100000 /* (us) */
106f9b604f6SGabor Juhos #define AH_TSF_WRITE_TIMEOUT        100    /* (us) */
107203c4805SLuis R. Rodriguez #define AH_TIME_QUANTUM             10
108203c4805SLuis R. Rodriguez #define AR_KEYTABLE_SIZE            128
109203c4805SLuis R. Rodriguez #define POWER_UP_TIME               200000
110203c4805SLuis R. Rodriguez #define SPUR_RSSI_THRESH            40
111203c4805SLuis R. Rodriguez 
112203c4805SLuis R. Rodriguez #define CAB_TIMEOUT_VAL             10
113203c4805SLuis R. Rodriguez #define BEACON_TIMEOUT_VAL          10
114203c4805SLuis R. Rodriguez #define MIN_BEACON_TIMEOUT_VAL      1
115203c4805SLuis R. Rodriguez #define SLEEP_SLOP                  3
116203c4805SLuis R. Rodriguez 
117203c4805SLuis R. Rodriguez #define INIT_CONFIG_STATUS          0x00000000
118203c4805SLuis R. Rodriguez #define INIT_RSSI_THR               0x00000700
119203c4805SLuis R. Rodriguez #define INIT_BCON_CNTRL_REG         0x00000000
120203c4805SLuis R. Rodriguez 
121203c4805SLuis R. Rodriguez #define TU_TO_USEC(_tu)             ((_tu) << 10)
122203c4805SLuis R. Rodriguez 
123203c4805SLuis R. Rodriguez enum wireless_mode {
124203c4805SLuis R. Rodriguez 	ATH9K_MODE_11A = 0,
125b9b6e15aSLuis R. Rodriguez 	ATH9K_MODE_11G,
126b9b6e15aSLuis R. Rodriguez 	ATH9K_MODE_11NA_HT20,
127b9b6e15aSLuis R. Rodriguez 	ATH9K_MODE_11NG_HT20,
128b9b6e15aSLuis R. Rodriguez 	ATH9K_MODE_11NA_HT40PLUS,
129b9b6e15aSLuis R. Rodriguez 	ATH9K_MODE_11NA_HT40MINUS,
130b9b6e15aSLuis R. Rodriguez 	ATH9K_MODE_11NG_HT40PLUS,
131b9b6e15aSLuis R. Rodriguez 	ATH9K_MODE_11NG_HT40MINUS,
132b9b6e15aSLuis R. Rodriguez 	ATH9K_MODE_MAX,
133203c4805SLuis R. Rodriguez };
134203c4805SLuis R. Rodriguez 
1351cf6873aSSujith enum ath9k_ant_setting {
1361cf6873aSSujith 	ATH9K_ANT_VARIABLE = 0,
1371cf6873aSSujith 	ATH9K_ANT_FIXED_A,
1381cf6873aSSujith 	ATH9K_ANT_FIXED_B
1391cf6873aSSujith };
1401cf6873aSSujith 
141203c4805SLuis R. Rodriguez enum ath9k_hw_caps {
142203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_MIC_AESCCM                 = BIT(0),
143203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_MIC_CKIP                   = BIT(1),
144203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_MIC_TKIP                   = BIT(2),
145203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(3),
146203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_CIPHER_CKIP                = BIT(4),
147203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_CIPHER_TKIP                = BIT(5),
148203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_VEOL                       = BIT(6),
149203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_BSSIDMASK                  = BIT(7),
150203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(8),
151203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_HT                         = BIT(9),
152203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_GTT                        = BIT(10),
153203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_FASTCC                     = BIT(11),
154203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_RFSILENT                   = BIT(12),
155203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_CST                        = BIT(13),
156203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_ENHANCEDPM                 = BIT(14),
157203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_AUTOSLEEP                  = BIT(15),
158203c4805SLuis R. Rodriguez 	ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(16),
159203c4805SLuis R. Rodriguez };
160203c4805SLuis R. Rodriguez 
161203c4805SLuis R. Rodriguez enum ath9k_capability_type {
162203c4805SLuis R. Rodriguez 	ATH9K_CAP_CIPHER = 0,
163203c4805SLuis R. Rodriguez 	ATH9K_CAP_TKIP_MIC,
164203c4805SLuis R. Rodriguez 	ATH9K_CAP_TKIP_SPLIT,
165203c4805SLuis R. Rodriguez 	ATH9K_CAP_DIVERSITY,
166203c4805SLuis R. Rodriguez 	ATH9K_CAP_TXPOW,
167203c4805SLuis R. Rodriguez 	ATH9K_CAP_MCAST_KEYSRCH,
168203c4805SLuis R. Rodriguez 	ATH9K_CAP_DS
169203c4805SLuis R. Rodriguez };
170203c4805SLuis R. Rodriguez 
171203c4805SLuis R. Rodriguez struct ath9k_hw_capabilities {
172203c4805SLuis R. Rodriguez 	u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
173203c4805SLuis R. Rodriguez 	DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
174203c4805SLuis R. Rodriguez 	u16 total_queues;
175203c4805SLuis R. Rodriguez 	u16 keycache_size;
176203c4805SLuis R. Rodriguez 	u16 low_5ghz_chan, high_5ghz_chan;
177203c4805SLuis R. Rodriguez 	u16 low_2ghz_chan, high_2ghz_chan;
178203c4805SLuis R. Rodriguez 	u16 rts_aggr_limit;
179203c4805SLuis R. Rodriguez 	u8 tx_chainmask;
180203c4805SLuis R. Rodriguez 	u8 rx_chainmask;
181203c4805SLuis R. Rodriguez 	u16 tx_triglevel_max;
182203c4805SLuis R. Rodriguez 	u16 reg_cap;
183203c4805SLuis R. Rodriguez 	u8 num_gpio_pins;
184203c4805SLuis R. Rodriguez 	u8 num_antcfg_2ghz;
185203c4805SLuis R. Rodriguez 	u8 num_antcfg_5ghz;
186203c4805SLuis R. Rodriguez };
187203c4805SLuis R. Rodriguez 
188203c4805SLuis R. Rodriguez struct ath9k_ops_config {
189203c4805SLuis R. Rodriguez 	int dma_beacon_response_time;
190203c4805SLuis R. Rodriguez 	int sw_beacon_response_time;
191203c4805SLuis R. Rodriguez 	int additional_swba_backoff;
192203c4805SLuis R. Rodriguez 	int ack_6mb;
193203c4805SLuis R. Rodriguez 	int cwm_ignore_extcca;
194203c4805SLuis R. Rodriguez 	u8 pcie_powersave_enable;
195203c4805SLuis R. Rodriguez 	u8 pcie_clock_req;
196203c4805SLuis R. Rodriguez 	u32 pcie_waen;
197203c4805SLuis R. Rodriguez 	u8 analog_shiftreg;
198203c4805SLuis R. Rodriguez 	u8 ht_enable;
199203c4805SLuis R. Rodriguez 	u32 ofdm_trig_low;
200203c4805SLuis R. Rodriguez 	u32 ofdm_trig_high;
201203c4805SLuis R. Rodriguez 	u32 cck_trig_high;
202203c4805SLuis R. Rodriguez 	u32 cck_trig_low;
203203c4805SLuis R. Rodriguez 	u32 enable_ani;
2041cf6873aSSujith 	enum ath9k_ant_setting diversity_control;
205203c4805SLuis R. Rodriguez 	u16 antenna_switch_swap;
206203c4805SLuis R. Rodriguez 	int serialize_regmode;
207203c4805SLuis R. Rodriguez 	bool intr_mitigation;
208203c4805SLuis R. Rodriguez #define SPUR_DISABLE        	0
209203c4805SLuis R. Rodriguez #define SPUR_ENABLE_IOCTL   	1
210203c4805SLuis R. Rodriguez #define SPUR_ENABLE_EEPROM  	2
211203c4805SLuis R. Rodriguez #define AR_EEPROM_MODAL_SPURS   5
212203c4805SLuis R. Rodriguez #define AR_SPUR_5413_1      	1640
213203c4805SLuis R. Rodriguez #define AR_SPUR_5413_2      	1200
214203c4805SLuis R. Rodriguez #define AR_NO_SPUR      	0x8000
215203c4805SLuis R. Rodriguez #define AR_BASE_FREQ_2GHZ   	2300
216203c4805SLuis R. Rodriguez #define AR_BASE_FREQ_5GHZ   	4900
217203c4805SLuis R. Rodriguez #define AR_SPUR_FEEQ_BOUND_HT40 19
218203c4805SLuis R. Rodriguez #define AR_SPUR_FEEQ_BOUND_HT20 10
219203c4805SLuis R. Rodriguez 	int spurmode;
220203c4805SLuis R. Rodriguez 	u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
221203c4805SLuis R. Rodriguez };
222203c4805SLuis R. Rodriguez 
223203c4805SLuis R. Rodriguez enum ath9k_int {
224203c4805SLuis R. Rodriguez 	ATH9K_INT_RX = 0x00000001,
225203c4805SLuis R. Rodriguez 	ATH9K_INT_RXDESC = 0x00000002,
226203c4805SLuis R. Rodriguez 	ATH9K_INT_RXNOFRM = 0x00000008,
227203c4805SLuis R. Rodriguez 	ATH9K_INT_RXEOL = 0x00000010,
228203c4805SLuis R. Rodriguez 	ATH9K_INT_RXORN = 0x00000020,
229203c4805SLuis R. Rodriguez 	ATH9K_INT_TX = 0x00000040,
230203c4805SLuis R. Rodriguez 	ATH9K_INT_TXDESC = 0x00000080,
231203c4805SLuis R. Rodriguez 	ATH9K_INT_TIM_TIMER = 0x00000100,
232203c4805SLuis R. Rodriguez 	ATH9K_INT_TXURN = 0x00000800,
233203c4805SLuis R. Rodriguez 	ATH9K_INT_MIB = 0x00001000,
234203c4805SLuis R. Rodriguez 	ATH9K_INT_RXPHY = 0x00004000,
235203c4805SLuis R. Rodriguez 	ATH9K_INT_RXKCM = 0x00008000,
236203c4805SLuis R. Rodriguez 	ATH9K_INT_SWBA = 0x00010000,
237203c4805SLuis R. Rodriguez 	ATH9K_INT_BMISS = 0x00040000,
238203c4805SLuis R. Rodriguez 	ATH9K_INT_BNR = 0x00100000,
239203c4805SLuis R. Rodriguez 	ATH9K_INT_TIM = 0x00200000,
240203c4805SLuis R. Rodriguez 	ATH9K_INT_DTIM = 0x00400000,
241203c4805SLuis R. Rodriguez 	ATH9K_INT_DTIMSYNC = 0x00800000,
242203c4805SLuis R. Rodriguez 	ATH9K_INT_GPIO = 0x01000000,
243203c4805SLuis R. Rodriguez 	ATH9K_INT_CABEND = 0x02000000,
244203c4805SLuis R. Rodriguez 	ATH9K_INT_TSFOOR = 0x04000000,
245ff155a45SVasanthakumar Thiagarajan 	ATH9K_INT_GENTIMER = 0x08000000,
246203c4805SLuis R. Rodriguez 	ATH9K_INT_CST = 0x10000000,
247203c4805SLuis R. Rodriguez 	ATH9K_INT_GTT = 0x20000000,
248203c4805SLuis R. Rodriguez 	ATH9K_INT_FATAL = 0x40000000,
249203c4805SLuis R. Rodriguez 	ATH9K_INT_GLOBAL = 0x80000000,
250203c4805SLuis R. Rodriguez 	ATH9K_INT_BMISC = ATH9K_INT_TIM |
251203c4805SLuis R. Rodriguez 		ATH9K_INT_DTIM |
252203c4805SLuis R. Rodriguez 		ATH9K_INT_DTIMSYNC |
253203c4805SLuis R. Rodriguez 		ATH9K_INT_TSFOOR |
254203c4805SLuis R. Rodriguez 		ATH9K_INT_CABEND,
255203c4805SLuis R. Rodriguez 	ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
256203c4805SLuis R. Rodriguez 		ATH9K_INT_RXDESC |
257203c4805SLuis R. Rodriguez 		ATH9K_INT_RXEOL |
258203c4805SLuis R. Rodriguez 		ATH9K_INT_RXORN |
259203c4805SLuis R. Rodriguez 		ATH9K_INT_TXURN |
260203c4805SLuis R. Rodriguez 		ATH9K_INT_TXDESC |
261203c4805SLuis R. Rodriguez 		ATH9K_INT_MIB |
262203c4805SLuis R. Rodriguez 		ATH9K_INT_RXPHY |
263203c4805SLuis R. Rodriguez 		ATH9K_INT_RXKCM |
264203c4805SLuis R. Rodriguez 		ATH9K_INT_SWBA |
265203c4805SLuis R. Rodriguez 		ATH9K_INT_BMISS |
266203c4805SLuis R. Rodriguez 		ATH9K_INT_GPIO,
267203c4805SLuis R. Rodriguez 	ATH9K_INT_NOCARD = 0xffffffff
268203c4805SLuis R. Rodriguez };
269203c4805SLuis R. Rodriguez 
270203c4805SLuis R. Rodriguez #define CHANNEL_CW_INT    0x00002
271203c4805SLuis R. Rodriguez #define CHANNEL_CCK       0x00020
272203c4805SLuis R. Rodriguez #define CHANNEL_OFDM      0x00040
273203c4805SLuis R. Rodriguez #define CHANNEL_2GHZ      0x00080
274203c4805SLuis R. Rodriguez #define CHANNEL_5GHZ      0x00100
275203c4805SLuis R. Rodriguez #define CHANNEL_PASSIVE   0x00200
276203c4805SLuis R. Rodriguez #define CHANNEL_DYN       0x00400
277203c4805SLuis R. Rodriguez #define CHANNEL_HALF      0x04000
278203c4805SLuis R. Rodriguez #define CHANNEL_QUARTER   0x08000
279203c4805SLuis R. Rodriguez #define CHANNEL_HT20      0x10000
280203c4805SLuis R. Rodriguez #define CHANNEL_HT40PLUS  0x20000
281203c4805SLuis R. Rodriguez #define CHANNEL_HT40MINUS 0x40000
282203c4805SLuis R. Rodriguez 
283203c4805SLuis R. Rodriguez #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
284203c4805SLuis R. Rodriguez #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
285203c4805SLuis R. Rodriguez #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
286203c4805SLuis R. Rodriguez #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
287203c4805SLuis R. Rodriguez #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
288203c4805SLuis R. Rodriguez #define CHANNEL_G_HT40PLUS  (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
289203c4805SLuis R. Rodriguez #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
290203c4805SLuis R. Rodriguez #define CHANNEL_A_HT40PLUS  (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
291203c4805SLuis R. Rodriguez #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
292203c4805SLuis R. Rodriguez #define CHANNEL_ALL				\
293203c4805SLuis R. Rodriguez 	(CHANNEL_OFDM|				\
294203c4805SLuis R. Rodriguez 	 CHANNEL_CCK|				\
295203c4805SLuis R. Rodriguez 	 CHANNEL_2GHZ |				\
296203c4805SLuis R. Rodriguez 	 CHANNEL_5GHZ |				\
297203c4805SLuis R. Rodriguez 	 CHANNEL_HT20 |				\
298203c4805SLuis R. Rodriguez 	 CHANNEL_HT40PLUS |			\
299203c4805SLuis R. Rodriguez 	 CHANNEL_HT40MINUS)
300203c4805SLuis R. Rodriguez 
301203c4805SLuis R. Rodriguez struct ath9k_channel {
302203c4805SLuis R. Rodriguez 	struct ieee80211_channel *chan;
303203c4805SLuis R. Rodriguez 	u16 channel;
304203c4805SLuis R. Rodriguez 	u32 channelFlags;
305203c4805SLuis R. Rodriguez 	u32 chanmode;
306203c4805SLuis R. Rodriguez 	int32_t CalValid;
307203c4805SLuis R. Rodriguez 	bool oneTimeCalsDone;
308203c4805SLuis R. Rodriguez 	int8_t iCoff;
309203c4805SLuis R. Rodriguez 	int8_t qCoff;
310203c4805SLuis R. Rodriguez 	int16_t rawNoiseFloor;
311203c4805SLuis R. Rodriguez };
312203c4805SLuis R. Rodriguez 
313203c4805SLuis R. Rodriguez #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
314203c4805SLuis R. Rodriguez        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
315203c4805SLuis R. Rodriguez        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
316203c4805SLuis R. Rodriguez        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
317203c4805SLuis R. Rodriguez #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
318203c4805SLuis R. Rodriguez #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
319203c4805SLuis R. Rodriguez #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
320203c4805SLuis R. Rodriguez #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
321203c4805SLuis R. Rodriguez #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
322203c4805SLuis R. Rodriguez #define IS_CHAN_A_5MHZ_SPACED(_c)			\
323203c4805SLuis R. Rodriguez 	((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&	\
324203c4805SLuis R. Rodriguez 	 (((_c)->channel % 20) != 0) &&			\
325203c4805SLuis R. Rodriguez 	 (((_c)->channel % 10) != 0))
326203c4805SLuis R. Rodriguez 
327203c4805SLuis R. Rodriguez /* These macros check chanmode and not channelFlags */
328203c4805SLuis R. Rodriguez #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
329203c4805SLuis R. Rodriguez #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) ||	\
330203c4805SLuis R. Rodriguez 			  ((_c)->chanmode == CHANNEL_G_HT20))
331203c4805SLuis R. Rodriguez #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||	\
332203c4805SLuis R. Rodriguez 			  ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||	\
333203c4805SLuis R. Rodriguez 			  ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||	\
334203c4805SLuis R. Rodriguez 			  ((_c)->chanmode == CHANNEL_G_HT40MINUS))
335203c4805SLuis R. Rodriguez #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
336203c4805SLuis R. Rodriguez 
337203c4805SLuis R. Rodriguez enum ath9k_power_mode {
338203c4805SLuis R. Rodriguez 	ATH9K_PM_AWAKE = 0,
339203c4805SLuis R. Rodriguez 	ATH9K_PM_FULL_SLEEP,
340203c4805SLuis R. Rodriguez 	ATH9K_PM_NETWORK_SLEEP,
341203c4805SLuis R. Rodriguez 	ATH9K_PM_UNDEFINED
342203c4805SLuis R. Rodriguez };
343203c4805SLuis R. Rodriguez 
344203c4805SLuis R. Rodriguez enum ath9k_tp_scale {
345203c4805SLuis R. Rodriguez 	ATH9K_TP_SCALE_MAX = 0,
346203c4805SLuis R. Rodriguez 	ATH9K_TP_SCALE_50,
347203c4805SLuis R. Rodriguez 	ATH9K_TP_SCALE_25,
348203c4805SLuis R. Rodriguez 	ATH9K_TP_SCALE_12,
349203c4805SLuis R. Rodriguez 	ATH9K_TP_SCALE_MIN
350203c4805SLuis R. Rodriguez };
351203c4805SLuis R. Rodriguez 
352203c4805SLuis R. Rodriguez enum ser_reg_mode {
353203c4805SLuis R. Rodriguez 	SER_REG_MODE_OFF = 0,
354203c4805SLuis R. Rodriguez 	SER_REG_MODE_ON = 1,
355203c4805SLuis R. Rodriguez 	SER_REG_MODE_AUTO = 2,
356203c4805SLuis R. Rodriguez };
357203c4805SLuis R. Rodriguez 
358203c4805SLuis R. Rodriguez struct ath9k_beacon_state {
359203c4805SLuis R. Rodriguez 	u32 bs_nexttbtt;
360203c4805SLuis R. Rodriguez 	u32 bs_nextdtim;
361203c4805SLuis R. Rodriguez 	u32 bs_intval;
362203c4805SLuis R. Rodriguez #define ATH9K_BEACON_PERIOD       0x0000ffff
363203c4805SLuis R. Rodriguez #define ATH9K_BEACON_ENA          0x00800000
364203c4805SLuis R. Rodriguez #define ATH9K_BEACON_RESET_TSF    0x01000000
365203c4805SLuis R. Rodriguez #define ATH9K_TSFOOR_THRESHOLD    0x00004240 /* 16k us */
366203c4805SLuis R. Rodriguez 	u32 bs_dtimperiod;
367203c4805SLuis R. Rodriguez 	u16 bs_cfpperiod;
368203c4805SLuis R. Rodriguez 	u16 bs_cfpmaxduration;
369203c4805SLuis R. Rodriguez 	u32 bs_cfpnext;
370203c4805SLuis R. Rodriguez 	u16 bs_timoffset;
371203c4805SLuis R. Rodriguez 	u16 bs_bmissthreshold;
372203c4805SLuis R. Rodriguez 	u32 bs_sleepduration;
373203c4805SLuis R. Rodriguez 	u32 bs_tsfoor_threshold;
374203c4805SLuis R. Rodriguez };
375203c4805SLuis R. Rodriguez 
376203c4805SLuis R. Rodriguez struct chan_centers {
377203c4805SLuis R. Rodriguez 	u16 synth_center;
378203c4805SLuis R. Rodriguez 	u16 ctl_center;
379203c4805SLuis R. Rodriguez 	u16 ext_center;
380203c4805SLuis R. Rodriguez };
381203c4805SLuis R. Rodriguez 
382203c4805SLuis R. Rodriguez enum {
383203c4805SLuis R. Rodriguez 	ATH9K_RESET_POWER_ON,
384203c4805SLuis R. Rodriguez 	ATH9K_RESET_WARM,
385203c4805SLuis R. Rodriguez 	ATH9K_RESET_COLD,
386203c4805SLuis R. Rodriguez };
387203c4805SLuis R. Rodriguez 
388203c4805SLuis R. Rodriguez struct ath9k_hw_version {
389203c4805SLuis R. Rodriguez 	u32 magic;
390203c4805SLuis R. Rodriguez 	u16 devid;
391203c4805SLuis R. Rodriguez 	u16 subvendorid;
392203c4805SLuis R. Rodriguez 	u32 macVersion;
393203c4805SLuis R. Rodriguez 	u16 macRev;
394203c4805SLuis R. Rodriguez 	u16 phyRev;
395203c4805SLuis R. Rodriguez 	u16 analog5GhzRev;
396203c4805SLuis R. Rodriguez 	u16 analog2GhzRev;
397aeac355dSVasanthakumar Thiagarajan 	u16 subsysid;
398203c4805SLuis R. Rodriguez };
399203c4805SLuis R. Rodriguez 
400ff155a45SVasanthakumar Thiagarajan /* Generic TSF timer definitions */
401ff155a45SVasanthakumar Thiagarajan 
402ff155a45SVasanthakumar Thiagarajan #define ATH_MAX_GEN_TIMER	16
403ff155a45SVasanthakumar Thiagarajan 
404ff155a45SVasanthakumar Thiagarajan #define AR_GENTMR_BIT(_index)	(1 << (_index))
405ff155a45SVasanthakumar Thiagarajan 
406ff155a45SVasanthakumar Thiagarajan /*
407ff155a45SVasanthakumar Thiagarajan  * Using de Bruijin sequence to to look up 1's index in a 32 bit number
408ff155a45SVasanthakumar Thiagarajan  * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
409ff155a45SVasanthakumar Thiagarajan  */
410ff155a45SVasanthakumar Thiagarajan #define debruijn32 0x077CB531UL
411ff155a45SVasanthakumar Thiagarajan 
412ff155a45SVasanthakumar Thiagarajan struct ath_gen_timer_configuration {
413ff155a45SVasanthakumar Thiagarajan 	u32 next_addr;
414ff155a45SVasanthakumar Thiagarajan 	u32 period_addr;
415ff155a45SVasanthakumar Thiagarajan 	u32 mode_addr;
416ff155a45SVasanthakumar Thiagarajan 	u32 mode_mask;
417ff155a45SVasanthakumar Thiagarajan };
418ff155a45SVasanthakumar Thiagarajan 
419ff155a45SVasanthakumar Thiagarajan struct ath_gen_timer {
420ff155a45SVasanthakumar Thiagarajan 	void (*trigger)(void *arg);
421ff155a45SVasanthakumar Thiagarajan 	void (*overflow)(void *arg);
422ff155a45SVasanthakumar Thiagarajan 	void *arg;
423ff155a45SVasanthakumar Thiagarajan 	u8 index;
424ff155a45SVasanthakumar Thiagarajan };
425ff155a45SVasanthakumar Thiagarajan 
426ff155a45SVasanthakumar Thiagarajan struct ath_gen_timer_table {
427ff155a45SVasanthakumar Thiagarajan 	u32 gen_timer_index[32];
428ff155a45SVasanthakumar Thiagarajan 	struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
429ff155a45SVasanthakumar Thiagarajan 	union {
430ff155a45SVasanthakumar Thiagarajan 		unsigned long timer_bits;
431ff155a45SVasanthakumar Thiagarajan 		u16 val;
432ff155a45SVasanthakumar Thiagarajan 	} timer_mask;
433ff155a45SVasanthakumar Thiagarajan };
434ff155a45SVasanthakumar Thiagarajan 
435203c4805SLuis R. Rodriguez struct ath_hw {
436203c4805SLuis R. Rodriguez 	struct ath_softc *ah_sc;
437203c4805SLuis R. Rodriguez 	struct ath9k_hw_version hw_version;
438203c4805SLuis R. Rodriguez 	struct ath9k_ops_config config;
439203c4805SLuis R. Rodriguez 	struct ath9k_hw_capabilities caps;
440203c4805SLuis R. Rodriguez 	struct ath9k_channel channels[38];
441203c4805SLuis R. Rodriguez 	struct ath9k_channel *curchan;
442203c4805SLuis R. Rodriguez 
443203c4805SLuis R. Rodriguez 	union {
444203c4805SLuis R. Rodriguez 		struct ar5416_eeprom_def def;
445203c4805SLuis R. Rodriguez 		struct ar5416_eeprom_4k map4k;
446475f5989SLuis R. Rodriguez 		struct ar9287_eeprom map9287;
447203c4805SLuis R. Rodriguez 	} eeprom;
448203c4805SLuis R. Rodriguez 	const struct eeprom_ops *eep_ops;
449203c4805SLuis R. Rodriguez 	enum ath9k_eep_map eep_map;
450203c4805SLuis R. Rodriguez 
451203c4805SLuis R. Rodriguez 	bool sw_mgmt_crypto;
452203c4805SLuis R. Rodriguez 	bool is_pciexpress;
453203c4805SLuis R. Rodriguez 	u8 macaddr[ETH_ALEN];
454203c4805SLuis R. Rodriguez 	u16 tx_trig_level;
455203c4805SLuis R. Rodriguez 	u16 rfsilent;
456203c4805SLuis R. Rodriguez 	u32 rfkill_gpio;
457203c4805SLuis R. Rodriguez 	u32 rfkill_polarity;
458203c4805SLuis R. Rodriguez 	u32 ah_flags;
459203c4805SLuis R. Rodriguez 
460d7e7d229SLuis R. Rodriguez 	bool htc_reset_init;
461d7e7d229SLuis R. Rodriguez 
462203c4805SLuis R. Rodriguez 	enum nl80211_iftype opmode;
463203c4805SLuis R. Rodriguez 	enum ath9k_power_mode power_mode;
464203c4805SLuis R. Rodriguez 
465203c4805SLuis R. Rodriguez 	struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
466a13883b0SSujith 	struct ath9k_pacal_info pacal_info;
467203c4805SLuis R. Rodriguez 	struct ar5416Stats stats;
468203c4805SLuis R. Rodriguez 	struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
469203c4805SLuis R. Rodriguez 
470203c4805SLuis R. Rodriguez 	int16_t curchan_rad_index;
471203c4805SLuis R. Rodriguez 	u32 mask_reg;
472203c4805SLuis R. Rodriguez 	u32 txok_interrupt_mask;
473203c4805SLuis R. Rodriguez 	u32 txerr_interrupt_mask;
474203c4805SLuis R. Rodriguez 	u32 txdesc_interrupt_mask;
475203c4805SLuis R. Rodriguez 	u32 txeol_interrupt_mask;
476203c4805SLuis R. Rodriguez 	u32 txurn_interrupt_mask;
477203c4805SLuis R. Rodriguez 	bool chip_fullsleep;
478203c4805SLuis R. Rodriguez 	u32 atim_window;
479203c4805SLuis R. Rodriguez 
480203c4805SLuis R. Rodriguez 	/* Calibration */
481cbfe9468SSujith 	enum ath9k_cal_types supp_cals;
482cbfe9468SSujith 	struct ath9k_cal_list iq_caldata;
483cbfe9468SSujith 	struct ath9k_cal_list adcgain_caldata;
484cbfe9468SSujith 	struct ath9k_cal_list adcdc_calinitdata;
485cbfe9468SSujith 	struct ath9k_cal_list adcdc_caldata;
486cbfe9468SSujith 	struct ath9k_cal_list *cal_list;
487cbfe9468SSujith 	struct ath9k_cal_list *cal_list_last;
488cbfe9468SSujith 	struct ath9k_cal_list *cal_list_curr;
489203c4805SLuis R. Rodriguez #define totalPowerMeasI meas0.unsign
490203c4805SLuis R. Rodriguez #define totalPowerMeasQ meas1.unsign
491203c4805SLuis R. Rodriguez #define totalIqCorrMeas meas2.sign
492203c4805SLuis R. Rodriguez #define totalAdcIOddPhase  meas0.unsign
493203c4805SLuis R. Rodriguez #define totalAdcIEvenPhase meas1.unsign
494203c4805SLuis R. Rodriguez #define totalAdcQOddPhase  meas2.unsign
495203c4805SLuis R. Rodriguez #define totalAdcQEvenPhase meas3.unsign
496203c4805SLuis R. Rodriguez #define totalAdcDcOffsetIOddPhase  meas0.sign
497203c4805SLuis R. Rodriguez #define totalAdcDcOffsetIEvenPhase meas1.sign
498203c4805SLuis R. Rodriguez #define totalAdcDcOffsetQOddPhase  meas2.sign
499203c4805SLuis R. Rodriguez #define totalAdcDcOffsetQEvenPhase meas3.sign
500203c4805SLuis R. Rodriguez 	union {
501203c4805SLuis R. Rodriguez 		u32 unsign[AR5416_MAX_CHAINS];
502203c4805SLuis R. Rodriguez 		int32_t sign[AR5416_MAX_CHAINS];
503203c4805SLuis R. Rodriguez 	} meas0;
504203c4805SLuis R. Rodriguez 	union {
505203c4805SLuis R. Rodriguez 		u32 unsign[AR5416_MAX_CHAINS];
506203c4805SLuis R. Rodriguez 		int32_t sign[AR5416_MAX_CHAINS];
507203c4805SLuis R. Rodriguez 	} meas1;
508203c4805SLuis R. Rodriguez 	union {
509203c4805SLuis R. Rodriguez 		u32 unsign[AR5416_MAX_CHAINS];
510203c4805SLuis R. Rodriguez 		int32_t sign[AR5416_MAX_CHAINS];
511203c4805SLuis R. Rodriguez 	} meas2;
512203c4805SLuis R. Rodriguez 	union {
513203c4805SLuis R. Rodriguez 		u32 unsign[AR5416_MAX_CHAINS];
514203c4805SLuis R. Rodriguez 		int32_t sign[AR5416_MAX_CHAINS];
515203c4805SLuis R. Rodriguez 	} meas3;
516203c4805SLuis R. Rodriguez 	u16 cal_samples;
517203c4805SLuis R. Rodriguez 
518203c4805SLuis R. Rodriguez 	u32 sta_id1_defaults;
519203c4805SLuis R. Rodriguez 	u32 misc_mode;
520203c4805SLuis R. Rodriguez 	enum {
521203c4805SLuis R. Rodriguez 		AUTO_32KHZ,
522203c4805SLuis R. Rodriguez 		USE_32KHZ,
523203c4805SLuis R. Rodriguez 		DONT_USE_32KHZ,
524203c4805SLuis R. Rodriguez 	} enable_32kHz_clock;
525203c4805SLuis R. Rodriguez 
526203c4805SLuis R. Rodriguez 	/* RF */
527203c4805SLuis R. Rodriguez 	u32 *analogBank0Data;
528203c4805SLuis R. Rodriguez 	u32 *analogBank1Data;
529203c4805SLuis R. Rodriguez 	u32 *analogBank2Data;
530203c4805SLuis R. Rodriguez 	u32 *analogBank3Data;
531203c4805SLuis R. Rodriguez 	u32 *analogBank6Data;
532203c4805SLuis R. Rodriguez 	u32 *analogBank6TPCData;
533203c4805SLuis R. Rodriguez 	u32 *analogBank7Data;
534203c4805SLuis R. Rodriguez 	u32 *addac5416_21;
535203c4805SLuis R. Rodriguez 	u32 *bank6Temp;
536203c4805SLuis R. Rodriguez 
537203c4805SLuis R. Rodriguez 	int16_t txpower_indexoffset;
538203c4805SLuis R. Rodriguez 	u32 beacon_interval;
539203c4805SLuis R. Rodriguez 	u32 slottime;
540203c4805SLuis R. Rodriguez 	u32 acktimeout;
541203c4805SLuis R. Rodriguez 	u32 ctstimeout;
542203c4805SLuis R. Rodriguez 	u32 globaltxtimeout;
543203c4805SLuis R. Rodriguez 	u8 gbeacon_rate;
544203c4805SLuis R. Rodriguez 
545203c4805SLuis R. Rodriguez 	/* ANI */
546203c4805SLuis R. Rodriguez 	u32 proc_phyerr;
547203c4805SLuis R. Rodriguez 	u32 aniperiod;
548203c4805SLuis R. Rodriguez 	struct ar5416AniState *curani;
549203c4805SLuis R. Rodriguez 	struct ar5416AniState ani[255];
550203c4805SLuis R. Rodriguez 	int totalSizeDesired[5];
551203c4805SLuis R. Rodriguez 	int coarse_high[5];
552203c4805SLuis R. Rodriguez 	int coarse_low[5];
553203c4805SLuis R. Rodriguez 	int firpwr[5];
554203c4805SLuis R. Rodriguez 	enum ath9k_ani_cmd ani_function;
555203c4805SLuis R. Rodriguez 
556203c4805SLuis R. Rodriguez 	u32 intr_txqs;
557203c4805SLuis R. Rodriguez 	enum ath9k_ht_extprotspacing extprotspacing;
558203c4805SLuis R. Rodriguez 	u8 txchainmask;
559203c4805SLuis R. Rodriguez 	u8 rxchainmask;
560203c4805SLuis R. Rodriguez 
561203c4805SLuis R. Rodriguez 	u32 originalGain[22];
562203c4805SLuis R. Rodriguez 	int initPDADC;
563203c4805SLuis R. Rodriguez 	int PDADCdelta;
56408fc5c1bSVivek Natarajan 	u8 led_pin;
565203c4805SLuis R. Rodriguez 
566203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniModes;
567203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniCommon;
568203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniBank0;
569203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniBB_RfGain;
570203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniBank1;
571203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniBank2;
572203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniBank3;
573203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniBank6;
574203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniBank6TPC;
575203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniBank7;
576203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniAddac;
577203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniPcieSerdes;
578203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniModesAdditional;
579203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniModesRxGain;
580203c4805SLuis R. Rodriguez 	struct ar5416IniArray iniModesTxGain;
581ff155a45SVasanthakumar Thiagarajan 
582ff155a45SVasanthakumar Thiagarajan 	u32 intr_gen_timer_trigger;
583ff155a45SVasanthakumar Thiagarajan 	u32 intr_gen_timer_thresh;
584ff155a45SVasanthakumar Thiagarajan 	struct ath_gen_timer_table hw_gen_timers;
585203c4805SLuis R. Rodriguez };
586203c4805SLuis R. Rodriguez 
587f637cfd6SLuis R. Rodriguez /* Initialization, Detach, Reset */
588203c4805SLuis R. Rodriguez const char *ath9k_hw_probe(u16 vendorid, u16 devid);
589203c4805SLuis R. Rodriguez void ath9k_hw_detach(struct ath_hw *ah);
590f637cfd6SLuis R. Rodriguez int ath9k_hw_init(struct ath_hw *ah);
591081b35abSLuis R. Rodriguez void ath9k_hw_rf_free(struct ath_hw *ah);
592203c4805SLuis R. Rodriguez int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
593203c4805SLuis R. Rodriguez 		   bool bChannelChange);
594203c4805SLuis R. Rodriguez void ath9k_hw_fill_cap_info(struct ath_hw *ah);
595203c4805SLuis R. Rodriguez bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
596203c4805SLuis R. Rodriguez 			    u32 capability, u32 *result);
597203c4805SLuis R. Rodriguez bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
598203c4805SLuis R. Rodriguez 			    u32 capability, u32 setting, int *status);
599203c4805SLuis R. Rodriguez 
600203c4805SLuis R. Rodriguez /* Key Cache Management */
601203c4805SLuis R. Rodriguez bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
602203c4805SLuis R. Rodriguez bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
603203c4805SLuis R. Rodriguez bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
604203c4805SLuis R. Rodriguez 				 const struct ath9k_keyval *k,
605203c4805SLuis R. Rodriguez 				 const u8 *mac);
606203c4805SLuis R. Rodriguez bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
607203c4805SLuis R. Rodriguez 
608203c4805SLuis R. Rodriguez /* GPIO / RFKILL / Antennae */
609203c4805SLuis R. Rodriguez void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
610203c4805SLuis R. Rodriguez u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
611203c4805SLuis R. Rodriguez void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
612203c4805SLuis R. Rodriguez 			 u32 ah_signal_type);
613203c4805SLuis R. Rodriguez void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
614203c4805SLuis R. Rodriguez u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
615203c4805SLuis R. Rodriguez void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
616203c4805SLuis R. Rodriguez bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
617203c4805SLuis R. Rodriguez 			       enum ath9k_ant_setting settings,
618203c4805SLuis R. Rodriguez 			       struct ath9k_channel *chan,
619203c4805SLuis R. Rodriguez 			       u8 *tx_chainmask, u8 *rx_chainmask,
620203c4805SLuis R. Rodriguez 			       u8 *antenna_cfgd);
621203c4805SLuis R. Rodriguez 
622203c4805SLuis R. Rodriguez /* General Operation */
623203c4805SLuis R. Rodriguez bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
624203c4805SLuis R. Rodriguez u32 ath9k_hw_reverse_bits(u32 val, u32 n);
625203c4805SLuis R. Rodriguez bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
6264f0fc7c3SLuis R. Rodriguez u16 ath9k_hw_computetxtime(struct ath_hw *ah,
6274f0fc7c3SLuis R. Rodriguez 			   const struct ath_rate_table *rates,
628203c4805SLuis R. Rodriguez 			   u32 frameLen, u16 rateix, bool shortPreamble);
629203c4805SLuis R. Rodriguez void ath9k_hw_get_channel_centers(struct ath_hw *ah,
630203c4805SLuis R. Rodriguez 				  struct ath9k_channel *chan,
631203c4805SLuis R. Rodriguez 				  struct chan_centers *centers);
632203c4805SLuis R. Rodriguez u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
633203c4805SLuis R. Rodriguez void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
634203c4805SLuis R. Rodriguez bool ath9k_hw_phy_disable(struct ath_hw *ah);
635203c4805SLuis R. Rodriguez bool ath9k_hw_disable(struct ath_hw *ah);
6368fbff4b8SVasanthakumar Thiagarajan void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
637203c4805SLuis R. Rodriguez void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
638203c4805SLuis R. Rodriguez void ath9k_hw_setopmode(struct ath_hw *ah);
639203c4805SLuis R. Rodriguez void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
640203c4805SLuis R. Rodriguez void ath9k_hw_setbssidmask(struct ath_softc *sc);
641203c4805SLuis R. Rodriguez void ath9k_hw_write_associd(struct ath_softc *sc);
642203c4805SLuis R. Rodriguez u64 ath9k_hw_gettsf64(struct ath_hw *ah);
643203c4805SLuis R. Rodriguez void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
644203c4805SLuis R. Rodriguez void ath9k_hw_reset_tsf(struct ath_hw *ah);
64554e4cec6SSujith void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
646203c4805SLuis R. Rodriguez bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
647203c4805SLuis R. Rodriguez void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
648203c4805SLuis R. Rodriguez void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
649203c4805SLuis R. Rodriguez void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
650203c4805SLuis R. Rodriguez 				    const struct ath9k_beacon_state *bs);
651203c4805SLuis R. Rodriguez bool ath9k_hw_setpower(struct ath_hw *ah,
652203c4805SLuis R. Rodriguez 		       enum ath9k_power_mode mode);
653203c4805SLuis R. Rodriguez void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore);
654203c4805SLuis R. Rodriguez 
655203c4805SLuis R. Rodriguez /* Interrupt Handling */
656203c4805SLuis R. Rodriguez bool ath9k_hw_intrpend(struct ath_hw *ah);
657203c4805SLuis R. Rodriguez bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
658203c4805SLuis R. Rodriguez enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
659203c4805SLuis R. Rodriguez 
660ff155a45SVasanthakumar Thiagarajan /* Generic hw timer primitives */
661ff155a45SVasanthakumar Thiagarajan struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
662ff155a45SVasanthakumar Thiagarajan 					  void (*trigger)(void *),
663ff155a45SVasanthakumar Thiagarajan 					  void (*overflow)(void *),
664ff155a45SVasanthakumar Thiagarajan 					  void *arg,
665ff155a45SVasanthakumar Thiagarajan 					  u8 timer_index);
666ff155a45SVasanthakumar Thiagarajan void ath_gen_timer_start(struct ath_hw *ah, struct ath_gen_timer *timer,
667ff155a45SVasanthakumar Thiagarajan 			 u32 timer_next, u32 timer_period);
668ff155a45SVasanthakumar Thiagarajan void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
669ff155a45SVasanthakumar Thiagarajan void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
670ff155a45SVasanthakumar Thiagarajan void ath_gen_timer_isr(struct ath_hw *hw);
6711773912bSVasanthakumar Thiagarajan u32 ath9k_hw_gettsf32(struct ath_hw *ah);
672ff155a45SVasanthakumar Thiagarajan 
6737b6840abSVasanthakumar Thiagarajan #define ATH_PCIE_CAP_LINK_CTRL	0x70
6747b6840abSVasanthakumar Thiagarajan #define ATH_PCIE_CAP_LINK_L0S	1
6757b6840abSVasanthakumar Thiagarajan #define ATH_PCIE_CAP_LINK_L1	2
6767b6840abSVasanthakumar Thiagarajan 
6777b6840abSVasanthakumar Thiagarajan void ath_pcie_aspm_disable(struct ath_softc *sc);
678203c4805SLuis R. Rodriguez #endif
679