1 /* 2 * Copyright (c) 2008-2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <asm/unaligned.h> 20 21 #include "hw.h" 22 #include "hw-ops.h" 23 #include "rc.h" 24 #include "ar9003_mac.h" 25 26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 27 28 MODULE_AUTHOR("Atheros Communications"); 29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 31 MODULE_LICENSE("Dual BSD/GPL"); 32 33 static int __init ath9k_init(void) 34 { 35 return 0; 36 } 37 module_init(ath9k_init); 38 39 static void __exit ath9k_exit(void) 40 { 41 return; 42 } 43 module_exit(ath9k_exit); 44 45 /* Private hardware callbacks */ 46 47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 48 { 49 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 50 } 51 52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 53 { 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 55 } 56 57 static bool ath9k_hw_macversion_supported(struct ath_hw *ah) 58 { 59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 60 61 return priv_ops->macversion_supported(ah->hw_version.macVersion); 62 } 63 64 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 65 struct ath9k_channel *chan) 66 { 67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 68 } 69 70 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 71 { 72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 73 return; 74 75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 76 } 77 78 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 79 { 80 /* You will not have this callback if using the old ANI */ 81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 82 return; 83 84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 85 } 86 87 /********************/ 88 /* Helper Functions */ 89 /********************/ 90 91 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) 92 { 93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 94 95 if (!ah->curchan) /* should really check for CCK instead */ 96 return usecs *ATH9K_CLOCK_RATE_CCK; 97 if (conf->channel->band == IEEE80211_BAND_2GHZ) 98 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; 99 100 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 101 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 102 else 103 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM; 104 } 105 106 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 107 { 108 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 109 110 if (conf_is_ht40(conf)) 111 return ath9k_hw_mac_clks(ah, usecs) * 2; 112 else 113 return ath9k_hw_mac_clks(ah, usecs); 114 } 115 116 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 117 { 118 int i; 119 120 BUG_ON(timeout < AH_TIME_QUANTUM); 121 122 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 123 if ((REG_READ(ah, reg) & mask) == val) 124 return true; 125 126 udelay(AH_TIME_QUANTUM); 127 } 128 129 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, 130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 131 timeout, reg, REG_READ(ah, reg), mask, val); 132 133 return false; 134 } 135 EXPORT_SYMBOL(ath9k_hw_wait); 136 137 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 138 { 139 u32 retval; 140 int i; 141 142 for (i = 0, retval = 0; i < n; i++) { 143 retval = (retval << 1) | (val & 1); 144 val >>= 1; 145 } 146 return retval; 147 } 148 149 bool ath9k_get_channel_edges(struct ath_hw *ah, 150 u16 flags, u16 *low, 151 u16 *high) 152 { 153 struct ath9k_hw_capabilities *pCap = &ah->caps; 154 155 if (flags & CHANNEL_5GHZ) { 156 *low = pCap->low_5ghz_chan; 157 *high = pCap->high_5ghz_chan; 158 return true; 159 } 160 if ((flags & CHANNEL_2GHZ)) { 161 *low = pCap->low_2ghz_chan; 162 *high = pCap->high_2ghz_chan; 163 return true; 164 } 165 return false; 166 } 167 168 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 169 u8 phy, int kbps, 170 u32 frameLen, u16 rateix, 171 bool shortPreamble) 172 { 173 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 174 175 if (kbps == 0) 176 return 0; 177 178 switch (phy) { 179 case WLAN_RC_PHY_CCK: 180 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 181 if (shortPreamble) 182 phyTime >>= 1; 183 numBits = frameLen << 3; 184 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 185 break; 186 case WLAN_RC_PHY_OFDM: 187 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 188 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 189 numBits = OFDM_PLCP_BITS + (frameLen << 3); 190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 191 txTime = OFDM_SIFS_TIME_QUARTER 192 + OFDM_PREAMBLE_TIME_QUARTER 193 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 194 } else if (ah->curchan && 195 IS_CHAN_HALF_RATE(ah->curchan)) { 196 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 197 numBits = OFDM_PLCP_BITS + (frameLen << 3); 198 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 199 txTime = OFDM_SIFS_TIME_HALF + 200 OFDM_PREAMBLE_TIME_HALF 201 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 202 } else { 203 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 204 numBits = OFDM_PLCP_BITS + (frameLen << 3); 205 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 206 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 207 + (numSymbols * OFDM_SYMBOL_TIME); 208 } 209 break; 210 default: 211 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 212 "Unknown phy %u (rate ix %u)\n", phy, rateix); 213 txTime = 0; 214 break; 215 } 216 217 return txTime; 218 } 219 EXPORT_SYMBOL(ath9k_hw_computetxtime); 220 221 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 222 struct ath9k_channel *chan, 223 struct chan_centers *centers) 224 { 225 int8_t extoff; 226 227 if (!IS_CHAN_HT40(chan)) { 228 centers->ctl_center = centers->ext_center = 229 centers->synth_center = chan->channel; 230 return; 231 } 232 233 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 234 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 235 centers->synth_center = 236 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 237 extoff = 1; 238 } else { 239 centers->synth_center = 240 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 241 extoff = -1; 242 } 243 244 centers->ctl_center = 245 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 246 /* 25 MHz spacing is supported by hw but not on upper layers */ 247 centers->ext_center = 248 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 249 } 250 251 /******************/ 252 /* Chip Revisions */ 253 /******************/ 254 255 static void ath9k_hw_read_revisions(struct ath_hw *ah) 256 { 257 u32 val; 258 259 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 260 261 if (val == 0xFF) { 262 val = REG_READ(ah, AR_SREV); 263 ah->hw_version.macVersion = 264 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 265 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 266 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 267 } else { 268 if (!AR_SREV_9100(ah)) 269 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 270 271 ah->hw_version.macRev = val & AR_SREV_REVISION; 272 273 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 274 ah->is_pciexpress = true; 275 } 276 } 277 278 /************************************/ 279 /* HW Attach, Detach, Init Routines */ 280 /************************************/ 281 282 static void ath9k_hw_disablepcie(struct ath_hw *ah) 283 { 284 if (AR_SREV_9100(ah)) 285 return; 286 287 ENABLE_REGWRITE_BUFFER(ah); 288 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 298 299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 300 301 REGWRITE_BUFFER_FLUSH(ah); 302 DISABLE_REGWRITE_BUFFER(ah); 303 } 304 305 /* This should work for all families including legacy */ 306 static bool ath9k_hw_chip_test(struct ath_hw *ah) 307 { 308 struct ath_common *common = ath9k_hw_common(ah); 309 u32 regAddr[2] = { AR_STA_ID0 }; 310 u32 regHold[2]; 311 u32 patternData[4] = { 0x55555555, 312 0xaaaaaaaa, 313 0x66666666, 314 0x99999999 }; 315 int i, j, loop_max; 316 317 if (!AR_SREV_9300_20_OR_LATER(ah)) { 318 loop_max = 2; 319 regAddr[1] = AR_PHY_BASE + (8 << 2); 320 } else 321 loop_max = 1; 322 323 for (i = 0; i < loop_max; i++) { 324 u32 addr = regAddr[i]; 325 u32 wrData, rdData; 326 327 regHold[i] = REG_READ(ah, addr); 328 for (j = 0; j < 0x100; j++) { 329 wrData = (j << 16) | j; 330 REG_WRITE(ah, addr, wrData); 331 rdData = REG_READ(ah, addr); 332 if (rdData != wrData) { 333 ath_print(common, ATH_DBG_FATAL, 334 "address test failed " 335 "addr: 0x%08x - wr:0x%08x != " 336 "rd:0x%08x\n", 337 addr, wrData, rdData); 338 return false; 339 } 340 } 341 for (j = 0; j < 4; j++) { 342 wrData = patternData[j]; 343 REG_WRITE(ah, addr, wrData); 344 rdData = REG_READ(ah, addr); 345 if (wrData != rdData) { 346 ath_print(common, ATH_DBG_FATAL, 347 "address test failed " 348 "addr: 0x%08x - wr:0x%08x != " 349 "rd:0x%08x\n", 350 addr, wrData, rdData); 351 return false; 352 } 353 } 354 REG_WRITE(ah, regAddr[i], regHold[i]); 355 } 356 udelay(100); 357 358 return true; 359 } 360 361 static void ath9k_hw_init_config(struct ath_hw *ah) 362 { 363 int i; 364 365 ah->config.dma_beacon_response_time = 2; 366 ah->config.sw_beacon_response_time = 10; 367 ah->config.additional_swba_backoff = 0; 368 ah->config.ack_6mb = 0x0; 369 ah->config.cwm_ignore_extcca = 0; 370 ah->config.pcie_powersave_enable = 0; 371 ah->config.pcie_clock_req = 0; 372 ah->config.pcie_waen = 0; 373 ah->config.analog_shiftreg = 1; 374 ah->config.ofdm_trig_low = 200; 375 ah->config.ofdm_trig_high = 500; 376 ah->config.cck_trig_high = 200; 377 ah->config.cck_trig_low = 100; 378 ah->config.enable_ani = true; 379 380 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 381 ah->config.spurchans[i][0] = AR_NO_SPUR; 382 ah->config.spurchans[i][1] = AR_NO_SPUR; 383 } 384 385 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 386 ah->config.ht_enable = 1; 387 else 388 ah->config.ht_enable = 0; 389 390 ah->config.rx_intr_mitigation = true; 391 ah->config.pcieSerDesWrite = true; 392 393 /* 394 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 395 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 396 * This means we use it for all AR5416 devices, and the few 397 * minor PCI AR9280 devices out there. 398 * 399 * Serialization is required because these devices do not handle 400 * well the case of two concurrent reads/writes due to the latency 401 * involved. During one read/write another read/write can be issued 402 * on another CPU while the previous read/write may still be working 403 * on our hardware, if we hit this case the hardware poops in a loop. 404 * We prevent this by serializing reads and writes. 405 * 406 * This issue is not present on PCI-Express devices or pre-AR5416 407 * devices (legacy, 802.11abg). 408 */ 409 if (num_possible_cpus() > 1) 410 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 411 } 412 413 static void ath9k_hw_init_defaults(struct ath_hw *ah) 414 { 415 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 416 417 regulatory->country_code = CTRY_DEFAULT; 418 regulatory->power_limit = MAX_RATE_POWER; 419 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 420 421 ah->hw_version.magic = AR5416_MAGIC; 422 ah->hw_version.subvendorid = 0; 423 424 ah->ah_flags = 0; 425 if (!AR_SREV_9100(ah)) 426 ah->ah_flags = AH_USE_EEPROM; 427 428 ah->atim_window = 0; 429 ah->sta_id1_defaults = 430 AR_STA_ID1_CRPT_MIC_ENABLE | 431 AR_STA_ID1_MCAST_KSRCH; 432 ah->beacon_interval = 100; 433 ah->enable_32kHz_clock = DONT_USE_32KHZ; 434 ah->slottime = (u32) -1; 435 ah->globaltxtimeout = (u32) -1; 436 ah->power_mode = ATH9K_PM_UNDEFINED; 437 } 438 439 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 440 { 441 struct ath_common *common = ath9k_hw_common(ah); 442 u32 sum; 443 int i; 444 u16 eeval; 445 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 446 447 sum = 0; 448 for (i = 0; i < 3; i++) { 449 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 450 sum += eeval; 451 common->macaddr[2 * i] = eeval >> 8; 452 common->macaddr[2 * i + 1] = eeval & 0xff; 453 } 454 if (sum == 0 || sum == 0xffff * 3) 455 return -EADDRNOTAVAIL; 456 457 return 0; 458 } 459 460 static int ath9k_hw_post_init(struct ath_hw *ah) 461 { 462 int ecode; 463 464 if (!AR_SREV_9271(ah)) { 465 if (!ath9k_hw_chip_test(ah)) 466 return -ENODEV; 467 } 468 469 if (!AR_SREV_9300_20_OR_LATER(ah)) { 470 ecode = ar9002_hw_rf_claim(ah); 471 if (ecode != 0) 472 return ecode; 473 } 474 475 ecode = ath9k_hw_eeprom_init(ah); 476 if (ecode != 0) 477 return ecode; 478 479 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, 480 "Eeprom VER: %d, REV: %d\n", 481 ah->eep_ops->get_eeprom_ver(ah), 482 ah->eep_ops->get_eeprom_rev(ah)); 483 484 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 485 if (ecode) { 486 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 487 "Failed allocating banks for " 488 "external radio\n"); 489 return ecode; 490 } 491 492 if (!AR_SREV_9100(ah)) { 493 ath9k_hw_ani_setup(ah); 494 ath9k_hw_ani_init(ah); 495 } 496 497 return 0; 498 } 499 500 static void ath9k_hw_attach_ops(struct ath_hw *ah) 501 { 502 if (AR_SREV_9300_20_OR_LATER(ah)) 503 ar9003_hw_attach_ops(ah); 504 else 505 ar9002_hw_attach_ops(ah); 506 } 507 508 /* Called for all hardware families */ 509 static int __ath9k_hw_init(struct ath_hw *ah) 510 { 511 struct ath_common *common = ath9k_hw_common(ah); 512 int r = 0; 513 514 if (ah->hw_version.devid == AR5416_AR9100_DEVID) 515 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 516 517 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 518 ath_print(common, ATH_DBG_FATAL, 519 "Couldn't reset chip\n"); 520 return -EIO; 521 } 522 523 ath9k_hw_init_defaults(ah); 524 ath9k_hw_init_config(ah); 525 526 ath9k_hw_attach_ops(ah); 527 528 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 529 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 530 return -EIO; 531 } 532 533 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 534 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 535 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 536 !ah->is_pciexpress)) { 537 ah->config.serialize_regmode = 538 SER_REG_MODE_ON; 539 } else { 540 ah->config.serialize_regmode = 541 SER_REG_MODE_OFF; 542 } 543 } 544 545 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 546 ah->config.serialize_regmode); 547 548 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 549 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 550 else 551 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 552 553 if (!ath9k_hw_macversion_supported(ah)) { 554 ath_print(common, ATH_DBG_FATAL, 555 "Mac Chip Rev 0x%02x.%x is not supported by " 556 "this driver\n", ah->hw_version.macVersion, 557 ah->hw_version.macRev); 558 return -EOPNOTSUPP; 559 } 560 561 if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) 562 ah->is_pciexpress = false; 563 564 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 565 ath9k_hw_init_cal_settings(ah); 566 567 ah->ani_function = ATH9K_ANI_ALL; 568 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 569 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 570 if (!AR_SREV_9300_20_OR_LATER(ah)) 571 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 572 573 ath9k_hw_init_mode_regs(ah); 574 575 /* 576 * Read back AR_WA into a permanent copy and set bits 14 and 17. 577 * We need to do this to avoid RMW of this register. We cannot 578 * read the reg when chip is asleep. 579 */ 580 ah->WARegVal = REG_READ(ah, AR_WA); 581 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 582 AR_WA_ASPM_TIMER_BASED_DISABLE); 583 584 if (ah->is_pciexpress) 585 ath9k_hw_configpcipowersave(ah, 0, 0); 586 else 587 ath9k_hw_disablepcie(ah); 588 589 if (!AR_SREV_9300_20_OR_LATER(ah)) 590 ar9002_hw_cck_chan14_spread(ah); 591 592 r = ath9k_hw_post_init(ah); 593 if (r) 594 return r; 595 596 ath9k_hw_init_mode_gain_regs(ah); 597 r = ath9k_hw_fill_cap_info(ah); 598 if (r) 599 return r; 600 601 r = ath9k_hw_init_macaddr(ah); 602 if (r) { 603 ath_print(common, ATH_DBG_FATAL, 604 "Failed to initialize MAC address\n"); 605 return r; 606 } 607 608 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 609 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 610 else 611 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 612 613 ah->bb_watchdog_timeout_ms = 25; 614 615 common->state = ATH_HW_INITIALIZED; 616 617 return 0; 618 } 619 620 int ath9k_hw_init(struct ath_hw *ah) 621 { 622 int ret; 623 struct ath_common *common = ath9k_hw_common(ah); 624 625 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 626 switch (ah->hw_version.devid) { 627 case AR5416_DEVID_PCI: 628 case AR5416_DEVID_PCIE: 629 case AR5416_AR9100_DEVID: 630 case AR9160_DEVID_PCI: 631 case AR9280_DEVID_PCI: 632 case AR9280_DEVID_PCIE: 633 case AR9285_DEVID_PCIE: 634 case AR9287_DEVID_PCI: 635 case AR9287_DEVID_PCIE: 636 case AR2427_DEVID_PCIE: 637 case AR9300_DEVID_PCIE: 638 break; 639 default: 640 if (common->bus_ops->ath_bus_type == ATH_USB) 641 break; 642 ath_print(common, ATH_DBG_FATAL, 643 "Hardware device ID 0x%04x not supported\n", 644 ah->hw_version.devid); 645 return -EOPNOTSUPP; 646 } 647 648 ret = __ath9k_hw_init(ah); 649 if (ret) { 650 ath_print(common, ATH_DBG_FATAL, 651 "Unable to initialize hardware; " 652 "initialization status: %d\n", ret); 653 return ret; 654 } 655 656 return 0; 657 } 658 EXPORT_SYMBOL(ath9k_hw_init); 659 660 static void ath9k_hw_init_qos(struct ath_hw *ah) 661 { 662 ENABLE_REGWRITE_BUFFER(ah); 663 664 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 665 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 666 667 REG_WRITE(ah, AR_QOS_NO_ACK, 668 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 669 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 670 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 671 672 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 673 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 674 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 675 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 676 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 677 678 REGWRITE_BUFFER_FLUSH(ah); 679 DISABLE_REGWRITE_BUFFER(ah); 680 } 681 682 static void ath9k_hw_init_pll(struct ath_hw *ah, 683 struct ath9k_channel *chan) 684 { 685 u32 pll = ath9k_hw_compute_pll_control(ah, chan); 686 687 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 688 689 /* Switch the core clock for ar9271 to 117Mhz */ 690 if (AR_SREV_9271(ah)) { 691 udelay(500); 692 REG_WRITE(ah, 0x50040, 0x304); 693 } 694 695 udelay(RTC_PLL_SETTLE_DELAY); 696 697 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 698 } 699 700 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 701 enum nl80211_iftype opmode) 702 { 703 u32 imr_reg = AR_IMR_TXERR | 704 AR_IMR_TXURN | 705 AR_IMR_RXERR | 706 AR_IMR_RXORN | 707 AR_IMR_BCNMISC; 708 709 if (AR_SREV_9300_20_OR_LATER(ah)) { 710 imr_reg |= AR_IMR_RXOK_HP; 711 if (ah->config.rx_intr_mitigation) 712 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 713 else 714 imr_reg |= AR_IMR_RXOK_LP; 715 716 } else { 717 if (ah->config.rx_intr_mitigation) 718 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 719 else 720 imr_reg |= AR_IMR_RXOK; 721 } 722 723 if (ah->config.tx_intr_mitigation) 724 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 725 else 726 imr_reg |= AR_IMR_TXOK; 727 728 if (opmode == NL80211_IFTYPE_AP) 729 imr_reg |= AR_IMR_MIB; 730 731 ENABLE_REGWRITE_BUFFER(ah); 732 733 REG_WRITE(ah, AR_IMR, imr_reg); 734 ah->imrs2_reg |= AR_IMR_S2_GTT; 735 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 736 737 if (!AR_SREV_9100(ah)) { 738 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 739 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 740 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 741 } 742 743 REGWRITE_BUFFER_FLUSH(ah); 744 DISABLE_REGWRITE_BUFFER(ah); 745 746 if (AR_SREV_9300_20_OR_LATER(ah)) { 747 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 748 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 749 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 750 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 751 } 752 } 753 754 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 755 { 756 u32 val = ath9k_hw_mac_to_clks(ah, us); 757 val = min(val, (u32) 0xFFFF); 758 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 759 } 760 761 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 762 { 763 u32 val = ath9k_hw_mac_to_clks(ah, us); 764 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 765 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 766 } 767 768 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 769 { 770 u32 val = ath9k_hw_mac_to_clks(ah, us); 771 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 772 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 773 } 774 775 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 776 { 777 if (tu > 0xFFFF) { 778 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 779 "bad global tx timeout %u\n", tu); 780 ah->globaltxtimeout = (u32) -1; 781 return false; 782 } else { 783 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 784 ah->globaltxtimeout = tu; 785 return true; 786 } 787 } 788 789 void ath9k_hw_init_global_settings(struct ath_hw *ah) 790 { 791 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 792 int acktimeout; 793 int slottime; 794 int sifstime; 795 796 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 797 ah->misc_mode); 798 799 if (ah->misc_mode != 0) 800 REG_WRITE(ah, AR_PCU_MISC, 801 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); 802 803 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 804 sifstime = 16; 805 else 806 sifstime = 10; 807 808 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 809 slottime = ah->slottime + 3 * ah->coverage_class; 810 acktimeout = slottime + sifstime; 811 812 /* 813 * Workaround for early ACK timeouts, add an offset to match the 814 * initval's 64us ack timeout value. 815 * This was initially only meant to work around an issue with delayed 816 * BA frames in some implementations, but it has been found to fix ACK 817 * timeout issues in other cases as well. 818 */ 819 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 820 acktimeout += 64 - sifstime - ah->slottime; 821 822 ath9k_hw_setslottime(ah, slottime); 823 ath9k_hw_set_ack_timeout(ah, acktimeout); 824 ath9k_hw_set_cts_timeout(ah, acktimeout); 825 if (ah->globaltxtimeout != (u32) -1) 826 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 827 } 828 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 829 830 void ath9k_hw_deinit(struct ath_hw *ah) 831 { 832 struct ath_common *common = ath9k_hw_common(ah); 833 834 if (common->state < ATH_HW_INITIALIZED) 835 goto free_hw; 836 837 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 838 839 free_hw: 840 ath9k_hw_rf_free_ext_banks(ah); 841 } 842 EXPORT_SYMBOL(ath9k_hw_deinit); 843 844 /*******/ 845 /* INI */ 846 /*******/ 847 848 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 849 { 850 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 851 852 if (IS_CHAN_B(chan)) 853 ctl |= CTL_11B; 854 else if (IS_CHAN_G(chan)) 855 ctl |= CTL_11G; 856 else 857 ctl |= CTL_11A; 858 859 return ctl; 860 } 861 862 /****************************************/ 863 /* Reset and Channel Switching Routines */ 864 /****************************************/ 865 866 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 867 { 868 struct ath_common *common = ath9k_hw_common(ah); 869 u32 regval; 870 871 ENABLE_REGWRITE_BUFFER(ah); 872 873 /* 874 * set AHB_MODE not to do cacheline prefetches 875 */ 876 if (!AR_SREV_9300_20_OR_LATER(ah)) { 877 regval = REG_READ(ah, AR_AHB_MODE); 878 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 879 } 880 881 /* 882 * let mac dma reads be in 128 byte chunks 883 */ 884 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 885 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 886 887 REGWRITE_BUFFER_FLUSH(ah); 888 DISABLE_REGWRITE_BUFFER(ah); 889 890 /* 891 * Restore TX Trigger Level to its pre-reset value. 892 * The initial value depends on whether aggregation is enabled, and is 893 * adjusted whenever underruns are detected. 894 */ 895 if (!AR_SREV_9300_20_OR_LATER(ah)) 896 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 897 898 ENABLE_REGWRITE_BUFFER(ah); 899 900 /* 901 * let mac dma writes be in 128 byte chunks 902 */ 903 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 904 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 905 906 /* 907 * Setup receive FIFO threshold to hold off TX activities 908 */ 909 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 910 911 if (AR_SREV_9300_20_OR_LATER(ah)) { 912 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 913 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 914 915 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 916 ah->caps.rx_status_len); 917 } 918 919 /* 920 * reduce the number of usable entries in PCU TXBUF to avoid 921 * wrap around issues. 922 */ 923 if (AR_SREV_9285(ah)) { 924 /* For AR9285 the number of Fifos are reduced to half. 925 * So set the usable tx buf size also to half to 926 * avoid data/delimiter underruns 927 */ 928 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 929 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 930 } else if (!AR_SREV_9271(ah)) { 931 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 932 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 933 } 934 935 REGWRITE_BUFFER_FLUSH(ah); 936 DISABLE_REGWRITE_BUFFER(ah); 937 938 if (AR_SREV_9300_20_OR_LATER(ah)) 939 ath9k_hw_reset_txstatus_ring(ah); 940 } 941 942 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 943 { 944 u32 val; 945 946 val = REG_READ(ah, AR_STA_ID1); 947 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 948 switch (opmode) { 949 case NL80211_IFTYPE_AP: 950 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 951 | AR_STA_ID1_KSRCH_MODE); 952 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 953 break; 954 case NL80211_IFTYPE_ADHOC: 955 case NL80211_IFTYPE_MESH_POINT: 956 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 957 | AR_STA_ID1_KSRCH_MODE); 958 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 959 break; 960 case NL80211_IFTYPE_STATION: 961 case NL80211_IFTYPE_MONITOR: 962 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 963 break; 964 } 965 } 966 967 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 968 u32 *coef_mantissa, u32 *coef_exponent) 969 { 970 u32 coef_exp, coef_man; 971 972 for (coef_exp = 31; coef_exp > 0; coef_exp--) 973 if ((coef_scaled >> coef_exp) & 0x1) 974 break; 975 976 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 977 978 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 979 980 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 981 *coef_exponent = coef_exp - 16; 982 } 983 984 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 985 { 986 u32 rst_flags; 987 u32 tmpReg; 988 989 if (AR_SREV_9100(ah)) { 990 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 991 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 992 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 993 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 994 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 995 } 996 997 ENABLE_REGWRITE_BUFFER(ah); 998 999 if (AR_SREV_9300_20_OR_LATER(ah)) { 1000 REG_WRITE(ah, AR_WA, ah->WARegVal); 1001 udelay(10); 1002 } 1003 1004 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1005 AR_RTC_FORCE_WAKE_ON_INT); 1006 1007 if (AR_SREV_9100(ah)) { 1008 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1009 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1010 } else { 1011 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1012 if (tmpReg & 1013 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1014 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1015 u32 val; 1016 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1017 1018 val = AR_RC_HOSTIF; 1019 if (!AR_SREV_9300_20_OR_LATER(ah)) 1020 val |= AR_RC_AHB; 1021 REG_WRITE(ah, AR_RC, val); 1022 1023 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1024 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1025 1026 rst_flags = AR_RTC_RC_MAC_WARM; 1027 if (type == ATH9K_RESET_COLD) 1028 rst_flags |= AR_RTC_RC_MAC_COLD; 1029 } 1030 1031 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1032 1033 REGWRITE_BUFFER_FLUSH(ah); 1034 DISABLE_REGWRITE_BUFFER(ah); 1035 1036 udelay(50); 1037 1038 REG_WRITE(ah, AR_RTC_RC, 0); 1039 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1040 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1041 "RTC stuck in MAC reset\n"); 1042 return false; 1043 } 1044 1045 if (!AR_SREV_9100(ah)) 1046 REG_WRITE(ah, AR_RC, 0); 1047 1048 if (AR_SREV_9100(ah)) 1049 udelay(50); 1050 1051 return true; 1052 } 1053 1054 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1055 { 1056 ENABLE_REGWRITE_BUFFER(ah); 1057 1058 if (AR_SREV_9300_20_OR_LATER(ah)) { 1059 REG_WRITE(ah, AR_WA, ah->WARegVal); 1060 udelay(10); 1061 } 1062 1063 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1064 AR_RTC_FORCE_WAKE_ON_INT); 1065 1066 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1067 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1068 1069 REG_WRITE(ah, AR_RTC_RESET, 0); 1070 udelay(2); 1071 1072 REGWRITE_BUFFER_FLUSH(ah); 1073 DISABLE_REGWRITE_BUFFER(ah); 1074 1075 if (!AR_SREV_9300_20_OR_LATER(ah)) 1076 udelay(2); 1077 1078 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1079 REG_WRITE(ah, AR_RC, 0); 1080 1081 REG_WRITE(ah, AR_RTC_RESET, 1); 1082 1083 if (!ath9k_hw_wait(ah, 1084 AR_RTC_STATUS, 1085 AR_RTC_STATUS_M, 1086 AR_RTC_STATUS_ON, 1087 AH_WAIT_TIMEOUT)) { 1088 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1089 "RTC not waking up\n"); 1090 return false; 1091 } 1092 1093 ath9k_hw_read_revisions(ah); 1094 1095 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1096 } 1097 1098 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1099 { 1100 if (AR_SREV_9300_20_OR_LATER(ah)) { 1101 REG_WRITE(ah, AR_WA, ah->WARegVal); 1102 udelay(10); 1103 } 1104 1105 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1106 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1107 1108 switch (type) { 1109 case ATH9K_RESET_POWER_ON: 1110 return ath9k_hw_set_reset_power_on(ah); 1111 case ATH9K_RESET_WARM: 1112 case ATH9K_RESET_COLD: 1113 return ath9k_hw_set_reset(ah, type); 1114 default: 1115 return false; 1116 } 1117 } 1118 1119 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1120 struct ath9k_channel *chan) 1121 { 1122 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1123 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1124 return false; 1125 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1126 return false; 1127 1128 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1129 return false; 1130 1131 ah->chip_fullsleep = false; 1132 ath9k_hw_init_pll(ah, chan); 1133 ath9k_hw_set_rfmode(ah, chan); 1134 1135 return true; 1136 } 1137 1138 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1139 struct ath9k_channel *chan) 1140 { 1141 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1142 struct ath_common *common = ath9k_hw_common(ah); 1143 struct ieee80211_channel *channel = chan->chan; 1144 u32 qnum; 1145 int r; 1146 1147 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1148 if (ath9k_hw_numtxpending(ah, qnum)) { 1149 ath_print(common, ATH_DBG_QUEUE, 1150 "Transmit frames pending on " 1151 "queue %d\n", qnum); 1152 return false; 1153 } 1154 } 1155 1156 if (!ath9k_hw_rfbus_req(ah)) { 1157 ath_print(common, ATH_DBG_FATAL, 1158 "Could not kill baseband RX\n"); 1159 return false; 1160 } 1161 1162 ath9k_hw_set_channel_regs(ah, chan); 1163 1164 r = ath9k_hw_rf_set_freq(ah, chan); 1165 if (r) { 1166 ath_print(common, ATH_DBG_FATAL, 1167 "Failed to set channel\n"); 1168 return false; 1169 } 1170 1171 ah->eep_ops->set_txpower(ah, chan, 1172 ath9k_regd_get_ctl(regulatory, chan), 1173 channel->max_antenna_gain * 2, 1174 channel->max_power * 2, 1175 min((u32) MAX_RATE_POWER, 1176 (u32) regulatory->power_limit)); 1177 1178 ath9k_hw_rfbus_done(ah); 1179 1180 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1181 ath9k_hw_set_delta_slope(ah, chan); 1182 1183 ath9k_hw_spur_mitigate_freq(ah, chan); 1184 1185 return true; 1186 } 1187 1188 bool ath9k_hw_check_alive(struct ath_hw *ah) 1189 { 1190 int count = 50; 1191 u32 reg; 1192 1193 if (AR_SREV_9285_10_OR_LATER(ah)) 1194 return true; 1195 1196 do { 1197 reg = REG_READ(ah, AR_OBS_BUS_1); 1198 1199 if ((reg & 0x7E7FFFEF) == 0x00702400) 1200 continue; 1201 1202 switch (reg & 0x7E000B00) { 1203 case 0x1E000000: 1204 case 0x52000B00: 1205 case 0x18000B00: 1206 continue; 1207 default: 1208 return true; 1209 } 1210 } while (count-- > 0); 1211 1212 return false; 1213 } 1214 EXPORT_SYMBOL(ath9k_hw_check_alive); 1215 1216 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1217 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1218 { 1219 struct ath_common *common = ath9k_hw_common(ah); 1220 u32 saveLedState; 1221 struct ath9k_channel *curchan = ah->curchan; 1222 u32 saveDefAntenna; 1223 u32 macStaId1; 1224 u64 tsf = 0; 1225 int i, r; 1226 1227 ah->txchainmask = common->tx_chainmask; 1228 ah->rxchainmask = common->rx_chainmask; 1229 1230 if (!ah->chip_fullsleep) { 1231 ath9k_hw_abortpcurecv(ah); 1232 if (!ath9k_hw_stopdmarecv(ah)) { 1233 ath_print(common, ATH_DBG_XMIT, 1234 "Failed to stop receive dma\n"); 1235 bChannelChange = false; 1236 } 1237 } 1238 1239 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1240 return -EIO; 1241 1242 if (curchan && !ah->chip_fullsleep && ah->caldata) 1243 ath9k_hw_getnf(ah, curchan); 1244 1245 ah->caldata = caldata; 1246 if (caldata && 1247 (chan->channel != caldata->channel || 1248 (chan->channelFlags & ~CHANNEL_CW_INT) != 1249 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1250 /* Operating channel changed, reset channel calibration data */ 1251 memset(caldata, 0, sizeof(*caldata)); 1252 ath9k_init_nfcal_hist_buffer(ah, chan); 1253 } 1254 1255 if (bChannelChange && 1256 (ah->chip_fullsleep != true) && 1257 (ah->curchan != NULL) && 1258 (chan->channel != ah->curchan->channel) && 1259 ((chan->channelFlags & CHANNEL_ALL) == 1260 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1261 !AR_SREV_9280(ah)) { 1262 1263 if (ath9k_hw_channel_change(ah, chan)) { 1264 ath9k_hw_loadnf(ah, ah->curchan); 1265 ath9k_hw_start_nfcal(ah, true); 1266 return 0; 1267 } 1268 } 1269 1270 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1271 if (saveDefAntenna == 0) 1272 saveDefAntenna = 1; 1273 1274 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1275 1276 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1277 if (AR_SREV_9100(ah) || 1278 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1279 tsf = ath9k_hw_gettsf64(ah); 1280 1281 saveLedState = REG_READ(ah, AR_CFG_LED) & 1282 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1283 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1284 1285 ath9k_hw_mark_phy_inactive(ah); 1286 1287 /* Only required on the first reset */ 1288 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1289 REG_WRITE(ah, 1290 AR9271_RESET_POWER_DOWN_CONTROL, 1291 AR9271_RADIO_RF_RST); 1292 udelay(50); 1293 } 1294 1295 if (!ath9k_hw_chip_reset(ah, chan)) { 1296 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); 1297 return -EINVAL; 1298 } 1299 1300 /* Only required on the first reset */ 1301 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1302 ah->htc_reset_init = false; 1303 REG_WRITE(ah, 1304 AR9271_RESET_POWER_DOWN_CONTROL, 1305 AR9271_GATE_MAC_CTL); 1306 udelay(50); 1307 } 1308 1309 /* Restore TSF */ 1310 if (tsf) 1311 ath9k_hw_settsf64(ah, tsf); 1312 1313 if (AR_SREV_9280_10_OR_LATER(ah)) 1314 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1315 1316 if (!AR_SREV_9300_20_OR_LATER(ah)) 1317 ar9002_hw_enable_async_fifo(ah); 1318 1319 r = ath9k_hw_process_ini(ah, chan); 1320 if (r) 1321 return r; 1322 1323 /* 1324 * Some AR91xx SoC devices frequently fail to accept TSF writes 1325 * right after the chip reset. When that happens, write a new 1326 * value after the initvals have been applied, with an offset 1327 * based on measured time difference 1328 */ 1329 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1330 tsf += 1500; 1331 ath9k_hw_settsf64(ah, tsf); 1332 } 1333 1334 /* Setup MFP options for CCMP */ 1335 if (AR_SREV_9280_20_OR_LATER(ah)) { 1336 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1337 * frames when constructing CCMP AAD. */ 1338 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1339 0xc7ff); 1340 ah->sw_mgmt_crypto = false; 1341 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1342 /* Disable hardware crypto for management frames */ 1343 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1344 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1345 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1346 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1347 ah->sw_mgmt_crypto = true; 1348 } else 1349 ah->sw_mgmt_crypto = true; 1350 1351 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1352 ath9k_hw_set_delta_slope(ah, chan); 1353 1354 ath9k_hw_spur_mitigate_freq(ah, chan); 1355 ah->eep_ops->set_board_values(ah, chan); 1356 1357 ath9k_hw_set_operating_mode(ah, ah->opmode); 1358 1359 ENABLE_REGWRITE_BUFFER(ah); 1360 1361 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1362 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1363 | macStaId1 1364 | AR_STA_ID1_RTS_USE_DEF 1365 | (ah->config. 1366 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1367 | ah->sta_id1_defaults); 1368 ath_hw_setbssidmask(common); 1369 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1370 ath9k_hw_write_associd(ah); 1371 REG_WRITE(ah, AR_ISR, ~0); 1372 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1373 1374 REGWRITE_BUFFER_FLUSH(ah); 1375 DISABLE_REGWRITE_BUFFER(ah); 1376 1377 r = ath9k_hw_rf_set_freq(ah, chan); 1378 if (r) 1379 return r; 1380 1381 ENABLE_REGWRITE_BUFFER(ah); 1382 1383 for (i = 0; i < AR_NUM_DCU; i++) 1384 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1385 1386 REGWRITE_BUFFER_FLUSH(ah); 1387 DISABLE_REGWRITE_BUFFER(ah); 1388 1389 ah->intr_txqs = 0; 1390 for (i = 0; i < ah->caps.total_queues; i++) 1391 ath9k_hw_resettxqueue(ah, i); 1392 1393 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1394 ath9k_hw_ani_cache_ini_regs(ah); 1395 ath9k_hw_init_qos(ah); 1396 1397 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1398 ath9k_enable_rfkill(ah); 1399 1400 ath9k_hw_init_global_settings(ah); 1401 1402 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1403 ar9002_hw_update_async_fifo(ah); 1404 ar9002_hw_enable_wep_aggregation(ah); 1405 } 1406 1407 REG_WRITE(ah, AR_STA_ID1, 1408 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 1409 1410 ath9k_hw_set_dma(ah); 1411 1412 REG_WRITE(ah, AR_OBS, 8); 1413 1414 if (ah->config.rx_intr_mitigation) { 1415 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1416 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1417 } 1418 1419 if (ah->config.tx_intr_mitigation) { 1420 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1421 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1422 } 1423 1424 ath9k_hw_init_bb(ah, chan); 1425 1426 if (!ath9k_hw_init_cal(ah, chan)) 1427 return -EIO; 1428 1429 ENABLE_REGWRITE_BUFFER(ah); 1430 1431 ath9k_hw_restore_chainmask(ah); 1432 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1433 1434 REGWRITE_BUFFER_FLUSH(ah); 1435 DISABLE_REGWRITE_BUFFER(ah); 1436 1437 /* 1438 * For big endian systems turn on swapping for descriptors 1439 */ 1440 if (AR_SREV_9100(ah)) { 1441 u32 mask; 1442 mask = REG_READ(ah, AR_CFG); 1443 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1444 ath_print(common, ATH_DBG_RESET, 1445 "CFG Byte Swap Set 0x%x\n", mask); 1446 } else { 1447 mask = 1448 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1449 REG_WRITE(ah, AR_CFG, mask); 1450 ath_print(common, ATH_DBG_RESET, 1451 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1452 } 1453 } else { 1454 if (common->bus_ops->ath_bus_type == ATH_USB) { 1455 /* Configure AR9271 target WLAN */ 1456 if (AR_SREV_9271(ah)) 1457 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1458 else 1459 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1460 } 1461 #ifdef __BIG_ENDIAN 1462 else 1463 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1464 #endif 1465 } 1466 1467 if (ah->btcoex_hw.enabled) 1468 ath9k_hw_btcoex_enable(ah); 1469 1470 if (AR_SREV_9300_20_OR_LATER(ah)) 1471 ar9003_hw_bb_watchdog_config(ah); 1472 1473 return 0; 1474 } 1475 EXPORT_SYMBOL(ath9k_hw_reset); 1476 1477 /************************/ 1478 /* Key Cache Management */ 1479 /************************/ 1480 1481 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) 1482 { 1483 u32 keyType; 1484 1485 if (entry >= ah->caps.keycache_size) { 1486 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1487 "keychache entry %u out of range\n", entry); 1488 return false; 1489 } 1490 1491 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 1492 1493 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 1494 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 1495 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 1496 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 1497 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 1498 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1499 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 1500 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 1501 1502 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 1503 u16 micentry = entry + 64; 1504 1505 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); 1506 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 1507 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); 1508 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 1509 1510 } 1511 1512 return true; 1513 } 1514 EXPORT_SYMBOL(ath9k_hw_keyreset); 1515 1516 static bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) 1517 { 1518 u32 macHi, macLo; 1519 u32 unicast_flag = AR_KEYTABLE_VALID; 1520 1521 if (entry >= ah->caps.keycache_size) { 1522 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1523 "keychache entry %u out of range\n", entry); 1524 return false; 1525 } 1526 1527 if (mac != NULL) { 1528 /* 1529 * AR_KEYTABLE_VALID indicates that the address is a unicast 1530 * address, which must match the transmitter address for 1531 * decrypting frames. 1532 * Not setting this bit allows the hardware to use the key 1533 * for multicast frame decryption. 1534 */ 1535 if (mac[0] & 0x01) 1536 unicast_flag = 0; 1537 1538 macHi = (mac[5] << 8) | mac[4]; 1539 macLo = (mac[3] << 24) | 1540 (mac[2] << 16) | 1541 (mac[1] << 8) | 1542 mac[0]; 1543 macLo >>= 1; 1544 macLo |= (macHi & 1) << 31; 1545 macHi >>= 1; 1546 } else { 1547 macLo = macHi = 0; 1548 } 1549 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 1550 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag); 1551 1552 return true; 1553 } 1554 1555 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, 1556 const struct ath9k_keyval *k, 1557 const u8 *mac) 1558 { 1559 const struct ath9k_hw_capabilities *pCap = &ah->caps; 1560 struct ath_common *common = ath9k_hw_common(ah); 1561 u32 key0, key1, key2, key3, key4; 1562 u32 keyType; 1563 1564 if (entry >= pCap->keycache_size) { 1565 ath_print(common, ATH_DBG_FATAL, 1566 "keycache entry %u out of range\n", entry); 1567 return false; 1568 } 1569 1570 switch (k->kv_type) { 1571 case ATH9K_CIPHER_AES_OCB: 1572 keyType = AR_KEYTABLE_TYPE_AES; 1573 break; 1574 case ATH9K_CIPHER_AES_CCM: 1575 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 1576 ath_print(common, ATH_DBG_ANY, 1577 "AES-CCM not supported by mac rev 0x%x\n", 1578 ah->hw_version.macRev); 1579 return false; 1580 } 1581 keyType = AR_KEYTABLE_TYPE_CCM; 1582 break; 1583 case ATH9K_CIPHER_TKIP: 1584 keyType = AR_KEYTABLE_TYPE_TKIP; 1585 if (ATH9K_IS_MIC_ENABLED(ah) 1586 && entry + 64 >= pCap->keycache_size) { 1587 ath_print(common, ATH_DBG_ANY, 1588 "entry %u inappropriate for TKIP\n", entry); 1589 return false; 1590 } 1591 break; 1592 case ATH9K_CIPHER_WEP: 1593 if (k->kv_len < WLAN_KEY_LEN_WEP40) { 1594 ath_print(common, ATH_DBG_ANY, 1595 "WEP key length %u too small\n", k->kv_len); 1596 return false; 1597 } 1598 if (k->kv_len <= WLAN_KEY_LEN_WEP40) 1599 keyType = AR_KEYTABLE_TYPE_40; 1600 else if (k->kv_len <= WLAN_KEY_LEN_WEP104) 1601 keyType = AR_KEYTABLE_TYPE_104; 1602 else 1603 keyType = AR_KEYTABLE_TYPE_128; 1604 break; 1605 case ATH9K_CIPHER_CLR: 1606 keyType = AR_KEYTABLE_TYPE_CLR; 1607 break; 1608 default: 1609 ath_print(common, ATH_DBG_FATAL, 1610 "cipher %u not supported\n", k->kv_type); 1611 return false; 1612 } 1613 1614 key0 = get_unaligned_le32(k->kv_val + 0); 1615 key1 = get_unaligned_le16(k->kv_val + 4); 1616 key2 = get_unaligned_le32(k->kv_val + 6); 1617 key3 = get_unaligned_le16(k->kv_val + 10); 1618 key4 = get_unaligned_le32(k->kv_val + 12); 1619 if (k->kv_len <= WLAN_KEY_LEN_WEP104) 1620 key4 &= 0xff; 1621 1622 /* 1623 * Note: Key cache registers access special memory area that requires 1624 * two 32-bit writes to actually update the values in the internal 1625 * memory. Consequently, the exact order and pairs used here must be 1626 * maintained. 1627 */ 1628 1629 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 1630 u16 micentry = entry + 64; 1631 1632 /* 1633 * Write inverted key[47:0] first to avoid Michael MIC errors 1634 * on frames that could be sent or received at the same time. 1635 * The correct key will be written in the end once everything 1636 * else is ready. 1637 */ 1638 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); 1639 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); 1640 1641 /* Write key[95:48] */ 1642 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 1643 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 1644 1645 /* Write key[127:96] and key type */ 1646 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 1647 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 1648 1649 /* Write MAC address for the entry */ 1650 (void) ath9k_hw_keysetmac(ah, entry, mac); 1651 1652 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { 1653 /* 1654 * TKIP uses two key cache entries: 1655 * Michael MIC TX/RX keys in the same key cache entry 1656 * (idx = main index + 64): 1657 * key0 [31:0] = RX key [31:0] 1658 * key1 [15:0] = TX key [31:16] 1659 * key1 [31:16] = reserved 1660 * key2 [31:0] = RX key [63:32] 1661 * key3 [15:0] = TX key [15:0] 1662 * key3 [31:16] = reserved 1663 * key4 [31:0] = TX key [63:32] 1664 */ 1665 u32 mic0, mic1, mic2, mic3, mic4; 1666 1667 mic0 = get_unaligned_le32(k->kv_mic + 0); 1668 mic2 = get_unaligned_le32(k->kv_mic + 4); 1669 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; 1670 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; 1671 mic4 = get_unaligned_le32(k->kv_txmic + 4); 1672 1673 /* Write RX[31:0] and TX[31:16] */ 1674 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 1675 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); 1676 1677 /* Write RX[63:32] and TX[15:0] */ 1678 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 1679 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); 1680 1681 /* Write TX[63:32] and keyType(reserved) */ 1682 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); 1683 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 1684 AR_KEYTABLE_TYPE_CLR); 1685 1686 } else { 1687 /* 1688 * TKIP uses four key cache entries (two for group 1689 * keys): 1690 * Michael MIC TX/RX keys are in different key cache 1691 * entries (idx = main index + 64 for TX and 1692 * main index + 32 + 96 for RX): 1693 * key0 [31:0] = TX/RX MIC key [31:0] 1694 * key1 [31:0] = reserved 1695 * key2 [31:0] = TX/RX MIC key [63:32] 1696 * key3 [31:0] = reserved 1697 * key4 [31:0] = reserved 1698 * 1699 * Upper layer code will call this function separately 1700 * for TX and RX keys when these registers offsets are 1701 * used. 1702 */ 1703 u32 mic0, mic2; 1704 1705 mic0 = get_unaligned_le32(k->kv_mic + 0); 1706 mic2 = get_unaligned_le32(k->kv_mic + 4); 1707 1708 /* Write MIC key[31:0] */ 1709 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 1710 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 1711 1712 /* Write MIC key[63:32] */ 1713 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 1714 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 1715 1716 /* Write TX[63:32] and keyType(reserved) */ 1717 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); 1718 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 1719 AR_KEYTABLE_TYPE_CLR); 1720 } 1721 1722 /* MAC address registers are reserved for the MIC entry */ 1723 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); 1724 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); 1725 1726 /* 1727 * Write the correct (un-inverted) key[47:0] last to enable 1728 * TKIP now that all other registers are set with correct 1729 * values. 1730 */ 1731 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 1732 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 1733 } else { 1734 /* Write key[47:0] */ 1735 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 1736 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 1737 1738 /* Write key[95:48] */ 1739 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 1740 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 1741 1742 /* Write key[127:96] and key type */ 1743 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 1744 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 1745 1746 /* Write MAC address for the entry */ 1747 (void) ath9k_hw_keysetmac(ah, entry, mac); 1748 } 1749 1750 return true; 1751 } 1752 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); 1753 1754 /******************************/ 1755 /* Power Management (Chipset) */ 1756 /******************************/ 1757 1758 /* 1759 * Notify Power Mgt is disabled in self-generated frames. 1760 * If requested, force chip to sleep. 1761 */ 1762 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1763 { 1764 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1765 if (setChip) { 1766 /* 1767 * Clear the RTC force wake bit to allow the 1768 * mac to go to sleep. 1769 */ 1770 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1771 AR_RTC_FORCE_WAKE_EN); 1772 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1773 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1774 1775 /* Shutdown chip. Active low */ 1776 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1777 REG_CLR_BIT(ah, (AR_RTC_RESET), 1778 AR_RTC_RESET_EN); 1779 } 1780 1781 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1782 if (AR_SREV_9300_20_OR_LATER(ah)) 1783 REG_WRITE(ah, AR_WA, 1784 ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1785 } 1786 1787 /* 1788 * Notify Power Management is enabled in self-generating 1789 * frames. If request, set power mode of chip to 1790 * auto/normal. Duration in units of 128us (1/8 TU). 1791 */ 1792 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1793 { 1794 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1795 if (setChip) { 1796 struct ath9k_hw_capabilities *pCap = &ah->caps; 1797 1798 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1799 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1800 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1801 AR_RTC_FORCE_WAKE_ON_INT); 1802 } else { 1803 /* 1804 * Clear the RTC force wake bit to allow the 1805 * mac to go to sleep. 1806 */ 1807 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1808 AR_RTC_FORCE_WAKE_EN); 1809 } 1810 } 1811 1812 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1813 if (AR_SREV_9300_20_OR_LATER(ah)) 1814 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1815 } 1816 1817 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1818 { 1819 u32 val; 1820 int i; 1821 1822 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1823 if (AR_SREV_9300_20_OR_LATER(ah)) { 1824 REG_WRITE(ah, AR_WA, ah->WARegVal); 1825 udelay(10); 1826 } 1827 1828 if (setChip) { 1829 if ((REG_READ(ah, AR_RTC_STATUS) & 1830 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1831 if (ath9k_hw_set_reset_reg(ah, 1832 ATH9K_RESET_POWER_ON) != true) { 1833 return false; 1834 } 1835 if (!AR_SREV_9300_20_OR_LATER(ah)) 1836 ath9k_hw_init_pll(ah, NULL); 1837 } 1838 if (AR_SREV_9100(ah)) 1839 REG_SET_BIT(ah, AR_RTC_RESET, 1840 AR_RTC_RESET_EN); 1841 1842 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1843 AR_RTC_FORCE_WAKE_EN); 1844 udelay(50); 1845 1846 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1847 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1848 if (val == AR_RTC_STATUS_ON) 1849 break; 1850 udelay(50); 1851 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1852 AR_RTC_FORCE_WAKE_EN); 1853 } 1854 if (i == 0) { 1855 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1856 "Failed to wakeup in %uus\n", 1857 POWER_UP_TIME / 20); 1858 return false; 1859 } 1860 } 1861 1862 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1863 1864 return true; 1865 } 1866 1867 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 1868 { 1869 struct ath_common *common = ath9k_hw_common(ah); 1870 int status = true, setChip = true; 1871 static const char *modes[] = { 1872 "AWAKE", 1873 "FULL-SLEEP", 1874 "NETWORK SLEEP", 1875 "UNDEFINED" 1876 }; 1877 1878 if (ah->power_mode == mode) 1879 return status; 1880 1881 ath_print(common, ATH_DBG_RESET, "%s -> %s\n", 1882 modes[ah->power_mode], modes[mode]); 1883 1884 switch (mode) { 1885 case ATH9K_PM_AWAKE: 1886 status = ath9k_hw_set_power_awake(ah, setChip); 1887 break; 1888 case ATH9K_PM_FULL_SLEEP: 1889 ath9k_set_power_sleep(ah, setChip); 1890 ah->chip_fullsleep = true; 1891 break; 1892 case ATH9K_PM_NETWORK_SLEEP: 1893 ath9k_set_power_network_sleep(ah, setChip); 1894 break; 1895 default: 1896 ath_print(common, ATH_DBG_FATAL, 1897 "Unknown power mode %u\n", mode); 1898 return false; 1899 } 1900 ah->power_mode = mode; 1901 1902 return status; 1903 } 1904 EXPORT_SYMBOL(ath9k_hw_setpower); 1905 1906 /*******************/ 1907 /* Beacon Handling */ 1908 /*******************/ 1909 1910 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 1911 { 1912 int flags = 0; 1913 1914 ah->beacon_interval = beacon_period; 1915 1916 ENABLE_REGWRITE_BUFFER(ah); 1917 1918 switch (ah->opmode) { 1919 case NL80211_IFTYPE_STATION: 1920 case NL80211_IFTYPE_MONITOR: 1921 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1922 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); 1923 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); 1924 flags |= AR_TBTT_TIMER_EN; 1925 break; 1926 case NL80211_IFTYPE_ADHOC: 1927 case NL80211_IFTYPE_MESH_POINT: 1928 REG_SET_BIT(ah, AR_TXCFG, 1929 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1930 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 1931 TU_TO_USEC(next_beacon + 1932 (ah->atim_window ? ah-> 1933 atim_window : 1))); 1934 flags |= AR_NDP_TIMER_EN; 1935 case NL80211_IFTYPE_AP: 1936 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1937 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 1938 TU_TO_USEC(next_beacon - 1939 ah->config. 1940 dma_beacon_response_time)); 1941 REG_WRITE(ah, AR_NEXT_SWBA, 1942 TU_TO_USEC(next_beacon - 1943 ah->config. 1944 sw_beacon_response_time)); 1945 flags |= 1946 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1947 break; 1948 default: 1949 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, 1950 "%s: unsupported opmode: %d\n", 1951 __func__, ah->opmode); 1952 return; 1953 break; 1954 } 1955 1956 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1957 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1958 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1959 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1960 1961 REGWRITE_BUFFER_FLUSH(ah); 1962 DISABLE_REGWRITE_BUFFER(ah); 1963 1964 beacon_period &= ~ATH9K_BEACON_ENA; 1965 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 1966 ath9k_hw_reset_tsf(ah); 1967 } 1968 1969 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1970 } 1971 EXPORT_SYMBOL(ath9k_hw_beaconinit); 1972 1973 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1974 const struct ath9k_beacon_state *bs) 1975 { 1976 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 1977 struct ath9k_hw_capabilities *pCap = &ah->caps; 1978 struct ath_common *common = ath9k_hw_common(ah); 1979 1980 ENABLE_REGWRITE_BUFFER(ah); 1981 1982 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1983 1984 REG_WRITE(ah, AR_BEACON_PERIOD, 1985 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1986 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1987 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1988 1989 REGWRITE_BUFFER_FLUSH(ah); 1990 DISABLE_REGWRITE_BUFFER(ah); 1991 1992 REG_RMW_FIELD(ah, AR_RSSI_THR, 1993 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1994 1995 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 1996 1997 if (bs->bs_sleepduration > beaconintval) 1998 beaconintval = bs->bs_sleepduration; 1999 2000 dtimperiod = bs->bs_dtimperiod; 2001 if (bs->bs_sleepduration > dtimperiod) 2002 dtimperiod = bs->bs_sleepduration; 2003 2004 if (beaconintval == dtimperiod) 2005 nextTbtt = bs->bs_nextdtim; 2006 else 2007 nextTbtt = bs->bs_nexttbtt; 2008 2009 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2010 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 2011 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 2012 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 2013 2014 ENABLE_REGWRITE_BUFFER(ah); 2015 2016 REG_WRITE(ah, AR_NEXT_DTIM, 2017 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2018 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2019 2020 REG_WRITE(ah, AR_SLEEP1, 2021 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2022 | AR_SLEEP1_ASSUME_DTIM); 2023 2024 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2025 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2026 else 2027 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2028 2029 REG_WRITE(ah, AR_SLEEP2, 2030 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2031 2032 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2033 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2034 2035 REGWRITE_BUFFER_FLUSH(ah); 2036 DISABLE_REGWRITE_BUFFER(ah); 2037 2038 REG_SET_BIT(ah, AR_TIMER_MODE, 2039 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2040 AR_DTIM_TIMER_EN); 2041 2042 /* TSF Out of Range Threshold */ 2043 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2044 } 2045 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2046 2047 /*******************/ 2048 /* HW Capabilities */ 2049 /*******************/ 2050 2051 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2052 { 2053 struct ath9k_hw_capabilities *pCap = &ah->caps; 2054 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2055 struct ath_common *common = ath9k_hw_common(ah); 2056 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 2057 2058 u16 capField = 0, eeval; 2059 u8 ant_div_ctl1; 2060 2061 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2062 regulatory->current_rd = eeval; 2063 2064 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 2065 if (AR_SREV_9285_10_OR_LATER(ah)) 2066 eeval |= AR9285_RDEXT_DEFAULT; 2067 regulatory->current_rd_ext = eeval; 2068 2069 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); 2070 2071 if (ah->opmode != NL80211_IFTYPE_AP && 2072 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2073 if (regulatory->current_rd == 0x64 || 2074 regulatory->current_rd == 0x65) 2075 regulatory->current_rd += 5; 2076 else if (regulatory->current_rd == 0x41) 2077 regulatory->current_rd = 0x43; 2078 ath_print(common, ATH_DBG_REGULATORY, 2079 "regdomain mapped to 0x%x\n", regulatory->current_rd); 2080 } 2081 2082 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2083 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2084 ath_print(common, ATH_DBG_FATAL, 2085 "no band has been marked as supported in EEPROM.\n"); 2086 return -EINVAL; 2087 } 2088 2089 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); 2090 2091 if (eeval & AR5416_OPFLAGS_11A) { 2092 set_bit(ATH9K_MODE_11A, pCap->wireless_modes); 2093 if (ah->config.ht_enable) { 2094 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) 2095 set_bit(ATH9K_MODE_11NA_HT20, 2096 pCap->wireless_modes); 2097 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { 2098 set_bit(ATH9K_MODE_11NA_HT40PLUS, 2099 pCap->wireless_modes); 2100 set_bit(ATH9K_MODE_11NA_HT40MINUS, 2101 pCap->wireless_modes); 2102 } 2103 } 2104 } 2105 2106 if (eeval & AR5416_OPFLAGS_11G) { 2107 set_bit(ATH9K_MODE_11G, pCap->wireless_modes); 2108 if (ah->config.ht_enable) { 2109 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) 2110 set_bit(ATH9K_MODE_11NG_HT20, 2111 pCap->wireless_modes); 2112 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { 2113 set_bit(ATH9K_MODE_11NG_HT40PLUS, 2114 pCap->wireless_modes); 2115 set_bit(ATH9K_MODE_11NG_HT40MINUS, 2116 pCap->wireless_modes); 2117 } 2118 } 2119 } 2120 2121 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2122 /* 2123 * For AR9271 we will temporarilly uses the rx chainmax as read from 2124 * the EEPROM. 2125 */ 2126 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2127 !(eeval & AR5416_OPFLAGS_11A) && 2128 !(AR_SREV_9271(ah))) 2129 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2130 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2131 else 2132 /* Use rx_chainmask from EEPROM. */ 2133 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2134 2135 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) 2136 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2137 2138 pCap->low_2ghz_chan = 2312; 2139 pCap->high_2ghz_chan = 2732; 2140 2141 pCap->low_5ghz_chan = 4920; 2142 pCap->high_5ghz_chan = 6100; 2143 2144 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; 2145 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; 2146 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; 2147 2148 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; 2149 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; 2150 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; 2151 2152 if (ah->config.ht_enable) 2153 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2154 else 2155 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2156 2157 pCap->hw_caps |= ATH9K_HW_CAP_GTT; 2158 pCap->hw_caps |= ATH9K_HW_CAP_VEOL; 2159 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; 2160 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; 2161 2162 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 2163 pCap->total_queues = 2164 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 2165 else 2166 pCap->total_queues = ATH9K_NUM_TX_QUEUES; 2167 2168 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 2169 pCap->keycache_size = 2170 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 2171 else 2172 pCap->keycache_size = AR_KEYTABLE_SIZE; 2173 2174 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; 2175 2176 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 2177 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; 2178 else 2179 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 2180 2181 if (AR_SREV_9271(ah)) 2182 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2183 else if (AR_DEVID_7010(ah)) 2184 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2185 else if (AR_SREV_9285_10_OR_LATER(ah)) 2186 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2187 else if (AR_SREV_9280_10_OR_LATER(ah)) 2188 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2189 else 2190 pCap->num_gpio_pins = AR_NUM_GPIO; 2191 2192 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 2193 pCap->hw_caps |= ATH9K_HW_CAP_CST; 2194 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2195 } else { 2196 pCap->rts_aggr_limit = (8 * 1024); 2197 } 2198 2199 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 2200 2201 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2202 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2203 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2204 ah->rfkill_gpio = 2205 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2206 ah->rfkill_polarity = 2207 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2208 2209 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2210 } 2211 #endif 2212 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2213 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2214 else 2215 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2216 2217 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2218 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2219 else 2220 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2221 2222 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2223 pCap->reg_cap = 2224 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2225 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2226 AR_EEPROM_EEREGCAP_EN_KK_U2 | 2227 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2228 } else { 2229 pCap->reg_cap = 2230 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2231 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2232 } 2233 2234 /* Advertise midband for AR5416 with FCC midband set in eeprom */ 2235 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && 2236 AR_SREV_5416(ah)) 2237 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2238 2239 pCap->num_antcfg_5ghz = 2240 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); 2241 pCap->num_antcfg_2ghz = 2242 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); 2243 2244 if (AR_SREV_9280_10_OR_LATER(ah) && 2245 ath9k_hw_btcoex_supported(ah)) { 2246 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 2247 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 2248 2249 if (AR_SREV_9285(ah)) { 2250 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2251 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; 2252 } else { 2253 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 2254 } 2255 } else { 2256 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2257 } 2258 2259 if (AR_SREV_9300_20_OR_LATER(ah)) { 2260 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC | 2261 ATH9K_HW_CAP_FASTCLOCK; 2262 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2263 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2264 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2265 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2266 pCap->txs_len = sizeof(struct ar9003_txs); 2267 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2268 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2269 } else { 2270 pCap->tx_desc_len = sizeof(struct ath_desc); 2271 if (AR_SREV_9280_20(ah) && 2272 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= 2273 AR5416_EEP_MINOR_VER_16) || 2274 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) 2275 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2276 } 2277 2278 if (AR_SREV_9300_20_OR_LATER(ah)) 2279 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2280 2281 if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah)) 2282 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2283 2284 if (AR_SREV_9285(ah)) 2285 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2286 ant_div_ctl1 = 2287 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2288 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) 2289 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2290 } 2291 2292 return 0; 2293 } 2294 2295 /****************************/ 2296 /* GPIO / RFKILL / Antennae */ 2297 /****************************/ 2298 2299 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2300 u32 gpio, u32 type) 2301 { 2302 int addr; 2303 u32 gpio_shift, tmp; 2304 2305 if (gpio > 11) 2306 addr = AR_GPIO_OUTPUT_MUX3; 2307 else if (gpio > 5) 2308 addr = AR_GPIO_OUTPUT_MUX2; 2309 else 2310 addr = AR_GPIO_OUTPUT_MUX1; 2311 2312 gpio_shift = (gpio % 6) * 5; 2313 2314 if (AR_SREV_9280_20_OR_LATER(ah) 2315 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2316 REG_RMW(ah, addr, (type << gpio_shift), 2317 (0x1f << gpio_shift)); 2318 } else { 2319 tmp = REG_READ(ah, addr); 2320 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2321 tmp &= ~(0x1f << gpio_shift); 2322 tmp |= (type << gpio_shift); 2323 REG_WRITE(ah, addr, tmp); 2324 } 2325 } 2326 2327 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2328 { 2329 u32 gpio_shift; 2330 2331 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2332 2333 if (AR_DEVID_7010(ah)) { 2334 gpio_shift = gpio; 2335 REG_RMW(ah, AR7010_GPIO_OE, 2336 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2337 (AR7010_GPIO_OE_MASK << gpio_shift)); 2338 return; 2339 } 2340 2341 gpio_shift = gpio << 1; 2342 REG_RMW(ah, 2343 AR_GPIO_OE_OUT, 2344 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2345 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2346 } 2347 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2348 2349 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2350 { 2351 #define MS_REG_READ(x, y) \ 2352 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2353 2354 if (gpio >= ah->caps.num_gpio_pins) 2355 return 0xffffffff; 2356 2357 if (AR_DEVID_7010(ah)) { 2358 u32 val; 2359 val = REG_READ(ah, AR7010_GPIO_IN); 2360 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2361 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2362 return MS_REG_READ(AR9300, gpio) != 0; 2363 else if (AR_SREV_9271(ah)) 2364 return MS_REG_READ(AR9271, gpio) != 0; 2365 else if (AR_SREV_9287_10_OR_LATER(ah)) 2366 return MS_REG_READ(AR9287, gpio) != 0; 2367 else if (AR_SREV_9285_10_OR_LATER(ah)) 2368 return MS_REG_READ(AR9285, gpio) != 0; 2369 else if (AR_SREV_9280_10_OR_LATER(ah)) 2370 return MS_REG_READ(AR928X, gpio) != 0; 2371 else 2372 return MS_REG_READ(AR, gpio) != 0; 2373 } 2374 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2375 2376 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2377 u32 ah_signal_type) 2378 { 2379 u32 gpio_shift; 2380 2381 if (AR_DEVID_7010(ah)) { 2382 gpio_shift = gpio; 2383 REG_RMW(ah, AR7010_GPIO_OE, 2384 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2385 (AR7010_GPIO_OE_MASK << gpio_shift)); 2386 return; 2387 } 2388 2389 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2390 gpio_shift = 2 * gpio; 2391 REG_RMW(ah, 2392 AR_GPIO_OE_OUT, 2393 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2394 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2395 } 2396 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2397 2398 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2399 { 2400 if (AR_DEVID_7010(ah)) { 2401 val = val ? 0 : 1; 2402 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2403 AR_GPIO_BIT(gpio)); 2404 return; 2405 } 2406 2407 if (AR_SREV_9271(ah)) 2408 val = ~val; 2409 2410 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2411 AR_GPIO_BIT(gpio)); 2412 } 2413 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2414 2415 u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2416 { 2417 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2418 } 2419 EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2420 2421 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2422 { 2423 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2424 } 2425 EXPORT_SYMBOL(ath9k_hw_setantenna); 2426 2427 /*********************/ 2428 /* General Operation */ 2429 /*********************/ 2430 2431 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2432 { 2433 u32 bits = REG_READ(ah, AR_RX_FILTER); 2434 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2435 2436 if (phybits & AR_PHY_ERR_RADAR) 2437 bits |= ATH9K_RX_FILTER_PHYRADAR; 2438 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2439 bits |= ATH9K_RX_FILTER_PHYERR; 2440 2441 return bits; 2442 } 2443 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2444 2445 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2446 { 2447 u32 phybits; 2448 2449 ENABLE_REGWRITE_BUFFER(ah); 2450 2451 REG_WRITE(ah, AR_RX_FILTER, bits); 2452 2453 phybits = 0; 2454 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2455 phybits |= AR_PHY_ERR_RADAR; 2456 if (bits & ATH9K_RX_FILTER_PHYERR) 2457 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2458 REG_WRITE(ah, AR_PHY_ERR, phybits); 2459 2460 if (phybits) 2461 REG_WRITE(ah, AR_RXCFG, 2462 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 2463 else 2464 REG_WRITE(ah, AR_RXCFG, 2465 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 2466 2467 REGWRITE_BUFFER_FLUSH(ah); 2468 DISABLE_REGWRITE_BUFFER(ah); 2469 } 2470 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2471 2472 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2473 { 2474 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2475 return false; 2476 2477 ath9k_hw_init_pll(ah, NULL); 2478 return true; 2479 } 2480 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2481 2482 bool ath9k_hw_disable(struct ath_hw *ah) 2483 { 2484 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2485 return false; 2486 2487 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2488 return false; 2489 2490 ath9k_hw_init_pll(ah, NULL); 2491 return true; 2492 } 2493 EXPORT_SYMBOL(ath9k_hw_disable); 2494 2495 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 2496 { 2497 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2498 struct ath9k_channel *chan = ah->curchan; 2499 struct ieee80211_channel *channel = chan->chan; 2500 2501 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 2502 2503 ah->eep_ops->set_txpower(ah, chan, 2504 ath9k_regd_get_ctl(regulatory, chan), 2505 channel->max_antenna_gain * 2, 2506 channel->max_power * 2, 2507 min((u32) MAX_RATE_POWER, 2508 (u32) regulatory->power_limit)); 2509 } 2510 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2511 2512 void ath9k_hw_setopmode(struct ath_hw *ah) 2513 { 2514 ath9k_hw_set_operating_mode(ah, ah->opmode); 2515 } 2516 EXPORT_SYMBOL(ath9k_hw_setopmode); 2517 2518 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2519 { 2520 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2521 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2522 } 2523 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2524 2525 void ath9k_hw_write_associd(struct ath_hw *ah) 2526 { 2527 struct ath_common *common = ath9k_hw_common(ah); 2528 2529 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2530 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2531 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2532 } 2533 EXPORT_SYMBOL(ath9k_hw_write_associd); 2534 2535 #define ATH9K_MAX_TSF_READ 10 2536 2537 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2538 { 2539 u32 tsf_lower, tsf_upper1, tsf_upper2; 2540 int i; 2541 2542 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2543 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2544 tsf_lower = REG_READ(ah, AR_TSF_L32); 2545 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2546 if (tsf_upper2 == tsf_upper1) 2547 break; 2548 tsf_upper1 = tsf_upper2; 2549 } 2550 2551 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2552 2553 return (((u64)tsf_upper1 << 32) | tsf_lower); 2554 } 2555 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2556 2557 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2558 { 2559 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2560 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2561 } 2562 EXPORT_SYMBOL(ath9k_hw_settsf64); 2563 2564 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2565 { 2566 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2567 AH_TSF_WRITE_TIMEOUT)) 2568 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 2569 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2570 2571 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2572 } 2573 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2574 2575 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2576 { 2577 if (setting) 2578 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2579 else 2580 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2581 } 2582 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2583 2584 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2585 { 2586 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2587 u32 macmode; 2588 2589 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2590 macmode = AR_2040_JOINED_RX_CLEAR; 2591 else 2592 macmode = 0; 2593 2594 REG_WRITE(ah, AR_2040_MODE, macmode); 2595 } 2596 2597 /* HW Generic timers configuration */ 2598 2599 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2600 { 2601 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2602 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2603 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2604 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2605 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2606 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2607 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2608 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2609 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2610 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2611 AR_NDP2_TIMER_MODE, 0x0002}, 2612 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2613 AR_NDP2_TIMER_MODE, 0x0004}, 2614 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2615 AR_NDP2_TIMER_MODE, 0x0008}, 2616 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2617 AR_NDP2_TIMER_MODE, 0x0010}, 2618 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2619 AR_NDP2_TIMER_MODE, 0x0020}, 2620 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2621 AR_NDP2_TIMER_MODE, 0x0040}, 2622 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2623 AR_NDP2_TIMER_MODE, 0x0080} 2624 }; 2625 2626 /* HW generic timer primitives */ 2627 2628 /* compute and clear index of rightmost 1 */ 2629 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2630 { 2631 u32 b; 2632 2633 b = *mask; 2634 b &= (0-b); 2635 *mask &= ~b; 2636 b *= debruijn32; 2637 b >>= 27; 2638 2639 return timer_table->gen_timer_index[b]; 2640 } 2641 2642 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2643 { 2644 return REG_READ(ah, AR_TSF_L32); 2645 } 2646 EXPORT_SYMBOL(ath9k_hw_gettsf32); 2647 2648 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2649 void (*trigger)(void *), 2650 void (*overflow)(void *), 2651 void *arg, 2652 u8 timer_index) 2653 { 2654 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2655 struct ath_gen_timer *timer; 2656 2657 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2658 2659 if (timer == NULL) { 2660 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2661 "Failed to allocate memory" 2662 "for hw timer[%d]\n", timer_index); 2663 return NULL; 2664 } 2665 2666 /* allocate a hardware generic timer slot */ 2667 timer_table->timers[timer_index] = timer; 2668 timer->index = timer_index; 2669 timer->trigger = trigger; 2670 timer->overflow = overflow; 2671 timer->arg = arg; 2672 2673 return timer; 2674 } 2675 EXPORT_SYMBOL(ath_gen_timer_alloc); 2676 2677 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2678 struct ath_gen_timer *timer, 2679 u32 timer_next, 2680 u32 timer_period) 2681 { 2682 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2683 u32 tsf; 2684 2685 BUG_ON(!timer_period); 2686 2687 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2688 2689 tsf = ath9k_hw_gettsf32(ah); 2690 2691 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2692 "curent tsf %x period %x" 2693 "timer_next %x\n", tsf, timer_period, timer_next); 2694 2695 /* 2696 * Pull timer_next forward if the current TSF already passed it 2697 * because of software latency 2698 */ 2699 if (timer_next < tsf) 2700 timer_next = tsf + timer_period; 2701 2702 /* 2703 * Program generic timer registers 2704 */ 2705 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2706 timer_next); 2707 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2708 timer_period); 2709 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2710 gen_tmr_configuration[timer->index].mode_mask); 2711 2712 /* Enable both trigger and thresh interrupt masks */ 2713 REG_SET_BIT(ah, AR_IMR_S5, 2714 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2715 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2716 } 2717 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2718 2719 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2720 { 2721 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2722 2723 if ((timer->index < AR_FIRST_NDP_TIMER) || 2724 (timer->index >= ATH_MAX_GEN_TIMER)) { 2725 return; 2726 } 2727 2728 /* Clear generic timer enable bits. */ 2729 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2730 gen_tmr_configuration[timer->index].mode_mask); 2731 2732 /* Disable both trigger and thresh interrupt masks */ 2733 REG_CLR_BIT(ah, AR_IMR_S5, 2734 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2735 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2736 2737 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2738 } 2739 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2740 2741 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2742 { 2743 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2744 2745 /* free the hardware generic timer slot */ 2746 timer_table->timers[timer->index] = NULL; 2747 kfree(timer); 2748 } 2749 EXPORT_SYMBOL(ath_gen_timer_free); 2750 2751 /* 2752 * Generic Timer Interrupts handling 2753 */ 2754 void ath_gen_timer_isr(struct ath_hw *ah) 2755 { 2756 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2757 struct ath_gen_timer *timer; 2758 struct ath_common *common = ath9k_hw_common(ah); 2759 u32 trigger_mask, thresh_mask, index; 2760 2761 /* get hardware generic timer interrupt status */ 2762 trigger_mask = ah->intr_gen_timer_trigger; 2763 thresh_mask = ah->intr_gen_timer_thresh; 2764 trigger_mask &= timer_table->timer_mask.val; 2765 thresh_mask &= timer_table->timer_mask.val; 2766 2767 trigger_mask &= ~thresh_mask; 2768 2769 while (thresh_mask) { 2770 index = rightmost_index(timer_table, &thresh_mask); 2771 timer = timer_table->timers[index]; 2772 BUG_ON(!timer); 2773 ath_print(common, ATH_DBG_HWTIMER, 2774 "TSF overflow for Gen timer %d\n", index); 2775 timer->overflow(timer->arg); 2776 } 2777 2778 while (trigger_mask) { 2779 index = rightmost_index(timer_table, &trigger_mask); 2780 timer = timer_table->timers[index]; 2781 BUG_ON(!timer); 2782 ath_print(common, ATH_DBG_HWTIMER, 2783 "Gen timer[%d] trigger\n", index); 2784 timer->trigger(timer->arg); 2785 } 2786 } 2787 EXPORT_SYMBOL(ath_gen_timer_isr); 2788 2789 /********/ 2790 /* HTC */ 2791 /********/ 2792 2793 void ath9k_hw_htc_resetinit(struct ath_hw *ah) 2794 { 2795 ah->htc_reset_init = true; 2796 } 2797 EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 2798 2799 static struct { 2800 u32 version; 2801 const char * name; 2802 } ath_mac_bb_names[] = { 2803 /* Devices with external radios */ 2804 { AR_SREV_VERSION_5416_PCI, "5416" }, 2805 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2806 { AR_SREV_VERSION_9100, "9100" }, 2807 { AR_SREV_VERSION_9160, "9160" }, 2808 /* Single-chip solutions */ 2809 { AR_SREV_VERSION_9280, "9280" }, 2810 { AR_SREV_VERSION_9285, "9285" }, 2811 { AR_SREV_VERSION_9287, "9287" }, 2812 { AR_SREV_VERSION_9271, "9271" }, 2813 { AR_SREV_VERSION_9300, "9300" }, 2814 }; 2815 2816 /* For devices with external radios */ 2817 static struct { 2818 u16 version; 2819 const char * name; 2820 } ath_rf_names[] = { 2821 { 0, "5133" }, 2822 { AR_RAD5133_SREV_MAJOR, "5133" }, 2823 { AR_RAD5122_SREV_MAJOR, "5122" }, 2824 { AR_RAD2133_SREV_MAJOR, "2133" }, 2825 { AR_RAD2122_SREV_MAJOR, "2122" } 2826 }; 2827 2828 /* 2829 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2830 */ 2831 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 2832 { 2833 int i; 2834 2835 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 2836 if (ath_mac_bb_names[i].version == mac_bb_version) { 2837 return ath_mac_bb_names[i].name; 2838 } 2839 } 2840 2841 return "????"; 2842 } 2843 2844 /* 2845 * Return the RF name. "????" is returned if the RF is unknown. 2846 * Used for devices with external radios. 2847 */ 2848 static const char *ath9k_hw_rf_name(u16 rf_version) 2849 { 2850 int i; 2851 2852 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 2853 if (ath_rf_names[i].version == rf_version) { 2854 return ath_rf_names[i].name; 2855 } 2856 } 2857 2858 return "????"; 2859 } 2860 2861 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 2862 { 2863 int used; 2864 2865 /* chipsets >= AR9280 are single-chip */ 2866 if (AR_SREV_9280_10_OR_LATER(ah)) { 2867 used = snprintf(hw_name, len, 2868 "Atheros AR%s Rev:%x", 2869 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2870 ah->hw_version.macRev); 2871 } 2872 else { 2873 used = snprintf(hw_name, len, 2874 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 2875 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2876 ah->hw_version.macRev, 2877 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 2878 AR_RADIO_SREV_MAJOR)), 2879 ah->hw_version.phyRev); 2880 } 2881 2882 hw_name[used] = '\0'; 2883 } 2884 EXPORT_SYMBOL(ath9k_hw_name); 2885