1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/module.h> 20 #include <asm/unaligned.h> 21 22 #include "hw.h" 23 #include "hw-ops.h" 24 #include "rc.h" 25 #include "ar9003_mac.h" 26 #include "ar9003_mci.h" 27 #include "ar9003_phy.h" 28 #include "debug.h" 29 #include "ath9k.h" 30 31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 32 33 MODULE_AUTHOR("Atheros Communications"); 34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 36 MODULE_LICENSE("Dual BSD/GPL"); 37 38 static int __init ath9k_init(void) 39 { 40 return 0; 41 } 42 module_init(ath9k_init); 43 44 static void __exit ath9k_exit(void) 45 { 46 return; 47 } 48 module_exit(ath9k_exit); 49 50 /* Private hardware callbacks */ 51 52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 53 { 54 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 55 } 56 57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 58 struct ath9k_channel *chan) 59 { 60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 61 } 62 63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 64 { 65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 66 return; 67 68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 69 } 70 71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 72 { 73 /* You will not have this callback if using the old ANI */ 74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 75 return; 76 77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 78 } 79 80 /********************/ 81 /* Helper Functions */ 82 /********************/ 83 84 #ifdef CONFIG_ATH9K_DEBUGFS 85 86 void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause) 87 { 88 struct ath_softc *sc = common->priv; 89 if (sync_cause) 90 sc->debug.stats.istats.sync_cause_all++; 91 if (sync_cause & AR_INTR_SYNC_RTC_IRQ) 92 sc->debug.stats.istats.sync_rtc_irq++; 93 if (sync_cause & AR_INTR_SYNC_MAC_IRQ) 94 sc->debug.stats.istats.sync_mac_irq++; 95 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS) 96 sc->debug.stats.istats.eeprom_illegal_access++; 97 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT) 98 sc->debug.stats.istats.apb_timeout++; 99 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT) 100 sc->debug.stats.istats.pci_mode_conflict++; 101 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) 102 sc->debug.stats.istats.host1_fatal++; 103 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) 104 sc->debug.stats.istats.host1_perr++; 105 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR) 106 sc->debug.stats.istats.trcv_fifo_perr++; 107 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP) 108 sc->debug.stats.istats.radm_cpl_ep++; 109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT) 110 sc->debug.stats.istats.radm_cpl_dllp_abort++; 111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT) 112 sc->debug.stats.istats.radm_cpl_tlp_abort++; 113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR) 114 sc->debug.stats.istats.radm_cpl_ecrc_err++; 115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) 116 sc->debug.stats.istats.radm_cpl_timeout++; 117 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) 118 sc->debug.stats.istats.local_timeout++; 119 if (sync_cause & AR_INTR_SYNC_PM_ACCESS) 120 sc->debug.stats.istats.pm_access++; 121 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE) 122 sc->debug.stats.istats.mac_awake++; 123 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP) 124 sc->debug.stats.istats.mac_asleep++; 125 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS) 126 sc->debug.stats.istats.mac_sleep_access++; 127 } 128 #endif 129 130 131 static void ath9k_hw_set_clockrate(struct ath_hw *ah) 132 { 133 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 134 struct ath_common *common = ath9k_hw_common(ah); 135 unsigned int clockrate; 136 137 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ 138 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) 139 clockrate = 117; 140 else if (!ah->curchan) /* should really check for CCK instead */ 141 clockrate = ATH9K_CLOCK_RATE_CCK; 142 else if (conf->chandef.chan->band == IEEE80211_BAND_2GHZ) 143 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 144 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 145 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 146 else 147 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; 148 149 if (conf_is_ht40(conf)) 150 clockrate *= 2; 151 152 if (ah->curchan) { 153 if (IS_CHAN_HALF_RATE(ah->curchan)) 154 clockrate /= 2; 155 if (IS_CHAN_QUARTER_RATE(ah->curchan)) 156 clockrate /= 4; 157 } 158 159 common->clockrate = clockrate; 160 } 161 162 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 163 { 164 struct ath_common *common = ath9k_hw_common(ah); 165 166 return usecs * common->clockrate; 167 } 168 169 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 170 { 171 int i; 172 173 BUG_ON(timeout < AH_TIME_QUANTUM); 174 175 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 176 if ((REG_READ(ah, reg) & mask) == val) 177 return true; 178 179 udelay(AH_TIME_QUANTUM); 180 } 181 182 ath_dbg(ath9k_hw_common(ah), ANY, 183 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 184 timeout, reg, REG_READ(ah, reg), mask, val); 185 186 return false; 187 } 188 EXPORT_SYMBOL(ath9k_hw_wait); 189 190 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, 191 int hw_delay) 192 { 193 if (IS_CHAN_B(chan)) 194 hw_delay = (4 * hw_delay) / 22; 195 else 196 hw_delay /= 10; 197 198 if (IS_CHAN_HALF_RATE(chan)) 199 hw_delay *= 2; 200 else if (IS_CHAN_QUARTER_RATE(chan)) 201 hw_delay *= 4; 202 203 udelay(hw_delay + BASE_ACTIVATE_DELAY); 204 } 205 206 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, 207 int column, unsigned int *writecnt) 208 { 209 int r; 210 211 ENABLE_REGWRITE_BUFFER(ah); 212 for (r = 0; r < array->ia_rows; r++) { 213 REG_WRITE(ah, INI_RA(array, r, 0), 214 INI_RA(array, r, column)); 215 DO_DELAY(*writecnt); 216 } 217 REGWRITE_BUFFER_FLUSH(ah); 218 } 219 220 u32 ath9k_hw_reverse_bits(u32 val, u32 n) 221 { 222 u32 retval; 223 int i; 224 225 for (i = 0, retval = 0; i < n; i++) { 226 retval = (retval << 1) | (val & 1); 227 val >>= 1; 228 } 229 return retval; 230 } 231 232 u16 ath9k_hw_computetxtime(struct ath_hw *ah, 233 u8 phy, int kbps, 234 u32 frameLen, u16 rateix, 235 bool shortPreamble) 236 { 237 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 238 239 if (kbps == 0) 240 return 0; 241 242 switch (phy) { 243 case WLAN_RC_PHY_CCK: 244 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 245 if (shortPreamble) 246 phyTime >>= 1; 247 numBits = frameLen << 3; 248 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 249 break; 250 case WLAN_RC_PHY_OFDM: 251 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 252 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 253 numBits = OFDM_PLCP_BITS + (frameLen << 3); 254 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 255 txTime = OFDM_SIFS_TIME_QUARTER 256 + OFDM_PREAMBLE_TIME_QUARTER 257 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 258 } else if (ah->curchan && 259 IS_CHAN_HALF_RATE(ah->curchan)) { 260 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 261 numBits = OFDM_PLCP_BITS + (frameLen << 3); 262 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 263 txTime = OFDM_SIFS_TIME_HALF + 264 OFDM_PREAMBLE_TIME_HALF 265 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 266 } else { 267 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 268 numBits = OFDM_PLCP_BITS + (frameLen << 3); 269 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 270 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 271 + (numSymbols * OFDM_SYMBOL_TIME); 272 } 273 break; 274 default: 275 ath_err(ath9k_hw_common(ah), 276 "Unknown phy %u (rate ix %u)\n", phy, rateix); 277 txTime = 0; 278 break; 279 } 280 281 return txTime; 282 } 283 EXPORT_SYMBOL(ath9k_hw_computetxtime); 284 285 void ath9k_hw_get_channel_centers(struct ath_hw *ah, 286 struct ath9k_channel *chan, 287 struct chan_centers *centers) 288 { 289 int8_t extoff; 290 291 if (!IS_CHAN_HT40(chan)) { 292 centers->ctl_center = centers->ext_center = 293 centers->synth_center = chan->channel; 294 return; 295 } 296 297 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 298 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 299 centers->synth_center = 300 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 301 extoff = 1; 302 } else { 303 centers->synth_center = 304 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 305 extoff = -1; 306 } 307 308 centers->ctl_center = 309 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 310 /* 25 MHz spacing is supported by hw but not on upper layers */ 311 centers->ext_center = 312 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 313 } 314 315 /******************/ 316 /* Chip Revisions */ 317 /******************/ 318 319 static void ath9k_hw_read_revisions(struct ath_hw *ah) 320 { 321 u32 val; 322 323 switch (ah->hw_version.devid) { 324 case AR5416_AR9100_DEVID: 325 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 326 break; 327 case AR9300_DEVID_AR9330: 328 ah->hw_version.macVersion = AR_SREV_VERSION_9330; 329 if (ah->get_mac_revision) { 330 ah->hw_version.macRev = ah->get_mac_revision(); 331 } else { 332 val = REG_READ(ah, AR_SREV); 333 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 334 } 335 return; 336 case AR9300_DEVID_AR9340: 337 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 338 val = REG_READ(ah, AR_SREV); 339 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 340 return; 341 case AR9300_DEVID_QCA955X: 342 ah->hw_version.macVersion = AR_SREV_VERSION_9550; 343 return; 344 } 345 346 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 347 348 if (val == 0xFF) { 349 val = REG_READ(ah, AR_SREV); 350 ah->hw_version.macVersion = 351 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 352 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 353 354 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 355 ah->is_pciexpress = true; 356 else 357 ah->is_pciexpress = (val & 358 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 359 } else { 360 if (!AR_SREV_9100(ah)) 361 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 362 363 ah->hw_version.macRev = val & AR_SREV_REVISION; 364 365 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 366 ah->is_pciexpress = true; 367 } 368 } 369 370 /************************************/ 371 /* HW Attach, Detach, Init Routines */ 372 /************************************/ 373 374 static void ath9k_hw_disablepcie(struct ath_hw *ah) 375 { 376 if (!AR_SREV_5416(ah)) 377 return; 378 379 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 380 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 381 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 382 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 383 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 384 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 385 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 386 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 387 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 388 389 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 390 } 391 392 /* This should work for all families including legacy */ 393 static bool ath9k_hw_chip_test(struct ath_hw *ah) 394 { 395 struct ath_common *common = ath9k_hw_common(ah); 396 u32 regAddr[2] = { AR_STA_ID0 }; 397 u32 regHold[2]; 398 static const u32 patternData[4] = { 399 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 400 }; 401 int i, j, loop_max; 402 403 if (!AR_SREV_9300_20_OR_LATER(ah)) { 404 loop_max = 2; 405 regAddr[1] = AR_PHY_BASE + (8 << 2); 406 } else 407 loop_max = 1; 408 409 for (i = 0; i < loop_max; i++) { 410 u32 addr = regAddr[i]; 411 u32 wrData, rdData; 412 413 regHold[i] = REG_READ(ah, addr); 414 for (j = 0; j < 0x100; j++) { 415 wrData = (j << 16) | j; 416 REG_WRITE(ah, addr, wrData); 417 rdData = REG_READ(ah, addr); 418 if (rdData != wrData) { 419 ath_err(common, 420 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 421 addr, wrData, rdData); 422 return false; 423 } 424 } 425 for (j = 0; j < 4; j++) { 426 wrData = patternData[j]; 427 REG_WRITE(ah, addr, wrData); 428 rdData = REG_READ(ah, addr); 429 if (wrData != rdData) { 430 ath_err(common, 431 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 432 addr, wrData, rdData); 433 return false; 434 } 435 } 436 REG_WRITE(ah, regAddr[i], regHold[i]); 437 } 438 udelay(100); 439 440 return true; 441 } 442 443 static void ath9k_hw_init_config(struct ath_hw *ah) 444 { 445 int i; 446 447 ah->config.dma_beacon_response_time = 1; 448 ah->config.sw_beacon_response_time = 6; 449 ah->config.additional_swba_backoff = 0; 450 ah->config.ack_6mb = 0x0; 451 ah->config.cwm_ignore_extcca = 0; 452 ah->config.pcie_clock_req = 0; 453 ah->config.analog_shiftreg = 1; 454 455 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 456 ah->config.spurchans[i][0] = AR_NO_SPUR; 457 ah->config.spurchans[i][1] = AR_NO_SPUR; 458 } 459 460 ah->config.rx_intr_mitigation = true; 461 ah->config.pcieSerDesWrite = true; 462 463 /* 464 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 465 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 466 * This means we use it for all AR5416 devices, and the few 467 * minor PCI AR9280 devices out there. 468 * 469 * Serialization is required because these devices do not handle 470 * well the case of two concurrent reads/writes due to the latency 471 * involved. During one read/write another read/write can be issued 472 * on another CPU while the previous read/write may still be working 473 * on our hardware, if we hit this case the hardware poops in a loop. 474 * We prevent this by serializing reads and writes. 475 * 476 * This issue is not present on PCI-Express devices or pre-AR5416 477 * devices (legacy, 802.11abg). 478 */ 479 if (num_possible_cpus() > 1) 480 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 481 } 482 483 static void ath9k_hw_init_defaults(struct ath_hw *ah) 484 { 485 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 486 487 regulatory->country_code = CTRY_DEFAULT; 488 regulatory->power_limit = MAX_RATE_POWER; 489 490 ah->hw_version.magic = AR5416_MAGIC; 491 ah->hw_version.subvendorid = 0; 492 493 ah->atim_window = 0; 494 ah->sta_id1_defaults = 495 AR_STA_ID1_CRPT_MIC_ENABLE | 496 AR_STA_ID1_MCAST_KSRCH; 497 if (AR_SREV_9100(ah)) 498 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; 499 ah->slottime = ATH9K_SLOT_TIME_9; 500 ah->globaltxtimeout = (u32) -1; 501 ah->power_mode = ATH9K_PM_UNDEFINED; 502 ah->htc_reset_init = true; 503 } 504 505 static int ath9k_hw_init_macaddr(struct ath_hw *ah) 506 { 507 struct ath_common *common = ath9k_hw_common(ah); 508 u32 sum; 509 int i; 510 u16 eeval; 511 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 512 513 sum = 0; 514 for (i = 0; i < 3; i++) { 515 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 516 sum += eeval; 517 common->macaddr[2 * i] = eeval >> 8; 518 common->macaddr[2 * i + 1] = eeval & 0xff; 519 } 520 if (sum == 0 || sum == 0xffff * 3) 521 return -EADDRNOTAVAIL; 522 523 return 0; 524 } 525 526 static int ath9k_hw_post_init(struct ath_hw *ah) 527 { 528 struct ath_common *common = ath9k_hw_common(ah); 529 int ecode; 530 531 if (common->bus_ops->ath_bus_type != ATH_USB) { 532 if (!ath9k_hw_chip_test(ah)) 533 return -ENODEV; 534 } 535 536 if (!AR_SREV_9300_20_OR_LATER(ah)) { 537 ecode = ar9002_hw_rf_claim(ah); 538 if (ecode != 0) 539 return ecode; 540 } 541 542 ecode = ath9k_hw_eeprom_init(ah); 543 if (ecode != 0) 544 return ecode; 545 546 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", 547 ah->eep_ops->get_eeprom_ver(ah), 548 ah->eep_ops->get_eeprom_rev(ah)); 549 550 ath9k_hw_ani_init(ah); 551 552 /* 553 * EEPROM needs to be initialized before we do this. 554 * This is required for regulatory compliance. 555 */ 556 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 557 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 558 if ((regdmn & 0xF0) == CTL_FCC) { 559 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_2GHZ; 560 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9462_FCC_5GHZ; 561 } 562 } 563 564 return 0; 565 } 566 567 static int ath9k_hw_attach_ops(struct ath_hw *ah) 568 { 569 if (!AR_SREV_9300_20_OR_LATER(ah)) 570 return ar9002_hw_attach_ops(ah); 571 572 ar9003_hw_attach_ops(ah); 573 return 0; 574 } 575 576 /* Called for all hardware families */ 577 static int __ath9k_hw_init(struct ath_hw *ah) 578 { 579 struct ath_common *common = ath9k_hw_common(ah); 580 int r = 0; 581 582 ath9k_hw_read_revisions(ah); 583 584 /* 585 * Read back AR_WA into a permanent copy and set bits 14 and 17. 586 * We need to do this to avoid RMW of this register. We cannot 587 * read the reg when chip is asleep. 588 */ 589 if (AR_SREV_9300_20_OR_LATER(ah)) { 590 ah->WARegVal = REG_READ(ah, AR_WA); 591 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 592 AR_WA_ASPM_TIMER_BASED_DISABLE); 593 } 594 595 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 596 ath_err(common, "Couldn't reset chip\n"); 597 return -EIO; 598 } 599 600 if (AR_SREV_9565(ah)) { 601 ah->WARegVal |= AR_WA_BIT22; 602 REG_WRITE(ah, AR_WA, ah->WARegVal); 603 } 604 605 ath9k_hw_init_defaults(ah); 606 ath9k_hw_init_config(ah); 607 608 r = ath9k_hw_attach_ops(ah); 609 if (r) 610 return r; 611 612 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 613 ath_err(common, "Couldn't wakeup chip\n"); 614 return -EIO; 615 } 616 617 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 618 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 619 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && 620 !ah->is_pciexpress)) { 621 ah->config.serialize_regmode = 622 SER_REG_MODE_ON; 623 } else { 624 ah->config.serialize_regmode = 625 SER_REG_MODE_OFF; 626 } 627 } 628 629 ath_dbg(common, RESET, "serialize_regmode is %d\n", 630 ah->config.serialize_regmode); 631 632 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 633 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 634 else 635 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 636 637 switch (ah->hw_version.macVersion) { 638 case AR_SREV_VERSION_5416_PCI: 639 case AR_SREV_VERSION_5416_PCIE: 640 case AR_SREV_VERSION_9160: 641 case AR_SREV_VERSION_9100: 642 case AR_SREV_VERSION_9280: 643 case AR_SREV_VERSION_9285: 644 case AR_SREV_VERSION_9287: 645 case AR_SREV_VERSION_9271: 646 case AR_SREV_VERSION_9300: 647 case AR_SREV_VERSION_9330: 648 case AR_SREV_VERSION_9485: 649 case AR_SREV_VERSION_9340: 650 case AR_SREV_VERSION_9462: 651 case AR_SREV_VERSION_9550: 652 case AR_SREV_VERSION_9565: 653 break; 654 default: 655 ath_err(common, 656 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", 657 ah->hw_version.macVersion, ah->hw_version.macRev); 658 return -EOPNOTSUPP; 659 } 660 661 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || 662 AR_SREV_9330(ah) || AR_SREV_9550(ah)) 663 ah->is_pciexpress = false; 664 665 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 666 ath9k_hw_init_cal_settings(ah); 667 668 ah->ani_function = ATH9K_ANI_ALL; 669 if (!AR_SREV_9300_20_OR_LATER(ah)) 670 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 671 672 if (!ah->is_pciexpress) 673 ath9k_hw_disablepcie(ah); 674 675 r = ath9k_hw_post_init(ah); 676 if (r) 677 return r; 678 679 ath9k_hw_init_mode_gain_regs(ah); 680 r = ath9k_hw_fill_cap_info(ah); 681 if (r) 682 return r; 683 684 r = ath9k_hw_init_macaddr(ah); 685 if (r) { 686 ath_err(common, "Failed to initialize MAC address\n"); 687 return r; 688 } 689 690 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 691 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 692 else 693 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 694 695 if (AR_SREV_9330(ah)) 696 ah->bb_watchdog_timeout_ms = 85; 697 else 698 ah->bb_watchdog_timeout_ms = 25; 699 700 common->state = ATH_HW_INITIALIZED; 701 702 return 0; 703 } 704 705 int ath9k_hw_init(struct ath_hw *ah) 706 { 707 int ret; 708 struct ath_common *common = ath9k_hw_common(ah); 709 710 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ 711 switch (ah->hw_version.devid) { 712 case AR5416_DEVID_PCI: 713 case AR5416_DEVID_PCIE: 714 case AR5416_AR9100_DEVID: 715 case AR9160_DEVID_PCI: 716 case AR9280_DEVID_PCI: 717 case AR9280_DEVID_PCIE: 718 case AR9285_DEVID_PCIE: 719 case AR9287_DEVID_PCI: 720 case AR9287_DEVID_PCIE: 721 case AR2427_DEVID_PCIE: 722 case AR9300_DEVID_PCIE: 723 case AR9300_DEVID_AR9485_PCIE: 724 case AR9300_DEVID_AR9330: 725 case AR9300_DEVID_AR9340: 726 case AR9300_DEVID_QCA955X: 727 case AR9300_DEVID_AR9580: 728 case AR9300_DEVID_AR9462: 729 case AR9485_DEVID_AR1111: 730 case AR9300_DEVID_AR9565: 731 break; 732 default: 733 if (common->bus_ops->ath_bus_type == ATH_USB) 734 break; 735 ath_err(common, "Hardware device ID 0x%04x not supported\n", 736 ah->hw_version.devid); 737 return -EOPNOTSUPP; 738 } 739 740 ret = __ath9k_hw_init(ah); 741 if (ret) { 742 ath_err(common, 743 "Unable to initialize hardware; initialization status: %d\n", 744 ret); 745 return ret; 746 } 747 748 return 0; 749 } 750 EXPORT_SYMBOL(ath9k_hw_init); 751 752 static void ath9k_hw_init_qos(struct ath_hw *ah) 753 { 754 ENABLE_REGWRITE_BUFFER(ah); 755 756 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 757 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 758 759 REG_WRITE(ah, AR_QOS_NO_ACK, 760 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 761 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 762 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 763 764 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 765 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 766 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 767 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 768 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 769 770 REGWRITE_BUFFER_FLUSH(ah); 771 } 772 773 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 774 { 775 struct ath_common *common = ath9k_hw_common(ah); 776 int i = 0; 777 778 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 779 udelay(100); 780 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 781 782 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { 783 784 udelay(100); 785 786 if (WARN_ON_ONCE(i >= 100)) { 787 ath_err(common, "PLL4 meaurement not done\n"); 788 break; 789 } 790 791 i++; 792 } 793 794 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 795 } 796 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 797 798 static void ath9k_hw_init_pll(struct ath_hw *ah, 799 struct ath9k_channel *chan) 800 { 801 u32 pll; 802 803 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 804 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ 805 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 806 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); 807 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 808 AR_CH0_DPLL2_KD, 0x40); 809 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 810 AR_CH0_DPLL2_KI, 0x4); 811 812 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 813 AR_CH0_BB_DPLL1_REFDIV, 0x5); 814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 815 AR_CH0_BB_DPLL1_NINI, 0x58); 816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, 817 AR_CH0_BB_DPLL1_NFRAC, 0x0); 818 819 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 820 AR_CH0_BB_DPLL2_OUTDIV, 0x1); 821 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 822 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); 823 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 824 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); 825 826 /* program BB PLL phase_shift to 0x6 */ 827 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 828 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); 829 830 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 831 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 832 udelay(1000); 833 } else if (AR_SREV_9330(ah)) { 834 u32 ddr_dpll2, pll_control2, kd; 835 836 if (ah->is_clk_25mhz) { 837 ddr_dpll2 = 0x18e82f01; 838 pll_control2 = 0xe04a3d; 839 kd = 0x1d; 840 } else { 841 ddr_dpll2 = 0x19e82f01; 842 pll_control2 = 0x886666; 843 kd = 0x3d; 844 } 845 846 /* program DDR PLL ki and kd value */ 847 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); 848 849 /* program DDR PLL phase_shift */ 850 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, 851 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); 852 853 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 854 udelay(1000); 855 856 /* program refdiv, nint, frac to RTC register */ 857 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); 858 859 /* program BB PLL kd and ki value */ 860 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); 861 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); 862 863 /* program BB PLL phase_shift */ 864 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, 865 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); 866 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 867 u32 regval, pll2_divint, pll2_divfrac, refdiv; 868 869 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); 870 udelay(1000); 871 872 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); 873 udelay(100); 874 875 if (ah->is_clk_25mhz) { 876 pll2_divint = 0x54; 877 pll2_divfrac = 0x1eb85; 878 refdiv = 3; 879 } else { 880 if (AR_SREV_9340(ah)) { 881 pll2_divint = 88; 882 pll2_divfrac = 0; 883 refdiv = 5; 884 } else { 885 pll2_divint = 0x11; 886 pll2_divfrac = 0x26666; 887 refdiv = 1; 888 } 889 } 890 891 regval = REG_READ(ah, AR_PHY_PLL_MODE); 892 regval |= (0x1 << 16); 893 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 894 udelay(100); 895 896 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | 897 (pll2_divint << 18) | pll2_divfrac); 898 udelay(100); 899 900 regval = REG_READ(ah, AR_PHY_PLL_MODE); 901 if (AR_SREV_9340(ah)) 902 regval = (regval & 0x80071fff) | (0x1 << 30) | 903 (0x1 << 13) | (0x4 << 26) | (0x18 << 19); 904 else 905 regval = (regval & 0x80071fff) | (0x3 << 30) | 906 (0x1 << 13) | (0x4 << 26) | (0x60 << 19); 907 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); 908 REG_WRITE(ah, AR_PHY_PLL_MODE, 909 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); 910 udelay(1000); 911 } 912 913 pll = ath9k_hw_compute_pll_control(ah, chan); 914 if (AR_SREV_9565(ah)) 915 pll |= 0x40000; 916 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 917 918 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || 919 AR_SREV_9550(ah)) 920 udelay(1000); 921 922 /* Switch the core clock for ar9271 to 117Mhz */ 923 if (AR_SREV_9271(ah)) { 924 udelay(500); 925 REG_WRITE(ah, 0x50040, 0x304); 926 } 927 928 udelay(RTC_PLL_SETTLE_DELAY); 929 930 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 931 932 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { 933 if (ah->is_clk_25mhz) { 934 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); 935 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); 936 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); 937 } else { 938 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); 939 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); 940 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); 941 } 942 udelay(100); 943 } 944 } 945 946 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 947 enum nl80211_iftype opmode) 948 { 949 u32 sync_default = AR_INTR_SYNC_DEFAULT; 950 u32 imr_reg = AR_IMR_TXERR | 951 AR_IMR_TXURN | 952 AR_IMR_RXERR | 953 AR_IMR_RXORN | 954 AR_IMR_BCNMISC; 955 956 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) 957 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; 958 959 if (AR_SREV_9300_20_OR_LATER(ah)) { 960 imr_reg |= AR_IMR_RXOK_HP; 961 if (ah->config.rx_intr_mitigation) 962 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 963 else 964 imr_reg |= AR_IMR_RXOK_LP; 965 966 } else { 967 if (ah->config.rx_intr_mitigation) 968 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 969 else 970 imr_reg |= AR_IMR_RXOK; 971 } 972 973 if (ah->config.tx_intr_mitigation) 974 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 975 else 976 imr_reg |= AR_IMR_TXOK; 977 978 ENABLE_REGWRITE_BUFFER(ah); 979 980 REG_WRITE(ah, AR_IMR, imr_reg); 981 ah->imrs2_reg |= AR_IMR_S2_GTT; 982 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 983 984 if (!AR_SREV_9100(ah)) { 985 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 986 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); 987 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 988 } 989 990 REGWRITE_BUFFER_FLUSH(ah); 991 992 if (AR_SREV_9300_20_OR_LATER(ah)) { 993 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 994 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 995 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 996 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 997 } 998 } 999 1000 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) 1001 { 1002 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); 1003 val = min(val, (u32) 0xFFFF); 1004 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); 1005 } 1006 1007 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 1008 { 1009 u32 val = ath9k_hw_mac_to_clks(ah, us); 1010 val = min(val, (u32) 0xFFFF); 1011 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 1012 } 1013 1014 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1015 { 1016 u32 val = ath9k_hw_mac_to_clks(ah, us); 1017 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 1018 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 1019 } 1020 1021 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1022 { 1023 u32 val = ath9k_hw_mac_to_clks(ah, us); 1024 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 1025 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 1026 } 1027 1028 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1029 { 1030 if (tu > 0xFFFF) { 1031 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", 1032 tu); 1033 ah->globaltxtimeout = (u32) -1; 1034 return false; 1035 } else { 1036 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 1037 ah->globaltxtimeout = tu; 1038 return true; 1039 } 1040 } 1041 1042 void ath9k_hw_init_global_settings(struct ath_hw *ah) 1043 { 1044 struct ath_common *common = ath9k_hw_common(ah); 1045 struct ieee80211_conf *conf = &common->hw->conf; 1046 const struct ath9k_channel *chan = ah->curchan; 1047 int acktimeout, ctstimeout, ack_offset = 0; 1048 int slottime; 1049 int sifstime; 1050 int rx_lat = 0, tx_lat = 0, eifs = 0; 1051 u32 reg; 1052 1053 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", 1054 ah->misc_mode); 1055 1056 if (!chan) 1057 return; 1058 1059 if (ah->misc_mode != 0) 1060 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 1061 1062 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1063 rx_lat = 41; 1064 else 1065 rx_lat = 37; 1066 tx_lat = 54; 1067 1068 if (IS_CHAN_5GHZ(chan)) 1069 sifstime = 16; 1070 else 1071 sifstime = 10; 1072 1073 if (IS_CHAN_HALF_RATE(chan)) { 1074 eifs = 175; 1075 rx_lat *= 2; 1076 tx_lat *= 2; 1077 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1078 tx_lat += 11; 1079 1080 sifstime = 32; 1081 ack_offset = 16; 1082 slottime = 13; 1083 } else if (IS_CHAN_QUARTER_RATE(chan)) { 1084 eifs = 340; 1085 rx_lat = (rx_lat * 4) - 1; 1086 tx_lat *= 4; 1087 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) 1088 tx_lat += 22; 1089 1090 sifstime = 64; 1091 ack_offset = 32; 1092 slottime = 21; 1093 } else { 1094 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 1095 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; 1096 reg = AR_USEC_ASYNC_FIFO; 1097 } else { 1098 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ 1099 common->clockrate; 1100 reg = REG_READ(ah, AR_USEC); 1101 } 1102 rx_lat = MS(reg, AR_USEC_RX_LAT); 1103 tx_lat = MS(reg, AR_USEC_TX_LAT); 1104 1105 slottime = ah->slottime; 1106 } 1107 1108 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1109 slottime += 3 * ah->coverage_class; 1110 acktimeout = slottime + sifstime + ack_offset; 1111 ctstimeout = acktimeout; 1112 1113 /* 1114 * Workaround for early ACK timeouts, add an offset to match the 1115 * initval's 64us ack timeout value. Use 48us for the CTS timeout. 1116 * This was initially only meant to work around an issue with delayed 1117 * BA frames in some implementations, but it has been found to fix ACK 1118 * timeout issues in other cases as well. 1119 */ 1120 if (conf->chandef.chan && 1121 conf->chandef.chan->band == IEEE80211_BAND_2GHZ && 1122 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { 1123 acktimeout += 64 - sifstime - ah->slottime; 1124 ctstimeout += 48 - sifstime - ah->slottime; 1125 } 1126 1127 ath9k_hw_set_sifs_time(ah, sifstime); 1128 ath9k_hw_setslottime(ah, slottime); 1129 ath9k_hw_set_ack_timeout(ah, acktimeout); 1130 ath9k_hw_set_cts_timeout(ah, ctstimeout); 1131 if (ah->globaltxtimeout != (u32) -1) 1132 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1133 1134 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); 1135 REG_RMW(ah, AR_USEC, 1136 (common->clockrate - 1) | 1137 SM(rx_lat, AR_USEC_RX_LAT) | 1138 SM(tx_lat, AR_USEC_TX_LAT), 1139 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); 1140 1141 } 1142 EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1143 1144 void ath9k_hw_deinit(struct ath_hw *ah) 1145 { 1146 struct ath_common *common = ath9k_hw_common(ah); 1147 1148 if (common->state < ATH_HW_INITIALIZED) 1149 return; 1150 1151 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1152 } 1153 EXPORT_SYMBOL(ath9k_hw_deinit); 1154 1155 /*******/ 1156 /* INI */ 1157 /*******/ 1158 1159 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 1160 { 1161 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1162 1163 if (IS_CHAN_B(chan)) 1164 ctl |= CTL_11B; 1165 else if (IS_CHAN_G(chan)) 1166 ctl |= CTL_11G; 1167 else 1168 ctl |= CTL_11A; 1169 1170 return ctl; 1171 } 1172 1173 /****************************************/ 1174 /* Reset and Channel Switching Routines */ 1175 /****************************************/ 1176 1177 static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1178 { 1179 struct ath_common *common = ath9k_hw_common(ah); 1180 int txbuf_size; 1181 1182 ENABLE_REGWRITE_BUFFER(ah); 1183 1184 /* 1185 * set AHB_MODE not to do cacheline prefetches 1186 */ 1187 if (!AR_SREV_9300_20_OR_LATER(ah)) 1188 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 1189 1190 /* 1191 * let mac dma reads be in 128 byte chunks 1192 */ 1193 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); 1194 1195 REGWRITE_BUFFER_FLUSH(ah); 1196 1197 /* 1198 * Restore TX Trigger Level to its pre-reset value. 1199 * The initial value depends on whether aggregation is enabled, and is 1200 * adjusted whenever underruns are detected. 1201 */ 1202 if (!AR_SREV_9300_20_OR_LATER(ah)) 1203 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 1204 1205 ENABLE_REGWRITE_BUFFER(ah); 1206 1207 /* 1208 * let mac dma writes be in 128 byte chunks 1209 */ 1210 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); 1211 1212 /* 1213 * Setup receive FIFO threshold to hold off TX activities 1214 */ 1215 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 1216 1217 if (AR_SREV_9300_20_OR_LATER(ah)) { 1218 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 1219 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 1220 1221 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 1222 ah->caps.rx_status_len); 1223 } 1224 1225 /* 1226 * reduce the number of usable entries in PCU TXBUF to avoid 1227 * wrap around issues. 1228 */ 1229 if (AR_SREV_9285(ah)) { 1230 /* For AR9285 the number of Fifos are reduced to half. 1231 * So set the usable tx buf size also to half to 1232 * avoid data/delimiter underruns 1233 */ 1234 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; 1235 } else if (AR_SREV_9340_13_OR_LATER(ah)) { 1236 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ 1237 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; 1238 } else { 1239 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; 1240 } 1241 1242 if (!AR_SREV_9271(ah)) 1243 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); 1244 1245 REGWRITE_BUFFER_FLUSH(ah); 1246 1247 if (AR_SREV_9300_20_OR_LATER(ah)) 1248 ath9k_hw_reset_txstatus_ring(ah); 1249 } 1250 1251 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 1252 { 1253 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; 1254 u32 set = AR_STA_ID1_KSRCH_MODE; 1255 1256 switch (opmode) { 1257 case NL80211_IFTYPE_ADHOC: 1258 set |= AR_STA_ID1_ADHOC; 1259 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1260 break; 1261 case NL80211_IFTYPE_MESH_POINT: 1262 case NL80211_IFTYPE_AP: 1263 set |= AR_STA_ID1_STA_AP; 1264 /* fall through */ 1265 case NL80211_IFTYPE_STATION: 1266 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 1267 break; 1268 default: 1269 if (!ah->is_monitoring) 1270 set = 0; 1271 break; 1272 } 1273 REG_RMW(ah, AR_STA_ID1, set, mask); 1274 } 1275 1276 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 1277 u32 *coef_mantissa, u32 *coef_exponent) 1278 { 1279 u32 coef_exp, coef_man; 1280 1281 for (coef_exp = 31; coef_exp > 0; coef_exp--) 1282 if ((coef_scaled >> coef_exp) & 0x1) 1283 break; 1284 1285 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 1286 1287 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 1288 1289 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 1290 *coef_exponent = coef_exp - 16; 1291 } 1292 1293 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1294 { 1295 u32 rst_flags; 1296 u32 tmpReg; 1297 1298 if (AR_SREV_9100(ah)) { 1299 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, 1300 AR_RTC_DERIVED_CLK_PERIOD, 1); 1301 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 1302 } 1303 1304 ENABLE_REGWRITE_BUFFER(ah); 1305 1306 if (AR_SREV_9300_20_OR_LATER(ah)) { 1307 REG_WRITE(ah, AR_WA, ah->WARegVal); 1308 udelay(10); 1309 } 1310 1311 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1312 AR_RTC_FORCE_WAKE_ON_INT); 1313 1314 if (AR_SREV_9100(ah)) { 1315 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1316 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1317 } else { 1318 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1319 if (AR_SREV_9340(ah)) 1320 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; 1321 else 1322 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | 1323 AR_INTR_SYNC_RADM_CPL_TIMEOUT; 1324 1325 if (tmpReg) { 1326 u32 val; 1327 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1328 1329 val = AR_RC_HOSTIF; 1330 if (!AR_SREV_9300_20_OR_LATER(ah)) 1331 val |= AR_RC_AHB; 1332 REG_WRITE(ah, AR_RC, val); 1333 1334 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1335 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1336 1337 rst_flags = AR_RTC_RC_MAC_WARM; 1338 if (type == ATH9K_RESET_COLD) 1339 rst_flags |= AR_RTC_RC_MAC_COLD; 1340 } 1341 1342 if (AR_SREV_9330(ah)) { 1343 int npend = 0; 1344 int i; 1345 1346 /* AR9330 WAR: 1347 * call external reset function to reset WMAC if: 1348 * - doing a cold reset 1349 * - we have pending frames in the TX queues 1350 */ 1351 1352 for (i = 0; i < AR_NUM_QCU; i++) { 1353 npend = ath9k_hw_numtxpending(ah, i); 1354 if (npend) 1355 break; 1356 } 1357 1358 if (ah->external_reset && 1359 (npend || type == ATH9K_RESET_COLD)) { 1360 int reset_err = 0; 1361 1362 ath_dbg(ath9k_hw_common(ah), RESET, 1363 "reset MAC via external reset\n"); 1364 1365 reset_err = ah->external_reset(); 1366 if (reset_err) { 1367 ath_err(ath9k_hw_common(ah), 1368 "External reset failed, err=%d\n", 1369 reset_err); 1370 return false; 1371 } 1372 1373 REG_WRITE(ah, AR_RTC_RESET, 1); 1374 } 1375 } 1376 1377 if (ath9k_hw_mci_is_enabled(ah)) 1378 ar9003_mci_check_gpm_offset(ah); 1379 1380 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1381 1382 REGWRITE_BUFFER_FLUSH(ah); 1383 1384 udelay(50); 1385 1386 REG_WRITE(ah, AR_RTC_RC, 0); 1387 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1388 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); 1389 return false; 1390 } 1391 1392 if (!AR_SREV_9100(ah)) 1393 REG_WRITE(ah, AR_RC, 0); 1394 1395 if (AR_SREV_9100(ah)) 1396 udelay(50); 1397 1398 return true; 1399 } 1400 1401 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1402 { 1403 ENABLE_REGWRITE_BUFFER(ah); 1404 1405 if (AR_SREV_9300_20_OR_LATER(ah)) { 1406 REG_WRITE(ah, AR_WA, ah->WARegVal); 1407 udelay(10); 1408 } 1409 1410 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1411 AR_RTC_FORCE_WAKE_ON_INT); 1412 1413 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1414 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1415 1416 REG_WRITE(ah, AR_RTC_RESET, 0); 1417 1418 REGWRITE_BUFFER_FLUSH(ah); 1419 1420 if (!AR_SREV_9300_20_OR_LATER(ah)) 1421 udelay(2); 1422 1423 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1424 REG_WRITE(ah, AR_RC, 0); 1425 1426 REG_WRITE(ah, AR_RTC_RESET, 1); 1427 1428 if (!ath9k_hw_wait(ah, 1429 AR_RTC_STATUS, 1430 AR_RTC_STATUS_M, 1431 AR_RTC_STATUS_ON, 1432 AH_WAIT_TIMEOUT)) { 1433 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); 1434 return false; 1435 } 1436 1437 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1438 } 1439 1440 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1441 { 1442 bool ret = false; 1443 1444 if (AR_SREV_9300_20_OR_LATER(ah)) { 1445 REG_WRITE(ah, AR_WA, ah->WARegVal); 1446 udelay(10); 1447 } 1448 1449 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1450 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1451 1452 if (!ah->reset_power_on) 1453 type = ATH9K_RESET_POWER_ON; 1454 1455 switch (type) { 1456 case ATH9K_RESET_POWER_ON: 1457 ret = ath9k_hw_set_reset_power_on(ah); 1458 if (ret) 1459 ah->reset_power_on = true; 1460 break; 1461 case ATH9K_RESET_WARM: 1462 case ATH9K_RESET_COLD: 1463 ret = ath9k_hw_set_reset(ah, type); 1464 break; 1465 default: 1466 break; 1467 } 1468 1469 return ret; 1470 } 1471 1472 static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1473 struct ath9k_channel *chan) 1474 { 1475 int reset_type = ATH9K_RESET_WARM; 1476 1477 if (AR_SREV_9280(ah)) { 1478 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 1479 reset_type = ATH9K_RESET_POWER_ON; 1480 else 1481 reset_type = ATH9K_RESET_COLD; 1482 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || 1483 (REG_READ(ah, AR_CR) & AR_CR_RXE)) 1484 reset_type = ATH9K_RESET_COLD; 1485 1486 if (!ath9k_hw_set_reset_reg(ah, reset_type)) 1487 return false; 1488 1489 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1490 return false; 1491 1492 ah->chip_fullsleep = false; 1493 1494 if (AR_SREV_9330(ah)) 1495 ar9003_hw_internal_regulator_apply(ah); 1496 ath9k_hw_init_pll(ah, chan); 1497 ath9k_hw_set_rfmode(ah, chan); 1498 1499 return true; 1500 } 1501 1502 static bool ath9k_hw_channel_change(struct ath_hw *ah, 1503 struct ath9k_channel *chan) 1504 { 1505 struct ath_common *common = ath9k_hw_common(ah); 1506 struct ath9k_hw_capabilities *pCap = &ah->caps; 1507 bool band_switch = false, mode_diff = false; 1508 u8 ini_reloaded = 0; 1509 u32 qnum; 1510 int r; 1511 1512 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { 1513 u32 cur = ah->curchan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ); 1514 u32 new = chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ); 1515 band_switch = (cur != new); 1516 mode_diff = (chan->chanmode != ah->curchan->chanmode); 1517 } 1518 1519 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1520 if (ath9k_hw_numtxpending(ah, qnum)) { 1521 ath_dbg(common, QUEUE, 1522 "Transmit frames pending on queue %d\n", qnum); 1523 return false; 1524 } 1525 } 1526 1527 if (!ath9k_hw_rfbus_req(ah)) { 1528 ath_err(common, "Could not kill baseband RX\n"); 1529 return false; 1530 } 1531 1532 if (band_switch || mode_diff) { 1533 ath9k_hw_mark_phy_inactive(ah); 1534 udelay(5); 1535 1536 if (band_switch) 1537 ath9k_hw_init_pll(ah, chan); 1538 1539 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { 1540 ath_err(common, "Failed to do fast channel change\n"); 1541 return false; 1542 } 1543 } 1544 1545 ath9k_hw_set_channel_regs(ah, chan); 1546 1547 r = ath9k_hw_rf_set_freq(ah, chan); 1548 if (r) { 1549 ath_err(common, "Failed to set channel\n"); 1550 return false; 1551 } 1552 ath9k_hw_set_clockrate(ah); 1553 ath9k_hw_apply_txpower(ah, chan, false); 1554 1555 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1556 ath9k_hw_set_delta_slope(ah, chan); 1557 1558 ath9k_hw_spur_mitigate_freq(ah, chan); 1559 1560 if (band_switch || ini_reloaded) 1561 ah->eep_ops->set_board_values(ah, chan); 1562 1563 ath9k_hw_init_bb(ah, chan); 1564 ath9k_hw_rfbus_done(ah); 1565 1566 if (band_switch || ini_reloaded) { 1567 ah->ah_flags |= AH_FASTCC; 1568 ath9k_hw_init_cal(ah, chan); 1569 ah->ah_flags &= ~AH_FASTCC; 1570 } 1571 1572 return true; 1573 } 1574 1575 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) 1576 { 1577 u32 gpio_mask = ah->gpio_mask; 1578 int i; 1579 1580 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { 1581 if (!(gpio_mask & 1)) 1582 continue; 1583 1584 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 1585 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); 1586 } 1587 } 1588 1589 static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states, 1590 int *hang_state, int *hang_pos) 1591 { 1592 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */ 1593 u32 chain_state, dcs_pos, i; 1594 1595 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) { 1596 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f; 1597 for (i = 0; i < 3; i++) { 1598 if (chain_state == dcu_chain_state[i]) { 1599 *hang_state = chain_state; 1600 *hang_pos = dcs_pos; 1601 return true; 1602 } 1603 } 1604 } 1605 return false; 1606 } 1607 1608 #define DCU_COMPLETE_STATE 1 1609 #define DCU_COMPLETE_STATE_MASK 0x3 1610 #define NUM_STATUS_READS 50 1611 static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah) 1612 { 1613 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4; 1614 u32 i, hang_pos, hang_state, num_state = 6; 1615 1616 comp_state = REG_READ(ah, AR_DMADBG_6); 1617 1618 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) { 1619 ath_dbg(ath9k_hw_common(ah), RESET, 1620 "MAC Hang signature not found at DCU complete\n"); 1621 return false; 1622 } 1623 1624 chain_state = REG_READ(ah, dcs_reg); 1625 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1626 goto hang_check_iter; 1627 1628 dcs_reg = AR_DMADBG_5; 1629 num_state = 4; 1630 chain_state = REG_READ(ah, dcs_reg); 1631 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos)) 1632 goto hang_check_iter; 1633 1634 ath_dbg(ath9k_hw_common(ah), RESET, 1635 "MAC Hang signature 1 not found\n"); 1636 return false; 1637 1638 hang_check_iter: 1639 ath_dbg(ath9k_hw_common(ah), RESET, 1640 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n", 1641 chain_state, comp_state, hang_state, hang_pos); 1642 1643 for (i = 0; i < NUM_STATUS_READS; i++) { 1644 chain_state = REG_READ(ah, dcs_reg); 1645 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f; 1646 comp_state = REG_READ(ah, AR_DMADBG_6); 1647 1648 if (((comp_state & DCU_COMPLETE_STATE_MASK) != 1649 DCU_COMPLETE_STATE) || 1650 (chain_state != hang_state)) 1651 return false; 1652 } 1653 1654 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n"); 1655 1656 return true; 1657 } 1658 1659 void ath9k_hw_check_nav(struct ath_hw *ah) 1660 { 1661 struct ath_common *common = ath9k_hw_common(ah); 1662 u32 val; 1663 1664 val = REG_READ(ah, AR_NAV); 1665 if (val != 0xdeadbeef && val > 0x7fff) { 1666 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); 1667 REG_WRITE(ah, AR_NAV, 0); 1668 } 1669 } 1670 EXPORT_SYMBOL(ath9k_hw_check_nav); 1671 1672 bool ath9k_hw_check_alive(struct ath_hw *ah) 1673 { 1674 int count = 50; 1675 u32 reg; 1676 1677 if (AR_SREV_9300(ah)) 1678 return !ath9k_hw_detect_mac_hang(ah); 1679 1680 if (AR_SREV_9285_12_OR_LATER(ah)) 1681 return true; 1682 1683 do { 1684 reg = REG_READ(ah, AR_OBS_BUS_1); 1685 1686 if ((reg & 0x7E7FFFEF) == 0x00702400) 1687 continue; 1688 1689 switch (reg & 0x7E000B00) { 1690 case 0x1E000000: 1691 case 0x52000B00: 1692 case 0x18000B00: 1693 continue; 1694 default: 1695 return true; 1696 } 1697 } while (count-- > 0); 1698 1699 return false; 1700 } 1701 EXPORT_SYMBOL(ath9k_hw_check_alive); 1702 1703 static void ath9k_hw_init_mfp(struct ath_hw *ah) 1704 { 1705 /* Setup MFP options for CCMP */ 1706 if (AR_SREV_9280_20_OR_LATER(ah)) { 1707 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1708 * frames when constructing CCMP AAD. */ 1709 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1710 0xc7ff); 1711 ah->sw_mgmt_crypto = false; 1712 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1713 /* Disable hardware crypto for management frames */ 1714 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1715 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1716 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1717 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1718 ah->sw_mgmt_crypto = true; 1719 } else { 1720 ah->sw_mgmt_crypto = true; 1721 } 1722 } 1723 1724 static void ath9k_hw_reset_opmode(struct ath_hw *ah, 1725 u32 macStaId1, u32 saveDefAntenna) 1726 { 1727 struct ath_common *common = ath9k_hw_common(ah); 1728 1729 ENABLE_REGWRITE_BUFFER(ah); 1730 1731 REG_RMW(ah, AR_STA_ID1, macStaId1 1732 | AR_STA_ID1_RTS_USE_DEF 1733 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1734 | ah->sta_id1_defaults, 1735 ~AR_STA_ID1_SADH_MASK); 1736 ath_hw_setbssidmask(common); 1737 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1738 ath9k_hw_write_associd(ah); 1739 REG_WRITE(ah, AR_ISR, ~0); 1740 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1741 1742 REGWRITE_BUFFER_FLUSH(ah); 1743 1744 ath9k_hw_set_operating_mode(ah, ah->opmode); 1745 } 1746 1747 static void ath9k_hw_init_queues(struct ath_hw *ah) 1748 { 1749 int i; 1750 1751 ENABLE_REGWRITE_BUFFER(ah); 1752 1753 for (i = 0; i < AR_NUM_DCU; i++) 1754 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1755 1756 REGWRITE_BUFFER_FLUSH(ah); 1757 1758 ah->intr_txqs = 0; 1759 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1760 ath9k_hw_resettxqueue(ah, i); 1761 } 1762 1763 /* 1764 * For big endian systems turn on swapping for descriptors 1765 */ 1766 static void ath9k_hw_init_desc(struct ath_hw *ah) 1767 { 1768 struct ath_common *common = ath9k_hw_common(ah); 1769 1770 if (AR_SREV_9100(ah)) { 1771 u32 mask; 1772 mask = REG_READ(ah, AR_CFG); 1773 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1774 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", 1775 mask); 1776 } else { 1777 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1778 REG_WRITE(ah, AR_CFG, mask); 1779 ath_dbg(common, RESET, "Setting CFG 0x%x\n", 1780 REG_READ(ah, AR_CFG)); 1781 } 1782 } else { 1783 if (common->bus_ops->ath_bus_type == ATH_USB) { 1784 /* Configure AR9271 target WLAN */ 1785 if (AR_SREV_9271(ah)) 1786 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1787 else 1788 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1789 } 1790 #ifdef __BIG_ENDIAN 1791 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || 1792 AR_SREV_9550(ah)) 1793 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1794 else 1795 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1796 #endif 1797 } 1798 } 1799 1800 /* 1801 * Fast channel change: 1802 * (Change synthesizer based on channel freq without resetting chip) 1803 */ 1804 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) 1805 { 1806 struct ath_common *common = ath9k_hw_common(ah); 1807 struct ath9k_hw_capabilities *pCap = &ah->caps; 1808 int ret; 1809 1810 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) 1811 goto fail; 1812 1813 if (ah->chip_fullsleep) 1814 goto fail; 1815 1816 if (!ah->curchan) 1817 goto fail; 1818 1819 if (chan->channel == ah->curchan->channel) 1820 goto fail; 1821 1822 if ((ah->curchan->channelFlags | chan->channelFlags) & 1823 (CHANNEL_HALF | CHANNEL_QUARTER)) 1824 goto fail; 1825 1826 /* 1827 * If cross-band fcc is not supoprted, bail out if 1828 * either channelFlags or chanmode differ. 1829 * 1830 * chanmode will be different if the HT operating mode 1831 * changes because of CSA. 1832 */ 1833 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH)) { 1834 if ((chan->channelFlags & CHANNEL_ALL) != 1835 (ah->curchan->channelFlags & CHANNEL_ALL)) 1836 goto fail; 1837 1838 if (chan->chanmode != ah->curchan->chanmode) 1839 goto fail; 1840 } 1841 1842 if (!ath9k_hw_check_alive(ah)) 1843 goto fail; 1844 1845 /* 1846 * For AR9462, make sure that calibration data for 1847 * re-using are present. 1848 */ 1849 if (AR_SREV_9462(ah) && (ah->caldata && 1850 (!ah->caldata->done_txiqcal_once || 1851 !ah->caldata->done_txclcal_once || 1852 !ah->caldata->rtt_done))) 1853 goto fail; 1854 1855 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", 1856 ah->curchan->channel, chan->channel); 1857 1858 ret = ath9k_hw_channel_change(ah, chan); 1859 if (!ret) 1860 goto fail; 1861 1862 if (ath9k_hw_mci_is_enabled(ah)) 1863 ar9003_mci_2g5g_switch(ah, false); 1864 1865 ath9k_hw_loadnf(ah, ah->curchan); 1866 ath9k_hw_start_nfcal(ah, true); 1867 1868 if (AR_SREV_9271(ah)) 1869 ar9002_hw_load_ani_reg(ah, chan); 1870 1871 return 0; 1872 fail: 1873 return -EINVAL; 1874 } 1875 1876 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1877 struct ath9k_hw_cal_data *caldata, bool fastcc) 1878 { 1879 struct ath_common *common = ath9k_hw_common(ah); 1880 u32 saveLedState; 1881 u32 saveDefAntenna; 1882 u32 macStaId1; 1883 u64 tsf = 0; 1884 int r; 1885 bool start_mci_reset = false; 1886 bool save_fullsleep = ah->chip_fullsleep; 1887 1888 if (ath9k_hw_mci_is_enabled(ah)) { 1889 start_mci_reset = ar9003_mci_start_reset(ah, chan); 1890 if (start_mci_reset) 1891 return 0; 1892 } 1893 1894 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1895 return -EIO; 1896 1897 if (ah->curchan && !ah->chip_fullsleep) 1898 ath9k_hw_getnf(ah, ah->curchan); 1899 1900 ah->caldata = caldata; 1901 if (caldata && (chan->channel != caldata->channel || 1902 chan->channelFlags != caldata->channelFlags || 1903 chan->chanmode != caldata->chanmode)) { 1904 /* Operating channel changed, reset channel calibration data */ 1905 memset(caldata, 0, sizeof(*caldata)); 1906 ath9k_init_nfcal_hist_buffer(ah, chan); 1907 } else if (caldata) { 1908 caldata->paprd_packet_sent = false; 1909 } 1910 ah->noise = ath9k_hw_getchan_noise(ah, chan); 1911 1912 if (fastcc) { 1913 r = ath9k_hw_do_fastcc(ah, chan); 1914 if (!r) 1915 return r; 1916 } 1917 1918 if (ath9k_hw_mci_is_enabled(ah)) 1919 ar9003_mci_stop_bt(ah, save_fullsleep); 1920 1921 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1922 if (saveDefAntenna == 0) 1923 saveDefAntenna = 1; 1924 1925 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1926 1927 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1928 if (AR_SREV_9100(ah) || 1929 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1930 tsf = ath9k_hw_gettsf64(ah); 1931 1932 saveLedState = REG_READ(ah, AR_CFG_LED) & 1933 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1934 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1935 1936 ath9k_hw_mark_phy_inactive(ah); 1937 1938 ah->paprd_table_write_done = false; 1939 1940 /* Only required on the first reset */ 1941 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1942 REG_WRITE(ah, 1943 AR9271_RESET_POWER_DOWN_CONTROL, 1944 AR9271_RADIO_RF_RST); 1945 udelay(50); 1946 } 1947 1948 if (!ath9k_hw_chip_reset(ah, chan)) { 1949 ath_err(common, "Chip reset failed\n"); 1950 return -EINVAL; 1951 } 1952 1953 /* Only required on the first reset */ 1954 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1955 ah->htc_reset_init = false; 1956 REG_WRITE(ah, 1957 AR9271_RESET_POWER_DOWN_CONTROL, 1958 AR9271_GATE_MAC_CTL); 1959 udelay(50); 1960 } 1961 1962 /* Restore TSF */ 1963 if (tsf) 1964 ath9k_hw_settsf64(ah, tsf); 1965 1966 if (AR_SREV_9280_20_OR_LATER(ah)) 1967 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1968 1969 if (!AR_SREV_9300_20_OR_LATER(ah)) 1970 ar9002_hw_enable_async_fifo(ah); 1971 1972 r = ath9k_hw_process_ini(ah, chan); 1973 if (r) 1974 return r; 1975 1976 if (ath9k_hw_mci_is_enabled(ah)) 1977 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); 1978 1979 /* 1980 * Some AR91xx SoC devices frequently fail to accept TSF writes 1981 * right after the chip reset. When that happens, write a new 1982 * value after the initvals have been applied, with an offset 1983 * based on measured time difference 1984 */ 1985 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1986 tsf += 1500; 1987 ath9k_hw_settsf64(ah, tsf); 1988 } 1989 1990 ath9k_hw_init_mfp(ah); 1991 1992 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1993 ath9k_hw_set_delta_slope(ah, chan); 1994 1995 ath9k_hw_spur_mitigate_freq(ah, chan); 1996 ah->eep_ops->set_board_values(ah, chan); 1997 1998 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); 1999 2000 r = ath9k_hw_rf_set_freq(ah, chan); 2001 if (r) 2002 return r; 2003 2004 ath9k_hw_set_clockrate(ah); 2005 2006 ath9k_hw_init_queues(ah); 2007 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 2008 ath9k_hw_ani_cache_ini_regs(ah); 2009 ath9k_hw_init_qos(ah); 2010 2011 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2012 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); 2013 2014 ath9k_hw_init_global_settings(ah); 2015 2016 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { 2017 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, 2018 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); 2019 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, 2020 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); 2021 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 2022 AR_PCU_MISC_MODE2_ENABLE_AGGWEP); 2023 } 2024 2025 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 2026 2027 ath9k_hw_set_dma(ah); 2028 2029 if (!ath9k_hw_mci_is_enabled(ah)) 2030 REG_WRITE(ah, AR_OBS, 8); 2031 2032 if (ah->config.rx_intr_mitigation) { 2033 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 2034 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 2035 } 2036 2037 if (ah->config.tx_intr_mitigation) { 2038 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 2039 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 2040 } 2041 2042 ath9k_hw_init_bb(ah, chan); 2043 2044 if (caldata) { 2045 caldata->done_txiqcal_once = false; 2046 caldata->done_txclcal_once = false; 2047 } 2048 if (!ath9k_hw_init_cal(ah, chan)) 2049 return -EIO; 2050 2051 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) 2052 return -EIO; 2053 2054 ENABLE_REGWRITE_BUFFER(ah); 2055 2056 ath9k_hw_restore_chainmask(ah); 2057 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 2058 2059 REGWRITE_BUFFER_FLUSH(ah); 2060 2061 ath9k_hw_init_desc(ah); 2062 2063 if (ath9k_hw_btcoex_is_enabled(ah)) 2064 ath9k_hw_btcoex_enable(ah); 2065 2066 if (ath9k_hw_mci_is_enabled(ah)) 2067 ar9003_mci_check_bt(ah); 2068 2069 ath9k_hw_loadnf(ah, chan); 2070 ath9k_hw_start_nfcal(ah, true); 2071 2072 if (AR_SREV_9300_20_OR_LATER(ah)) { 2073 ar9003_hw_bb_watchdog_config(ah); 2074 ar9003_hw_disable_phy_restart(ah); 2075 } 2076 2077 ath9k_hw_apply_gpio_override(ah); 2078 2079 if (AR_SREV_9565(ah) && common->bt_ant_diversity) 2080 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); 2081 2082 return 0; 2083 } 2084 EXPORT_SYMBOL(ath9k_hw_reset); 2085 2086 /******************************/ 2087 /* Power Management (Chipset) */ 2088 /******************************/ 2089 2090 /* 2091 * Notify Power Mgt is disabled in self-generated frames. 2092 * If requested, force chip to sleep. 2093 */ 2094 static void ath9k_set_power_sleep(struct ath_hw *ah) 2095 { 2096 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2097 2098 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2099 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); 2100 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); 2101 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); 2102 /* xxx Required for WLAN only case ? */ 2103 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2104 udelay(100); 2105 } 2106 2107 /* 2108 * Clear the RTC force wake bit to allow the 2109 * mac to go to sleep. 2110 */ 2111 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2112 2113 if (ath9k_hw_mci_is_enabled(ah)) 2114 udelay(100); 2115 2116 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2117 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2118 2119 /* Shutdown chip. Active low */ 2120 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { 2121 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 2122 udelay(2); 2123 } 2124 2125 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 2126 if (AR_SREV_9300_20_OR_LATER(ah)) 2127 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2128 } 2129 2130 /* 2131 * Notify Power Management is enabled in self-generating 2132 * frames. If request, set power mode of chip to 2133 * auto/normal. Duration in units of 128us (1/8 TU). 2134 */ 2135 static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2136 { 2137 struct ath9k_hw_capabilities *pCap = &ah->caps; 2138 2139 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2140 2141 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 2142 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 2143 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 2144 AR_RTC_FORCE_WAKE_ON_INT); 2145 } else { 2146 2147 /* When chip goes into network sleep, it could be waken 2148 * up by MCI_INT interrupt caused by BT's HW messages 2149 * (LNA_xxx, CONT_xxx) which chould be in a very fast 2150 * rate (~100us). This will cause chip to leave and 2151 * re-enter network sleep mode frequently, which in 2152 * consequence will have WLAN MCI HW to generate lots of 2153 * SYS_WAKING and SYS_SLEEPING messages which will make 2154 * BT CPU to busy to process. 2155 */ 2156 if (ath9k_hw_mci_is_enabled(ah)) 2157 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 2158 AR_MCI_INTERRUPT_RX_HW_MSG_MASK); 2159 /* 2160 * Clear the RTC force wake bit to allow the 2161 * mac to go to sleep. 2162 */ 2163 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2164 2165 if (ath9k_hw_mci_is_enabled(ah)) 2166 udelay(30); 2167 } 2168 2169 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 2170 if (AR_SREV_9300_20_OR_LATER(ah)) 2171 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 2172 } 2173 2174 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) 2175 { 2176 u32 val; 2177 int i; 2178 2179 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 2180 if (AR_SREV_9300_20_OR_LATER(ah)) { 2181 REG_WRITE(ah, AR_WA, ah->WARegVal); 2182 udelay(10); 2183 } 2184 2185 if ((REG_READ(ah, AR_RTC_STATUS) & 2186 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 2187 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 2188 return false; 2189 } 2190 if (!AR_SREV_9300_20_OR_LATER(ah)) 2191 ath9k_hw_init_pll(ah, NULL); 2192 } 2193 if (AR_SREV_9100(ah)) 2194 REG_SET_BIT(ah, AR_RTC_RESET, 2195 AR_RTC_RESET_EN); 2196 2197 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2198 AR_RTC_FORCE_WAKE_EN); 2199 udelay(50); 2200 2201 for (i = POWER_UP_TIME / 50; i > 0; i--) { 2202 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 2203 if (val == AR_RTC_STATUS_ON) 2204 break; 2205 udelay(50); 2206 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 2207 AR_RTC_FORCE_WAKE_EN); 2208 } 2209 if (i == 0) { 2210 ath_err(ath9k_hw_common(ah), 2211 "Failed to wakeup in %uus\n", 2212 POWER_UP_TIME / 20); 2213 return false; 2214 } 2215 2216 if (ath9k_hw_mci_is_enabled(ah)) 2217 ar9003_mci_set_power_awake(ah); 2218 2219 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2220 2221 return true; 2222 } 2223 2224 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 2225 { 2226 struct ath_common *common = ath9k_hw_common(ah); 2227 int status = true; 2228 static const char *modes[] = { 2229 "AWAKE", 2230 "FULL-SLEEP", 2231 "NETWORK SLEEP", 2232 "UNDEFINED" 2233 }; 2234 2235 if (ah->power_mode == mode) 2236 return status; 2237 2238 ath_dbg(common, RESET, "%s -> %s\n", 2239 modes[ah->power_mode], modes[mode]); 2240 2241 switch (mode) { 2242 case ATH9K_PM_AWAKE: 2243 status = ath9k_hw_set_power_awake(ah); 2244 break; 2245 case ATH9K_PM_FULL_SLEEP: 2246 if (ath9k_hw_mci_is_enabled(ah)) 2247 ar9003_mci_set_full_sleep(ah); 2248 2249 ath9k_set_power_sleep(ah); 2250 ah->chip_fullsleep = true; 2251 break; 2252 case ATH9K_PM_NETWORK_SLEEP: 2253 ath9k_set_power_network_sleep(ah); 2254 break; 2255 default: 2256 ath_err(common, "Unknown power mode %u\n", mode); 2257 return false; 2258 } 2259 ah->power_mode = mode; 2260 2261 /* 2262 * XXX: If this warning never comes up after a while then 2263 * simply keep the ATH_DBG_WARN_ON_ONCE() but make 2264 * ath9k_hw_setpower() return type void. 2265 */ 2266 2267 if (!(ah->ah_flags & AH_UNPLUGGED)) 2268 ATH_DBG_WARN_ON_ONCE(!status); 2269 2270 return status; 2271 } 2272 EXPORT_SYMBOL(ath9k_hw_setpower); 2273 2274 /*******************/ 2275 /* Beacon Handling */ 2276 /*******************/ 2277 2278 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 2279 { 2280 int flags = 0; 2281 2282 ENABLE_REGWRITE_BUFFER(ah); 2283 2284 switch (ah->opmode) { 2285 case NL80211_IFTYPE_ADHOC: 2286 REG_SET_BIT(ah, AR_TXCFG, 2287 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 2288 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + 2289 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); 2290 flags |= AR_NDP_TIMER_EN; 2291 case NL80211_IFTYPE_MESH_POINT: 2292 case NL80211_IFTYPE_AP: 2293 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); 2294 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - 2295 TU_TO_USEC(ah->config.dma_beacon_response_time)); 2296 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - 2297 TU_TO_USEC(ah->config.sw_beacon_response_time)); 2298 flags |= 2299 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 2300 break; 2301 default: 2302 ath_dbg(ath9k_hw_common(ah), BEACON, 2303 "%s: unsupported opmode: %d\n", __func__, ah->opmode); 2304 return; 2305 break; 2306 } 2307 2308 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); 2309 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); 2310 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); 2311 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); 2312 2313 REGWRITE_BUFFER_FLUSH(ah); 2314 2315 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 2316 } 2317 EXPORT_SYMBOL(ath9k_hw_beaconinit); 2318 2319 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 2320 const struct ath9k_beacon_state *bs) 2321 { 2322 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 2323 struct ath9k_hw_capabilities *pCap = &ah->caps; 2324 struct ath_common *common = ath9k_hw_common(ah); 2325 2326 ENABLE_REGWRITE_BUFFER(ah); 2327 2328 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 2329 2330 REG_WRITE(ah, AR_BEACON_PERIOD, 2331 TU_TO_USEC(bs->bs_intval)); 2332 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 2333 TU_TO_USEC(bs->bs_intval)); 2334 2335 REGWRITE_BUFFER_FLUSH(ah); 2336 2337 REG_RMW_FIELD(ah, AR_RSSI_THR, 2338 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 2339 2340 beaconintval = bs->bs_intval; 2341 2342 if (bs->bs_sleepduration > beaconintval) 2343 beaconintval = bs->bs_sleepduration; 2344 2345 dtimperiod = bs->bs_dtimperiod; 2346 if (bs->bs_sleepduration > dtimperiod) 2347 dtimperiod = bs->bs_sleepduration; 2348 2349 if (beaconintval == dtimperiod) 2350 nextTbtt = bs->bs_nextdtim; 2351 else 2352 nextTbtt = bs->bs_nexttbtt; 2353 2354 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2355 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); 2356 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); 2357 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); 2358 2359 ENABLE_REGWRITE_BUFFER(ah); 2360 2361 REG_WRITE(ah, AR_NEXT_DTIM, 2362 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2363 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2364 2365 REG_WRITE(ah, AR_SLEEP1, 2366 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2367 | AR_SLEEP1_ASSUME_DTIM); 2368 2369 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2370 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2371 else 2372 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2373 2374 REG_WRITE(ah, AR_SLEEP2, 2375 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2376 2377 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2378 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2379 2380 REGWRITE_BUFFER_FLUSH(ah); 2381 2382 REG_SET_BIT(ah, AR_TIMER_MODE, 2383 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2384 AR_DTIM_TIMER_EN); 2385 2386 /* TSF Out of Range Threshold */ 2387 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2388 } 2389 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2390 2391 /*******************/ 2392 /* HW Capabilities */ 2393 /*******************/ 2394 2395 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) 2396 { 2397 eeprom_chainmask &= chip_chainmask; 2398 if (eeprom_chainmask) 2399 return eeprom_chainmask; 2400 else 2401 return chip_chainmask; 2402 } 2403 2404 /** 2405 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset 2406 * @ah: the atheros hardware data structure 2407 * 2408 * We enable DFS support upstream on chipsets which have passed a series 2409 * of tests. The testing requirements are going to be documented. Desired 2410 * test requirements are documented at: 2411 * 2412 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs 2413 * 2414 * Once a new chipset gets properly tested an individual commit can be used 2415 * to document the testing for DFS for that chipset. 2416 */ 2417 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) 2418 { 2419 2420 switch (ah->hw_version.macVersion) { 2421 /* for temporary testing DFS with 9280 */ 2422 case AR_SREV_VERSION_9280: 2423 /* AR9580 will likely be our first target to get testing on */ 2424 case AR_SREV_VERSION_9580: 2425 return true; 2426 default: 2427 return false; 2428 } 2429 } 2430 2431 int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2432 { 2433 struct ath9k_hw_capabilities *pCap = &ah->caps; 2434 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2435 struct ath_common *common = ath9k_hw_common(ah); 2436 unsigned int chip_chainmask; 2437 2438 u16 eeval; 2439 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2440 2441 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2442 regulatory->current_rd = eeval; 2443 2444 if (ah->opmode != NL80211_IFTYPE_AP && 2445 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2446 if (regulatory->current_rd == 0x64 || 2447 regulatory->current_rd == 0x65) 2448 regulatory->current_rd += 5; 2449 else if (regulatory->current_rd == 0x41) 2450 regulatory->current_rd = 0x43; 2451 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", 2452 regulatory->current_rd); 2453 } 2454 2455 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2456 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2457 ath_err(common, 2458 "no band has been marked as supported in EEPROM\n"); 2459 return -EINVAL; 2460 } 2461 2462 if (eeval & AR5416_OPFLAGS_11A) 2463 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; 2464 2465 if (eeval & AR5416_OPFLAGS_11G) 2466 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2467 2468 if (AR_SREV_9485(ah) || 2469 AR_SREV_9285(ah) || 2470 AR_SREV_9330(ah) || 2471 AR_SREV_9565(ah)) 2472 chip_chainmask = 1; 2473 else if (AR_SREV_9462(ah)) 2474 chip_chainmask = 3; 2475 else if (!AR_SREV_9280_20_OR_LATER(ah)) 2476 chip_chainmask = 7; 2477 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) 2478 chip_chainmask = 3; 2479 else 2480 chip_chainmask = 7; 2481 2482 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2483 /* 2484 * For AR9271 we will temporarilly uses the rx chainmax as read from 2485 * the EEPROM. 2486 */ 2487 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2488 !(eeval & AR5416_OPFLAGS_11A) && 2489 !(AR_SREV_9271(ah))) 2490 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2491 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2492 else if (AR_SREV_9100(ah)) 2493 pCap->rx_chainmask = 0x7; 2494 else 2495 /* Use rx_chainmask from EEPROM. */ 2496 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2497 2498 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); 2499 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); 2500 ah->txchainmask = pCap->tx_chainmask; 2501 ah->rxchainmask = pCap->rx_chainmask; 2502 2503 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2504 2505 /* enable key search for every frame in an aggregate */ 2506 if (AR_SREV_9300_20_OR_LATER(ah)) 2507 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; 2508 2509 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; 2510 2511 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 2512 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2513 else 2514 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2515 2516 if (AR_SREV_9271(ah)) 2517 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2518 else if (AR_DEVID_7010(ah)) 2519 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2520 else if (AR_SREV_9300_20_OR_LATER(ah)) 2521 pCap->num_gpio_pins = AR9300_NUM_GPIO; 2522 else if (AR_SREV_9287_11_OR_LATER(ah)) 2523 pCap->num_gpio_pins = AR9287_NUM_GPIO; 2524 else if (AR_SREV_9285_12_OR_LATER(ah)) 2525 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2526 else if (AR_SREV_9280_20_OR_LATER(ah)) 2527 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2528 else 2529 pCap->num_gpio_pins = AR_NUM_GPIO; 2530 2531 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) 2532 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2533 else 2534 pCap->rts_aggr_limit = (8 * 1024); 2535 2536 #ifdef CONFIG_ATH9K_RFKILL 2537 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2538 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2539 ah->rfkill_gpio = 2540 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2541 ah->rfkill_polarity = 2542 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2543 2544 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2545 } 2546 #endif 2547 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2548 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2549 else 2550 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2551 2552 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2553 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2554 else 2555 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2556 2557 if (AR_SREV_9300_20_OR_LATER(ah)) { 2558 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2559 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) 2560 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2561 2562 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2563 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2564 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2565 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2566 pCap->txs_len = sizeof(struct ar9003_txs); 2567 } else { 2568 pCap->tx_desc_len = sizeof(struct ath_desc); 2569 if (AR_SREV_9280_20(ah)) 2570 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2571 } 2572 2573 if (AR_SREV_9300_20_OR_LATER(ah)) 2574 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2575 2576 if (AR_SREV_9300_20_OR_LATER(ah)) 2577 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); 2578 2579 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) 2580 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2581 2582 if (AR_SREV_9285(ah)) { 2583 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { 2584 ant_div_ctl1 = 2585 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2586 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { 2587 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2588 ath_info(common, "Enable LNA combining\n"); 2589 } 2590 } 2591 } 2592 2593 if (AR_SREV_9300_20_OR_LATER(ah)) { 2594 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) 2595 pCap->hw_caps |= ATH9K_HW_CAP_APM; 2596 } 2597 2598 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { 2599 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2600 if ((ant_div_ctl1 >> 0x6) == 0x3) { 2601 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; 2602 ath_info(common, "Enable LNA combining\n"); 2603 } 2604 } 2605 2606 if (ath9k_hw_dfs_tested(ah)) 2607 pCap->hw_caps |= ATH9K_HW_CAP_DFS; 2608 2609 tx_chainmask = pCap->tx_chainmask; 2610 rx_chainmask = pCap->rx_chainmask; 2611 while (tx_chainmask || rx_chainmask) { 2612 if (tx_chainmask & BIT(0)) 2613 pCap->max_txchains++; 2614 if (rx_chainmask & BIT(0)) 2615 pCap->max_rxchains++; 2616 2617 tx_chainmask >>= 1; 2618 rx_chainmask >>= 1; 2619 } 2620 2621 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 2622 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) 2623 pCap->hw_caps |= ATH9K_HW_CAP_MCI; 2624 2625 if (AR_SREV_9462_20_OR_LATER(ah)) 2626 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2627 } 2628 2629 if (AR_SREV_9462(ah)) 2630 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE; 2631 2632 if (AR_SREV_9300_20_OR_LATER(ah) && 2633 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2634 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2635 2636 /* 2637 * Fast channel change across bands is available 2638 * only for AR9462 and AR9565. 2639 */ 2640 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2641 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH; 2642 2643 return 0; 2644 } 2645 2646 /****************************/ 2647 /* GPIO / RFKILL / Antennae */ 2648 /****************************/ 2649 2650 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2651 u32 gpio, u32 type) 2652 { 2653 int addr; 2654 u32 gpio_shift, tmp; 2655 2656 if (gpio > 11) 2657 addr = AR_GPIO_OUTPUT_MUX3; 2658 else if (gpio > 5) 2659 addr = AR_GPIO_OUTPUT_MUX2; 2660 else 2661 addr = AR_GPIO_OUTPUT_MUX1; 2662 2663 gpio_shift = (gpio % 6) * 5; 2664 2665 if (AR_SREV_9280_20_OR_LATER(ah) 2666 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2667 REG_RMW(ah, addr, (type << gpio_shift), 2668 (0x1f << gpio_shift)); 2669 } else { 2670 tmp = REG_READ(ah, addr); 2671 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2672 tmp &= ~(0x1f << gpio_shift); 2673 tmp |= (type << gpio_shift); 2674 REG_WRITE(ah, addr, tmp); 2675 } 2676 } 2677 2678 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2679 { 2680 u32 gpio_shift; 2681 2682 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2683 2684 if (AR_DEVID_7010(ah)) { 2685 gpio_shift = gpio; 2686 REG_RMW(ah, AR7010_GPIO_OE, 2687 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2688 (AR7010_GPIO_OE_MASK << gpio_shift)); 2689 return; 2690 } 2691 2692 gpio_shift = gpio << 1; 2693 REG_RMW(ah, 2694 AR_GPIO_OE_OUT, 2695 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2696 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2697 } 2698 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2699 2700 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2701 { 2702 #define MS_REG_READ(x, y) \ 2703 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2704 2705 if (gpio >= ah->caps.num_gpio_pins) 2706 return 0xffffffff; 2707 2708 if (AR_DEVID_7010(ah)) { 2709 u32 val; 2710 val = REG_READ(ah, AR7010_GPIO_IN); 2711 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2712 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2713 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2714 AR_GPIO_BIT(gpio)) != 0; 2715 else if (AR_SREV_9271(ah)) 2716 return MS_REG_READ(AR9271, gpio) != 0; 2717 else if (AR_SREV_9287_11_OR_LATER(ah)) 2718 return MS_REG_READ(AR9287, gpio) != 0; 2719 else if (AR_SREV_9285_12_OR_LATER(ah)) 2720 return MS_REG_READ(AR9285, gpio) != 0; 2721 else if (AR_SREV_9280_20_OR_LATER(ah)) 2722 return MS_REG_READ(AR928X, gpio) != 0; 2723 else 2724 return MS_REG_READ(AR, gpio) != 0; 2725 } 2726 EXPORT_SYMBOL(ath9k_hw_gpio_get); 2727 2728 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2729 u32 ah_signal_type) 2730 { 2731 u32 gpio_shift; 2732 2733 if (AR_DEVID_7010(ah)) { 2734 gpio_shift = gpio; 2735 REG_RMW(ah, AR7010_GPIO_OE, 2736 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2737 (AR7010_GPIO_OE_MASK << gpio_shift)); 2738 return; 2739 } 2740 2741 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2742 gpio_shift = 2 * gpio; 2743 REG_RMW(ah, 2744 AR_GPIO_OE_OUT, 2745 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2746 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2747 } 2748 EXPORT_SYMBOL(ath9k_hw_cfg_output); 2749 2750 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2751 { 2752 if (AR_DEVID_7010(ah)) { 2753 val = val ? 0 : 1; 2754 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2755 AR_GPIO_BIT(gpio)); 2756 return; 2757 } 2758 2759 if (AR_SREV_9271(ah)) 2760 val = ~val; 2761 2762 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2763 AR_GPIO_BIT(gpio)); 2764 } 2765 EXPORT_SYMBOL(ath9k_hw_set_gpio); 2766 2767 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2768 { 2769 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2770 } 2771 EXPORT_SYMBOL(ath9k_hw_setantenna); 2772 2773 /*********************/ 2774 /* General Operation */ 2775 /*********************/ 2776 2777 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2778 { 2779 u32 bits = REG_READ(ah, AR_RX_FILTER); 2780 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2781 2782 if (phybits & AR_PHY_ERR_RADAR) 2783 bits |= ATH9K_RX_FILTER_PHYRADAR; 2784 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2785 bits |= ATH9K_RX_FILTER_PHYERR; 2786 2787 return bits; 2788 } 2789 EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2790 2791 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2792 { 2793 u32 phybits; 2794 2795 ENABLE_REGWRITE_BUFFER(ah); 2796 2797 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) 2798 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2799 2800 REG_WRITE(ah, AR_RX_FILTER, bits); 2801 2802 phybits = 0; 2803 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2804 phybits |= AR_PHY_ERR_RADAR; 2805 if (bits & ATH9K_RX_FILTER_PHYERR) 2806 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2807 REG_WRITE(ah, AR_PHY_ERR, phybits); 2808 2809 if (phybits) 2810 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2811 else 2812 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); 2813 2814 REGWRITE_BUFFER_FLUSH(ah); 2815 } 2816 EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2817 2818 bool ath9k_hw_phy_disable(struct ath_hw *ah) 2819 { 2820 if (ath9k_hw_mci_is_enabled(ah)) 2821 ar9003_mci_bt_gain_ctrl(ah); 2822 2823 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2824 return false; 2825 2826 ath9k_hw_init_pll(ah, NULL); 2827 ah->htc_reset_init = true; 2828 return true; 2829 } 2830 EXPORT_SYMBOL(ath9k_hw_phy_disable); 2831 2832 bool ath9k_hw_disable(struct ath_hw *ah) 2833 { 2834 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2835 return false; 2836 2837 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2838 return false; 2839 2840 ath9k_hw_init_pll(ah, NULL); 2841 return true; 2842 } 2843 EXPORT_SYMBOL(ath9k_hw_disable); 2844 2845 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) 2846 { 2847 enum eeprom_param gain_param; 2848 2849 if (IS_CHAN_2GHZ(chan)) 2850 gain_param = EEP_ANTENNA_GAIN_2G; 2851 else 2852 gain_param = EEP_ANTENNA_GAIN_5G; 2853 2854 return ah->eep_ops->get_eeprom(ah, gain_param); 2855 } 2856 2857 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, 2858 bool test) 2859 { 2860 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2861 struct ieee80211_channel *channel; 2862 int chan_pwr, new_pwr, max_gain; 2863 int ant_gain, ant_reduction = 0; 2864 2865 if (!chan) 2866 return; 2867 2868 channel = chan->chan; 2869 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); 2870 new_pwr = min_t(int, chan_pwr, reg->power_limit); 2871 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; 2872 2873 ant_gain = get_antenna_gain(ah, chan); 2874 if (ant_gain > max_gain) 2875 ant_reduction = ant_gain - max_gain; 2876 2877 ah->eep_ops->set_txpower(ah, chan, 2878 ath9k_regd_get_ctl(reg, chan), 2879 ant_reduction, new_pwr, test); 2880 } 2881 2882 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) 2883 { 2884 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); 2885 struct ath9k_channel *chan = ah->curchan; 2886 struct ieee80211_channel *channel = chan->chan; 2887 2888 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); 2889 if (test) 2890 channel->max_power = MAX_RATE_POWER / 2; 2891 2892 ath9k_hw_apply_txpower(ah, chan, test); 2893 2894 if (test) 2895 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); 2896 } 2897 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2898 2899 void ath9k_hw_setopmode(struct ath_hw *ah) 2900 { 2901 ath9k_hw_set_operating_mode(ah, ah->opmode); 2902 } 2903 EXPORT_SYMBOL(ath9k_hw_setopmode); 2904 2905 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2906 { 2907 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2908 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2909 } 2910 EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2911 2912 void ath9k_hw_write_associd(struct ath_hw *ah) 2913 { 2914 struct ath_common *common = ath9k_hw_common(ah); 2915 2916 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2917 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2918 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2919 } 2920 EXPORT_SYMBOL(ath9k_hw_write_associd); 2921 2922 #define ATH9K_MAX_TSF_READ 10 2923 2924 u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2925 { 2926 u32 tsf_lower, tsf_upper1, tsf_upper2; 2927 int i; 2928 2929 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2930 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2931 tsf_lower = REG_READ(ah, AR_TSF_L32); 2932 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2933 if (tsf_upper2 == tsf_upper1) 2934 break; 2935 tsf_upper1 = tsf_upper2; 2936 } 2937 2938 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2939 2940 return (((u64)tsf_upper1 << 32) | tsf_lower); 2941 } 2942 EXPORT_SYMBOL(ath9k_hw_gettsf64); 2943 2944 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2945 { 2946 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2947 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2948 } 2949 EXPORT_SYMBOL(ath9k_hw_settsf64); 2950 2951 void ath9k_hw_reset_tsf(struct ath_hw *ah) 2952 { 2953 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2954 AH_TSF_WRITE_TIMEOUT)) 2955 ath_dbg(ath9k_hw_common(ah), RESET, 2956 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2957 2958 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2959 } 2960 EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2961 2962 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) 2963 { 2964 if (set) 2965 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2966 else 2967 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2968 } 2969 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2970 2971 void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2972 { 2973 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2974 u32 macmode; 2975 2976 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2977 macmode = AR_2040_JOINED_RX_CLEAR; 2978 else 2979 macmode = 0; 2980 2981 REG_WRITE(ah, AR_2040_MODE, macmode); 2982 } 2983 2984 /* HW Generic timers configuration */ 2985 2986 static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2987 { 2988 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2989 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2990 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2991 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2992 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2993 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2994 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2995 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2996 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2997 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2998 AR_NDP2_TIMER_MODE, 0x0002}, 2999 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 3000 AR_NDP2_TIMER_MODE, 0x0004}, 3001 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 3002 AR_NDP2_TIMER_MODE, 0x0008}, 3003 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 3004 AR_NDP2_TIMER_MODE, 0x0010}, 3005 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 3006 AR_NDP2_TIMER_MODE, 0x0020}, 3007 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 3008 AR_NDP2_TIMER_MODE, 0x0040}, 3009 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 3010 AR_NDP2_TIMER_MODE, 0x0080} 3011 }; 3012 3013 /* HW generic timer primitives */ 3014 3015 /* compute and clear index of rightmost 1 */ 3016 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 3017 { 3018 u32 b; 3019 3020 b = *mask; 3021 b &= (0-b); 3022 *mask &= ~b; 3023 b *= debruijn32; 3024 b >>= 27; 3025 3026 return timer_table->gen_timer_index[b]; 3027 } 3028 3029 u32 ath9k_hw_gettsf32(struct ath_hw *ah) 3030 { 3031 return REG_READ(ah, AR_TSF_L32); 3032 } 3033 EXPORT_SYMBOL(ath9k_hw_gettsf32); 3034 3035 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 3036 void (*trigger)(void *), 3037 void (*overflow)(void *), 3038 void *arg, 3039 u8 timer_index) 3040 { 3041 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3042 struct ath_gen_timer *timer; 3043 3044 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 3045 if (timer == NULL) 3046 return NULL; 3047 3048 /* allocate a hardware generic timer slot */ 3049 timer_table->timers[timer_index] = timer; 3050 timer->index = timer_index; 3051 timer->trigger = trigger; 3052 timer->overflow = overflow; 3053 timer->arg = arg; 3054 3055 return timer; 3056 } 3057 EXPORT_SYMBOL(ath_gen_timer_alloc); 3058 3059 void ath9k_hw_gen_timer_start(struct ath_hw *ah, 3060 struct ath_gen_timer *timer, 3061 u32 trig_timeout, 3062 u32 timer_period) 3063 { 3064 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3065 u32 tsf, timer_next; 3066 3067 BUG_ON(!timer_period); 3068 3069 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 3070 3071 tsf = ath9k_hw_gettsf32(ah); 3072 3073 timer_next = tsf + trig_timeout; 3074 3075 ath_dbg(ath9k_hw_common(ah), BTCOEX, 3076 "current tsf %x period %x timer_next %x\n", 3077 tsf, timer_period, timer_next); 3078 3079 /* 3080 * Program generic timer registers 3081 */ 3082 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 3083 timer_next); 3084 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 3085 timer_period); 3086 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3087 gen_tmr_configuration[timer->index].mode_mask); 3088 3089 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3090 /* 3091 * Starting from AR9462, each generic timer can select which tsf 3092 * to use. But we still follow the old rule, 0 - 7 use tsf and 3093 * 8 - 15 use tsf2. 3094 */ 3095 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) 3096 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3097 (1 << timer->index)); 3098 else 3099 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3100 (1 << timer->index)); 3101 } 3102 3103 /* Enable both trigger and thresh interrupt masks */ 3104 REG_SET_BIT(ah, AR_IMR_S5, 3105 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3106 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3107 } 3108 EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 3109 3110 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 3111 { 3112 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3113 3114 if ((timer->index < AR_FIRST_NDP_TIMER) || 3115 (timer->index >= ATH_MAX_GEN_TIMER)) { 3116 return; 3117 } 3118 3119 /* Clear generic timer enable bits. */ 3120 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 3121 gen_tmr_configuration[timer->index].mode_mask); 3122 3123 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { 3124 /* 3125 * Need to switch back to TSF if it was using TSF2. 3126 */ 3127 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { 3128 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, 3129 (1 << timer->index)); 3130 } 3131 } 3132 3133 /* Disable both trigger and thresh interrupt masks */ 3134 REG_CLR_BIT(ah, AR_IMR_S5, 3135 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 3136 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 3137 3138 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 3139 } 3140 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 3141 3142 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 3143 { 3144 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3145 3146 /* free the hardware generic timer slot */ 3147 timer_table->timers[timer->index] = NULL; 3148 kfree(timer); 3149 } 3150 EXPORT_SYMBOL(ath_gen_timer_free); 3151 3152 /* 3153 * Generic Timer Interrupts handling 3154 */ 3155 void ath_gen_timer_isr(struct ath_hw *ah) 3156 { 3157 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 3158 struct ath_gen_timer *timer; 3159 struct ath_common *common = ath9k_hw_common(ah); 3160 u32 trigger_mask, thresh_mask, index; 3161 3162 /* get hardware generic timer interrupt status */ 3163 trigger_mask = ah->intr_gen_timer_trigger; 3164 thresh_mask = ah->intr_gen_timer_thresh; 3165 trigger_mask &= timer_table->timer_mask.val; 3166 thresh_mask &= timer_table->timer_mask.val; 3167 3168 trigger_mask &= ~thresh_mask; 3169 3170 while (thresh_mask) { 3171 index = rightmost_index(timer_table, &thresh_mask); 3172 timer = timer_table->timers[index]; 3173 BUG_ON(!timer); 3174 ath_dbg(common, BTCOEX, "TSF overflow for Gen timer %d\n", 3175 index); 3176 timer->overflow(timer->arg); 3177 } 3178 3179 while (trigger_mask) { 3180 index = rightmost_index(timer_table, &trigger_mask); 3181 timer = timer_table->timers[index]; 3182 BUG_ON(!timer); 3183 ath_dbg(common, BTCOEX, 3184 "Gen timer[%d] trigger\n", index); 3185 timer->trigger(timer->arg); 3186 } 3187 } 3188 EXPORT_SYMBOL(ath_gen_timer_isr); 3189 3190 /********/ 3191 /* HTC */ 3192 /********/ 3193 3194 static struct { 3195 u32 version; 3196 const char * name; 3197 } ath_mac_bb_names[] = { 3198 /* Devices with external radios */ 3199 { AR_SREV_VERSION_5416_PCI, "5416" }, 3200 { AR_SREV_VERSION_5416_PCIE, "5418" }, 3201 { AR_SREV_VERSION_9100, "9100" }, 3202 { AR_SREV_VERSION_9160, "9160" }, 3203 /* Single-chip solutions */ 3204 { AR_SREV_VERSION_9280, "9280" }, 3205 { AR_SREV_VERSION_9285, "9285" }, 3206 { AR_SREV_VERSION_9287, "9287" }, 3207 { AR_SREV_VERSION_9271, "9271" }, 3208 { AR_SREV_VERSION_9300, "9300" }, 3209 { AR_SREV_VERSION_9330, "9330" }, 3210 { AR_SREV_VERSION_9340, "9340" }, 3211 { AR_SREV_VERSION_9485, "9485" }, 3212 { AR_SREV_VERSION_9462, "9462" }, 3213 { AR_SREV_VERSION_9550, "9550" }, 3214 { AR_SREV_VERSION_9565, "9565" }, 3215 }; 3216 3217 /* For devices with external radios */ 3218 static struct { 3219 u16 version; 3220 const char * name; 3221 } ath_rf_names[] = { 3222 { 0, "5133" }, 3223 { AR_RAD5133_SREV_MAJOR, "5133" }, 3224 { AR_RAD5122_SREV_MAJOR, "5122" }, 3225 { AR_RAD2133_SREV_MAJOR, "2133" }, 3226 { AR_RAD2122_SREV_MAJOR, "2122" } 3227 }; 3228 3229 /* 3230 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 3231 */ 3232 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 3233 { 3234 int i; 3235 3236 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 3237 if (ath_mac_bb_names[i].version == mac_bb_version) { 3238 return ath_mac_bb_names[i].name; 3239 } 3240 } 3241 3242 return "????"; 3243 } 3244 3245 /* 3246 * Return the RF name. "????" is returned if the RF is unknown. 3247 * Used for devices with external radios. 3248 */ 3249 static const char *ath9k_hw_rf_name(u16 rf_version) 3250 { 3251 int i; 3252 3253 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 3254 if (ath_rf_names[i].version == rf_version) { 3255 return ath_rf_names[i].name; 3256 } 3257 } 3258 3259 return "????"; 3260 } 3261 3262 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 3263 { 3264 int used; 3265 3266 /* chipsets >= AR9280 are single-chip */ 3267 if (AR_SREV_9280_20_OR_LATER(ah)) { 3268 used = scnprintf(hw_name, len, 3269 "Atheros AR%s Rev:%x", 3270 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3271 ah->hw_version.macRev); 3272 } 3273 else { 3274 used = scnprintf(hw_name, len, 3275 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 3276 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 3277 ah->hw_version.macRev, 3278 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev 3279 & AR_RADIO_SREV_MAJOR)), 3280 ah->hw_version.phyRev); 3281 } 3282 3283 hw_name[used] = '\0'; 3284 } 3285 EXPORT_SYMBOL(ath9k_hw_name); 3286