1203c4805SLuis R. Rodriguez /* 25b68138eSSujith Manoharan * Copyright (c) 2008-2011 Atheros Communications Inc. 3203c4805SLuis R. Rodriguez * 4203c4805SLuis R. Rodriguez * Permission to use, copy, modify, and/or distribute this software for any 5203c4805SLuis R. Rodriguez * purpose with or without fee is hereby granted, provided that the above 6203c4805SLuis R. Rodriguez * copyright notice and this permission notice appear in all copies. 7203c4805SLuis R. Rodriguez * 8203c4805SLuis R. Rodriguez * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9203c4805SLuis R. Rodriguez * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10203c4805SLuis R. Rodriguez * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11203c4805SLuis R. Rodriguez * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12203c4805SLuis R. Rodriguez * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13203c4805SLuis R. Rodriguez * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14203c4805SLuis R. Rodriguez * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15203c4805SLuis R. Rodriguez */ 16203c4805SLuis R. Rodriguez 17203c4805SLuis R. Rodriguez #ifndef EEPROM_H 18203c4805SLuis R. Rodriguez #define EEPROM_H 19203c4805SLuis R. Rodriguez 204ddfcd7dSFelix Fietkau #define AR_EEPROM_MODAL_SPURS 5 214ddfcd7dSFelix Fietkau 225bb12791SLuis R. Rodriguez #include "../ath.h" 23d3236553SJohannes Berg #include <net/cfg80211.h> 2415c9ee7aSSenthil Balasubramanian #include "ar9003_eeprom.h" 25203c4805SLuis R. Rodriguez 264bca5303SMartin Blumenstingl /* helpers to swap EEPROM fields, which are stored as __le16 or __le32. Since 274bca5303SMartin Blumenstingl * we are 100% sure about it we __force these to u16/u32 for the swab calls to 284bca5303SMartin Blumenstingl * silence the sparse checks. These macros are used when we have a Big Endian 294bca5303SMartin Blumenstingl * EEPROM (according to AR5416_EEPMISC_BIG_ENDIAN) and need to convert the 304bca5303SMartin Blumenstingl * fields to __le16/__le32. 314bca5303SMartin Blumenstingl */ 324bca5303SMartin Blumenstingl #define EEPROM_FIELD_SWAB16(field) \ 334bca5303SMartin Blumenstingl (field = (__force __le16)swab16((__force u16)field)) 344bca5303SMartin Blumenstingl #define EEPROM_FIELD_SWAB32(field) \ 354bca5303SMartin Blumenstingl (field = (__force __le32)swab32((__force u32)field)) 364bca5303SMartin Blumenstingl 37203c4805SLuis R. Rodriguez #ifdef __BIG_ENDIAN 38203c4805SLuis R. Rodriguez #define AR5416_EEPROM_MAGIC 0x5aa5 39203c4805SLuis R. Rodriguez #else 40203c4805SLuis R. Rodriguez #define AR5416_EEPROM_MAGIC 0xa55a 41203c4805SLuis R. Rodriguez #endif 42203c4805SLuis R. Rodriguez 43203c4805SLuis R. Rodriguez #define CTRY_DEBUG 0x1ff 44203c4805SLuis R. Rodriguez #define CTRY_DEFAULT 0 45203c4805SLuis R. Rodriguez 46203c4805SLuis R. Rodriguez #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 47203c4805SLuis R. Rodriguez #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 48203c4805SLuis R. Rodriguez #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 49203c4805SLuis R. Rodriguez #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 50203c4805SLuis R. Rodriguez #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 51203c4805SLuis R. Rodriguez #define AR_EEPROM_EEPCAP_MAXQCU_S 4 52203c4805SLuis R. Rodriguez #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 53203c4805SLuis R. Rodriguez #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 54203c4805SLuis R. Rodriguez #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 55203c4805SLuis R. Rodriguez 56203c4805SLuis R. Rodriguez #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 57203c4805SLuis R. Rodriguez #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 58203c4805SLuis R. Rodriguez #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 59203c4805SLuis R. Rodriguez #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 60203c4805SLuis R. Rodriguez #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 61203c4805SLuis R. Rodriguez #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 62203c4805SLuis R. Rodriguez 63203c4805SLuis R. Rodriguez #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 64203c4805SLuis R. Rodriguez #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 65203c4805SLuis R. Rodriguez 66203c4805SLuis R. Rodriguez #define AR5416_EEPROM_MAGIC_OFFSET 0x0 67203c4805SLuis R. Rodriguez #define AR5416_EEPROM_S 2 68203c4805SLuis R. Rodriguez #define AR5416_EEPROM_OFFSET 0x2000 69203c4805SLuis R. Rodriguez #define AR5416_EEPROM_MAX 0xae0 70203c4805SLuis R. Rodriguez 71203c4805SLuis R. Rodriguez #define AR5416_EEPROM_START_ADDR \ 72203c4805SLuis R. Rodriguez (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 73203c4805SLuis R. Rodriguez 74203c4805SLuis R. Rodriguez #define SD_NO_CTL 0xE0 75203c4805SLuis R. Rodriguez #define NO_CTL 0xff 7690487974SLuis R. Rodriguez #define CTL_MODE_M 0xf 77203c4805SLuis R. Rodriguez #define CTL_11A 0 78203c4805SLuis R. Rodriguez #define CTL_11B 1 79203c4805SLuis R. Rodriguez #define CTL_11G 2 80203c4805SLuis R. Rodriguez #define CTL_2GHT20 5 81203c4805SLuis R. Rodriguez #define CTL_5GHT20 6 82203c4805SLuis R. Rodriguez #define CTL_2GHT40 7 83203c4805SLuis R. Rodriguez #define CTL_5GHT40 8 84203c4805SLuis R. Rodriguez 85203c4805SLuis R. Rodriguez #define EXT_ADDITIVE (0x8000) 86203c4805SLuis R. Rodriguez #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 87203c4805SLuis R. Rodriguez #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 88203c4805SLuis R. Rodriguez #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 89203c4805SLuis R. Rodriguez 90203c4805SLuis R. Rodriguez #define SUB_NUM_CTL_MODES_AT_5G_40 2 91203c4805SLuis R. Rodriguez #define SUB_NUM_CTL_MODES_AT_2G_40 3 92203c4805SLuis R. Rodriguez 936010e72cSGabor Juhos #define POWER_CORRECTION_FOR_TWO_CHAIN 6 /* 10*log10(2)*2 */ 946010e72cSGabor Juhos #define POWER_CORRECTION_FOR_THREE_CHAIN 10 /* 10*log10(3)*2 */ 95ea6f792bSGabor Juhos 96203c4805SLuis R. Rodriguez /* 97203c4805SLuis R. Rodriguez * For AR9285 and later chipsets, the following bits are not being programmed 98203c4805SLuis R. Rodriguez * in EEPROM and so need to be enabled always. 99203c4805SLuis R. Rodriguez * 100203c4805SLuis R. Rodriguez * Bit 0: en_fcc_mid 101203c4805SLuis R. Rodriguez * Bit 1: en_jap_mid 102203c4805SLuis R. Rodriguez * Bit 2: en_fcc_dfs_ht40 103203c4805SLuis R. Rodriguez * Bit 3: en_jap_ht40 104203c4805SLuis R. Rodriguez * Bit 4: en_jap_dfs_ht40 105203c4805SLuis R. Rodriguez */ 106203c4805SLuis R. Rodriguez #define AR9285_RDEXT_DEFAULT 0x1F 107203c4805SLuis R. Rodriguez 108203c4805SLuis R. Rodriguez #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 109*627871b7SMatthias Kaehlcke #define FREQ2FBIN(x, y) (u8)((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 110420e2b1bSRajkumar Manoharan #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) 111203c4805SLuis R. Rodriguez #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) 112203c4805SLuis R. Rodriguez 113203c4805SLuis R. Rodriguez #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ 114203c4805SLuis R. Rodriguez ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 115a42acef0SFelix Fietkau #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \ 116ac88b6ecSVivek Natarajan ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 117203c4805SLuis R. Rodriguez 118203c4805SLuis R. Rodriguez #define EEP_RFSILENT_ENABLED 0x0001 119203c4805SLuis R. Rodriguez #define EEP_RFSILENT_ENABLED_S 0 120203c4805SLuis R. Rodriguez #define EEP_RFSILENT_POLARITY 0x0002 121203c4805SLuis R. Rodriguez #define EEP_RFSILENT_POLARITY_S 1 122a4a2954fSSujith Manoharan #define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c) 123203c4805SLuis R. Rodriguez #define EEP_RFSILENT_GPIO_SEL_S 2 124203c4805SLuis R. Rodriguez 125203c4805SLuis R. Rodriguez #define AR5416_OPFLAGS_11A 0x01 126203c4805SLuis R. Rodriguez #define AR5416_OPFLAGS_11G 0x02 127203c4805SLuis R. Rodriguez #define AR5416_OPFLAGS_N_5G_HT40 0x04 128203c4805SLuis R. Rodriguez #define AR5416_OPFLAGS_N_2G_HT40 0x08 129203c4805SLuis R. Rodriguez #define AR5416_OPFLAGS_N_5G_HT20 0x10 130203c4805SLuis R. Rodriguez #define AR5416_OPFLAGS_N_2G_HT20 0x20 131203c4805SLuis R. Rodriguez 132203c4805SLuis R. Rodriguez #define AR5416_EEP_NO_BACK_VER 0x1 133203c4805SLuis R. Rodriguez #define AR5416_EEP_VER 0xE 1349bff7428SMartin Blumenstingl #define AR5416_EEP_VER_MAJOR_SHIFT 12 1359bff7428SMartin Blumenstingl #define AR5416_EEP_VER_MAJOR_MASK 0xF000 136203c4805SLuis R. Rodriguez #define AR5416_EEP_VER_MINOR_MASK 0x0FFF 137203c4805SLuis R. Rodriguez #define AR5416_EEP_MINOR_VER_2 0x2 138203c4805SLuis R. Rodriguez #define AR5416_EEP_MINOR_VER_3 0x3 139203c4805SLuis R. Rodriguez #define AR5416_EEP_MINOR_VER_7 0x7 140203c4805SLuis R. Rodriguez #define AR5416_EEP_MINOR_VER_9 0x9 141203c4805SLuis R. Rodriguez #define AR5416_EEP_MINOR_VER_16 0x10 142203c4805SLuis R. Rodriguez #define AR5416_EEP_MINOR_VER_17 0x11 143203c4805SLuis R. Rodriguez #define AR5416_EEP_MINOR_VER_19 0x13 144203c4805SLuis R. Rodriguez #define AR5416_EEP_MINOR_VER_20 0x14 145e41f0bfcSSenthil Balasubramanian #define AR5416_EEP_MINOR_VER_21 0x15 146203c4805SLuis R. Rodriguez #define AR5416_EEP_MINOR_VER_22 0x16 147203c4805SLuis R. Rodriguez 148203c4805SLuis R. Rodriguez #define AR5416_NUM_5G_CAL_PIERS 8 149203c4805SLuis R. Rodriguez #define AR5416_NUM_2G_CAL_PIERS 4 150203c4805SLuis R. Rodriguez #define AR5416_NUM_5G_20_TARGET_POWERS 8 151203c4805SLuis R. Rodriguez #define AR5416_NUM_5G_40_TARGET_POWERS 8 152203c4805SLuis R. Rodriguez #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 153203c4805SLuis R. Rodriguez #define AR5416_NUM_2G_20_TARGET_POWERS 4 154203c4805SLuis R. Rodriguez #define AR5416_NUM_2G_40_TARGET_POWERS 4 155203c4805SLuis R. Rodriguez #define AR5416_NUM_CTLS 24 156203c4805SLuis R. Rodriguez #define AR5416_NUM_BAND_EDGES 8 157203c4805SLuis R. Rodriguez #define AR5416_NUM_PD_GAINS 4 158203c4805SLuis R. Rodriguez #define AR5416_PD_GAINS_IN_MASK 4 159203c4805SLuis R. Rodriguez #define AR5416_PD_GAIN_ICEPTS 5 160203c4805SLuis R. Rodriguez #define AR5416_NUM_PDADC_VALUES 128 161203c4805SLuis R. Rodriguez #define AR5416_BCHAN_UNUSED 0xFF 162203c4805SLuis R. Rodriguez #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 163203c4805SLuis R. Rodriguez #define AR5416_MAX_CHAINS 3 164df23acaaSLuis R. Rodriguez #define AR9300_MAX_CHAINS 3 165e41f0bfcSSenthil Balasubramanian #define AR5416_PWR_TABLE_OFFSET_DB -5 166203c4805SLuis R. Rodriguez 167203c4805SLuis R. Rodriguez /* Rx gain type values */ 168203c4805SLuis R. Rodriguez #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 169203c4805SLuis R. Rodriguez #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 170203c4805SLuis R. Rodriguez #define AR5416_EEP_RXGAIN_ORIG 2 171203c4805SLuis R. Rodriguez 172203c4805SLuis R. Rodriguez /* Tx gain type values */ 173203c4805SLuis R. Rodriguez #define AR5416_EEP_TXGAIN_ORIGINAL 0 174203c4805SLuis R. Rodriguez #define AR5416_EEP_TXGAIN_HIGH_POWER 1 175203c4805SLuis R. Rodriguez 17681a834e3SMartin Blumenstingl /* Endianness of EEPROM content */ 17781a834e3SMartin Blumenstingl #define AR5416_EEPMISC_BIG_ENDIAN 0x01 17881a834e3SMartin Blumenstingl 179203c4805SLuis R. Rodriguez #define AR5416_EEP4K_START_LOC 64 180203c4805SLuis R. Rodriguez #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 181203c4805SLuis R. Rodriguez #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 182203c4805SLuis R. Rodriguez #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 183203c4805SLuis R. Rodriguez #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 184203c4805SLuis R. Rodriguez #define AR5416_EEP4K_NUM_CTLS 12 185203c4805SLuis R. Rodriguez #define AR5416_EEP4K_NUM_BAND_EDGES 4 186203c4805SLuis R. Rodriguez #define AR5416_EEP4K_NUM_PD_GAINS 2 187203c4805SLuis R. Rodriguez #define AR5416_EEP4K_MAX_CHAINS 1 188203c4805SLuis R. Rodriguez 189203c4805SLuis R. Rodriguez #define AR9280_TX_GAIN_TABLE_SIZE 22 190203c4805SLuis R. Rodriguez 191ac88b6ecSVivek Natarajan #define AR9287_EEP_VER 0xE 192ac88b6ecSVivek Natarajan #define AR9287_EEP_MINOR_VER_1 0x1 193ac88b6ecSVivek Natarajan #define AR9287_EEP_MINOR_VER_2 0x2 194ac88b6ecSVivek Natarajan #define AR9287_EEP_MINOR_VER_3 0x3 195ac88b6ecSVivek Natarajan #define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3 196ac88b6ecSVivek Natarajan #define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER 197ac88b6ecSVivek Natarajan #define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1 198ac88b6ecSVivek Natarajan 199ac88b6ecSVivek Natarajan #define AR9287_EEP_START_LOC 128 200ca6cff1fSRajkumar Manoharan #define AR9287_HTC_EEP_START_LOC 256 201ac88b6ecSVivek Natarajan #define AR9287_NUM_2G_CAL_PIERS 3 202ac88b6ecSVivek Natarajan #define AR9287_NUM_2G_CCK_TARGET_POWERS 3 203ac88b6ecSVivek Natarajan #define AR9287_NUM_2G_20_TARGET_POWERS 3 204ac88b6ecSVivek Natarajan #define AR9287_NUM_2G_40_TARGET_POWERS 3 205ac88b6ecSVivek Natarajan #define AR9287_NUM_CTLS 12 206ac88b6ecSVivek Natarajan #define AR9287_NUM_BAND_EDGES 4 207ac88b6ecSVivek Natarajan #define AR9287_PD_GAIN_ICEPTS 1 208ac88b6ecSVivek Natarajan #define AR9287_EEPMISC_WOW 0x02 209ac88b6ecSVivek Natarajan #define AR9287_MAX_CHAINS 2 210ac88b6ecSVivek Natarajan #define AR9287_ANT_16S 32 211ac88b6ecSVivek Natarajan 212ac88b6ecSVivek Natarajan #define AR9287_DATA_SZ 32 213ac88b6ecSVivek Natarajan 214ac88b6ecSVivek Natarajan #define AR9287_PWR_TABLE_OFFSET_DB -5 215ac88b6ecSVivek Natarajan 216ac88b6ecSVivek Natarajan #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1) 217ac88b6ecSVivek Natarajan 218e702ba18SFelix Fietkau #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f) 219e702ba18SFelix Fietkau #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03) 220e702ba18SFelix Fietkau 221f67e07ebSFelix Fietkau #define LNA_CTL_BUF_MODE BIT(0) 222f67e07ebSFelix Fietkau #define LNA_CTL_ISEL_LO BIT(1) 223f67e07ebSFelix Fietkau #define LNA_CTL_ISEL_HI BIT(2) 224f67e07ebSFelix Fietkau #define LNA_CTL_BUF_IN BIT(3) 225f67e07ebSFelix Fietkau #define LNA_CTL_FEM_BAND BIT(4) 226f67e07ebSFelix Fietkau #define LNA_CTL_LOCAL_BIAS BIT(5) 227f67e07ebSFelix Fietkau #define LNA_CTL_FORCE_XPA BIT(6) 228f67e07ebSFelix Fietkau #define LNA_CTL_USE_ANT1 BIT(7) 229f67e07ebSFelix Fietkau 230203c4805SLuis R. Rodriguez enum eeprom_param { 231203c4805SLuis R. Rodriguez EEP_NFTHRESH_5, 232203c4805SLuis R. Rodriguez EEP_NFTHRESH_2, 233203c4805SLuis R. Rodriguez EEP_MAC_MSW, 234203c4805SLuis R. Rodriguez EEP_MAC_MID, 235203c4805SLuis R. Rodriguez EEP_MAC_LSW, 236203c4805SLuis R. Rodriguez EEP_REG_0, 237203c4805SLuis R. Rodriguez EEP_OP_CAP, 238203c4805SLuis R. Rodriguez EEP_OP_MODE, 239203c4805SLuis R. Rodriguez EEP_RF_SILENT, 240203c4805SLuis R. Rodriguez EEP_OB_5, 241203c4805SLuis R. Rodriguez EEP_DB_5, 242203c4805SLuis R. Rodriguez EEP_OB_2, 243203c4805SLuis R. Rodriguez EEP_DB_2, 244203c4805SLuis R. Rodriguez EEP_TX_MASK, 245203c4805SLuis R. Rodriguez EEP_RX_MASK, 24615c9ee7aSSenthil Balasubramanian EEP_FSTCLK_5G, 247203c4805SLuis R. Rodriguez EEP_RXGAIN_TYPE, 248203c4805SLuis R. Rodriguez EEP_OL_PWRCTRL, 24915c9ee7aSSenthil Balasubramanian EEP_TXGAIN_TYPE, 250203c4805SLuis R. Rodriguez EEP_RC_CHAIN_MASK, 251203c4805SLuis R. Rodriguez EEP_DAC_HPWR_5G, 252ac88b6ecSVivek Natarajan EEP_FRAC_N_5G, 253ac88b6ecSVivek Natarajan EEP_DEV_TYPE, 254ac88b6ecSVivek Natarajan EEP_TEMPSENSE_SLOPE, 255ac88b6ecSVivek Natarajan EEP_TEMPSENSE_SLOPE_PAL_ON, 25615c9ee7aSSenthil Balasubramanian EEP_PWR_TABLE_OFFSET, 2574935250aSFelix Fietkau EEP_PAPRD, 258754dc536SVasanthakumar Thiagarajan EEP_MODAL_VER, 259754dc536SVasanthakumar Thiagarajan EEP_ANT_DIV_CTL1, 260ca2c68ccSFelix Fietkau EEP_CHAIN_MASK_REDUCE, 261ca2c68ccSFelix Fietkau EEP_ANTENNA_GAIN_2G, 262df222edcSRajkumar Manoharan EEP_ANTENNA_GAIN_5G, 263203c4805SLuis R. Rodriguez }; 264203c4805SLuis R. Rodriguez 265203c4805SLuis R. Rodriguez enum ar5416_rates { 266203c4805SLuis R. Rodriguez rate6mb, rate9mb, rate12mb, rate18mb, 267203c4805SLuis R. Rodriguez rate24mb, rate36mb, rate48mb, rate54mb, 268203c4805SLuis R. Rodriguez rate1l, rate2l, rate2s, rate5_5l, 269203c4805SLuis R. Rodriguez rate5_5s, rate11l, rate11s, rateXr, 270203c4805SLuis R. Rodriguez rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 271203c4805SLuis R. Rodriguez rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 272203c4805SLuis R. Rodriguez rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 273203c4805SLuis R. Rodriguez rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 274203c4805SLuis R. Rodriguez rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 275203c4805SLuis R. Rodriguez Ar5416RateSize 276203c4805SLuis R. Rodriguez }; 277203c4805SLuis R. Rodriguez 278203c4805SLuis R. Rodriguez enum ath9k_hal_freq_band { 279203c4805SLuis R. Rodriguez ATH9K_HAL_FREQ_BAND_5GHZ = 0, 280203c4805SLuis R. Rodriguez ATH9K_HAL_FREQ_BAND_2GHZ = 1 281203c4805SLuis R. Rodriguez }; 282203c4805SLuis R. Rodriguez 283203c4805SLuis R. Rodriguez struct base_eep_header { 2844bca5303SMartin Blumenstingl __le16 length; 2854bca5303SMartin Blumenstingl __le16 checksum; 2864bca5303SMartin Blumenstingl __le16 version; 287203c4805SLuis R. Rodriguez u8 opCapFlags; 288203c4805SLuis R. Rodriguez u8 eepMisc; 2894bca5303SMartin Blumenstingl __le16 regDmn[2]; 290203c4805SLuis R. Rodriguez u8 macAddr[6]; 291203c4805SLuis R. Rodriguez u8 rxMask; 292203c4805SLuis R. Rodriguez u8 txMask; 2934bca5303SMartin Blumenstingl __le16 rfSilent; 2944bca5303SMartin Blumenstingl __le16 blueToothOptions; 2954bca5303SMartin Blumenstingl __le16 deviceCap; 2964bca5303SMartin Blumenstingl __le32 binBuildNumber; 297203c4805SLuis R. Rodriguez u8 deviceType; 298203c4805SLuis R. Rodriguez u8 pwdclkind; 2995b75d0fcSFelix Fietkau u8 fastClk5g; 3005b75d0fcSFelix Fietkau u8 divChain; 301203c4805SLuis R. Rodriguez u8 rxGainType; 302203c4805SLuis R. Rodriguez u8 dacHiPwrMode_5G; 303203c4805SLuis R. Rodriguez u8 openLoopPwrCntl; 304203c4805SLuis R. Rodriguez u8 dacLpMode; 305203c4805SLuis R. Rodriguez u8 txGainType; 306203c4805SLuis R. Rodriguez u8 rcChainMask; 307203c4805SLuis R. Rodriguez u8 desiredScaleCCK; 308e41f0bfcSSenthil Balasubramanian u8 pwr_table_offset; 309203c4805SLuis R. Rodriguez u8 frac_n_5g; 310203c4805SLuis R. Rodriguez u8 futureBase_3[21]; 311203c4805SLuis R. Rodriguez } __packed; 312203c4805SLuis R. Rodriguez 313203c4805SLuis R. Rodriguez struct base_eep_header_4k { 3144bca5303SMartin Blumenstingl __le16 length; 3154bca5303SMartin Blumenstingl __le16 checksum; 3164bca5303SMartin Blumenstingl __le16 version; 317203c4805SLuis R. Rodriguez u8 opCapFlags; 318203c4805SLuis R. Rodriguez u8 eepMisc; 3194bca5303SMartin Blumenstingl __le16 regDmn[2]; 320203c4805SLuis R. Rodriguez u8 macAddr[6]; 321203c4805SLuis R. Rodriguez u8 rxMask; 322203c4805SLuis R. Rodriguez u8 txMask; 3234bca5303SMartin Blumenstingl __le16 rfSilent; 3244bca5303SMartin Blumenstingl __le16 blueToothOptions; 3254bca5303SMartin Blumenstingl __le16 deviceCap; 3264bca5303SMartin Blumenstingl __le32 binBuildNumber; 327203c4805SLuis R. Rodriguez u8 deviceType; 328203c4805SLuis R. Rodriguez u8 txGainType; 329203c4805SLuis R. Rodriguez } __packed; 330203c4805SLuis R. Rodriguez 331203c4805SLuis R. Rodriguez 332203c4805SLuis R. Rodriguez struct spur_chan { 3334bca5303SMartin Blumenstingl __le16 spurChan; 334203c4805SLuis R. Rodriguez u8 spurRangeLow; 335203c4805SLuis R. Rodriguez u8 spurRangeHigh; 336203c4805SLuis R. Rodriguez } __packed; 337203c4805SLuis R. Rodriguez 338203c4805SLuis R. Rodriguez struct modal_eep_header { 3394bca5303SMartin Blumenstingl __le32 antCtrlChain[AR5416_MAX_CHAINS]; 3404bca5303SMartin Blumenstingl __le32 antCtrlCommon; 341203c4805SLuis R. Rodriguez u8 antennaGainCh[AR5416_MAX_CHAINS]; 342203c4805SLuis R. Rodriguez u8 switchSettling; 343203c4805SLuis R. Rodriguez u8 txRxAttenCh[AR5416_MAX_CHAINS]; 344203c4805SLuis R. Rodriguez u8 rxTxMarginCh[AR5416_MAX_CHAINS]; 345203c4805SLuis R. Rodriguez u8 adcDesiredSize; 346203c4805SLuis R. Rodriguez u8 pgaDesiredSize; 347203c4805SLuis R. Rodriguez u8 xlnaGainCh[AR5416_MAX_CHAINS]; 348203c4805SLuis R. Rodriguez u8 txEndToXpaOff; 349203c4805SLuis R. Rodriguez u8 txEndToRxOn; 350203c4805SLuis R. Rodriguez u8 txFrameToXpaOn; 351203c4805SLuis R. Rodriguez u8 thresh62; 352203c4805SLuis R. Rodriguez u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; 353203c4805SLuis R. Rodriguez u8 xpdGain; 354203c4805SLuis R. Rodriguez u8 xpd; 355203c4805SLuis R. Rodriguez u8 iqCalICh[AR5416_MAX_CHAINS]; 356203c4805SLuis R. Rodriguez u8 iqCalQCh[AR5416_MAX_CHAINS]; 357203c4805SLuis R. Rodriguez u8 pdGainOverlap; 358203c4805SLuis R. Rodriguez u8 ob; 359203c4805SLuis R. Rodriguez u8 db; 360203c4805SLuis R. Rodriguez u8 xpaBiasLvl; 361203c4805SLuis R. Rodriguez u8 pwrDecreaseFor2Chain; 362203c4805SLuis R. Rodriguez u8 pwrDecreaseFor3Chain; 363203c4805SLuis R. Rodriguez u8 txFrameToDataStart; 364203c4805SLuis R. Rodriguez u8 txFrameToPaOn; 365203c4805SLuis R. Rodriguez u8 ht40PowerIncForPdadc; 366203c4805SLuis R. Rodriguez u8 bswAtten[AR5416_MAX_CHAINS]; 367203c4805SLuis R. Rodriguez u8 bswMargin[AR5416_MAX_CHAINS]; 368203c4805SLuis R. Rodriguez u8 swSettleHt40; 369203c4805SLuis R. Rodriguez u8 xatten2Db[AR5416_MAX_CHAINS]; 370203c4805SLuis R. Rodriguez u8 xatten2Margin[AR5416_MAX_CHAINS]; 371203c4805SLuis R. Rodriguez u8 ob_ch1; 372203c4805SLuis R. Rodriguez u8 db_ch1; 373f67e07ebSFelix Fietkau u8 lna_ctl; 374203c4805SLuis R. Rodriguez u8 miscBits; 3754bca5303SMartin Blumenstingl __le16 xpaBiasLvlFreq[3]; 376203c4805SLuis R. Rodriguez u8 futureModal[6]; 377203c4805SLuis R. Rodriguez 3784ddfcd7dSFelix Fietkau struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 379203c4805SLuis R. Rodriguez } __packed; 380203c4805SLuis R. Rodriguez 381203c4805SLuis R. Rodriguez struct calDataPerFreqOpLoop { 382203c4805SLuis R. Rodriguez u8 pwrPdg[2][5]; 383203c4805SLuis R. Rodriguez u8 vpdPdg[2][5]; 384203c4805SLuis R. Rodriguez u8 pcdac[2][5]; 385203c4805SLuis R. Rodriguez u8 empty[2][5]; 386203c4805SLuis R. Rodriguez } __packed; 387203c4805SLuis R. Rodriguez 388203c4805SLuis R. Rodriguez struct modal_eep_4k_header { 3894bca5303SMartin Blumenstingl __le32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; 3904bca5303SMartin Blumenstingl __le32 antCtrlCommon; 391203c4805SLuis R. Rodriguez u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; 392203c4805SLuis R. Rodriguez u8 switchSettling; 393203c4805SLuis R. Rodriguez u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; 394203c4805SLuis R. Rodriguez u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; 395203c4805SLuis R. Rodriguez u8 adcDesiredSize; 396203c4805SLuis R. Rodriguez u8 pgaDesiredSize; 397203c4805SLuis R. Rodriguez u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; 398203c4805SLuis R. Rodriguez u8 txEndToXpaOff; 399203c4805SLuis R. Rodriguez u8 txEndToRxOn; 400203c4805SLuis R. Rodriguez u8 txFrameToXpaOn; 401203c4805SLuis R. Rodriguez u8 thresh62; 402203c4805SLuis R. Rodriguez u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; 403203c4805SLuis R. Rodriguez u8 xpdGain; 404203c4805SLuis R. Rodriguez u8 xpd; 405203c4805SLuis R. Rodriguez u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; 406203c4805SLuis R. Rodriguez u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; 407203c4805SLuis R. Rodriguez u8 pdGainOverlap; 4087f63845fSSujith #ifdef __BIG_ENDIAN_BITFIELD 4097f63845fSSujith u8 ob_1:4, ob_0:4; 4107f63845fSSujith u8 db1_1:4, db1_0:4; 4117f63845fSSujith #else 4127f63845fSSujith u8 ob_0:4, ob_1:4; 4137f63845fSSujith u8 db1_0:4, db1_1:4; 4147f63845fSSujith #endif 415203c4805SLuis R. Rodriguez u8 xpaBiasLvl; 416203c4805SLuis R. Rodriguez u8 txFrameToDataStart; 417203c4805SLuis R. Rodriguez u8 txFrameToPaOn; 418203c4805SLuis R. Rodriguez u8 ht40PowerIncForPdadc; 419203c4805SLuis R. Rodriguez u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; 420203c4805SLuis R. Rodriguez u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; 421203c4805SLuis R. Rodriguez u8 swSettleHt40; 422203c4805SLuis R. Rodriguez u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; 423203c4805SLuis R. Rodriguez u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; 4247f63845fSSujith #ifdef __BIG_ENDIAN_BITFIELD 4257f63845fSSujith u8 db2_1:4, db2_0:4; 4267f63845fSSujith #else 4277f63845fSSujith u8 db2_0:4, db2_1:4; 4287f63845fSSujith #endif 429203c4805SLuis R. Rodriguez u8 version; 4307f63845fSSujith #ifdef __BIG_ENDIAN_BITFIELD 4317f63845fSSujith u8 ob_3:4, ob_2:4; 4327f63845fSSujith u8 antdiv_ctl1:4, ob_4:4; 4337f63845fSSujith u8 db1_3:4, db1_2:4; 4347f63845fSSujith u8 antdiv_ctl2:4, db1_4:4; 4357f63845fSSujith u8 db2_2:4, db2_3:4; 4367f63845fSSujith u8 reserved:4, db2_4:4; 4377f63845fSSujith #else 4387f63845fSSujith u8 ob_2:4, ob_3:4; 4397f63845fSSujith u8 ob_4:4, antdiv_ctl1:4; 4407f63845fSSujith u8 db1_2:4, db1_3:4; 4417f63845fSSujith u8 db1_4:4, antdiv_ctl2:4; 4427f63845fSSujith u8 db2_2:4, db2_3:4; 4437f63845fSSujith u8 db2_4:4, reserved:4; 4447f63845fSSujith #endif 445d88525e8SRajkumar Manoharan u8 tx_diversity; 446d88525e8SRajkumar Manoharan u8 flc_pwr_thresh; 447d88525e8SRajkumar Manoharan u8 bb_scale_smrt_antenna; 448d88525e8SRajkumar Manoharan #define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f 449d88525e8SRajkumar Manoharan u8 futureModal[1]; 4504ddfcd7dSFelix Fietkau struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 451203c4805SLuis R. Rodriguez } __packed; 452203c4805SLuis R. Rodriguez 453ac88b6ecSVivek Natarajan struct base_eep_ar9287_header { 4544bca5303SMartin Blumenstingl __le16 length; 4554bca5303SMartin Blumenstingl __le16 checksum; 4564bca5303SMartin Blumenstingl __le16 version; 457ac88b6ecSVivek Natarajan u8 opCapFlags; 458ac88b6ecSVivek Natarajan u8 eepMisc; 4594bca5303SMartin Blumenstingl __le16 regDmn[2]; 460ac88b6ecSVivek Natarajan u8 macAddr[6]; 461ac88b6ecSVivek Natarajan u8 rxMask; 462ac88b6ecSVivek Natarajan u8 txMask; 4634bca5303SMartin Blumenstingl __le16 rfSilent; 4644bca5303SMartin Blumenstingl __le16 blueToothOptions; 4654bca5303SMartin Blumenstingl __le16 deviceCap; 4664bca5303SMartin Blumenstingl __le32 binBuildNumber; 467ac88b6ecSVivek Natarajan u8 deviceType; 468ac88b6ecSVivek Natarajan u8 openLoopPwrCntl; 469ac88b6ecSVivek Natarajan int8_t pwrTableOffset; 470ac88b6ecSVivek Natarajan int8_t tempSensSlope; 471ac88b6ecSVivek Natarajan int8_t tempSensSlopePalOn; 472ac88b6ecSVivek Natarajan u8 futureBase[29]; 473ac88b6ecSVivek Natarajan } __packed; 474ac88b6ecSVivek Natarajan 475ac88b6ecSVivek Natarajan struct modal_eep_ar9287_header { 4764bca5303SMartin Blumenstingl __le32 antCtrlChain[AR9287_MAX_CHAINS]; 4774bca5303SMartin Blumenstingl __le32 antCtrlCommon; 478ac88b6ecSVivek Natarajan int8_t antennaGainCh[AR9287_MAX_CHAINS]; 479ac88b6ecSVivek Natarajan u8 switchSettling; 480ac88b6ecSVivek Natarajan u8 txRxAttenCh[AR9287_MAX_CHAINS]; 481ac88b6ecSVivek Natarajan u8 rxTxMarginCh[AR9287_MAX_CHAINS]; 482ac88b6ecSVivek Natarajan int8_t adcDesiredSize; 483ac88b6ecSVivek Natarajan u8 txEndToXpaOff; 484ac88b6ecSVivek Natarajan u8 txEndToRxOn; 485ac88b6ecSVivek Natarajan u8 txFrameToXpaOn; 486ac88b6ecSVivek Natarajan u8 thresh62; 487ac88b6ecSVivek Natarajan int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; 488ac88b6ecSVivek Natarajan u8 xpdGain; 489ac88b6ecSVivek Natarajan u8 xpd; 490ac88b6ecSVivek Natarajan int8_t iqCalICh[AR9287_MAX_CHAINS]; 491ac88b6ecSVivek Natarajan int8_t iqCalQCh[AR9287_MAX_CHAINS]; 492ac88b6ecSVivek Natarajan u8 pdGainOverlap; 493ac88b6ecSVivek Natarajan u8 xpaBiasLvl; 494ac88b6ecSVivek Natarajan u8 txFrameToDataStart; 495ac88b6ecSVivek Natarajan u8 txFrameToPaOn; 496ac88b6ecSVivek Natarajan u8 ht40PowerIncForPdadc; 497ac88b6ecSVivek Natarajan u8 bswAtten[AR9287_MAX_CHAINS]; 498ac88b6ecSVivek Natarajan u8 bswMargin[AR9287_MAX_CHAINS]; 499ac88b6ecSVivek Natarajan u8 swSettleHt40; 500ac88b6ecSVivek Natarajan u8 version; 501ac88b6ecSVivek Natarajan u8 db1; 502ac88b6ecSVivek Natarajan u8 db2; 503ac88b6ecSVivek Natarajan u8 ob_cck; 504ac88b6ecSVivek Natarajan u8 ob_psk; 505ac88b6ecSVivek Natarajan u8 ob_qam; 506ac88b6ecSVivek Natarajan u8 ob_pal_off; 507ac88b6ecSVivek Natarajan u8 futureModal[30]; 5084ddfcd7dSFelix Fietkau struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 509ac88b6ecSVivek Natarajan } __packed; 510ac88b6ecSVivek Natarajan 511203c4805SLuis R. Rodriguez struct cal_data_per_freq { 512203c4805SLuis R. Rodriguez u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 513203c4805SLuis R. Rodriguez u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 514203c4805SLuis R. Rodriguez } __packed; 515203c4805SLuis R. Rodriguez 516203c4805SLuis R. Rodriguez struct cal_data_per_freq_4k { 5174ddfcd7dSFelix Fietkau u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 5184ddfcd7dSFelix Fietkau u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 519203c4805SLuis R. Rodriguez } __packed; 520203c4805SLuis R. Rodriguez 521203c4805SLuis R. Rodriguez struct cal_target_power_leg { 522203c4805SLuis R. Rodriguez u8 bChannel; 523203c4805SLuis R. Rodriguez u8 tPow2x[4]; 524203c4805SLuis R. Rodriguez } __packed; 525203c4805SLuis R. Rodriguez 526203c4805SLuis R. Rodriguez struct cal_target_power_ht { 527203c4805SLuis R. Rodriguez u8 bChannel; 528203c4805SLuis R. Rodriguez u8 tPow2x[8]; 529203c4805SLuis R. Rodriguez } __packed; 530203c4805SLuis R. Rodriguez 531203c4805SLuis R. Rodriguez struct cal_ctl_edges { 532203c4805SLuis R. Rodriguez u8 bChannel; 533e702ba18SFelix Fietkau u8 ctl; 534203c4805SLuis R. Rodriguez } __packed; 535203c4805SLuis R. Rodriguez 536ac88b6ecSVivek Natarajan struct cal_data_op_loop_ar9287 { 537ac88b6ecSVivek Natarajan u8 pwrPdg[2][5]; 538ac88b6ecSVivek Natarajan u8 vpdPdg[2][5]; 539ac88b6ecSVivek Natarajan u8 pcdac[2][5]; 540ac88b6ecSVivek Natarajan u8 empty[2][5]; 541ac88b6ecSVivek Natarajan } __packed; 542ac88b6ecSVivek Natarajan 543ac88b6ecSVivek Natarajan struct cal_data_per_freq_ar9287 { 5444ddfcd7dSFelix Fietkau u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 5454ddfcd7dSFelix Fietkau u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 546ac88b6ecSVivek Natarajan } __packed; 547ac88b6ecSVivek Natarajan 548ac88b6ecSVivek Natarajan union cal_data_per_freq_ar9287_u { 549ac88b6ecSVivek Natarajan struct cal_data_op_loop_ar9287 calDataOpen; 550ac88b6ecSVivek Natarajan struct cal_data_per_freq_ar9287 calDataClose; 551ac88b6ecSVivek Natarajan } __packed; 552ac88b6ecSVivek Natarajan 553ac88b6ecSVivek Natarajan struct cal_ctl_data_ar9287 { 554ac88b6ecSVivek Natarajan struct cal_ctl_edges 555ac88b6ecSVivek Natarajan ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]; 556ac88b6ecSVivek Natarajan } __packed; 557ac88b6ecSVivek Natarajan 558203c4805SLuis R. Rodriguez struct cal_ctl_data { 559203c4805SLuis R. Rodriguez struct cal_ctl_edges 560203c4805SLuis R. Rodriguez ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 561203c4805SLuis R. Rodriguez } __packed; 562203c4805SLuis R. Rodriguez 563203c4805SLuis R. Rodriguez struct cal_ctl_data_4k { 564203c4805SLuis R. Rodriguez struct cal_ctl_edges 565203c4805SLuis R. Rodriguez ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; 566203c4805SLuis R. Rodriguez } __packed; 567203c4805SLuis R. Rodriguez 568203c4805SLuis R. Rodriguez struct ar5416_eeprom_def { 569203c4805SLuis R. Rodriguez struct base_eep_header baseEepHeader; 570203c4805SLuis R. Rodriguez u8 custData[64]; 571203c4805SLuis R. Rodriguez struct modal_eep_header modalHeader[2]; 572203c4805SLuis R. Rodriguez u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 573203c4805SLuis R. Rodriguez u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 574203c4805SLuis R. Rodriguez struct cal_data_per_freq 575203c4805SLuis R. Rodriguez calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; 576203c4805SLuis R. Rodriguez struct cal_data_per_freq 577203c4805SLuis R. Rodriguez calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 578203c4805SLuis R. Rodriguez struct cal_target_power_leg 579203c4805SLuis R. Rodriguez calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; 580203c4805SLuis R. Rodriguez struct cal_target_power_ht 581203c4805SLuis R. Rodriguez calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 582203c4805SLuis R. Rodriguez struct cal_target_power_ht 583203c4805SLuis R. Rodriguez calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 584203c4805SLuis R. Rodriguez struct cal_target_power_leg 585203c4805SLuis R. Rodriguez calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 586203c4805SLuis R. Rodriguez struct cal_target_power_leg 587203c4805SLuis R. Rodriguez calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; 588203c4805SLuis R. Rodriguez struct cal_target_power_ht 589203c4805SLuis R. Rodriguez calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 590203c4805SLuis R. Rodriguez struct cal_target_power_ht 591203c4805SLuis R. Rodriguez calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 592203c4805SLuis R. Rodriguez u8 ctlIndex[AR5416_NUM_CTLS]; 593203c4805SLuis R. Rodriguez struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; 594203c4805SLuis R. Rodriguez u8 padding; 595203c4805SLuis R. Rodriguez } __packed; 596203c4805SLuis R. Rodriguez 597203c4805SLuis R. Rodriguez struct ar5416_eeprom_4k { 598203c4805SLuis R. Rodriguez struct base_eep_header_4k baseEepHeader; 599203c4805SLuis R. Rodriguez u8 custData[20]; 600203c4805SLuis R. Rodriguez struct modal_eep_4k_header modalHeader; 601203c4805SLuis R. Rodriguez u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; 602203c4805SLuis R. Rodriguez struct cal_data_per_freq_4k 603203c4805SLuis R. Rodriguez calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; 604203c4805SLuis R. Rodriguez struct cal_target_power_leg 605203c4805SLuis R. Rodriguez calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; 606203c4805SLuis R. Rodriguez struct cal_target_power_leg 607203c4805SLuis R. Rodriguez calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 608203c4805SLuis R. Rodriguez struct cal_target_power_ht 609203c4805SLuis R. Rodriguez calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 610203c4805SLuis R. Rodriguez struct cal_target_power_ht 611203c4805SLuis R. Rodriguez calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; 612203c4805SLuis R. Rodriguez u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; 613203c4805SLuis R. Rodriguez struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; 614203c4805SLuis R. Rodriguez u8 padding; 615203c4805SLuis R. Rodriguez } __packed; 616203c4805SLuis R. Rodriguez 617475f5989SLuis R. Rodriguez struct ar9287_eeprom { 618ac88b6ecSVivek Natarajan struct base_eep_ar9287_header baseEepHeader; 619ac88b6ecSVivek Natarajan u8 custData[AR9287_DATA_SZ]; 620ac88b6ecSVivek Natarajan struct modal_eep_ar9287_header modalHeader; 621ac88b6ecSVivek Natarajan u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; 622ac88b6ecSVivek Natarajan union cal_data_per_freq_ar9287_u 623ac88b6ecSVivek Natarajan calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; 624ac88b6ecSVivek Natarajan struct cal_target_power_leg 625ac88b6ecSVivek Natarajan calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; 626ac88b6ecSVivek Natarajan struct cal_target_power_leg 627ac88b6ecSVivek Natarajan calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; 628ac88b6ecSVivek Natarajan struct cal_target_power_ht 629ac88b6ecSVivek Natarajan calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; 630ac88b6ecSVivek Natarajan struct cal_target_power_ht 631ac88b6ecSVivek Natarajan calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; 632ac88b6ecSVivek Natarajan u8 ctlIndex[AR9287_NUM_CTLS]; 633ac88b6ecSVivek Natarajan struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; 634ac88b6ecSVivek Natarajan u8 padding; 635ac88b6ecSVivek Natarajan } __packed; 636ac88b6ecSVivek Natarajan 637203c4805SLuis R. Rodriguez enum reg_ext_bitmap { 638ebb90cfcSSenthil Balasubramanian REG_EXT_FCC_MIDBAND = 0, 639203c4805SLuis R. Rodriguez REG_EXT_JAPAN_MIDBAND = 1, 640203c4805SLuis R. Rodriguez REG_EXT_FCC_DFS_HT40 = 2, 641203c4805SLuis R. Rodriguez REG_EXT_JAPAN_NONDFS_HT40 = 3, 642203c4805SLuis R. Rodriguez REG_EXT_JAPAN_DFS_HT40 = 4 643203c4805SLuis R. Rodriguez }; 644203c4805SLuis R. Rodriguez 645203c4805SLuis R. Rodriguez struct ath9k_country_entry { 646203c4805SLuis R. Rodriguez u16 countryCode; 647203c4805SLuis R. Rodriguez u16 regDmnEnum; 648203c4805SLuis R. Rodriguez u16 regDmn5G; 649203c4805SLuis R. Rodriguez u16 regDmn2G; 650203c4805SLuis R. Rodriguez u8 isMultidomain; 651203c4805SLuis R. Rodriguez u8 iso[3]; 652203c4805SLuis R. Rodriguez }; 653203c4805SLuis R. Rodriguez 654203c4805SLuis R. Rodriguez struct eeprom_ops { 655203c4805SLuis R. Rodriguez int (*check_eeprom)(struct ath_hw *hw); 656203c4805SLuis R. Rodriguez u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); 657203c4805SLuis R. Rodriguez bool (*fill_eeprom)(struct ath_hw *hw); 65826526202SRajkumar Manoharan u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf, 65926526202SRajkumar Manoharan u32 len, u32 size); 660203c4805SLuis R. Rodriguez int (*get_eeprom_ver)(struct ath_hw *hw); 661203c4805SLuis R. Rodriguez int (*get_eeprom_rev)(struct ath_hw *hw); 662203c4805SLuis R. Rodriguez void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); 663203c4805SLuis R. Rodriguez void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); 6648fbff4b8SVasanthakumar Thiagarajan void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, 665203c4805SLuis R. Rodriguez u16 cfgCtl, u8 twiceAntennaReduction, 666ca2c68ccSFelix Fietkau u8 powerLimit, bool test); 667203c4805SLuis R. Rodriguez u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); 668d8ec2e2aSMartin Blumenstingl u8 (*get_eepmisc)(struct ath_hw *ah); 669203c4805SLuis R. Rodriguez }; 670203c4805SLuis R. Rodriguez 67179d7f4bcSSujith void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val); 672b5aec950SSujith void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, 673b5aec950SSujith u32 shift, u32 val); 674b5aec950SSujith int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, 675b5aec950SSujith int16_t targetLeft, 676b5aec950SSujith int16_t targetRight); 677b5aec950SSujith bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, 678b5aec950SSujith u16 *indexL, u16 *indexR); 6790e4b9f2fSGabor Juhos bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data); 6806fa658fdSMartin Blumenstingl int ath9k_hw_nvram_swap_data(struct ath_hw *ah, bool *swap_needed, int size); 6816fa658fdSMartin Blumenstingl bool ath9k_hw_nvram_validate_checksum(struct ath_hw *ah, int size); 6826fa658fdSMartin Blumenstingl bool ath9k_hw_nvram_check_version(struct ath_hw *ah, int version, int minrev); 68304cf53f4SSujith Manoharan void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, 68404cf53f4SSujith Manoharan int eep_start_loc, int size); 685b5aec950SSujith void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 686b5aec950SSujith u8 *pVpdList, u16 numIntercepts, 687b5aec950SSujith u8 *pRetVpdList); 688b5aec950SSujith void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, 689b5aec950SSujith struct ath9k_channel *chan, 690b5aec950SSujith struct cal_target_power_leg *powInfo, 691b5aec950SSujith u16 numChannels, 692b5aec950SSujith struct cal_target_power_leg *pNewPower, 693b5aec950SSujith u16 numRates, bool isExtTarget); 694b5aec950SSujith void ath9k_hw_get_target_powers(struct ath_hw *ah, 695b5aec950SSujith struct ath9k_channel *chan, 696b5aec950SSujith struct cal_target_power_ht *powInfo, 697b5aec950SSujith u16 numChannels, 698b5aec950SSujith struct cal_target_power_ht *pNewPower, 699b5aec950SSujith u16 numRates, bool isHt40Target); 700b5aec950SSujith u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 701b5aec950SSujith bool is2GHz, int num_band_edges); 702ea6f792bSGabor Juhos u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit, 703ea6f792bSGabor Juhos u8 antenna_reduction); 704a55f8588SSujith void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah); 705b5aec950SSujith int ath9k_hw_eeprom_init(struct ath_hw *ah); 706b5aec950SSujith 707115277a3SFelix Fietkau void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, 708115277a3SFelix Fietkau struct ath9k_channel *chan, 709115277a3SFelix Fietkau void *pRawDataSet, 710115277a3SFelix Fietkau u8 *bChans, u16 availPiers, 711115277a3SFelix Fietkau u16 tPdGainOverlap, 712115277a3SFelix Fietkau u16 *pPdGainBoundaries, u8 *pPDADCValues, 713115277a3SFelix Fietkau u16 numXpdGains); 714115277a3SFelix Fietkau 71523bd7cedSGabor Juhos static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 71623bd7cedSGabor Juhos { 71723bd7cedSGabor Juhos if (fbin == AR5416_BCHAN_UNUSED) 71823bd7cedSGabor Juhos return fbin; 71923bd7cedSGabor Juhos 72023bd7cedSGabor Juhos return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 72123bd7cedSGabor Juhos } 72223bd7cedSGabor Juhos 723203c4805SLuis R. Rodriguez #define ar5416_get_ntxchains(_txchainmask) \ 724203c4805SLuis R. Rodriguez (((_txchainmask >> 2) & 1) + \ 725203c4805SLuis R. Rodriguez ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 726203c4805SLuis R. Rodriguez 727b5aec950SSujith extern const struct eeprom_ops eep_def_ops; 728b5aec950SSujith extern const struct eeprom_ops eep_4k_ops; 7290b8f6f2bSLuis R. Rodriguez extern const struct eeprom_ops eep_ar9287_ops; 73015c9ee7aSSenthil Balasubramanian extern const struct eeprom_ops eep_ar9287_ops; 73115c9ee7aSSenthil Balasubramanian extern const struct eeprom_ops eep_ar9300_ops; 732203c4805SLuis R. Rodriguez 733203c4805SLuis R. Rodriguez #endif /* EEPROM_H */ 734