1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef ATH9K_H 18 #define ATH9K_H 19 20 #include <linux/etherdevice.h> 21 #include <linux/device.h> 22 #include <linux/interrupt.h> 23 #include <linux/leds.h> 24 #include <linux/completion.h> 25 26 #include "debug.h" 27 #include "common.h" 28 #include "mci.h" 29 #include "dfs.h" 30 #include "spectral.h" 31 32 struct ath_node; 33 struct ath_rate_table; 34 35 extern struct ieee80211_ops ath9k_ops; 36 extern int ath9k_modparam_nohwcrypt; 37 extern int led_blink; 38 extern bool is_ath9k_unloaded; 39 40 struct ath_config { 41 u16 txpowlimit; 42 }; 43 44 /*************************/ 45 /* Descriptor Management */ 46 /*************************/ 47 48 #define ATH_TXSTATUS_RING_SIZE 512 49 50 /* Macro to expand scalars to 64-bit objects */ 51 #define ito64(x) (sizeof(x) == 1) ? \ 52 (((unsigned long long int)(x)) & (0xff)) : \ 53 (sizeof(x) == 2) ? \ 54 (((unsigned long long int)(x)) & 0xffff) : \ 55 ((sizeof(x) == 4) ? \ 56 (((unsigned long long int)(x)) & 0xffffffff) : \ 57 (unsigned long long int)(x)) 58 59 #define ATH_TXBUF_RESET(_bf) do { \ 60 (_bf)->bf_lastbf = NULL; \ 61 (_bf)->bf_next = NULL; \ 62 memset(&((_bf)->bf_state), 0, \ 63 sizeof(struct ath_buf_state)); \ 64 } while (0) 65 66 #define DS2PHYS(_dd, _ds) \ 67 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 68 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) 69 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) 70 71 struct ath_descdma { 72 void *dd_desc; 73 dma_addr_t dd_desc_paddr; 74 u32 dd_desc_len; 75 }; 76 77 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, 78 struct list_head *head, const char *name, 79 int nbuf, int ndesc, bool is_tx); 80 81 /***********/ 82 /* RX / TX */ 83 /***********/ 84 85 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) 86 87 /* increment with wrap-around */ 88 #define INCR(_l, _sz) do { \ 89 (_l)++; \ 90 (_l) &= ((_sz) - 1); \ 91 } while (0) 92 93 #define ATH_RXBUF 512 94 #define ATH_TXBUF 512 95 #define ATH_TXBUF_RESERVE 5 96 #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) 97 #define ATH_TXMAXTRY 13 98 #define ATH_MAX_SW_RETRIES 30 99 100 #define TID_TO_WME_AC(_tid) \ 101 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \ 102 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \ 103 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \ 104 IEEE80211_AC_VO) 105 106 #define ATH_AGGR_DELIM_SZ 4 107 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 108 /* number of delimiters for encryption padding */ 109 #define ATH_AGGR_ENCRYPTDELIM 10 110 /* minimum h/w qdepth to be sustained to maximize aggregation */ 111 #define ATH_AGGR_MIN_QDEPTH 2 112 /* minimum h/w qdepth for non-aggregated traffic */ 113 #define ATH_NON_AGGR_MIN_QDEPTH 8 114 #define ATH_TX_COMPLETE_POLL_INT 1000 115 #define ATH_TXFIFO_DEPTH 8 116 #define ATH_TX_ERROR 0x01 117 118 #define IEEE80211_SEQ_SEQ_SHIFT 4 119 #define IEEE80211_SEQ_MAX 4096 120 #define IEEE80211_WEP_IVLEN 3 121 #define IEEE80211_WEP_KIDLEN 1 122 #define IEEE80211_WEP_CRCLEN 4 123 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 124 (IEEE80211_WEP_IVLEN + \ 125 IEEE80211_WEP_KIDLEN + \ 126 IEEE80211_WEP_CRCLEN)) 127 128 /* return whether a bit at index _n in bitmap _bm is set 129 * _sz is the size of the bitmap */ 130 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ 131 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) 132 133 /* return block-ack bitmap index given sequence and starting sequence */ 134 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) 135 136 /* return the seqno for _start + _offset */ 137 #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) 138 139 /* returns delimiter padding required given the packet length */ 140 #define ATH_AGGR_GET_NDELIM(_len) \ 141 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ 142 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) 143 144 #define BAW_WITHIN(_start, _bawsz, _seqno) \ 145 ((((_seqno) - (_start)) & 4095) < (_bawsz)) 146 147 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) 148 149 #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e)) 150 151 struct ath_txq { 152 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ 153 u32 axq_qnum; /* ath9k hardware queue number */ 154 void *axq_link; 155 struct list_head axq_q; 156 spinlock_t axq_lock; 157 u32 axq_depth; 158 u32 axq_ampdu_depth; 159 bool stopped; 160 bool axq_tx_inprogress; 161 struct list_head axq_acq; 162 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 163 u8 txq_headidx; 164 u8 txq_tailidx; 165 int pending_frames; 166 struct sk_buff_head complete_q; 167 }; 168 169 struct ath_atx_ac { 170 struct ath_txq *txq; 171 struct list_head list; 172 struct list_head tid_q; 173 bool clear_ps_filter; 174 bool sched; 175 }; 176 177 struct ath_frame_info { 178 struct ath_buf *bf; 179 int framelen; 180 enum ath9k_key_type keytype; 181 u8 keyix; 182 u8 rtscts_rate; 183 u8 retries : 7; 184 u8 baw_tracked : 1; 185 }; 186 187 struct ath_rxbuf { 188 struct list_head list; 189 struct sk_buff *bf_mpdu; 190 void *bf_desc; 191 dma_addr_t bf_daddr; 192 dma_addr_t bf_buf_addr; 193 }; 194 195 /** 196 * enum buffer_type - Buffer type flags 197 * 198 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) 199 * @BUF_AGGR: Indicates whether the buffer can be aggregated 200 * (used in aggregation scheduling) 201 */ 202 enum buffer_type { 203 BUF_AMPDU = BIT(0), 204 BUF_AGGR = BIT(1), 205 }; 206 207 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) 208 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) 209 210 struct ath_buf_state { 211 u8 bf_type; 212 u8 bfs_paprd; 213 u8 ndelim; 214 bool stale; 215 u16 seqno; 216 unsigned long bfs_paprd_timestamp; 217 }; 218 219 struct ath_buf { 220 struct list_head list; 221 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or 222 an aggregate) */ 223 struct ath_buf *bf_next; /* next subframe in the aggregate */ 224 struct sk_buff *bf_mpdu; /* enclosing frame structure */ 225 void *bf_desc; /* virtual addr of desc */ 226 dma_addr_t bf_daddr; /* physical addr of desc */ 227 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ 228 struct ieee80211_tx_rate rates[4]; 229 struct ath_buf_state bf_state; 230 }; 231 232 struct ath_atx_tid { 233 struct list_head list; 234 struct sk_buff_head buf_q; 235 struct sk_buff_head retry_q; 236 struct ath_node *an; 237 struct ath_atx_ac *ac; 238 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; 239 u16 seq_start; 240 u16 seq_next; 241 u16 baw_size; 242 u8 tidno; 243 int baw_head; /* first un-acked tx buffer */ 244 int baw_tail; /* next unused tx buffer slot */ 245 246 s8 bar_index; 247 bool sched; 248 bool paused; 249 bool active; 250 }; 251 252 struct ath_node { 253 struct ath_softc *sc; 254 struct ieee80211_sta *sta; /* station struct we're part of */ 255 struct ieee80211_vif *vif; /* interface with which we're associated */ 256 struct ath_atx_tid tid[IEEE80211_NUM_TIDS]; 257 struct ath_atx_ac ac[IEEE80211_NUM_ACS]; 258 259 u16 maxampdu; 260 u8 mpdudensity; 261 s8 ps_key; 262 263 bool sleeping; 264 bool no_ps_filter; 265 }; 266 267 struct ath_tx_control { 268 struct ath_txq *txq; 269 struct ath_node *an; 270 u8 paprd; 271 struct ieee80211_sta *sta; 272 }; 273 274 275 /** 276 * @txq_map: Index is mac80211 queue number. This is 277 * not necessarily the same as the hardware queue number 278 * (axq_qnum). 279 */ 280 struct ath_tx { 281 u16 seq_no; 282 u32 txqsetup; 283 spinlock_t txbuflock; 284 struct list_head txbuf; 285 struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; 286 struct ath_descdma txdma; 287 struct ath_txq *txq_map[IEEE80211_NUM_ACS]; 288 struct ath_txq *uapsdq; 289 u32 txq_max_pending[IEEE80211_NUM_ACS]; 290 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32]; 291 }; 292 293 struct ath_rx_edma { 294 struct sk_buff_head rx_fifo; 295 u32 rx_fifo_hwsize; 296 }; 297 298 struct ath_rx { 299 u8 defant; 300 u8 rxotherant; 301 bool discard_next; 302 u32 *rxlink; 303 u32 num_pkts; 304 unsigned int rxfilter; 305 struct list_head rxbuf; 306 struct ath_descdma rxdma; 307 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; 308 309 struct ath_rxbuf *buf_hold; 310 struct sk_buff *frag; 311 312 u32 ampdu_ref; 313 }; 314 315 int ath_startrecv(struct ath_softc *sc); 316 bool ath_stoprecv(struct ath_softc *sc); 317 u32 ath_calcrxfilter(struct ath_softc *sc); 318 int ath_rx_init(struct ath_softc *sc, int nbufs); 319 void ath_rx_cleanup(struct ath_softc *sc); 320 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); 321 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); 322 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq); 323 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq); 324 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); 325 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); 326 bool ath_drain_all_txq(struct ath_softc *sc); 327 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq); 328 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); 329 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); 330 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); 331 int ath_tx_init(struct ath_softc *sc, int nbufs); 332 int ath_txq_update(struct ath_softc *sc, int qnum, 333 struct ath9k_tx_queue_info *q); 334 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); 335 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 336 struct ath_tx_control *txctl); 337 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 338 struct sk_buff *skb); 339 void ath_tx_tasklet(struct ath_softc *sc); 340 void ath_tx_edma_tasklet(struct ath_softc *sc); 341 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 342 u16 tid, u16 *ssn); 343 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 344 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); 345 346 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); 347 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 348 struct ath_node *an); 349 void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 350 struct ieee80211_sta *sta, 351 u16 tids, int nframes, 352 enum ieee80211_frame_release_type reason, 353 bool more_data); 354 355 /********/ 356 /* VIFs */ 357 /********/ 358 359 struct ath_vif { 360 struct ath_node mcast_node; 361 int av_bslot; 362 bool primary_sta_vif; 363 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ 364 struct ath_buf *av_bcbuf; 365 }; 366 367 struct ath9k_vif_iter_data { 368 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */ 369 u8 mask[ETH_ALEN]; /* bssid mask */ 370 bool has_hw_macaddr; 371 372 int naps; /* number of AP vifs */ 373 int nmeshes; /* number of mesh vifs */ 374 int nstations; /* number of station vifs */ 375 int nwds; /* number of WDS vifs */ 376 int nadhocs; /* number of adhoc vifs */ 377 }; 378 379 void ath9k_calculate_iter_data(struct ieee80211_hw *hw, 380 struct ieee80211_vif *vif, 381 struct ath9k_vif_iter_data *iter_data); 382 383 /*******************/ 384 /* Beacon Handling */ 385 /*******************/ 386 387 /* 388 * Regardless of the number of beacons we stagger, (i.e. regardless of the 389 * number of BSSIDs) if a given beacon does not go out even after waiting this 390 * number of beacon intervals, the game's up. 391 */ 392 #define BSTUCK_THRESH 9 393 #define ATH_BCBUF 8 394 #define ATH_DEFAULT_BINTVAL 100 /* TU */ 395 #define ATH_DEFAULT_BMISS_LIMIT 10 396 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 397 398 #define TSF_TO_TU(_h,_l) \ 399 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 400 401 struct ath_beacon_config { 402 int beacon_interval; 403 u16 listen_interval; 404 u16 dtim_period; 405 u16 bmiss_timeout; 406 u8 dtim_count; 407 bool enable_beacon; 408 bool ibss_creator; 409 }; 410 411 struct ath_beacon { 412 enum { 413 OK, /* no change needed */ 414 UPDATE, /* update pending */ 415 COMMIT /* beacon sent, commit change */ 416 } updateslot; /* slot time update fsm */ 417 418 u32 beaconq; 419 u32 bmisscnt; 420 u32 bc_tstamp; 421 struct ieee80211_vif *bslot[ATH_BCBUF]; 422 int slottime; 423 int slotupdate; 424 struct ath9k_tx_queue_info beacon_qi; 425 struct ath_descdma bdma; 426 struct ath_txq *cabq; 427 struct list_head bbuf; 428 429 bool tx_processed; 430 bool tx_last; 431 }; 432 433 void ath9k_beacon_tasklet(unsigned long data); 434 void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif, 435 u32 changed); 436 void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 437 void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); 438 void ath9k_set_beacon(struct ath_softc *sc); 439 bool ath9k_csa_is_finished(struct ath_softc *sc); 440 441 /*******************/ 442 /* Link Monitoring */ 443 /*******************/ 444 445 #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ 446 #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ 447 #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ 448 #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ 449 #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ 450 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ 451 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ 452 #define ATH_ANI_MAX_SKIP_COUNT 10 453 #define ATH_PAPRD_TIMEOUT 100 /* msecs */ 454 #define ATH_PLL_WORK_INTERVAL 100 455 456 void ath_tx_complete_poll_work(struct work_struct *work); 457 void ath_reset_work(struct work_struct *work); 458 bool ath_hw_check(struct ath_softc *sc); 459 void ath_hw_pll_work(struct work_struct *work); 460 void ath_paprd_calibrate(struct work_struct *work); 461 void ath_ani_calibrate(unsigned long data); 462 void ath_start_ani(struct ath_softc *sc); 463 void ath_stop_ani(struct ath_softc *sc); 464 void ath_check_ani(struct ath_softc *sc); 465 int ath_update_survey_stats(struct ath_softc *sc); 466 void ath_update_survey_nf(struct ath_softc *sc, int channel); 467 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); 468 void ath_ps_full_sleep(unsigned long data); 469 470 /**********/ 471 /* BTCOEX */ 472 /**********/ 473 474 #define ATH_DUMP_BTCOEX(_s, _val) \ 475 do { \ 476 len += scnprintf(buf + len, size - len, \ 477 "%20s : %10d\n", _s, (_val)); \ 478 } while (0) 479 480 enum bt_op_flags { 481 BT_OP_PRIORITY_DETECTED, 482 BT_OP_SCAN, 483 }; 484 485 struct ath_btcoex { 486 spinlock_t btcoex_lock; 487 struct timer_list period_timer; /* Timer for BT period */ 488 struct timer_list no_stomp_timer; 489 u32 bt_priority_cnt; 490 unsigned long bt_priority_time; 491 unsigned long op_flags; 492 int bt_stomp_type; /* Types of BT stomping */ 493 u32 btcoex_no_stomp; /* in msec */ 494 u32 btcoex_period; /* in msec */ 495 u32 btscan_no_stomp; /* in msec */ 496 u32 duty_cycle; 497 u32 bt_wait_time; 498 int rssi_count; 499 struct ath_mci_profile mci; 500 u8 stomp_audio; 501 }; 502 503 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 504 int ath9k_init_btcoex(struct ath_softc *sc); 505 void ath9k_deinit_btcoex(struct ath_softc *sc); 506 void ath9k_start_btcoex(struct ath_softc *sc); 507 void ath9k_stop_btcoex(struct ath_softc *sc); 508 void ath9k_btcoex_timer_resume(struct ath_softc *sc); 509 void ath9k_btcoex_timer_pause(struct ath_softc *sc); 510 void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); 511 u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); 512 void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); 513 int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size); 514 #else 515 static inline int ath9k_init_btcoex(struct ath_softc *sc) 516 { 517 return 0; 518 } 519 static inline void ath9k_deinit_btcoex(struct ath_softc *sc) 520 { 521 } 522 static inline void ath9k_start_btcoex(struct ath_softc *sc) 523 { 524 } 525 static inline void ath9k_stop_btcoex(struct ath_softc *sc) 526 { 527 } 528 static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, 529 u32 status) 530 { 531 } 532 static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, 533 u32 max_4ms_framelen) 534 { 535 return 0; 536 } 537 static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) 538 { 539 } 540 static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size) 541 { 542 return 0; 543 } 544 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ 545 546 /********************/ 547 /* LED Control */ 548 /********************/ 549 550 #define ATH_LED_PIN_DEF 1 551 #define ATH_LED_PIN_9287 8 552 #define ATH_LED_PIN_9300 10 553 #define ATH_LED_PIN_9485 6 554 #define ATH_LED_PIN_9462 4 555 556 #ifdef CONFIG_MAC80211_LEDS 557 void ath_init_leds(struct ath_softc *sc); 558 void ath_deinit_leds(struct ath_softc *sc); 559 void ath_fill_led_pin(struct ath_softc *sc); 560 #else 561 static inline void ath_init_leds(struct ath_softc *sc) 562 { 563 } 564 565 static inline void ath_deinit_leds(struct ath_softc *sc) 566 { 567 } 568 static inline void ath_fill_led_pin(struct ath_softc *sc) 569 { 570 } 571 #endif 572 573 /************************/ 574 /* Wake on Wireless LAN */ 575 /************************/ 576 577 struct ath9k_wow_pattern { 578 u8 pattern_bytes[MAX_PATTERN_SIZE]; 579 u8 mask_bytes[MAX_PATTERN_SIZE]; 580 u32 pattern_len; 581 }; 582 583 #ifdef CONFIG_ATH9K_WOW 584 void ath9k_init_wow(struct ieee80211_hw *hw); 585 int ath9k_suspend(struct ieee80211_hw *hw, 586 struct cfg80211_wowlan *wowlan); 587 int ath9k_resume(struct ieee80211_hw *hw); 588 void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled); 589 #else 590 static inline void ath9k_init_wow(struct ieee80211_hw *hw) 591 { 592 } 593 static inline int ath9k_suspend(struct ieee80211_hw *hw, 594 struct cfg80211_wowlan *wowlan) 595 { 596 return 0; 597 } 598 static inline int ath9k_resume(struct ieee80211_hw *hw) 599 { 600 return 0; 601 } 602 static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) 603 { 604 } 605 #endif /* CONFIG_ATH9K_WOW */ 606 607 /*******************************/ 608 /* Antenna diversity/combining */ 609 /*******************************/ 610 611 #define ATH_ANT_RX_CURRENT_SHIFT 4 612 #define ATH_ANT_RX_MAIN_SHIFT 2 613 #define ATH_ANT_RX_MASK 0x3 614 615 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 616 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 617 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 618 #define ATH_ANT_DIV_COMB_INIT_COUNT 95 619 #define ATH_ANT_DIV_COMB_MAX_COUNT 100 620 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 621 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 622 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50 623 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50 624 625 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 626 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 627 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 628 629 struct ath_ant_comb { 630 u16 count; 631 u16 total_pkt_count; 632 bool scan; 633 bool scan_not_start; 634 int main_total_rssi; 635 int alt_total_rssi; 636 int alt_recv_cnt; 637 int main_recv_cnt; 638 int rssi_lna1; 639 int rssi_lna2; 640 int rssi_add; 641 int rssi_sub; 642 int rssi_first; 643 int rssi_second; 644 int rssi_third; 645 int ant_ratio; 646 int ant_ratio2; 647 bool alt_good; 648 int quick_scan_cnt; 649 enum ath9k_ant_div_comb_lna_conf main_conf; 650 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; 651 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; 652 bool first_ratio; 653 bool second_ratio; 654 unsigned long scan_start_time; 655 656 /* 657 * Card-specific config values. 658 */ 659 int low_rssi_thresh; 660 int fast_div_bias; 661 }; 662 663 void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); 664 665 /********************/ 666 /* Main driver core */ 667 /********************/ 668 669 #define ATH9K_PCI_CUS198 0x0001 670 #define ATH9K_PCI_CUS230 0x0002 671 #define ATH9K_PCI_CUS217 0x0004 672 #define ATH9K_PCI_CUS252 0x0008 673 #define ATH9K_PCI_WOW 0x0010 674 #define ATH9K_PCI_BT_ANT_DIV 0x0020 675 #define ATH9K_PCI_D3_L1_WAR 0x0040 676 #define ATH9K_PCI_AR9565_1ANT 0x0080 677 #define ATH9K_PCI_AR9565_2ANT 0x0100 678 #define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200 679 #define ATH9K_PCI_KILLER 0x0400 680 681 /* 682 * Default cache line size, in bytes. 683 * Used when PCI device not fully initialized by bootrom/BIOS 684 */ 685 #define DEFAULT_CACHELINE 32 686 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ 687 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ 688 689 enum sc_op_flags { 690 SC_OP_INVALID, 691 SC_OP_BEACONS, 692 SC_OP_ANI_RUN, 693 SC_OP_PRIM_STA_VIF, 694 SC_OP_HW_RESET, 695 SC_OP_SCANNING, 696 }; 697 698 /* Powersave flags */ 699 #define PS_WAIT_FOR_BEACON BIT(0) 700 #define PS_WAIT_FOR_CAB BIT(1) 701 #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) 702 #define PS_WAIT_FOR_TX_ACK BIT(3) 703 #define PS_BEACON_SYNC BIT(4) 704 #define PS_WAIT_FOR_ANI BIT(5) 705 706 struct ath_softc { 707 struct ieee80211_hw *hw; 708 struct device *dev; 709 710 struct survey_info *cur_survey; 711 struct survey_info survey[ATH9K_NUM_CHANNELS]; 712 713 struct tasklet_struct intr_tq; 714 struct tasklet_struct bcon_tasklet; 715 struct ath_hw *sc_ah; 716 void __iomem *mem; 717 int irq; 718 spinlock_t sc_serial_rw; 719 spinlock_t sc_pm_lock; 720 spinlock_t sc_pcu_lock; 721 struct mutex mutex; 722 struct work_struct paprd_work; 723 struct work_struct hw_reset_work; 724 struct completion paprd_complete; 725 wait_queue_head_t tx_wait; 726 727 unsigned long sc_flags; 728 unsigned long driver_data; 729 730 u32 intrstatus; 731 u16 ps_flags; /* PS_* */ 732 u16 curtxpow; 733 bool ps_enabled; 734 bool ps_idle; 735 short nbcnvifs; 736 short nvifs; 737 unsigned long ps_usecount; 738 739 struct ath_config config; 740 struct ath_rx rx; 741 struct ath_tx tx; 742 struct ath_beacon beacon; 743 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 744 745 #ifdef CONFIG_MAC80211_LEDS 746 bool led_registered; 747 char led_name[32]; 748 struct led_classdev led_cdev; 749 #endif 750 751 struct ath9k_hw_cal_data caldata; 752 int last_rssi; 753 754 #ifdef CONFIG_ATH9K_DEBUGFS 755 struct ath9k_debug debug; 756 #endif 757 struct ath_beacon_config cur_beacon_conf; 758 struct delayed_work tx_complete_work; 759 struct delayed_work hw_pll_work; 760 struct timer_list sleep_timer; 761 762 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 763 struct ath_btcoex btcoex; 764 struct ath_mci_coex mci_coex; 765 struct work_struct mci_work; 766 #endif 767 768 struct ath_descdma txsdma; 769 struct ieee80211_vif *csa_vif; 770 771 struct ath_ant_comb ant_comb; 772 u8 ant_tx, ant_rx; 773 struct dfs_pattern_detector *dfs_detector; 774 u32 wow_enabled; 775 /* relay(fs) channel for spectral scan */ 776 struct rchan *rfs_chan_spec_scan; 777 enum spectral_mode spectral_mode; 778 struct ath_spec_scan spec_config; 779 780 struct ieee80211_vif *tx99_vif; 781 struct sk_buff *tx99_skb; 782 bool tx99_state; 783 s16 tx99_power; 784 785 #ifdef CONFIG_ATH9K_WOW 786 atomic_t wow_got_bmiss_intr; 787 atomic_t wow_sleep_proc_intr; /* in the middle of WoW sleep ? */ 788 u32 wow_intr_before_sleep; 789 #endif 790 }; 791 792 /********/ 793 /* TX99 */ 794 /********/ 795 796 #ifdef CONFIG_ATH9K_TX99 797 void ath9k_tx99_init_debug(struct ath_softc *sc); 798 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, 799 struct ath_tx_control *txctl); 800 #else 801 static inline void ath9k_tx99_init_debug(struct ath_softc *sc) 802 { 803 } 804 static inline int ath9k_tx99_send(struct ath_softc *sc, 805 struct sk_buff *skb, 806 struct ath_tx_control *txctl) 807 { 808 return 0; 809 } 810 #endif /* CONFIG_ATH9K_TX99 */ 811 812 static inline void ath_read_cachesize(struct ath_common *common, int *csz) 813 { 814 common->bus_ops->read_cachesize(common, csz); 815 } 816 817 void ath9k_tasklet(unsigned long data); 818 int ath_cabq_update(struct ath_softc *); 819 u8 ath9k_parse_mpdudensity(u8 mpdudensity); 820 irqreturn_t ath_isr(int irq, void *dev); 821 int ath_reset(struct ath_softc *sc); 822 void ath_cancel_work(struct ath_softc *sc); 823 void ath_restart_work(struct ath_softc *sc); 824 int ath9k_init_device(u16 devid, struct ath_softc *sc, 825 const struct ath_bus_ops *bus_ops); 826 void ath9k_deinit_device(struct ath_softc *sc); 827 void ath9k_reload_chainmask_settings(struct ath_softc *sc); 828 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); 829 void ath_start_rfkill_poll(struct ath_softc *sc); 830 void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); 831 void ath9k_ps_wakeup(struct ath_softc *sc); 832 void ath9k_ps_restore(struct ath_softc *sc); 833 834 #ifdef CONFIG_ATH9K_PCI 835 int ath_pci_init(void); 836 void ath_pci_exit(void); 837 #else 838 static inline int ath_pci_init(void) { return 0; }; 839 static inline void ath_pci_exit(void) {}; 840 #endif 841 842 #ifdef CONFIG_ATH9K_AHB 843 int ath_ahb_init(void); 844 void ath_ahb_exit(void); 845 #else 846 static inline int ath_ahb_init(void) { return 0; }; 847 static inline void ath_ahb_exit(void) {}; 848 #endif 849 850 #endif /* ATH9K_H */ 851