1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 3bdcd8170SKalle Valo * 4bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd8170SKalle Valo * 8bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd8170SKalle Valo */ 16bdcd8170SKalle Valo 17bdcd8170SKalle Valo #include "core.h" 18bdcd8170SKalle Valo #include "debug.h" 19bdcd8170SKalle Valo 20bdcd8170SKalle Valo static u8 ath6kl_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, 21bdcd8170SKalle Valo u32 *map_no) 22bdcd8170SKalle Valo { 23bdcd8170SKalle Valo struct ath6kl *ar = ath6kl_priv(dev); 24bdcd8170SKalle Valo struct ethhdr *eth_hdr; 25bdcd8170SKalle Valo u32 i, ep_map = -1; 26bdcd8170SKalle Valo u8 *datap; 27bdcd8170SKalle Valo 28bdcd8170SKalle Valo *map_no = 0; 29bdcd8170SKalle Valo datap = skb->data; 30bdcd8170SKalle Valo eth_hdr = (struct ethhdr *) (datap + sizeof(struct wmi_data_hdr)); 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo if (is_multicast_ether_addr(eth_hdr->h_dest)) 33bdcd8170SKalle Valo return ENDPOINT_2; 34bdcd8170SKalle Valo 35bdcd8170SKalle Valo for (i = 0; i < ar->node_num; i++) { 36bdcd8170SKalle Valo if (memcmp(eth_hdr->h_dest, ar->node_map[i].mac_addr, 37bdcd8170SKalle Valo ETH_ALEN) == 0) { 38bdcd8170SKalle Valo *map_no = i + 1; 39bdcd8170SKalle Valo ar->node_map[i].tx_pend++; 40bdcd8170SKalle Valo return ar->node_map[i].ep_id; 41bdcd8170SKalle Valo } 42bdcd8170SKalle Valo 43bdcd8170SKalle Valo if ((ep_map == -1) && !ar->node_map[i].tx_pend) 44bdcd8170SKalle Valo ep_map = i; 45bdcd8170SKalle Valo } 46bdcd8170SKalle Valo 47bdcd8170SKalle Valo if (ep_map == -1) { 48bdcd8170SKalle Valo ep_map = ar->node_num; 49bdcd8170SKalle Valo ar->node_num++; 50bdcd8170SKalle Valo if (ar->node_num > MAX_NODE_NUM) 51bdcd8170SKalle Valo return ENDPOINT_UNUSED; 52bdcd8170SKalle Valo } 53bdcd8170SKalle Valo 54bdcd8170SKalle Valo memcpy(ar->node_map[ep_map].mac_addr, eth_hdr->h_dest, ETH_ALEN); 55bdcd8170SKalle Valo 56bdcd8170SKalle Valo for (i = ENDPOINT_2; i <= ENDPOINT_5; i++) { 57bdcd8170SKalle Valo if (!ar->tx_pending[i]) { 58bdcd8170SKalle Valo ar->node_map[ep_map].ep_id = i; 59bdcd8170SKalle Valo break; 60bdcd8170SKalle Valo } 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo /* 63bdcd8170SKalle Valo * No free endpoint is available, start redistribution on 64bdcd8170SKalle Valo * the inuse endpoints. 65bdcd8170SKalle Valo */ 66bdcd8170SKalle Valo if (i == ENDPOINT_5) { 67bdcd8170SKalle Valo ar->node_map[ep_map].ep_id = ar->next_ep_id; 68bdcd8170SKalle Valo ar->next_ep_id++; 69bdcd8170SKalle Valo if (ar->next_ep_id > ENDPOINT_5) 70bdcd8170SKalle Valo ar->next_ep_id = ENDPOINT_2; 71bdcd8170SKalle Valo } 72bdcd8170SKalle Valo } 73bdcd8170SKalle Valo 74bdcd8170SKalle Valo *map_no = ep_map + 1; 75bdcd8170SKalle Valo ar->node_map[ep_map].tx_pend++; 76bdcd8170SKalle Valo 77bdcd8170SKalle Valo return ar->node_map[ep_map].ep_id; 78bdcd8170SKalle Valo } 79bdcd8170SKalle Valo 80*c1762a3fSThirumalai Pachamuthu static bool ath6kl_process_uapsdq(struct ath6kl_sta *conn, 81*c1762a3fSThirumalai Pachamuthu struct ath6kl_vif *vif, 82*c1762a3fSThirumalai Pachamuthu struct sk_buff *skb, 83*c1762a3fSThirumalai Pachamuthu u32 *flags) 84*c1762a3fSThirumalai Pachamuthu { 85*c1762a3fSThirumalai Pachamuthu struct ath6kl *ar = vif->ar; 86*c1762a3fSThirumalai Pachamuthu bool is_apsdq_empty = false; 87*c1762a3fSThirumalai Pachamuthu struct ethhdr *datap = (struct ethhdr *) skb->data; 88*c1762a3fSThirumalai Pachamuthu u8 up, traffic_class, *ip_hdr; 89*c1762a3fSThirumalai Pachamuthu u16 ether_type; 90*c1762a3fSThirumalai Pachamuthu struct ath6kl_llc_snap_hdr *llc_hdr; 91*c1762a3fSThirumalai Pachamuthu 92*c1762a3fSThirumalai Pachamuthu if (conn->sta_flags & STA_PS_APSD_TRIGGER) { 93*c1762a3fSThirumalai Pachamuthu /* 94*c1762a3fSThirumalai Pachamuthu * This tx is because of a uAPSD trigger, determine 95*c1762a3fSThirumalai Pachamuthu * more and EOSP bit. Set EOSP if queue is empty 96*c1762a3fSThirumalai Pachamuthu * or sufficient frames are delivered for this trigger. 97*c1762a3fSThirumalai Pachamuthu */ 98*c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 99*c1762a3fSThirumalai Pachamuthu if (!skb_queue_empty(&conn->apsdq)) 100*c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_MORE; 101*c1762a3fSThirumalai Pachamuthu else if (conn->sta_flags & STA_PS_APSD_EOSP) 102*c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_EOSP; 103*c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_UAPSD; 104*c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 105*c1762a3fSThirumalai Pachamuthu return false; 106*c1762a3fSThirumalai Pachamuthu } else if (!conn->apsd_info) 107*c1762a3fSThirumalai Pachamuthu return false; 108*c1762a3fSThirumalai Pachamuthu 109*c1762a3fSThirumalai Pachamuthu if (test_bit(WMM_ENABLED, &vif->flags)) { 110*c1762a3fSThirumalai Pachamuthu ether_type = be16_to_cpu(datap->h_proto); 111*c1762a3fSThirumalai Pachamuthu if (is_ethertype(ether_type)) { 112*c1762a3fSThirumalai Pachamuthu /* packet is in DIX format */ 113*c1762a3fSThirumalai Pachamuthu ip_hdr = (u8 *)(datap + 1); 114*c1762a3fSThirumalai Pachamuthu } else { 115*c1762a3fSThirumalai Pachamuthu /* packet is in 802.3 format */ 116*c1762a3fSThirumalai Pachamuthu llc_hdr = (struct ath6kl_llc_snap_hdr *) 117*c1762a3fSThirumalai Pachamuthu (datap + 1); 118*c1762a3fSThirumalai Pachamuthu ether_type = be16_to_cpu(llc_hdr->eth_type); 119*c1762a3fSThirumalai Pachamuthu ip_hdr = (u8 *)(llc_hdr + 1); 120*c1762a3fSThirumalai Pachamuthu } 121*c1762a3fSThirumalai Pachamuthu 122*c1762a3fSThirumalai Pachamuthu if (ether_type == IP_ETHERTYPE) 123*c1762a3fSThirumalai Pachamuthu up = ath6kl_wmi_determine_user_priority( 124*c1762a3fSThirumalai Pachamuthu ip_hdr, 0); 125*c1762a3fSThirumalai Pachamuthu } else { 126*c1762a3fSThirumalai Pachamuthu up = 0; 127*c1762a3fSThirumalai Pachamuthu } 128*c1762a3fSThirumalai Pachamuthu 129*c1762a3fSThirumalai Pachamuthu traffic_class = ath6kl_wmi_get_traffic_class(up); 130*c1762a3fSThirumalai Pachamuthu 131*c1762a3fSThirumalai Pachamuthu if ((conn->apsd_info & (1 << traffic_class)) == 0) 132*c1762a3fSThirumalai Pachamuthu return false; 133*c1762a3fSThirumalai Pachamuthu 134*c1762a3fSThirumalai Pachamuthu /* Queue the frames if the STA is sleeping */ 135*c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 136*c1762a3fSThirumalai Pachamuthu is_apsdq_empty = skb_queue_empty(&conn->apsdq); 137*c1762a3fSThirumalai Pachamuthu skb_queue_tail(&conn->apsdq, skb); 138*c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 139*c1762a3fSThirumalai Pachamuthu 140*c1762a3fSThirumalai Pachamuthu /* 141*c1762a3fSThirumalai Pachamuthu * If this is the first pkt getting queued 142*c1762a3fSThirumalai Pachamuthu * for this STA, update the PVB for this STA 143*c1762a3fSThirumalai Pachamuthu */ 144*c1762a3fSThirumalai Pachamuthu if (is_apsdq_empty) { 145*c1762a3fSThirumalai Pachamuthu ath6kl_wmi_set_apsd_bfrd_traf(ar->wmi, 146*c1762a3fSThirumalai Pachamuthu vif->fw_vif_idx, 147*c1762a3fSThirumalai Pachamuthu conn->aid, 1, 0); 148*c1762a3fSThirumalai Pachamuthu } 149*c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_UAPSD; 150*c1762a3fSThirumalai Pachamuthu 151*c1762a3fSThirumalai Pachamuthu return true; 152*c1762a3fSThirumalai Pachamuthu } 153*c1762a3fSThirumalai Pachamuthu 154*c1762a3fSThirumalai Pachamuthu static bool ath6kl_process_psq(struct ath6kl_sta *conn, 155*c1762a3fSThirumalai Pachamuthu struct ath6kl_vif *vif, 156*c1762a3fSThirumalai Pachamuthu struct sk_buff *skb, 157*c1762a3fSThirumalai Pachamuthu u32 *flags) 158*c1762a3fSThirumalai Pachamuthu { 159*c1762a3fSThirumalai Pachamuthu bool is_psq_empty = false; 160*c1762a3fSThirumalai Pachamuthu struct ath6kl *ar = vif->ar; 161*c1762a3fSThirumalai Pachamuthu 162*c1762a3fSThirumalai Pachamuthu if (conn->sta_flags & STA_PS_POLLED) { 163*c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 164*c1762a3fSThirumalai Pachamuthu if (!skb_queue_empty(&conn->psq)) 165*c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_MORE; 166*c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 167*c1762a3fSThirumalai Pachamuthu return false; 168*c1762a3fSThirumalai Pachamuthu } 169*c1762a3fSThirumalai Pachamuthu 170*c1762a3fSThirumalai Pachamuthu /* Queue the frames if the STA is sleeping */ 171*c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 172*c1762a3fSThirumalai Pachamuthu is_psq_empty = skb_queue_empty(&conn->psq); 173*c1762a3fSThirumalai Pachamuthu skb_queue_tail(&conn->psq, skb); 174*c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 175*c1762a3fSThirumalai Pachamuthu 176*c1762a3fSThirumalai Pachamuthu /* 177*c1762a3fSThirumalai Pachamuthu * If this is the first pkt getting queued 178*c1762a3fSThirumalai Pachamuthu * for this STA, update the PVB for this 179*c1762a3fSThirumalai Pachamuthu * STA. 180*c1762a3fSThirumalai Pachamuthu */ 181*c1762a3fSThirumalai Pachamuthu if (is_psq_empty) 182*c1762a3fSThirumalai Pachamuthu ath6kl_wmi_set_pvb_cmd(ar->wmi, 183*c1762a3fSThirumalai Pachamuthu vif->fw_vif_idx, 184*c1762a3fSThirumalai Pachamuthu conn->aid, 1); 185*c1762a3fSThirumalai Pachamuthu return true; 186*c1762a3fSThirumalai Pachamuthu } 187*c1762a3fSThirumalai Pachamuthu 1886765d0aaSVasanthakumar Thiagarajan static bool ath6kl_powersave_ap(struct ath6kl_vif *vif, struct sk_buff *skb, 189*c1762a3fSThirumalai Pachamuthu u32 *flags) 190bdcd8170SKalle Valo { 191bdcd8170SKalle Valo struct ethhdr *datap = (struct ethhdr *) skb->data; 192bdcd8170SKalle Valo struct ath6kl_sta *conn = NULL; 193*c1762a3fSThirumalai Pachamuthu bool ps_queued = false; 1946765d0aaSVasanthakumar Thiagarajan struct ath6kl *ar = vif->ar; 195bdcd8170SKalle Valo 196bdcd8170SKalle Valo if (is_multicast_ether_addr(datap->h_dest)) { 197bdcd8170SKalle Valo u8 ctr = 0; 198bdcd8170SKalle Valo bool q_mcast = false; 199bdcd8170SKalle Valo 200bdcd8170SKalle Valo for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { 201bdcd8170SKalle Valo if (ar->sta_list[ctr].sta_flags & STA_PS_SLEEP) { 202bdcd8170SKalle Valo q_mcast = true; 203bdcd8170SKalle Valo break; 204bdcd8170SKalle Valo } 205bdcd8170SKalle Valo } 206bdcd8170SKalle Valo 207bdcd8170SKalle Valo if (q_mcast) { 208bdcd8170SKalle Valo /* 209bdcd8170SKalle Valo * If this transmit is not because of a Dtim Expiry 210bdcd8170SKalle Valo * q it. 211bdcd8170SKalle Valo */ 21259c98449SVasanthakumar Thiagarajan if (!test_bit(DTIM_EXPIRED, &vif->flags)) { 213bdcd8170SKalle Valo bool is_mcastq_empty = false; 214bdcd8170SKalle Valo 215bdcd8170SKalle Valo spin_lock_bh(&ar->mcastpsq_lock); 216bdcd8170SKalle Valo is_mcastq_empty = 217bdcd8170SKalle Valo skb_queue_empty(&ar->mcastpsq); 218bdcd8170SKalle Valo skb_queue_tail(&ar->mcastpsq, skb); 219bdcd8170SKalle Valo spin_unlock_bh(&ar->mcastpsq_lock); 220bdcd8170SKalle Valo 221bdcd8170SKalle Valo /* 222bdcd8170SKalle Valo * If this is the first Mcast pkt getting 223bdcd8170SKalle Valo * queued indicate to the target to set the 224bdcd8170SKalle Valo * BitmapControl LSB of the TIM IE. 225bdcd8170SKalle Valo */ 226bdcd8170SKalle Valo if (is_mcastq_empty) 227bdcd8170SKalle Valo ath6kl_wmi_set_pvb_cmd(ar->wmi, 228334234b5SVasanthakumar Thiagarajan vif->fw_vif_idx, 229bdcd8170SKalle Valo MCAST_AID, 1); 230bdcd8170SKalle Valo 231bdcd8170SKalle Valo ps_queued = true; 232bdcd8170SKalle Valo } else { 233bdcd8170SKalle Valo /* 234bdcd8170SKalle Valo * This transmit is because of Dtim expiry. 235bdcd8170SKalle Valo * Determine if MoreData bit has to be set. 236bdcd8170SKalle Valo */ 237bdcd8170SKalle Valo spin_lock_bh(&ar->mcastpsq_lock); 238bdcd8170SKalle Valo if (!skb_queue_empty(&ar->mcastpsq)) 239*c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_MORE; 240bdcd8170SKalle Valo spin_unlock_bh(&ar->mcastpsq_lock); 241bdcd8170SKalle Valo } 242bdcd8170SKalle Valo } 243bdcd8170SKalle Valo } else { 2446765d0aaSVasanthakumar Thiagarajan conn = ath6kl_find_sta(vif, datap->h_dest); 245bdcd8170SKalle Valo if (!conn) { 246bdcd8170SKalle Valo dev_kfree_skb(skb); 247bdcd8170SKalle Valo 248bdcd8170SKalle Valo /* Inform the caller that the skb is consumed */ 249bdcd8170SKalle Valo return true; 250bdcd8170SKalle Valo } 251bdcd8170SKalle Valo 252bdcd8170SKalle Valo if (conn->sta_flags & STA_PS_SLEEP) { 253*c1762a3fSThirumalai Pachamuthu ps_queued = ath6kl_process_uapsdq(conn, 254*c1762a3fSThirumalai Pachamuthu vif, skb, flags); 255*c1762a3fSThirumalai Pachamuthu if (!(*flags & WMI_DATA_HDR_FLAGS_UAPSD)) 256*c1762a3fSThirumalai Pachamuthu ps_queued = ath6kl_process_psq(conn, 257*c1762a3fSThirumalai Pachamuthu vif, skb, flags); 258bdcd8170SKalle Valo } 259bdcd8170SKalle Valo } 260bdcd8170SKalle Valo return ps_queued; 261bdcd8170SKalle Valo } 262bdcd8170SKalle Valo 263bdcd8170SKalle Valo /* Tx functions */ 264bdcd8170SKalle Valo 265bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 266bdcd8170SKalle Valo enum htc_endpoint_id eid) 267bdcd8170SKalle Valo { 268bdcd8170SKalle Valo struct ath6kl *ar = devt; 269bdcd8170SKalle Valo int status = 0; 270bdcd8170SKalle Valo struct ath6kl_cookie *cookie = NULL; 271bdcd8170SKalle Valo 272bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 273bdcd8170SKalle Valo 274bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 275bdcd8170SKalle Valo "%s: skb=0x%p, len=0x%x eid =%d\n", __func__, 276bdcd8170SKalle Valo skb, skb->len, eid); 277bdcd8170SKalle Valo 278bdcd8170SKalle Valo if (test_bit(WMI_CTRL_EP_FULL, &ar->flag) && (eid == ar->ctrl_ep)) { 279bdcd8170SKalle Valo /* 280bdcd8170SKalle Valo * Control endpoint is full, don't allocate resources, we 281bdcd8170SKalle Valo * are just going to drop this packet. 282bdcd8170SKalle Valo */ 283bdcd8170SKalle Valo cookie = NULL; 284bdcd8170SKalle Valo ath6kl_err("wmi ctrl ep full, dropping pkt : 0x%p, len:%d\n", 285bdcd8170SKalle Valo skb, skb->len); 286bdcd8170SKalle Valo } else 287bdcd8170SKalle Valo cookie = ath6kl_alloc_cookie(ar); 288bdcd8170SKalle Valo 289bdcd8170SKalle Valo if (cookie == NULL) { 290bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 291bdcd8170SKalle Valo status = -ENOMEM; 292bdcd8170SKalle Valo goto fail_ctrl_tx; 293bdcd8170SKalle Valo } 294bdcd8170SKalle Valo 295bdcd8170SKalle Valo ar->tx_pending[eid]++; 296bdcd8170SKalle Valo 297bdcd8170SKalle Valo if (eid != ar->ctrl_ep) 298bdcd8170SKalle Valo ar->total_tx_data_pend++; 299bdcd8170SKalle Valo 300bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 301bdcd8170SKalle Valo 302bdcd8170SKalle Valo cookie->skb = skb; 303bdcd8170SKalle Valo cookie->map_no = 0; 304bdcd8170SKalle Valo set_htc_pkt_info(&cookie->htc_pkt, cookie, skb->data, skb->len, 305bdcd8170SKalle Valo eid, ATH6KL_CONTROL_PKT_TAG); 306bdcd8170SKalle Valo 307bdcd8170SKalle Valo /* 308bdcd8170SKalle Valo * This interface is asynchronous, if there is an error, cleanup 309bdcd8170SKalle Valo * will happen in the TX completion callback. 310bdcd8170SKalle Valo */ 311ad226ec2SKalle Valo ath6kl_htc_tx(ar->htc_target, &cookie->htc_pkt); 312bdcd8170SKalle Valo 313bdcd8170SKalle Valo return 0; 314bdcd8170SKalle Valo 315bdcd8170SKalle Valo fail_ctrl_tx: 316bdcd8170SKalle Valo dev_kfree_skb(skb); 317bdcd8170SKalle Valo return status; 318bdcd8170SKalle Valo } 319bdcd8170SKalle Valo 320bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev) 321bdcd8170SKalle Valo { 322bdcd8170SKalle Valo struct ath6kl *ar = ath6kl_priv(dev); 323bdcd8170SKalle Valo struct ath6kl_cookie *cookie = NULL; 324bdcd8170SKalle Valo enum htc_endpoint_id eid = ENDPOINT_UNUSED; 32559c98449SVasanthakumar Thiagarajan struct ath6kl_vif *vif = netdev_priv(dev); 326bdcd8170SKalle Valo u32 map_no = 0; 327bdcd8170SKalle Valo u16 htc_tag = ATH6KL_DATA_PKT_TAG; 328bdcd8170SKalle Valo u8 ac = 99 ; /* initialize to unmapped ac */ 329*c1762a3fSThirumalai Pachamuthu bool chk_adhoc_ps_mapping = false; 330bdcd8170SKalle Valo int ret; 331bc48ad31SRishi Panjwani struct wmi_tx_meta_v2 meta_v2; 332bc48ad31SRishi Panjwani void *meta; 333bc48ad31SRishi Panjwani u8 csum_start = 0, csum_dest = 0, csum = skb->ip_summed; 334bc48ad31SRishi Panjwani u8 meta_ver = 0; 335*c1762a3fSThirumalai Pachamuthu u32 flags = 0; 336bdcd8170SKalle Valo 337bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 338bdcd8170SKalle Valo "%s: skb=0x%p, data=0x%p, len=0x%x\n", __func__, 339bdcd8170SKalle Valo skb, skb->data, skb->len); 340bdcd8170SKalle Valo 341bdcd8170SKalle Valo /* If target is not associated */ 34259c98449SVasanthakumar Thiagarajan if (!test_bit(CONNECTED, &vif->flags)) { 343bdcd8170SKalle Valo dev_kfree_skb(skb); 344bdcd8170SKalle Valo return 0; 345bdcd8170SKalle Valo } 346bdcd8170SKalle Valo 347bdcd8170SKalle Valo if (!test_bit(WMI_READY, &ar->flag)) 348bdcd8170SKalle Valo goto fail_tx; 349bdcd8170SKalle Valo 350bdcd8170SKalle Valo /* AP mode Power saving processing */ 351f5938f24SVasanthakumar Thiagarajan if (vif->nw_type == AP_NETWORK) { 352*c1762a3fSThirumalai Pachamuthu if (ath6kl_powersave_ap(vif, skb, &flags)) 353bdcd8170SKalle Valo return 0; 354bdcd8170SKalle Valo } 355bdcd8170SKalle Valo 356bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) { 357bc48ad31SRishi Panjwani if ((dev->features & NETIF_F_IP_CSUM) && 358bc48ad31SRishi Panjwani (csum == CHECKSUM_PARTIAL)) { 359bc48ad31SRishi Panjwani csum_start = skb->csum_start - 360bc48ad31SRishi Panjwani (skb_network_header(skb) - skb->head) + 361bc48ad31SRishi Panjwani sizeof(struct ath6kl_llc_snap_hdr); 362bc48ad31SRishi Panjwani csum_dest = skb->csum_offset + csum_start; 363bc48ad31SRishi Panjwani } 364bc48ad31SRishi Panjwani 365bdcd8170SKalle Valo if (skb_headroom(skb) < dev->needed_headroom) { 366a29517ceSVasanthakumar Thiagarajan struct sk_buff *tmp_skb = skb; 367a29517ceSVasanthakumar Thiagarajan 368a29517ceSVasanthakumar Thiagarajan skb = skb_realloc_headroom(skb, dev->needed_headroom); 369a29517ceSVasanthakumar Thiagarajan kfree_skb(tmp_skb); 370a29517ceSVasanthakumar Thiagarajan if (skb == NULL) { 371a29517ceSVasanthakumar Thiagarajan vif->net_stats.tx_dropped++; 372a29517ceSVasanthakumar Thiagarajan return 0; 373a29517ceSVasanthakumar Thiagarajan } 374bdcd8170SKalle Valo } 375bdcd8170SKalle Valo 376bdcd8170SKalle Valo if (ath6kl_wmi_dix_2_dot3(ar->wmi, skb)) { 377bdcd8170SKalle Valo ath6kl_err("ath6kl_wmi_dix_2_dot3 failed\n"); 378bdcd8170SKalle Valo goto fail_tx; 379bdcd8170SKalle Valo } 380bdcd8170SKalle Valo 381bc48ad31SRishi Panjwani if ((dev->features & NETIF_F_IP_CSUM) && 382bc48ad31SRishi Panjwani (csum == CHECKSUM_PARTIAL)) { 383bc48ad31SRishi Panjwani meta_v2.csum_start = csum_start; 384bc48ad31SRishi Panjwani meta_v2.csum_dest = csum_dest; 385bc48ad31SRishi Panjwani 386bc48ad31SRishi Panjwani /* instruct target to calculate checksum */ 387bc48ad31SRishi Panjwani meta_v2.csum_flags = WMI_META_V2_FLAG_CSUM_OFFLOAD; 388bc48ad31SRishi Panjwani meta_ver = WMI_META_VERSION_2; 389bc48ad31SRishi Panjwani meta = &meta_v2; 390bc48ad31SRishi Panjwani } else { 391bc48ad31SRishi Panjwani meta_ver = 0; 392bc48ad31SRishi Panjwani meta = NULL; 393bc48ad31SRishi Panjwani } 394bc48ad31SRishi Panjwani 395bc48ad31SRishi Panjwani ret = ath6kl_wmi_data_hdr_add(ar->wmi, skb, 396*c1762a3fSThirumalai Pachamuthu DATA_MSGTYPE, flags, 0, 397bc48ad31SRishi Panjwani meta_ver, 398bc48ad31SRishi Panjwani meta, vif->fw_vif_idx); 399bc48ad31SRishi Panjwani 400bc48ad31SRishi Panjwani if (ret) { 401bc48ad31SRishi Panjwani ath6kl_warn("failed to add wmi data header:%d\n" 402bc48ad31SRishi Panjwani , ret); 403bdcd8170SKalle Valo goto fail_tx; 404bdcd8170SKalle Valo } 405bdcd8170SKalle Valo 406f5938f24SVasanthakumar Thiagarajan if ((vif->nw_type == ADHOC_NETWORK) && 40759c98449SVasanthakumar Thiagarajan ar->ibss_ps_enable && test_bit(CONNECTED, &vif->flags)) 408bdcd8170SKalle Valo chk_adhoc_ps_mapping = true; 409bdcd8170SKalle Valo else { 410bdcd8170SKalle Valo /* get the stream mapping */ 411240d2799SVasanthakumar Thiagarajan ret = ath6kl_wmi_implicit_create_pstream(ar->wmi, 412240d2799SVasanthakumar Thiagarajan vif->fw_vif_idx, skb, 41359c98449SVasanthakumar Thiagarajan 0, test_bit(WMM_ENABLED, &vif->flags), &ac); 414bdcd8170SKalle Valo if (ret) 415bdcd8170SKalle Valo goto fail_tx; 416bdcd8170SKalle Valo } 417bdcd8170SKalle Valo } else 418bdcd8170SKalle Valo goto fail_tx; 419bdcd8170SKalle Valo 420bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 421bdcd8170SKalle Valo 422bdcd8170SKalle Valo if (chk_adhoc_ps_mapping) 423bdcd8170SKalle Valo eid = ath6kl_ibss_map_epid(skb, dev, &map_no); 424bdcd8170SKalle Valo else 425bdcd8170SKalle Valo eid = ar->ac2ep_map[ac]; 426bdcd8170SKalle Valo 427bdcd8170SKalle Valo if (eid == 0 || eid == ENDPOINT_UNUSED) { 428bdcd8170SKalle Valo ath6kl_err("eid %d is not mapped!\n", eid); 429bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 430bdcd8170SKalle Valo goto fail_tx; 431bdcd8170SKalle Valo } 432bdcd8170SKalle Valo 433bdcd8170SKalle Valo /* allocate resource for this packet */ 434bdcd8170SKalle Valo cookie = ath6kl_alloc_cookie(ar); 435bdcd8170SKalle Valo 436bdcd8170SKalle Valo if (!cookie) { 437bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 438bdcd8170SKalle Valo goto fail_tx; 439bdcd8170SKalle Valo } 440bdcd8170SKalle Valo 441bdcd8170SKalle Valo /* update counts while the lock is held */ 442bdcd8170SKalle Valo ar->tx_pending[eid]++; 443bdcd8170SKalle Valo ar->total_tx_data_pend++; 444bdcd8170SKalle Valo 445bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 446bdcd8170SKalle Valo 44700b1edf1SJouni Malinen if (!IS_ALIGNED((unsigned long) skb->data - HTC_HDR_LENGTH, 4) && 44800b1edf1SJouni Malinen skb_cloned(skb)) { 44900b1edf1SJouni Malinen /* 45000b1edf1SJouni Malinen * We will touch (move the buffer data to align it. Since the 45100b1edf1SJouni Malinen * skb buffer is cloned and not only the header is changed, we 45200b1edf1SJouni Malinen * have to copy it to allow the changes. Since we are copying 45300b1edf1SJouni Malinen * the data here, we may as well align it by reserving suitable 45400b1edf1SJouni Malinen * headroom to avoid the memmove in ath6kl_htc_tx_buf_align(). 45500b1edf1SJouni Malinen */ 45600b1edf1SJouni Malinen struct sk_buff *nskb; 45700b1edf1SJouni Malinen 45800b1edf1SJouni Malinen nskb = skb_copy_expand(skb, HTC_HDR_LENGTH, 0, GFP_ATOMIC); 45900b1edf1SJouni Malinen if (nskb == NULL) 46000b1edf1SJouni Malinen goto fail_tx; 46100b1edf1SJouni Malinen kfree_skb(skb); 46200b1edf1SJouni Malinen skb = nskb; 46300b1edf1SJouni Malinen } 46400b1edf1SJouni Malinen 465bdcd8170SKalle Valo cookie->skb = skb; 466bdcd8170SKalle Valo cookie->map_no = map_no; 467bdcd8170SKalle Valo set_htc_pkt_info(&cookie->htc_pkt, cookie, skb->data, skb->len, 468bdcd8170SKalle Valo eid, htc_tag); 469bdcd8170SKalle Valo 470ef094103SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_RAW_BYTES, __func__, "tx ", 471ef094103SKalle Valo skb->data, skb->len); 472bdcd8170SKalle Valo 473bdcd8170SKalle Valo /* 474bdcd8170SKalle Valo * HTC interface is asynchronous, if this fails, cleanup will 475bdcd8170SKalle Valo * happen in the ath6kl_tx_complete callback. 476bdcd8170SKalle Valo */ 477ad226ec2SKalle Valo ath6kl_htc_tx(ar->htc_target, &cookie->htc_pkt); 478bdcd8170SKalle Valo 479bdcd8170SKalle Valo return 0; 480bdcd8170SKalle Valo 481bdcd8170SKalle Valo fail_tx: 482bdcd8170SKalle Valo dev_kfree_skb(skb); 483bdcd8170SKalle Valo 484b95907a7SVasanthakumar Thiagarajan vif->net_stats.tx_dropped++; 485b95907a7SVasanthakumar Thiagarajan vif->net_stats.tx_aborted_errors++; 486bdcd8170SKalle Valo 487bdcd8170SKalle Valo return 0; 488bdcd8170SKalle Valo } 489bdcd8170SKalle Valo 490bdcd8170SKalle Valo /* indicate tx activity or inactivity on a WMI stream */ 491bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active) 492bdcd8170SKalle Valo { 493bdcd8170SKalle Valo struct ath6kl *ar = devt; 494bdcd8170SKalle Valo enum htc_endpoint_id eid; 495bdcd8170SKalle Valo int i; 496bdcd8170SKalle Valo 497bdcd8170SKalle Valo eid = ar->ac2ep_map[traffic_class]; 498bdcd8170SKalle Valo 499bdcd8170SKalle Valo if (!test_bit(WMI_ENABLED, &ar->flag)) 500bdcd8170SKalle Valo goto notify_htc; 501bdcd8170SKalle Valo 502bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 503bdcd8170SKalle Valo 504bdcd8170SKalle Valo ar->ac_stream_active[traffic_class] = active; 505bdcd8170SKalle Valo 506bdcd8170SKalle Valo if (active) { 507bdcd8170SKalle Valo /* 508bdcd8170SKalle Valo * Keep track of the active stream with the highest 509bdcd8170SKalle Valo * priority. 510bdcd8170SKalle Valo */ 511bdcd8170SKalle Valo if (ar->ac_stream_pri_map[traffic_class] > 512bdcd8170SKalle Valo ar->hiac_stream_active_pri) 513bdcd8170SKalle Valo /* set the new highest active priority */ 514bdcd8170SKalle Valo ar->hiac_stream_active_pri = 515bdcd8170SKalle Valo ar->ac_stream_pri_map[traffic_class]; 516bdcd8170SKalle Valo 517bdcd8170SKalle Valo } else { 518bdcd8170SKalle Valo /* 519bdcd8170SKalle Valo * We may have to search for the next active stream 520bdcd8170SKalle Valo * that is the highest priority. 521bdcd8170SKalle Valo */ 522bdcd8170SKalle Valo if (ar->hiac_stream_active_pri == 523bdcd8170SKalle Valo ar->ac_stream_pri_map[traffic_class]) { 524bdcd8170SKalle Valo /* 525bdcd8170SKalle Valo * The highest priority stream just went inactive 526bdcd8170SKalle Valo * reset and search for the "next" highest "active" 527bdcd8170SKalle Valo * priority stream. 528bdcd8170SKalle Valo */ 529bdcd8170SKalle Valo ar->hiac_stream_active_pri = 0; 530bdcd8170SKalle Valo 531bdcd8170SKalle Valo for (i = 0; i < WMM_NUM_AC; i++) { 532bdcd8170SKalle Valo if (ar->ac_stream_active[i] && 533bdcd8170SKalle Valo (ar->ac_stream_pri_map[i] > 534bdcd8170SKalle Valo ar->hiac_stream_active_pri)) 535bdcd8170SKalle Valo /* 536bdcd8170SKalle Valo * Set the new highest active 537bdcd8170SKalle Valo * priority. 538bdcd8170SKalle Valo */ 539bdcd8170SKalle Valo ar->hiac_stream_active_pri = 540bdcd8170SKalle Valo ar->ac_stream_pri_map[i]; 541bdcd8170SKalle Valo } 542bdcd8170SKalle Valo } 543bdcd8170SKalle Valo } 544bdcd8170SKalle Valo 545bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 546bdcd8170SKalle Valo 547bdcd8170SKalle Valo notify_htc: 548bdcd8170SKalle Valo /* notify HTC, this may cause credit distribution changes */ 549ad226ec2SKalle Valo ath6kl_htc_indicate_activity_change(ar->htc_target, eid, active); 550bdcd8170SKalle Valo } 551bdcd8170SKalle Valo 552bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 553bdcd8170SKalle Valo struct htc_packet *packet) 554bdcd8170SKalle Valo { 555bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 556990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif; 557bdcd8170SKalle Valo enum htc_endpoint_id endpoint = packet->endpoint; 558990bd915SVasanthakumar Thiagarajan enum htc_send_full_action action = HTC_SEND_FULL_KEEP; 559bdcd8170SKalle Valo 560bdcd8170SKalle Valo if (endpoint == ar->ctrl_ep) { 561bdcd8170SKalle Valo /* 562bdcd8170SKalle Valo * Under normal WMI if this is getting full, then something 563bdcd8170SKalle Valo * is running rampant the host should not be exhausting the 564bdcd8170SKalle Valo * WMI queue with too many commands the only exception to 565bdcd8170SKalle Valo * this is during testing using endpointping. 566bdcd8170SKalle Valo */ 567bdcd8170SKalle Valo set_bit(WMI_CTRL_EP_FULL, &ar->flag); 568bdcd8170SKalle Valo ath6kl_err("wmi ctrl ep is full\n"); 569901db39cSVasanthakumar Thiagarajan return action; 570bdcd8170SKalle Valo } 571bdcd8170SKalle Valo 572bdcd8170SKalle Valo if (packet->info.tx.tag == ATH6KL_CONTROL_PKT_TAG) 573901db39cSVasanthakumar Thiagarajan return action; 574bdcd8170SKalle Valo 575bdcd8170SKalle Valo /* 576bdcd8170SKalle Valo * The last MAX_HI_COOKIE_NUM "batch" of cookies are reserved for 577bdcd8170SKalle Valo * the highest active stream. 578bdcd8170SKalle Valo */ 579bdcd8170SKalle Valo if (ar->ac_stream_pri_map[ar->ep2ac_map[endpoint]] < 580bdcd8170SKalle Valo ar->hiac_stream_active_pri && 581901db39cSVasanthakumar Thiagarajan ar->cookie_count <= MAX_HI_COOKIE_NUM) 582bdcd8170SKalle Valo /* 583bdcd8170SKalle Valo * Give preference to the highest priority stream by 584bdcd8170SKalle Valo * dropping the packets which overflowed. 585bdcd8170SKalle Valo */ 586990bd915SVasanthakumar Thiagarajan action = HTC_SEND_FULL_DROP; 587bdcd8170SKalle Valo 588990bd915SVasanthakumar Thiagarajan /* FIXME: Locking */ 58911f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 590990bd915SVasanthakumar Thiagarajan list_for_each_entry(vif, &ar->vif_list, list) { 591901db39cSVasanthakumar Thiagarajan if (vif->nw_type == ADHOC_NETWORK || 592901db39cSVasanthakumar Thiagarajan action != HTC_SEND_FULL_DROP) { 59311f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 594990bd915SVasanthakumar Thiagarajan 59559c98449SVasanthakumar Thiagarajan set_bit(NETQ_STOPPED, &vif->flags); 59628ae58ddSVasanthakumar Thiagarajan netif_stop_queue(vif->ndev); 597bdcd8170SKalle Valo 598990bd915SVasanthakumar Thiagarajan return action; 599990bd915SVasanthakumar Thiagarajan } 600990bd915SVasanthakumar Thiagarajan } 60111f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 602990bd915SVasanthakumar Thiagarajan 603990bd915SVasanthakumar Thiagarajan return action; 604bdcd8170SKalle Valo } 605bdcd8170SKalle Valo 606bdcd8170SKalle Valo /* TODO this needs to be looked at */ 607990bd915SVasanthakumar Thiagarajan static void ath6kl_tx_clear_node_map(struct ath6kl_vif *vif, 608bdcd8170SKalle Valo enum htc_endpoint_id eid, u32 map_no) 609bdcd8170SKalle Valo { 610990bd915SVasanthakumar Thiagarajan struct ath6kl *ar = vif->ar; 611bdcd8170SKalle Valo u32 i; 612bdcd8170SKalle Valo 613f5938f24SVasanthakumar Thiagarajan if (vif->nw_type != ADHOC_NETWORK) 614bdcd8170SKalle Valo return; 615bdcd8170SKalle Valo 616bdcd8170SKalle Valo if (!ar->ibss_ps_enable) 617bdcd8170SKalle Valo return; 618bdcd8170SKalle Valo 619bdcd8170SKalle Valo if (eid == ar->ctrl_ep) 620bdcd8170SKalle Valo return; 621bdcd8170SKalle Valo 622bdcd8170SKalle Valo if (map_no == 0) 623bdcd8170SKalle Valo return; 624bdcd8170SKalle Valo 625bdcd8170SKalle Valo map_no--; 626bdcd8170SKalle Valo ar->node_map[map_no].tx_pend--; 627bdcd8170SKalle Valo 628bdcd8170SKalle Valo if (ar->node_map[map_no].tx_pend) 629bdcd8170SKalle Valo return; 630bdcd8170SKalle Valo 631bdcd8170SKalle Valo if (map_no != (ar->node_num - 1)) 632bdcd8170SKalle Valo return; 633bdcd8170SKalle Valo 634bdcd8170SKalle Valo for (i = ar->node_num; i > 0; i--) { 635bdcd8170SKalle Valo if (ar->node_map[i - 1].tx_pend) 636bdcd8170SKalle Valo break; 637bdcd8170SKalle Valo 638bdcd8170SKalle Valo memset(&ar->node_map[i - 1], 0, 639bdcd8170SKalle Valo sizeof(struct ath6kl_node_mapping)); 640bdcd8170SKalle Valo ar->node_num--; 641bdcd8170SKalle Valo } 642bdcd8170SKalle Valo } 643bdcd8170SKalle Valo 644bdcd8170SKalle Valo void ath6kl_tx_complete(void *context, struct list_head *packet_queue) 645bdcd8170SKalle Valo { 646bdcd8170SKalle Valo struct ath6kl *ar = context; 647bdcd8170SKalle Valo struct sk_buff_head skb_queue; 648bdcd8170SKalle Valo struct htc_packet *packet; 649bdcd8170SKalle Valo struct sk_buff *skb; 650bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_cookie; 651bdcd8170SKalle Valo u32 map_no = 0; 652bdcd8170SKalle Valo int status; 653bdcd8170SKalle Valo enum htc_endpoint_id eid; 654bdcd8170SKalle Valo bool wake_event = false; 65571f96ee6SKalle Valo bool flushing[ATH6KL_VIF_MAX] = {false}; 6566765d0aaSVasanthakumar Thiagarajan u8 if_idx; 657990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif; 658bdcd8170SKalle Valo 659bdcd8170SKalle Valo skb_queue_head_init(&skb_queue); 660bdcd8170SKalle Valo 661bdcd8170SKalle Valo /* lock the driver as we update internal state */ 662bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 663bdcd8170SKalle Valo 664bdcd8170SKalle Valo /* reap completed packets */ 665bdcd8170SKalle Valo while (!list_empty(packet_queue)) { 666bdcd8170SKalle Valo 667bdcd8170SKalle Valo packet = list_first_entry(packet_queue, struct htc_packet, 668bdcd8170SKalle Valo list); 669bdcd8170SKalle Valo list_del(&packet->list); 670bdcd8170SKalle Valo 671bdcd8170SKalle Valo ath6kl_cookie = (struct ath6kl_cookie *)packet->pkt_cntxt; 672bdcd8170SKalle Valo if (!ath6kl_cookie) 673bdcd8170SKalle Valo goto fatal; 674bdcd8170SKalle Valo 675bdcd8170SKalle Valo status = packet->status; 676bdcd8170SKalle Valo skb = ath6kl_cookie->skb; 677bdcd8170SKalle Valo eid = packet->endpoint; 678bdcd8170SKalle Valo map_no = ath6kl_cookie->map_no; 679bdcd8170SKalle Valo 680bdcd8170SKalle Valo if (!skb || !skb->data) 681bdcd8170SKalle Valo goto fatal; 682bdcd8170SKalle Valo 683bdcd8170SKalle Valo __skb_queue_tail(&skb_queue, skb); 684bdcd8170SKalle Valo 685bdcd8170SKalle Valo if (!status && (packet->act_len != skb->len)) 686bdcd8170SKalle Valo goto fatal; 687bdcd8170SKalle Valo 688bdcd8170SKalle Valo ar->tx_pending[eid]--; 689bdcd8170SKalle Valo 690bdcd8170SKalle Valo if (eid != ar->ctrl_ep) 691bdcd8170SKalle Valo ar->total_tx_data_pend--; 692bdcd8170SKalle Valo 693bdcd8170SKalle Valo if (eid == ar->ctrl_ep) { 694bdcd8170SKalle Valo if (test_bit(WMI_CTRL_EP_FULL, &ar->flag)) 695bdcd8170SKalle Valo clear_bit(WMI_CTRL_EP_FULL, &ar->flag); 696bdcd8170SKalle Valo 697bdcd8170SKalle Valo if (ar->tx_pending[eid] == 0) 698bdcd8170SKalle Valo wake_event = true; 699bdcd8170SKalle Valo } 700bdcd8170SKalle Valo 7016765d0aaSVasanthakumar Thiagarajan if (eid == ar->ctrl_ep) { 7026765d0aaSVasanthakumar Thiagarajan if_idx = wmi_cmd_hdr_get_if_idx( 703f3803eb2SVasanthakumar Thiagarajan (struct wmi_cmd_hdr *) packet->buf); 7046765d0aaSVasanthakumar Thiagarajan } else { 7056765d0aaSVasanthakumar Thiagarajan if_idx = wmi_data_hdr_get_if_idx( 706f3803eb2SVasanthakumar Thiagarajan (struct wmi_data_hdr *) packet->buf); 7076765d0aaSVasanthakumar Thiagarajan } 7086765d0aaSVasanthakumar Thiagarajan 7096765d0aaSVasanthakumar Thiagarajan vif = ath6kl_get_vif_by_index(ar, if_idx); 7106765d0aaSVasanthakumar Thiagarajan if (!vif) { 7116765d0aaSVasanthakumar Thiagarajan ath6kl_free_cookie(ar, ath6kl_cookie); 7126765d0aaSVasanthakumar Thiagarajan continue; 7136765d0aaSVasanthakumar Thiagarajan } 7146765d0aaSVasanthakumar Thiagarajan 715bdcd8170SKalle Valo if (status) { 716bdcd8170SKalle Valo if (status == -ECANCELED) 717bdcd8170SKalle Valo /* a packet was flushed */ 718990bd915SVasanthakumar Thiagarajan flushing[if_idx] = true; 719bdcd8170SKalle Valo 720b95907a7SVasanthakumar Thiagarajan vif->net_stats.tx_errors++; 721bdcd8170SKalle Valo 722778e6502SKalle Valo if (status != -ENOSPC && status != -ECANCELED) 723778e6502SKalle Valo ath6kl_warn("tx complete error: %d\n", status); 724778e6502SKalle Valo 725bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 726bdcd8170SKalle Valo "%s: skb=0x%p data=0x%p len=0x%x eid=%d %s\n", 727bdcd8170SKalle Valo __func__, skb, packet->buf, packet->act_len, 728bdcd8170SKalle Valo eid, "error!"); 729bdcd8170SKalle Valo } else { 730bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 731bdcd8170SKalle Valo "%s: skb=0x%p data=0x%p len=0x%x eid=%d %s\n", 732bdcd8170SKalle Valo __func__, skb, packet->buf, packet->act_len, 733bdcd8170SKalle Valo eid, "OK"); 734bdcd8170SKalle Valo 735990bd915SVasanthakumar Thiagarajan flushing[if_idx] = false; 736b95907a7SVasanthakumar Thiagarajan vif->net_stats.tx_packets++; 737b95907a7SVasanthakumar Thiagarajan vif->net_stats.tx_bytes += skb->len; 738bdcd8170SKalle Valo } 739bdcd8170SKalle Valo 740990bd915SVasanthakumar Thiagarajan ath6kl_tx_clear_node_map(vif, eid, map_no); 741bdcd8170SKalle Valo 742bdcd8170SKalle Valo ath6kl_free_cookie(ar, ath6kl_cookie); 743bdcd8170SKalle Valo 74459c98449SVasanthakumar Thiagarajan if (test_bit(NETQ_STOPPED, &vif->flags)) 74559c98449SVasanthakumar Thiagarajan clear_bit(NETQ_STOPPED, &vif->flags); 746bdcd8170SKalle Valo } 747bdcd8170SKalle Valo 748bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 749bdcd8170SKalle Valo 750bdcd8170SKalle Valo __skb_queue_purge(&skb_queue); 751bdcd8170SKalle Valo 752990bd915SVasanthakumar Thiagarajan /* FIXME: Locking */ 75311f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 754990bd915SVasanthakumar Thiagarajan list_for_each_entry(vif, &ar->vif_list, list) { 755990bd915SVasanthakumar Thiagarajan if (test_bit(CONNECTED, &vif->flags) && 756990bd915SVasanthakumar Thiagarajan !flushing[vif->fw_vif_idx]) { 75711f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 75828ae58ddSVasanthakumar Thiagarajan netif_wake_queue(vif->ndev); 75911f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 760bdcd8170SKalle Valo } 761990bd915SVasanthakumar Thiagarajan } 76211f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 763bdcd8170SKalle Valo 764bdcd8170SKalle Valo if (wake_event) 765bdcd8170SKalle Valo wake_up(&ar->event_wq); 766bdcd8170SKalle Valo 767bdcd8170SKalle Valo return; 768bdcd8170SKalle Valo 769bdcd8170SKalle Valo fatal: 770bdcd8170SKalle Valo WARN_ON(1); 771bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 772bdcd8170SKalle Valo return; 773bdcd8170SKalle Valo } 774bdcd8170SKalle Valo 775bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar) 776bdcd8170SKalle Valo { 777bdcd8170SKalle Valo int i; 778bdcd8170SKalle Valo 779bdcd8170SKalle Valo /* flush all the data (non-control) streams */ 780bdcd8170SKalle Valo for (i = 0; i < WMM_NUM_AC; i++) 781ad226ec2SKalle Valo ath6kl_htc_flush_txep(ar->htc_target, ar->ac2ep_map[i], 782bdcd8170SKalle Valo ATH6KL_DATA_PKT_TAG); 783bdcd8170SKalle Valo } 784bdcd8170SKalle Valo 785bdcd8170SKalle Valo /* Rx functions */ 786bdcd8170SKalle Valo 787bdcd8170SKalle Valo static void ath6kl_deliver_frames_to_nw_stack(struct net_device *dev, 788bdcd8170SKalle Valo struct sk_buff *skb) 789bdcd8170SKalle Valo { 790bdcd8170SKalle Valo if (!skb) 791bdcd8170SKalle Valo return; 792bdcd8170SKalle Valo 793bdcd8170SKalle Valo skb->dev = dev; 794bdcd8170SKalle Valo 795bdcd8170SKalle Valo if (!(skb->dev->flags & IFF_UP)) { 796bdcd8170SKalle Valo dev_kfree_skb(skb); 797bdcd8170SKalle Valo return; 798bdcd8170SKalle Valo } 799bdcd8170SKalle Valo 800bdcd8170SKalle Valo skb->protocol = eth_type_trans(skb, skb->dev); 801bdcd8170SKalle Valo 802bdcd8170SKalle Valo netif_rx_ni(skb); 803bdcd8170SKalle Valo } 804bdcd8170SKalle Valo 805bdcd8170SKalle Valo static void ath6kl_alloc_netbufs(struct sk_buff_head *q, u16 num) 806bdcd8170SKalle Valo { 807bdcd8170SKalle Valo struct sk_buff *skb; 808bdcd8170SKalle Valo 809bdcd8170SKalle Valo while (num) { 810bdcd8170SKalle Valo skb = ath6kl_buf_alloc(ATH6KL_BUFFER_SIZE); 811bdcd8170SKalle Valo if (!skb) { 812bdcd8170SKalle Valo ath6kl_err("netbuf allocation failed\n"); 813bdcd8170SKalle Valo return; 814bdcd8170SKalle Valo } 815bdcd8170SKalle Valo skb_queue_tail(q, skb); 816bdcd8170SKalle Valo num--; 817bdcd8170SKalle Valo } 818bdcd8170SKalle Valo } 819bdcd8170SKalle Valo 820bdcd8170SKalle Valo static struct sk_buff *aggr_get_free_skb(struct aggr_info *p_aggr) 821bdcd8170SKalle Valo { 822bdcd8170SKalle Valo struct sk_buff *skb = NULL; 823bdcd8170SKalle Valo 824bdcd8170SKalle Valo if (skb_queue_len(&p_aggr->free_q) < (AGGR_NUM_OF_FREE_NETBUFS >> 2)) 825bdcd8170SKalle Valo ath6kl_alloc_netbufs(&p_aggr->free_q, AGGR_NUM_OF_FREE_NETBUFS); 826bdcd8170SKalle Valo 827bdcd8170SKalle Valo skb = skb_dequeue(&p_aggr->free_q); 828bdcd8170SKalle Valo 829bdcd8170SKalle Valo return skb; 830bdcd8170SKalle Valo } 831bdcd8170SKalle Valo 832bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, enum htc_endpoint_id endpoint) 833bdcd8170SKalle Valo { 834bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 835bdcd8170SKalle Valo struct sk_buff *skb; 836bdcd8170SKalle Valo int rx_buf; 837bdcd8170SKalle Valo int n_buf_refill; 838bdcd8170SKalle Valo struct htc_packet *packet; 839bdcd8170SKalle Valo struct list_head queue; 840bdcd8170SKalle Valo 841bdcd8170SKalle Valo n_buf_refill = ATH6KL_MAX_RX_BUFFERS - 842ad226ec2SKalle Valo ath6kl_htc_get_rxbuf_num(ar->htc_target, endpoint); 843bdcd8170SKalle Valo 844bdcd8170SKalle Valo if (n_buf_refill <= 0) 845bdcd8170SKalle Valo return; 846bdcd8170SKalle Valo 847bdcd8170SKalle Valo INIT_LIST_HEAD(&queue); 848bdcd8170SKalle Valo 849bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, 850bdcd8170SKalle Valo "%s: providing htc with %d buffers at eid=%d\n", 851bdcd8170SKalle Valo __func__, n_buf_refill, endpoint); 852bdcd8170SKalle Valo 853bdcd8170SKalle Valo for (rx_buf = 0; rx_buf < n_buf_refill; rx_buf++) { 854bdcd8170SKalle Valo skb = ath6kl_buf_alloc(ATH6KL_BUFFER_SIZE); 855bdcd8170SKalle Valo if (!skb) 856bdcd8170SKalle Valo break; 857bdcd8170SKalle Valo 858bdcd8170SKalle Valo packet = (struct htc_packet *) skb->head; 85994e532d1SVasanthakumar Thiagarajan if (!IS_ALIGNED((unsigned long) skb->data, 4)) 8601df94a85SVasanthakumar Thiagarajan skb->data = PTR_ALIGN(skb->data - 4, 4); 861bdcd8170SKalle Valo set_htc_rxpkt_info(packet, skb, skb->data, 862bdcd8170SKalle Valo ATH6KL_BUFFER_SIZE, endpoint); 863bdcd8170SKalle Valo list_add_tail(&packet->list, &queue); 864bdcd8170SKalle Valo } 865bdcd8170SKalle Valo 866bdcd8170SKalle Valo if (!list_empty(&queue)) 867ad226ec2SKalle Valo ath6kl_htc_add_rxbuf_multiple(ar->htc_target, &queue); 868bdcd8170SKalle Valo } 869bdcd8170SKalle Valo 870bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count) 871bdcd8170SKalle Valo { 872bdcd8170SKalle Valo struct htc_packet *packet; 873bdcd8170SKalle Valo struct sk_buff *skb; 874bdcd8170SKalle Valo 875bdcd8170SKalle Valo while (count) { 876bdcd8170SKalle Valo skb = ath6kl_buf_alloc(ATH6KL_AMSDU_BUFFER_SIZE); 877bdcd8170SKalle Valo if (!skb) 878bdcd8170SKalle Valo return; 879bdcd8170SKalle Valo 880bdcd8170SKalle Valo packet = (struct htc_packet *) skb->head; 88194e532d1SVasanthakumar Thiagarajan if (!IS_ALIGNED((unsigned long) skb->data, 4)) 8821df94a85SVasanthakumar Thiagarajan skb->data = PTR_ALIGN(skb->data - 4, 4); 883bdcd8170SKalle Valo set_htc_rxpkt_info(packet, skb, skb->data, 884bdcd8170SKalle Valo ATH6KL_AMSDU_BUFFER_SIZE, 0); 885bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 886bdcd8170SKalle Valo list_add_tail(&packet->list, &ar->amsdu_rx_buffer_queue); 887bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 888bdcd8170SKalle Valo count--; 889bdcd8170SKalle Valo } 890bdcd8170SKalle Valo } 891bdcd8170SKalle Valo 892bdcd8170SKalle Valo /* 893bdcd8170SKalle Valo * Callback to allocate a receive buffer for a pending packet. We use a 894bdcd8170SKalle Valo * pre-allocated list of buffers of maximum AMSDU size (4K). 895bdcd8170SKalle Valo */ 896bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 897bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 898bdcd8170SKalle Valo int len) 899bdcd8170SKalle Valo { 900bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 901bdcd8170SKalle Valo struct htc_packet *packet = NULL; 902bdcd8170SKalle Valo struct list_head *pkt_pos; 903bdcd8170SKalle Valo int refill_cnt = 0, depth = 0; 904bdcd8170SKalle Valo 905bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, "%s: eid=%d, len:%d\n", 906bdcd8170SKalle Valo __func__, endpoint, len); 907bdcd8170SKalle Valo 908bdcd8170SKalle Valo if ((len <= ATH6KL_BUFFER_SIZE) || 909bdcd8170SKalle Valo (len > ATH6KL_AMSDU_BUFFER_SIZE)) 910bdcd8170SKalle Valo return NULL; 911bdcd8170SKalle Valo 912bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 913bdcd8170SKalle Valo 914bdcd8170SKalle Valo if (list_empty(&ar->amsdu_rx_buffer_queue)) { 915bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 916bdcd8170SKalle Valo refill_cnt = ATH6KL_MAX_AMSDU_RX_BUFFERS; 917bdcd8170SKalle Valo goto refill_buf; 918bdcd8170SKalle Valo } 919bdcd8170SKalle Valo 920bdcd8170SKalle Valo packet = list_first_entry(&ar->amsdu_rx_buffer_queue, 921bdcd8170SKalle Valo struct htc_packet, list); 922bdcd8170SKalle Valo list_del(&packet->list); 923bdcd8170SKalle Valo list_for_each(pkt_pos, &ar->amsdu_rx_buffer_queue) 924bdcd8170SKalle Valo depth++; 925bdcd8170SKalle Valo 926bdcd8170SKalle Valo refill_cnt = ATH6KL_MAX_AMSDU_RX_BUFFERS - depth; 927bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 928bdcd8170SKalle Valo 929bdcd8170SKalle Valo /* set actual endpoint ID */ 930bdcd8170SKalle Valo packet->endpoint = endpoint; 931bdcd8170SKalle Valo 932bdcd8170SKalle Valo refill_buf: 933bdcd8170SKalle Valo if (refill_cnt >= ATH6KL_AMSDU_REFILL_THRESHOLD) 934bdcd8170SKalle Valo ath6kl_refill_amsdu_rxbufs(ar, refill_cnt); 935bdcd8170SKalle Valo 936bdcd8170SKalle Valo return packet; 937bdcd8170SKalle Valo } 938bdcd8170SKalle Valo 939bdcd8170SKalle Valo static void aggr_slice_amsdu(struct aggr_info *p_aggr, 940bdcd8170SKalle Valo struct rxtid *rxtid, struct sk_buff *skb) 941bdcd8170SKalle Valo { 942bdcd8170SKalle Valo struct sk_buff *new_skb; 943bdcd8170SKalle Valo struct ethhdr *hdr; 944bdcd8170SKalle Valo u16 frame_8023_len, payload_8023_len, mac_hdr_len, amsdu_len; 945bdcd8170SKalle Valo u8 *framep; 946bdcd8170SKalle Valo 947bdcd8170SKalle Valo mac_hdr_len = sizeof(struct ethhdr); 948bdcd8170SKalle Valo framep = skb->data + mac_hdr_len; 949bdcd8170SKalle Valo amsdu_len = skb->len - mac_hdr_len; 950bdcd8170SKalle Valo 951bdcd8170SKalle Valo while (amsdu_len > mac_hdr_len) { 952bdcd8170SKalle Valo hdr = (struct ethhdr *) framep; 953bdcd8170SKalle Valo payload_8023_len = ntohs(hdr->h_proto); 954bdcd8170SKalle Valo 955bdcd8170SKalle Valo if (payload_8023_len < MIN_MSDU_SUBFRAME_PAYLOAD_LEN || 956bdcd8170SKalle Valo payload_8023_len > MAX_MSDU_SUBFRAME_PAYLOAD_LEN) { 957bdcd8170SKalle Valo ath6kl_err("802.3 AMSDU frame bound check failed. len %d\n", 958bdcd8170SKalle Valo payload_8023_len); 959bdcd8170SKalle Valo break; 960bdcd8170SKalle Valo } 961bdcd8170SKalle Valo 962bdcd8170SKalle Valo frame_8023_len = payload_8023_len + mac_hdr_len; 963bdcd8170SKalle Valo new_skb = aggr_get_free_skb(p_aggr); 964bdcd8170SKalle Valo if (!new_skb) { 965bdcd8170SKalle Valo ath6kl_err("no buffer available\n"); 966bdcd8170SKalle Valo break; 967bdcd8170SKalle Valo } 968bdcd8170SKalle Valo 969bdcd8170SKalle Valo memcpy(new_skb->data, framep, frame_8023_len); 970bdcd8170SKalle Valo skb_put(new_skb, frame_8023_len); 971bdcd8170SKalle Valo if (ath6kl_wmi_dot3_2_dix(new_skb)) { 972bdcd8170SKalle Valo ath6kl_err("dot3_2_dix error\n"); 973bdcd8170SKalle Valo dev_kfree_skb(new_skb); 974bdcd8170SKalle Valo break; 975bdcd8170SKalle Valo } 976bdcd8170SKalle Valo 977bdcd8170SKalle Valo skb_queue_tail(&rxtid->q, new_skb); 978bdcd8170SKalle Valo 979bdcd8170SKalle Valo /* Is this the last subframe within this aggregate ? */ 980bdcd8170SKalle Valo if ((amsdu_len - frame_8023_len) == 0) 981bdcd8170SKalle Valo break; 982bdcd8170SKalle Valo 983bdcd8170SKalle Valo /* Add the length of A-MSDU subframe padding bytes - 984bdcd8170SKalle Valo * Round to nearest word. 985bdcd8170SKalle Valo */ 98613e34ea1SVasanthakumar Thiagarajan frame_8023_len = ALIGN(frame_8023_len, 4); 987bdcd8170SKalle Valo 988bdcd8170SKalle Valo framep += frame_8023_len; 989bdcd8170SKalle Valo amsdu_len -= frame_8023_len; 990bdcd8170SKalle Valo } 991bdcd8170SKalle Valo 992bdcd8170SKalle Valo dev_kfree_skb(skb); 993bdcd8170SKalle Valo } 994bdcd8170SKalle Valo 995bdcd8170SKalle Valo static void aggr_deque_frms(struct aggr_info *p_aggr, u8 tid, 996bdcd8170SKalle Valo u16 seq_no, u8 order) 997bdcd8170SKalle Valo { 998bdcd8170SKalle Valo struct sk_buff *skb; 999bdcd8170SKalle Valo struct rxtid *rxtid; 1000bdcd8170SKalle Valo struct skb_hold_q *node; 1001bdcd8170SKalle Valo u16 idx, idx_end, seq_end; 1002bdcd8170SKalle Valo struct rxtid_stats *stats; 1003bdcd8170SKalle Valo 1004bdcd8170SKalle Valo if (!p_aggr) 1005bdcd8170SKalle Valo return; 1006bdcd8170SKalle Valo 1007bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1008bdcd8170SKalle Valo stats = &p_aggr->stat[tid]; 1009bdcd8170SKalle Valo 1010bdcd8170SKalle Valo idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz); 1011bdcd8170SKalle Valo 1012bdcd8170SKalle Valo /* 1013bdcd8170SKalle Valo * idx_end is typically the last possible frame in the window, 1014bdcd8170SKalle Valo * but changes to 'the' seq_no, when BAR comes. If seq_no 1015bdcd8170SKalle Valo * is non-zero, we will go up to that and stop. 1016bdcd8170SKalle Valo * Note: last seq no in current window will occupy the same 1017bdcd8170SKalle Valo * index position as index that is just previous to start. 1018bdcd8170SKalle Valo * An imp point : if win_sz is 7, for seq_no space of 4095, 1019bdcd8170SKalle Valo * then, there would be holes when sequence wrap around occurs. 1020bdcd8170SKalle Valo * Target should judiciously choose the win_sz, based on 1021bdcd8170SKalle Valo * this condition. For 4095, (TID_WINDOW_SZ = 2 x win_sz 1022bdcd8170SKalle Valo * 2, 4, 8, 16 win_sz works fine). 1023bdcd8170SKalle Valo * We must deque from "idx" to "idx_end", including both. 1024bdcd8170SKalle Valo */ 1025bdcd8170SKalle Valo seq_end = seq_no ? seq_no : rxtid->seq_next; 1026bdcd8170SKalle Valo idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz); 1027bdcd8170SKalle Valo 1028bdcd8170SKalle Valo spin_lock_bh(&rxtid->lock); 1029bdcd8170SKalle Valo 1030bdcd8170SKalle Valo do { 1031bdcd8170SKalle Valo node = &rxtid->hold_q[idx]; 1032bdcd8170SKalle Valo if ((order == 1) && (!node->skb)) 1033bdcd8170SKalle Valo break; 1034bdcd8170SKalle Valo 1035bdcd8170SKalle Valo if (node->skb) { 1036bdcd8170SKalle Valo if (node->is_amsdu) 1037bdcd8170SKalle Valo aggr_slice_amsdu(p_aggr, rxtid, node->skb); 1038bdcd8170SKalle Valo else 1039bdcd8170SKalle Valo skb_queue_tail(&rxtid->q, node->skb); 1040bdcd8170SKalle Valo node->skb = NULL; 1041bdcd8170SKalle Valo } else 1042bdcd8170SKalle Valo stats->num_hole++; 1043bdcd8170SKalle Valo 1044bdcd8170SKalle Valo rxtid->seq_next = ATH6KL_NEXT_SEQ_NO(rxtid->seq_next); 1045bdcd8170SKalle Valo idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz); 1046bdcd8170SKalle Valo } while (idx != idx_end); 1047bdcd8170SKalle Valo 1048bdcd8170SKalle Valo spin_unlock_bh(&rxtid->lock); 1049bdcd8170SKalle Valo 1050bdcd8170SKalle Valo stats->num_delivered += skb_queue_len(&rxtid->q); 1051bdcd8170SKalle Valo 1052bdcd8170SKalle Valo while ((skb = skb_dequeue(&rxtid->q))) 1053bdcd8170SKalle Valo ath6kl_deliver_frames_to_nw_stack(p_aggr->dev, skb); 1054bdcd8170SKalle Valo } 1055bdcd8170SKalle Valo 1056bdcd8170SKalle Valo static bool aggr_process_recv_frm(struct aggr_info *agg_info, u8 tid, 1057bdcd8170SKalle Valo u16 seq_no, 1058bdcd8170SKalle Valo bool is_amsdu, struct sk_buff *frame) 1059bdcd8170SKalle Valo { 1060bdcd8170SKalle Valo struct rxtid *rxtid; 1061bdcd8170SKalle Valo struct rxtid_stats *stats; 1062bdcd8170SKalle Valo struct sk_buff *skb; 1063bdcd8170SKalle Valo struct skb_hold_q *node; 1064bdcd8170SKalle Valo u16 idx, st, cur, end; 1065bdcd8170SKalle Valo bool is_queued = false; 1066bdcd8170SKalle Valo u16 extended_end; 1067bdcd8170SKalle Valo 1068bdcd8170SKalle Valo rxtid = &agg_info->rx_tid[tid]; 1069bdcd8170SKalle Valo stats = &agg_info->stat[tid]; 1070bdcd8170SKalle Valo 1071bdcd8170SKalle Valo stats->num_into_aggr++; 1072bdcd8170SKalle Valo 1073bdcd8170SKalle Valo if (!rxtid->aggr) { 1074bdcd8170SKalle Valo if (is_amsdu) { 1075bdcd8170SKalle Valo aggr_slice_amsdu(agg_info, rxtid, frame); 1076bdcd8170SKalle Valo is_queued = true; 1077bdcd8170SKalle Valo stats->num_amsdu++; 1078bdcd8170SKalle Valo while ((skb = skb_dequeue(&rxtid->q))) 1079bdcd8170SKalle Valo ath6kl_deliver_frames_to_nw_stack(agg_info->dev, 1080bdcd8170SKalle Valo skb); 1081bdcd8170SKalle Valo } 1082bdcd8170SKalle Valo return is_queued; 1083bdcd8170SKalle Valo } 1084bdcd8170SKalle Valo 1085bdcd8170SKalle Valo /* Check the incoming sequence no, if it's in the window */ 1086bdcd8170SKalle Valo st = rxtid->seq_next; 1087bdcd8170SKalle Valo cur = seq_no; 1088bdcd8170SKalle Valo end = (st + rxtid->hold_q_sz-1) & ATH6KL_MAX_SEQ_NO; 1089bdcd8170SKalle Valo 1090bdcd8170SKalle Valo if (((st < end) && (cur < st || cur > end)) || 1091bdcd8170SKalle Valo ((st > end) && (cur > end) && (cur < st))) { 1092bdcd8170SKalle Valo extended_end = (end + rxtid->hold_q_sz - 1) & 1093bdcd8170SKalle Valo ATH6KL_MAX_SEQ_NO; 1094bdcd8170SKalle Valo 1095bdcd8170SKalle Valo if (((end < extended_end) && 1096bdcd8170SKalle Valo (cur < end || cur > extended_end)) || 1097bdcd8170SKalle Valo ((end > extended_end) && (cur > extended_end) && 1098bdcd8170SKalle Valo (cur < end))) { 1099bdcd8170SKalle Valo aggr_deque_frms(agg_info, tid, 0, 0); 1100bdcd8170SKalle Valo if (cur >= rxtid->hold_q_sz - 1) 1101bdcd8170SKalle Valo rxtid->seq_next = cur - (rxtid->hold_q_sz - 1); 1102bdcd8170SKalle Valo else 1103bdcd8170SKalle Valo rxtid->seq_next = ATH6KL_MAX_SEQ_NO - 1104bdcd8170SKalle Valo (rxtid->hold_q_sz - 2 - cur); 1105bdcd8170SKalle Valo } else { 1106bdcd8170SKalle Valo /* 1107bdcd8170SKalle Valo * Dequeue only those frames that are outside the 1108bdcd8170SKalle Valo * new shifted window. 1109bdcd8170SKalle Valo */ 1110bdcd8170SKalle Valo if (cur >= rxtid->hold_q_sz - 1) 1111bdcd8170SKalle Valo st = cur - (rxtid->hold_q_sz - 1); 1112bdcd8170SKalle Valo else 1113bdcd8170SKalle Valo st = ATH6KL_MAX_SEQ_NO - 1114bdcd8170SKalle Valo (rxtid->hold_q_sz - 2 - cur); 1115bdcd8170SKalle Valo 1116bdcd8170SKalle Valo aggr_deque_frms(agg_info, tid, st, 0); 1117bdcd8170SKalle Valo } 1118bdcd8170SKalle Valo 1119bdcd8170SKalle Valo stats->num_oow++; 1120bdcd8170SKalle Valo } 1121bdcd8170SKalle Valo 1122bdcd8170SKalle Valo idx = AGGR_WIN_IDX(seq_no, rxtid->hold_q_sz); 1123bdcd8170SKalle Valo 1124bdcd8170SKalle Valo node = &rxtid->hold_q[idx]; 1125bdcd8170SKalle Valo 1126bdcd8170SKalle Valo spin_lock_bh(&rxtid->lock); 1127bdcd8170SKalle Valo 1128bdcd8170SKalle Valo /* 1129bdcd8170SKalle Valo * Is the cur frame duplicate or something beyond our window(hold_q 1130bdcd8170SKalle Valo * -> which is 2x, already)? 1131bdcd8170SKalle Valo * 1132bdcd8170SKalle Valo * 1. Duplicate is easy - drop incoming frame. 1133bdcd8170SKalle Valo * 2. Not falling in current sliding window. 1134bdcd8170SKalle Valo * 2a. is the frame_seq_no preceding current tid_seq_no? 1135bdcd8170SKalle Valo * -> drop the frame. perhaps sender did not get our ACK. 1136bdcd8170SKalle Valo * this is taken care of above. 1137bdcd8170SKalle Valo * 2b. is the frame_seq_no beyond window(st, TID_WINDOW_SZ); 1138bdcd8170SKalle Valo * -> Taken care of it above, by moving window forward. 1139bdcd8170SKalle Valo */ 1140bdcd8170SKalle Valo dev_kfree_skb(node->skb); 1141bdcd8170SKalle Valo stats->num_dups++; 1142bdcd8170SKalle Valo 1143bdcd8170SKalle Valo node->skb = frame; 1144bdcd8170SKalle Valo is_queued = true; 1145bdcd8170SKalle Valo node->is_amsdu = is_amsdu; 1146bdcd8170SKalle Valo node->seq_no = seq_no; 1147bdcd8170SKalle Valo 1148bdcd8170SKalle Valo if (node->is_amsdu) 1149bdcd8170SKalle Valo stats->num_amsdu++; 1150bdcd8170SKalle Valo else 1151bdcd8170SKalle Valo stats->num_mpdu++; 1152bdcd8170SKalle Valo 1153bdcd8170SKalle Valo spin_unlock_bh(&rxtid->lock); 1154bdcd8170SKalle Valo 1155bdcd8170SKalle Valo aggr_deque_frms(agg_info, tid, 0, 1); 1156bdcd8170SKalle Valo 1157bdcd8170SKalle Valo if (agg_info->timer_scheduled) 1158bdcd8170SKalle Valo rxtid->progress = true; 1159bdcd8170SKalle Valo else 1160bdcd8170SKalle Valo for (idx = 0 ; idx < rxtid->hold_q_sz; idx++) { 1161bdcd8170SKalle Valo if (rxtid->hold_q[idx].skb) { 1162bdcd8170SKalle Valo /* 1163bdcd8170SKalle Valo * There is a frame in the queue and no 1164bdcd8170SKalle Valo * timer so start a timer to ensure that 1165bdcd8170SKalle Valo * the frame doesn't remain stuck 1166bdcd8170SKalle Valo * forever. 1167bdcd8170SKalle Valo */ 1168bdcd8170SKalle Valo agg_info->timer_scheduled = true; 1169bdcd8170SKalle Valo mod_timer(&agg_info->timer, 1170bdcd8170SKalle Valo (jiffies + 1171bdcd8170SKalle Valo HZ * (AGGR_RX_TIMEOUT) / 1000)); 1172bdcd8170SKalle Valo rxtid->progress = false; 1173bdcd8170SKalle Valo rxtid->timer_mon = true; 1174bdcd8170SKalle Valo break; 1175bdcd8170SKalle Valo } 1176bdcd8170SKalle Valo } 1177bdcd8170SKalle Valo 1178bdcd8170SKalle Valo return is_queued; 1179bdcd8170SKalle Valo } 1180bdcd8170SKalle Valo 1181*c1762a3fSThirumalai Pachamuthu static void ath6kl_uapsd_trigger_frame_rx(struct ath6kl_vif *vif, 1182*c1762a3fSThirumalai Pachamuthu struct ath6kl_sta *conn) 1183*c1762a3fSThirumalai Pachamuthu { 1184*c1762a3fSThirumalai Pachamuthu struct ath6kl *ar = vif->ar; 1185*c1762a3fSThirumalai Pachamuthu bool is_apsdq_empty, is_apsdq_empty_at_start; 1186*c1762a3fSThirumalai Pachamuthu u32 num_frames_to_deliver, flags; 1187*c1762a3fSThirumalai Pachamuthu struct sk_buff *skb = NULL; 1188*c1762a3fSThirumalai Pachamuthu 1189*c1762a3fSThirumalai Pachamuthu /* 1190*c1762a3fSThirumalai Pachamuthu * If the APSD q for this STA is not empty, dequeue and 1191*c1762a3fSThirumalai Pachamuthu * send a pkt from the head of the q. Also update the 1192*c1762a3fSThirumalai Pachamuthu * More data bit in the WMI_DATA_HDR if there are 1193*c1762a3fSThirumalai Pachamuthu * more pkts for this STA in the APSD q. 1194*c1762a3fSThirumalai Pachamuthu * If there are no more pkts for this STA, 1195*c1762a3fSThirumalai Pachamuthu * update the APSD bitmap for this STA. 1196*c1762a3fSThirumalai Pachamuthu */ 1197*c1762a3fSThirumalai Pachamuthu 1198*c1762a3fSThirumalai Pachamuthu num_frames_to_deliver = (conn->apsd_info >> ATH6KL_APSD_NUM_OF_AC) & 1199*c1762a3fSThirumalai Pachamuthu ATH6KL_APSD_FRAME_MASK; 1200*c1762a3fSThirumalai Pachamuthu /* 1201*c1762a3fSThirumalai Pachamuthu * Number of frames to send in a service period is 1202*c1762a3fSThirumalai Pachamuthu * indicated by the station 1203*c1762a3fSThirumalai Pachamuthu * in the QOS_INFO of the association request 1204*c1762a3fSThirumalai Pachamuthu * If it is zero, send all frames 1205*c1762a3fSThirumalai Pachamuthu */ 1206*c1762a3fSThirumalai Pachamuthu if (!num_frames_to_deliver) 1207*c1762a3fSThirumalai Pachamuthu num_frames_to_deliver = ATH6KL_APSD_ALL_FRAME; 1208*c1762a3fSThirumalai Pachamuthu 1209*c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 1210*c1762a3fSThirumalai Pachamuthu is_apsdq_empty = skb_queue_empty(&conn->apsdq); 1211*c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 1212*c1762a3fSThirumalai Pachamuthu is_apsdq_empty_at_start = is_apsdq_empty; 1213*c1762a3fSThirumalai Pachamuthu 1214*c1762a3fSThirumalai Pachamuthu while ((!is_apsdq_empty) && (num_frames_to_deliver)) { 1215*c1762a3fSThirumalai Pachamuthu 1216*c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 1217*c1762a3fSThirumalai Pachamuthu skb = skb_dequeue(&conn->apsdq); 1218*c1762a3fSThirumalai Pachamuthu is_apsdq_empty = skb_queue_empty(&conn->apsdq); 1219*c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 1220*c1762a3fSThirumalai Pachamuthu 1221*c1762a3fSThirumalai Pachamuthu /* 1222*c1762a3fSThirumalai Pachamuthu * Set the STA flag to Trigger delivery, 1223*c1762a3fSThirumalai Pachamuthu * so that the frame will go out 1224*c1762a3fSThirumalai Pachamuthu */ 1225*c1762a3fSThirumalai Pachamuthu conn->sta_flags |= STA_PS_APSD_TRIGGER; 1226*c1762a3fSThirumalai Pachamuthu num_frames_to_deliver--; 1227*c1762a3fSThirumalai Pachamuthu 1228*c1762a3fSThirumalai Pachamuthu /* Last frame in the service period, set EOSP or queue empty */ 1229*c1762a3fSThirumalai Pachamuthu if ((is_apsdq_empty) || (!num_frames_to_deliver)) 1230*c1762a3fSThirumalai Pachamuthu conn->sta_flags |= STA_PS_APSD_EOSP; 1231*c1762a3fSThirumalai Pachamuthu 1232*c1762a3fSThirumalai Pachamuthu ath6kl_data_tx(skb, vif->ndev); 1233*c1762a3fSThirumalai Pachamuthu conn->sta_flags &= ~(STA_PS_APSD_TRIGGER); 1234*c1762a3fSThirumalai Pachamuthu conn->sta_flags &= ~(STA_PS_APSD_EOSP); 1235*c1762a3fSThirumalai Pachamuthu } 1236*c1762a3fSThirumalai Pachamuthu 1237*c1762a3fSThirumalai Pachamuthu if (is_apsdq_empty) { 1238*c1762a3fSThirumalai Pachamuthu if (is_apsdq_empty_at_start) 1239*c1762a3fSThirumalai Pachamuthu flags = WMI_AP_APSD_NO_DELIVERY_FRAMES; 1240*c1762a3fSThirumalai Pachamuthu else 1241*c1762a3fSThirumalai Pachamuthu flags = 0; 1242*c1762a3fSThirumalai Pachamuthu 1243*c1762a3fSThirumalai Pachamuthu ath6kl_wmi_set_apsd_bfrd_traf(ar->wmi, 1244*c1762a3fSThirumalai Pachamuthu vif->fw_vif_idx, 1245*c1762a3fSThirumalai Pachamuthu conn->aid, 0, flags); 1246*c1762a3fSThirumalai Pachamuthu } 1247*c1762a3fSThirumalai Pachamuthu 1248*c1762a3fSThirumalai Pachamuthu return; 1249*c1762a3fSThirumalai Pachamuthu } 1250*c1762a3fSThirumalai Pachamuthu 1251bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet) 1252bdcd8170SKalle Valo { 1253bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 1254bdcd8170SKalle Valo struct sk_buff *skb = packet->pkt_cntxt; 1255bdcd8170SKalle Valo struct wmi_rx_meta_v2 *meta; 1256bdcd8170SKalle Valo struct wmi_data_hdr *dhdr; 1257bdcd8170SKalle Valo int min_hdr_len; 1258bdcd8170SKalle Valo u8 meta_type, dot11_hdr = 0; 1259bdcd8170SKalle Valo int status = packet->status; 1260bdcd8170SKalle Valo enum htc_endpoint_id ept = packet->endpoint; 1261bdcd8170SKalle Valo bool is_amsdu, prev_ps, ps_state = false; 1262*c1762a3fSThirumalai Pachamuthu bool trig_state = false; 1263bdcd8170SKalle Valo struct ath6kl_sta *conn = NULL; 1264bdcd8170SKalle Valo struct sk_buff *skb1 = NULL; 1265bdcd8170SKalle Valo struct ethhdr *datap = NULL; 12666765d0aaSVasanthakumar Thiagarajan struct ath6kl_vif *vif; 1267bdcd8170SKalle Valo u16 seq_no, offset; 12686765d0aaSVasanthakumar Thiagarajan u8 tid, if_idx; 1269bdcd8170SKalle Valo 1270bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, 1271bdcd8170SKalle Valo "%s: ar=0x%p eid=%d, skb=0x%p, data=0x%p, len=0x%x status:%d", 1272bdcd8170SKalle Valo __func__, ar, ept, skb, packet->buf, 1273bdcd8170SKalle Valo packet->act_len, status); 1274bdcd8170SKalle Valo 1275bdcd8170SKalle Valo if (status || !(skb->data + HTC_HDR_LENGTH)) { 12766765d0aaSVasanthakumar Thiagarajan dev_kfree_skb(skb); 12776765d0aaSVasanthakumar Thiagarajan return; 12786765d0aaSVasanthakumar Thiagarajan } 12796765d0aaSVasanthakumar Thiagarajan 12806765d0aaSVasanthakumar Thiagarajan skb_put(skb, packet->act_len + HTC_HDR_LENGTH); 12816765d0aaSVasanthakumar Thiagarajan skb_pull(skb, HTC_HDR_LENGTH); 12826765d0aaSVasanthakumar Thiagarajan 12836765d0aaSVasanthakumar Thiagarajan if (ept == ar->ctrl_ep) { 12846765d0aaSVasanthakumar Thiagarajan if_idx = 12856765d0aaSVasanthakumar Thiagarajan wmi_cmd_hdr_get_if_idx((struct wmi_cmd_hdr *) skb->data); 12866765d0aaSVasanthakumar Thiagarajan } else { 12876765d0aaSVasanthakumar Thiagarajan if_idx = 12886765d0aaSVasanthakumar Thiagarajan wmi_data_hdr_get_if_idx((struct wmi_data_hdr *) skb->data); 12896765d0aaSVasanthakumar Thiagarajan } 12906765d0aaSVasanthakumar Thiagarajan 12916765d0aaSVasanthakumar Thiagarajan vif = ath6kl_get_vif_by_index(ar, if_idx); 12926765d0aaSVasanthakumar Thiagarajan if (!vif) { 1293bdcd8170SKalle Valo dev_kfree_skb(skb); 1294bdcd8170SKalle Valo return; 1295bdcd8170SKalle Valo } 1296bdcd8170SKalle Valo 1297bdcd8170SKalle Valo /* 1298bdcd8170SKalle Valo * Take lock to protect buffer counts and adaptive power throughput 1299bdcd8170SKalle Valo * state. 1300bdcd8170SKalle Valo */ 1301478ac027SVasanthakumar Thiagarajan spin_lock_bh(&vif->if_lock); 1302bdcd8170SKalle Valo 1303b95907a7SVasanthakumar Thiagarajan vif->net_stats.rx_packets++; 1304b95907a7SVasanthakumar Thiagarajan vif->net_stats.rx_bytes += packet->act_len; 1305bdcd8170SKalle Valo 1306478ac027SVasanthakumar Thiagarajan spin_unlock_bh(&vif->if_lock); 130783dc5f2fSVasanthakumar Thiagarajan 1308bdcd8170SKalle Valo 1309ef094103SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_RAW_BYTES, __func__, "rx ", 1310ef094103SKalle Valo skb->data, skb->len); 1311bdcd8170SKalle Valo 131228ae58ddSVasanthakumar Thiagarajan skb->dev = vif->ndev; 1313bdcd8170SKalle Valo 1314bdcd8170SKalle Valo if (!test_bit(WMI_ENABLED, &ar->flag)) { 1315bdcd8170SKalle Valo if (EPPING_ALIGNMENT_PAD > 0) 1316bdcd8170SKalle Valo skb_pull(skb, EPPING_ALIGNMENT_PAD); 131728ae58ddSVasanthakumar Thiagarajan ath6kl_deliver_frames_to_nw_stack(vif->ndev, skb); 1318bdcd8170SKalle Valo return; 1319bdcd8170SKalle Valo } 1320bdcd8170SKalle Valo 1321a918fb3cSRaja Mani ath6kl_check_wow_status(ar); 1322a918fb3cSRaja Mani 1323bdcd8170SKalle Valo if (ept == ar->ctrl_ep) { 1324bdcd8170SKalle Valo ath6kl_wmi_control_rx(ar->wmi, skb); 1325bdcd8170SKalle Valo return; 1326bdcd8170SKalle Valo } 1327bdcd8170SKalle Valo 132867f9178fSVasanthakumar Thiagarajan min_hdr_len = sizeof(struct ethhdr) + sizeof(struct wmi_data_hdr) + 1329bdcd8170SKalle Valo sizeof(struct ath6kl_llc_snap_hdr); 1330bdcd8170SKalle Valo 1331bdcd8170SKalle Valo dhdr = (struct wmi_data_hdr *) skb->data; 1332bdcd8170SKalle Valo 1333bdcd8170SKalle Valo /* 1334bdcd8170SKalle Valo * In the case of AP mode we may receive NULL data frames 1335bdcd8170SKalle Valo * that do not have LLC hdr. They are 16 bytes in size. 1336bdcd8170SKalle Valo * Allow these frames in the AP mode. 1337bdcd8170SKalle Valo */ 1338f5938f24SVasanthakumar Thiagarajan if (vif->nw_type != AP_NETWORK && 1339bdcd8170SKalle Valo ((packet->act_len < min_hdr_len) || 1340bdcd8170SKalle Valo (packet->act_len > WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH))) { 1341bdcd8170SKalle Valo ath6kl_info("frame len is too short or too long\n"); 1342b95907a7SVasanthakumar Thiagarajan vif->net_stats.rx_errors++; 1343b95907a7SVasanthakumar Thiagarajan vif->net_stats.rx_length_errors++; 1344bdcd8170SKalle Valo dev_kfree_skb(skb); 1345bdcd8170SKalle Valo return; 1346bdcd8170SKalle Valo } 1347bdcd8170SKalle Valo 1348bdcd8170SKalle Valo /* Get the Power save state of the STA */ 1349f5938f24SVasanthakumar Thiagarajan if (vif->nw_type == AP_NETWORK) { 1350bdcd8170SKalle Valo meta_type = wmi_data_hdr_get_meta(dhdr); 1351bdcd8170SKalle Valo 1352bdcd8170SKalle Valo ps_state = !!((dhdr->info >> WMI_DATA_HDR_PS_SHIFT) & 1353bdcd8170SKalle Valo WMI_DATA_HDR_PS_MASK); 1354bdcd8170SKalle Valo 1355bdcd8170SKalle Valo offset = sizeof(struct wmi_data_hdr); 1356*c1762a3fSThirumalai Pachamuthu trig_state = !!(le16_to_cpu(dhdr->info3) & WMI_DATA_HDR_TRIG); 1357bdcd8170SKalle Valo 1358bdcd8170SKalle Valo switch (meta_type) { 1359bdcd8170SKalle Valo case 0: 1360bdcd8170SKalle Valo break; 1361bdcd8170SKalle Valo case WMI_META_VERSION_1: 1362bdcd8170SKalle Valo offset += sizeof(struct wmi_rx_meta_v1); 1363bdcd8170SKalle Valo break; 1364bdcd8170SKalle Valo case WMI_META_VERSION_2: 1365bdcd8170SKalle Valo offset += sizeof(struct wmi_rx_meta_v2); 1366bdcd8170SKalle Valo break; 1367bdcd8170SKalle Valo default: 1368bdcd8170SKalle Valo break; 1369bdcd8170SKalle Valo } 1370bdcd8170SKalle Valo 1371bdcd8170SKalle Valo datap = (struct ethhdr *) (skb->data + offset); 13726765d0aaSVasanthakumar Thiagarajan conn = ath6kl_find_sta(vif, datap->h_source); 1373bdcd8170SKalle Valo 1374bdcd8170SKalle Valo if (!conn) { 1375bdcd8170SKalle Valo dev_kfree_skb(skb); 1376bdcd8170SKalle Valo return; 1377bdcd8170SKalle Valo } 1378bdcd8170SKalle Valo 1379bdcd8170SKalle Valo /* 1380bdcd8170SKalle Valo * If there is a change in PS state of the STA, 1381bdcd8170SKalle Valo * take appropriate steps: 1382bdcd8170SKalle Valo * 1383bdcd8170SKalle Valo * 1. If Sleep-->Awake, flush the psq for the STA 1384bdcd8170SKalle Valo * Clear the PVB for the STA. 1385bdcd8170SKalle Valo * 2. If Awake-->Sleep, Starting queueing frames 1386bdcd8170SKalle Valo * the STA. 1387bdcd8170SKalle Valo */ 1388bdcd8170SKalle Valo prev_ps = !!(conn->sta_flags & STA_PS_SLEEP); 1389bdcd8170SKalle Valo 1390bdcd8170SKalle Valo if (ps_state) 1391bdcd8170SKalle Valo conn->sta_flags |= STA_PS_SLEEP; 1392bdcd8170SKalle Valo else 1393bdcd8170SKalle Valo conn->sta_flags &= ~STA_PS_SLEEP; 1394bdcd8170SKalle Valo 1395*c1762a3fSThirumalai Pachamuthu /* Accept trigger only when the station is in sleep */ 1396*c1762a3fSThirumalai Pachamuthu if ((conn->sta_flags & STA_PS_SLEEP) && trig_state) 1397*c1762a3fSThirumalai Pachamuthu ath6kl_uapsd_trigger_frame_rx(vif, conn); 1398*c1762a3fSThirumalai Pachamuthu 1399bdcd8170SKalle Valo if (prev_ps ^ !!(conn->sta_flags & STA_PS_SLEEP)) { 1400bdcd8170SKalle Valo if (!(conn->sta_flags & STA_PS_SLEEP)) { 1401bdcd8170SKalle Valo struct sk_buff *skbuff = NULL; 1402*c1762a3fSThirumalai Pachamuthu bool is_apsdq_empty; 1403bdcd8170SKalle Valo 1404bdcd8170SKalle Valo spin_lock_bh(&conn->psq_lock); 1405*c1762a3fSThirumalai Pachamuthu while ((skbuff = skb_dequeue(&conn->psq))) { 1406*c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 1407*c1762a3fSThirumalai Pachamuthu ath6kl_data_tx(skbuff, vif->ndev); 1408*c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 1409*c1762a3fSThirumalai Pachamuthu } 1410*c1762a3fSThirumalai Pachamuthu 1411*c1762a3fSThirumalai Pachamuthu is_apsdq_empty = skb_queue_empty(&conn->apsdq); 1412*c1762a3fSThirumalai Pachamuthu while ((skbuff = skb_dequeue(&conn->apsdq))) { 1413bdcd8170SKalle Valo spin_unlock_bh(&conn->psq_lock); 141428ae58ddSVasanthakumar Thiagarajan ath6kl_data_tx(skbuff, vif->ndev); 1415bdcd8170SKalle Valo spin_lock_bh(&conn->psq_lock); 1416bdcd8170SKalle Valo } 1417bdcd8170SKalle Valo spin_unlock_bh(&conn->psq_lock); 1418*c1762a3fSThirumalai Pachamuthu 1419*c1762a3fSThirumalai Pachamuthu if (!is_apsdq_empty) 1420*c1762a3fSThirumalai Pachamuthu ath6kl_wmi_set_apsd_bfrd_traf( 1421*c1762a3fSThirumalai Pachamuthu ar->wmi, 1422*c1762a3fSThirumalai Pachamuthu vif->fw_vif_idx, 1423*c1762a3fSThirumalai Pachamuthu conn->aid, 0, 0); 1424*c1762a3fSThirumalai Pachamuthu 1425bdcd8170SKalle Valo /* Clear the PVB for this STA */ 1426334234b5SVasanthakumar Thiagarajan ath6kl_wmi_set_pvb_cmd(ar->wmi, vif->fw_vif_idx, 1427334234b5SVasanthakumar Thiagarajan conn->aid, 0); 1428bdcd8170SKalle Valo } 1429bdcd8170SKalle Valo } 1430bdcd8170SKalle Valo 1431bdcd8170SKalle Valo /* drop NULL data frames here */ 1432bdcd8170SKalle Valo if ((packet->act_len < min_hdr_len) || 1433bdcd8170SKalle Valo (packet->act_len > 1434bdcd8170SKalle Valo WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH)) { 1435bdcd8170SKalle Valo dev_kfree_skb(skb); 1436bdcd8170SKalle Valo return; 1437bdcd8170SKalle Valo } 1438bdcd8170SKalle Valo } 1439bdcd8170SKalle Valo 1440bdcd8170SKalle Valo is_amsdu = wmi_data_hdr_is_amsdu(dhdr) ? true : false; 1441bdcd8170SKalle Valo tid = wmi_data_hdr_get_up(dhdr); 1442bdcd8170SKalle Valo seq_no = wmi_data_hdr_get_seqno(dhdr); 1443bdcd8170SKalle Valo meta_type = wmi_data_hdr_get_meta(dhdr); 1444bdcd8170SKalle Valo dot11_hdr = wmi_data_hdr_get_dot11(dhdr); 1445594a0bc8SVasanthakumar Thiagarajan skb_pull(skb, sizeof(struct wmi_data_hdr)); 1446bdcd8170SKalle Valo 1447bdcd8170SKalle Valo switch (meta_type) { 1448bdcd8170SKalle Valo case WMI_META_VERSION_1: 1449bdcd8170SKalle Valo skb_pull(skb, sizeof(struct wmi_rx_meta_v1)); 1450bdcd8170SKalle Valo break; 1451bdcd8170SKalle Valo case WMI_META_VERSION_2: 1452bdcd8170SKalle Valo meta = (struct wmi_rx_meta_v2 *) skb->data; 1453bdcd8170SKalle Valo if (meta->csum_flags & 0x1) { 1454bdcd8170SKalle Valo skb->ip_summed = CHECKSUM_COMPLETE; 1455bdcd8170SKalle Valo skb->csum = (__force __wsum) meta->csum; 1456bdcd8170SKalle Valo } 1457bdcd8170SKalle Valo skb_pull(skb, sizeof(struct wmi_rx_meta_v2)); 1458bdcd8170SKalle Valo break; 1459bdcd8170SKalle Valo default: 1460bdcd8170SKalle Valo break; 1461bdcd8170SKalle Valo } 1462bdcd8170SKalle Valo 1463bdcd8170SKalle Valo if (dot11_hdr) 1464bdcd8170SKalle Valo status = ath6kl_wmi_dot11_hdr_remove(ar->wmi, skb); 1465bdcd8170SKalle Valo else if (!is_amsdu) 1466bdcd8170SKalle Valo status = ath6kl_wmi_dot3_2_dix(skb); 1467bdcd8170SKalle Valo 1468bdcd8170SKalle Valo if (status) { 1469bdcd8170SKalle Valo /* 1470bdcd8170SKalle Valo * Drop frames that could not be processed (lack of 1471bdcd8170SKalle Valo * memory, etc.) 1472bdcd8170SKalle Valo */ 1473bdcd8170SKalle Valo dev_kfree_skb(skb); 1474bdcd8170SKalle Valo return; 1475bdcd8170SKalle Valo } 1476bdcd8170SKalle Valo 147728ae58ddSVasanthakumar Thiagarajan if (!(vif->ndev->flags & IFF_UP)) { 1478bdcd8170SKalle Valo dev_kfree_skb(skb); 1479bdcd8170SKalle Valo return; 1480bdcd8170SKalle Valo } 1481bdcd8170SKalle Valo 1482f5938f24SVasanthakumar Thiagarajan if (vif->nw_type == AP_NETWORK) { 1483bdcd8170SKalle Valo datap = (struct ethhdr *) skb->data; 1484bdcd8170SKalle Valo if (is_multicast_ether_addr(datap->h_dest)) 1485bdcd8170SKalle Valo /* 1486bdcd8170SKalle Valo * Bcast/Mcast frames should be sent to the 1487bdcd8170SKalle Valo * OS stack as well as on the air. 1488bdcd8170SKalle Valo */ 1489bdcd8170SKalle Valo skb1 = skb_copy(skb, GFP_ATOMIC); 1490bdcd8170SKalle Valo else { 1491bdcd8170SKalle Valo /* 1492bdcd8170SKalle Valo * Search for a connected STA with dstMac 1493bdcd8170SKalle Valo * as the Mac address. If found send the 1494bdcd8170SKalle Valo * frame to it on the air else send the 1495bdcd8170SKalle Valo * frame up the stack. 1496bdcd8170SKalle Valo */ 14976765d0aaSVasanthakumar Thiagarajan conn = ath6kl_find_sta(vif, datap->h_dest); 1498bdcd8170SKalle Valo 1499bdcd8170SKalle Valo if (conn && ar->intra_bss) { 1500bdcd8170SKalle Valo skb1 = skb; 1501bdcd8170SKalle Valo skb = NULL; 1502bdcd8170SKalle Valo } else if (conn && !ar->intra_bss) { 1503bdcd8170SKalle Valo dev_kfree_skb(skb); 1504bdcd8170SKalle Valo skb = NULL; 1505bdcd8170SKalle Valo } 1506bdcd8170SKalle Valo } 1507bdcd8170SKalle Valo if (skb1) 150828ae58ddSVasanthakumar Thiagarajan ath6kl_data_tx(skb1, vif->ndev); 1509ad3f78b9SKalle Valo 1510ad3f78b9SKalle Valo if (skb == NULL) { 1511ad3f78b9SKalle Valo /* nothing to deliver up the stack */ 1512ad3f78b9SKalle Valo return; 1513ad3f78b9SKalle Valo } 1514bdcd8170SKalle Valo } 1515bdcd8170SKalle Valo 15165694f962SKalle Valo datap = (struct ethhdr *) skb->data; 15175694f962SKalle Valo 15185694f962SKalle Valo if (is_unicast_ether_addr(datap->h_dest) && 15192132c69cSVasanthakumar Thiagarajan aggr_process_recv_frm(vif->aggr_cntxt, tid, seq_no, 1520bdcd8170SKalle Valo is_amsdu, skb)) 15215694f962SKalle Valo /* aggregation code will handle the skb */ 15225694f962SKalle Valo return; 15235694f962SKalle Valo 152428ae58ddSVasanthakumar Thiagarajan ath6kl_deliver_frames_to_nw_stack(vif->ndev, skb); 1525bdcd8170SKalle Valo } 1526bdcd8170SKalle Valo 1527bdcd8170SKalle Valo static void aggr_timeout(unsigned long arg) 1528bdcd8170SKalle Valo { 1529bdcd8170SKalle Valo u8 i, j; 1530bdcd8170SKalle Valo struct aggr_info *p_aggr = (struct aggr_info *) arg; 1531bdcd8170SKalle Valo struct rxtid *rxtid; 1532bdcd8170SKalle Valo struct rxtid_stats *stats; 1533bdcd8170SKalle Valo 1534bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1535bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[i]; 1536bdcd8170SKalle Valo stats = &p_aggr->stat[i]; 1537bdcd8170SKalle Valo 1538bdcd8170SKalle Valo if (!rxtid->aggr || !rxtid->timer_mon || rxtid->progress) 1539bdcd8170SKalle Valo continue; 1540bdcd8170SKalle Valo 1541bdcd8170SKalle Valo stats->num_timeouts++; 154237ca6335SKalle Valo ath6kl_dbg(ATH6KL_DBG_AGGR, 154337ca6335SKalle Valo "aggr timeout (st %d end %d)\n", 1544bdcd8170SKalle Valo rxtid->seq_next, 1545bdcd8170SKalle Valo ((rxtid->seq_next + rxtid->hold_q_sz-1) & 1546bdcd8170SKalle Valo ATH6KL_MAX_SEQ_NO)); 1547bdcd8170SKalle Valo aggr_deque_frms(p_aggr, i, 0, 0); 1548bdcd8170SKalle Valo } 1549bdcd8170SKalle Valo 1550bdcd8170SKalle Valo p_aggr->timer_scheduled = false; 1551bdcd8170SKalle Valo 1552bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1553bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[i]; 1554bdcd8170SKalle Valo 1555bdcd8170SKalle Valo if (rxtid->aggr && rxtid->hold_q) { 1556bdcd8170SKalle Valo for (j = 0; j < rxtid->hold_q_sz; j++) { 1557bdcd8170SKalle Valo if (rxtid->hold_q[j].skb) { 1558bdcd8170SKalle Valo p_aggr->timer_scheduled = true; 1559bdcd8170SKalle Valo rxtid->timer_mon = true; 1560bdcd8170SKalle Valo rxtid->progress = false; 1561bdcd8170SKalle Valo break; 1562bdcd8170SKalle Valo } 1563bdcd8170SKalle Valo } 1564bdcd8170SKalle Valo 1565bdcd8170SKalle Valo if (j >= rxtid->hold_q_sz) 1566bdcd8170SKalle Valo rxtid->timer_mon = false; 1567bdcd8170SKalle Valo } 1568bdcd8170SKalle Valo } 1569bdcd8170SKalle Valo 1570bdcd8170SKalle Valo if (p_aggr->timer_scheduled) 1571bdcd8170SKalle Valo mod_timer(&p_aggr->timer, 1572bdcd8170SKalle Valo jiffies + msecs_to_jiffies(AGGR_RX_TIMEOUT)); 1573bdcd8170SKalle Valo } 1574bdcd8170SKalle Valo 1575bdcd8170SKalle Valo static void aggr_delete_tid_state(struct aggr_info *p_aggr, u8 tid) 1576bdcd8170SKalle Valo { 1577bdcd8170SKalle Valo struct rxtid *rxtid; 1578bdcd8170SKalle Valo struct rxtid_stats *stats; 1579bdcd8170SKalle Valo 1580bdcd8170SKalle Valo if (!p_aggr || tid >= NUM_OF_TIDS) 1581bdcd8170SKalle Valo return; 1582bdcd8170SKalle Valo 1583bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1584bdcd8170SKalle Valo stats = &p_aggr->stat[tid]; 1585bdcd8170SKalle Valo 1586bdcd8170SKalle Valo if (rxtid->aggr) 1587bdcd8170SKalle Valo aggr_deque_frms(p_aggr, tid, 0, 0); 1588bdcd8170SKalle Valo 1589bdcd8170SKalle Valo rxtid->aggr = false; 1590bdcd8170SKalle Valo rxtid->progress = false; 1591bdcd8170SKalle Valo rxtid->timer_mon = false; 1592bdcd8170SKalle Valo rxtid->win_sz = 0; 1593bdcd8170SKalle Valo rxtid->seq_next = 0; 1594bdcd8170SKalle Valo rxtid->hold_q_sz = 0; 1595bdcd8170SKalle Valo 1596bdcd8170SKalle Valo kfree(rxtid->hold_q); 1597bdcd8170SKalle Valo rxtid->hold_q = NULL; 1598bdcd8170SKalle Valo 1599bdcd8170SKalle Valo memset(stats, 0, sizeof(struct rxtid_stats)); 1600bdcd8170SKalle Valo } 1601bdcd8170SKalle Valo 1602240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no, 1603240d2799SVasanthakumar Thiagarajan u8 win_sz) 1604bdcd8170SKalle Valo { 16052132c69cSVasanthakumar Thiagarajan struct aggr_info *p_aggr = vif->aggr_cntxt; 1606bdcd8170SKalle Valo struct rxtid *rxtid; 1607bdcd8170SKalle Valo struct rxtid_stats *stats; 1608bdcd8170SKalle Valo u16 hold_q_size; 1609bdcd8170SKalle Valo 1610bdcd8170SKalle Valo if (!p_aggr) 1611bdcd8170SKalle Valo return; 1612bdcd8170SKalle Valo 1613bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1614bdcd8170SKalle Valo stats = &p_aggr->stat[tid]; 1615bdcd8170SKalle Valo 1616bdcd8170SKalle Valo if (win_sz < AGGR_WIN_SZ_MIN || win_sz > AGGR_WIN_SZ_MAX) 1617bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, "%s: win_sz %d, tid %d\n", 1618bdcd8170SKalle Valo __func__, win_sz, tid); 1619bdcd8170SKalle Valo 1620bdcd8170SKalle Valo if (rxtid->aggr) 1621bdcd8170SKalle Valo aggr_delete_tid_state(p_aggr, tid); 1622bdcd8170SKalle Valo 1623bdcd8170SKalle Valo rxtid->seq_next = seq_no; 1624bdcd8170SKalle Valo hold_q_size = TID_WINDOW_SZ(win_sz) * sizeof(struct skb_hold_q); 1625bdcd8170SKalle Valo rxtid->hold_q = kzalloc(hold_q_size, GFP_KERNEL); 1626bdcd8170SKalle Valo if (!rxtid->hold_q) 1627bdcd8170SKalle Valo return; 1628bdcd8170SKalle Valo 1629bdcd8170SKalle Valo rxtid->win_sz = win_sz; 1630bdcd8170SKalle Valo rxtid->hold_q_sz = TID_WINDOW_SZ(win_sz); 1631bdcd8170SKalle Valo if (!skb_queue_empty(&rxtid->q)) 1632bdcd8170SKalle Valo return; 1633bdcd8170SKalle Valo 1634bdcd8170SKalle Valo rxtid->aggr = true; 1635bdcd8170SKalle Valo } 1636bdcd8170SKalle Valo 1637bdcd8170SKalle Valo struct aggr_info *aggr_init(struct net_device *dev) 1638bdcd8170SKalle Valo { 1639bdcd8170SKalle Valo struct aggr_info *p_aggr = NULL; 1640bdcd8170SKalle Valo struct rxtid *rxtid; 1641bdcd8170SKalle Valo u8 i; 1642bdcd8170SKalle Valo 1643bdcd8170SKalle Valo p_aggr = kzalloc(sizeof(struct aggr_info), GFP_KERNEL); 1644bdcd8170SKalle Valo if (!p_aggr) { 1645bdcd8170SKalle Valo ath6kl_err("failed to alloc memory for aggr_node\n"); 1646bdcd8170SKalle Valo return NULL; 1647bdcd8170SKalle Valo } 1648bdcd8170SKalle Valo 1649bdcd8170SKalle Valo p_aggr->aggr_sz = AGGR_SZ_DEFAULT; 1650bdcd8170SKalle Valo p_aggr->dev = dev; 1651bdcd8170SKalle Valo init_timer(&p_aggr->timer); 1652bdcd8170SKalle Valo p_aggr->timer.function = aggr_timeout; 1653bdcd8170SKalle Valo p_aggr->timer.data = (unsigned long) p_aggr; 1654bdcd8170SKalle Valo 1655bdcd8170SKalle Valo p_aggr->timer_scheduled = false; 1656bdcd8170SKalle Valo skb_queue_head_init(&p_aggr->free_q); 1657bdcd8170SKalle Valo 1658bdcd8170SKalle Valo ath6kl_alloc_netbufs(&p_aggr->free_q, AGGR_NUM_OF_FREE_NETBUFS); 1659bdcd8170SKalle Valo 1660bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1661bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[i]; 1662bdcd8170SKalle Valo rxtid->aggr = false; 1663bdcd8170SKalle Valo rxtid->progress = false; 1664bdcd8170SKalle Valo rxtid->timer_mon = false; 1665bdcd8170SKalle Valo skb_queue_head_init(&rxtid->q); 1666bdcd8170SKalle Valo spin_lock_init(&rxtid->lock); 1667bdcd8170SKalle Valo } 1668bdcd8170SKalle Valo 1669bdcd8170SKalle Valo return p_aggr; 1670bdcd8170SKalle Valo } 1671bdcd8170SKalle Valo 1672240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid) 1673bdcd8170SKalle Valo { 16742132c69cSVasanthakumar Thiagarajan struct aggr_info *p_aggr = vif->aggr_cntxt; 1675bdcd8170SKalle Valo struct rxtid *rxtid; 1676bdcd8170SKalle Valo 1677bdcd8170SKalle Valo if (!p_aggr) 1678bdcd8170SKalle Valo return; 1679bdcd8170SKalle Valo 1680bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1681bdcd8170SKalle Valo 1682bdcd8170SKalle Valo if (rxtid->aggr) 1683bdcd8170SKalle Valo aggr_delete_tid_state(p_aggr, tid); 1684bdcd8170SKalle Valo } 1685bdcd8170SKalle Valo 1686bdcd8170SKalle Valo void aggr_reset_state(struct aggr_info *aggr_info) 1687bdcd8170SKalle Valo { 1688bdcd8170SKalle Valo u8 tid; 1689bdcd8170SKalle Valo 1690bdcd8170SKalle Valo for (tid = 0; tid < NUM_OF_TIDS; tid++) 1691bdcd8170SKalle Valo aggr_delete_tid_state(aggr_info, tid); 1692bdcd8170SKalle Valo } 1693bdcd8170SKalle Valo 1694bdcd8170SKalle Valo /* clean up our amsdu buffer list */ 1695bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar) 1696bdcd8170SKalle Valo { 1697bdcd8170SKalle Valo struct htc_packet *packet, *tmp_pkt; 1698bdcd8170SKalle Valo 1699bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 1700bdcd8170SKalle Valo if (list_empty(&ar->amsdu_rx_buffer_queue)) { 1701bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 1702bdcd8170SKalle Valo return; 1703bdcd8170SKalle Valo } 1704bdcd8170SKalle Valo 1705bdcd8170SKalle Valo list_for_each_entry_safe(packet, tmp_pkt, &ar->amsdu_rx_buffer_queue, 1706bdcd8170SKalle Valo list) { 1707bdcd8170SKalle Valo list_del(&packet->list); 1708bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 1709bdcd8170SKalle Valo dev_kfree_skb(packet->pkt_cntxt); 1710bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 1711bdcd8170SKalle Valo } 1712bdcd8170SKalle Valo 1713bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 1714bdcd8170SKalle Valo } 1715bdcd8170SKalle Valo 1716bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info) 1717bdcd8170SKalle Valo { 1718bdcd8170SKalle Valo struct rxtid *rxtid; 1719bdcd8170SKalle Valo u8 i, k; 1720bdcd8170SKalle Valo 1721bdcd8170SKalle Valo if (!aggr_info) 1722bdcd8170SKalle Valo return; 1723bdcd8170SKalle Valo 1724bdcd8170SKalle Valo if (aggr_info->timer_scheduled) { 1725bdcd8170SKalle Valo del_timer(&aggr_info->timer); 1726bdcd8170SKalle Valo aggr_info->timer_scheduled = false; 1727bdcd8170SKalle Valo } 1728bdcd8170SKalle Valo 1729bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1730bdcd8170SKalle Valo rxtid = &aggr_info->rx_tid[i]; 1731bdcd8170SKalle Valo if (rxtid->hold_q) { 1732bdcd8170SKalle Valo for (k = 0; k < rxtid->hold_q_sz; k++) 1733bdcd8170SKalle Valo dev_kfree_skb(rxtid->hold_q[k].skb); 1734bdcd8170SKalle Valo kfree(rxtid->hold_q); 1735bdcd8170SKalle Valo } 1736bdcd8170SKalle Valo 1737bdcd8170SKalle Valo skb_queue_purge(&rxtid->q); 1738bdcd8170SKalle Valo } 1739bdcd8170SKalle Valo 1740bdcd8170SKalle Valo skb_queue_purge(&aggr_info->free_q); 1741bdcd8170SKalle Valo kfree(aggr_info); 1742bdcd8170SKalle Valo } 1743