xref: /openbmc/linux/drivers/net/wireless/ath/ath6kl/txrx.c (revision bc48ad31c5814feb4ff8faca9a8d422279593cb1)
1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo  * Copyright (c) 2004-2011 Atheros Communications Inc.
3bdcd8170SKalle Valo  *
4bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
5bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
6bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
7bdcd8170SKalle Valo  *
8bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15bdcd8170SKalle Valo  */
16bdcd8170SKalle Valo 
17bdcd8170SKalle Valo #include "core.h"
18bdcd8170SKalle Valo #include "debug.h"
19bdcd8170SKalle Valo 
20bdcd8170SKalle Valo static u8 ath6kl_ibss_map_epid(struct sk_buff *skb, struct net_device *dev,
21bdcd8170SKalle Valo 			       u32 *map_no)
22bdcd8170SKalle Valo {
23bdcd8170SKalle Valo 	struct ath6kl *ar = ath6kl_priv(dev);
24bdcd8170SKalle Valo 	struct ethhdr *eth_hdr;
25bdcd8170SKalle Valo 	u32 i, ep_map = -1;
26bdcd8170SKalle Valo 	u8 *datap;
27bdcd8170SKalle Valo 
28bdcd8170SKalle Valo 	*map_no = 0;
29bdcd8170SKalle Valo 	datap = skb->data;
30bdcd8170SKalle Valo 	eth_hdr = (struct ethhdr *) (datap + sizeof(struct wmi_data_hdr));
31bdcd8170SKalle Valo 
32bdcd8170SKalle Valo 	if (is_multicast_ether_addr(eth_hdr->h_dest))
33bdcd8170SKalle Valo 		return ENDPOINT_2;
34bdcd8170SKalle Valo 
35bdcd8170SKalle Valo 	for (i = 0; i < ar->node_num; i++) {
36bdcd8170SKalle Valo 		if (memcmp(eth_hdr->h_dest, ar->node_map[i].mac_addr,
37bdcd8170SKalle Valo 			   ETH_ALEN) == 0) {
38bdcd8170SKalle Valo 			*map_no = i + 1;
39bdcd8170SKalle Valo 			ar->node_map[i].tx_pend++;
40bdcd8170SKalle Valo 			return ar->node_map[i].ep_id;
41bdcd8170SKalle Valo 		}
42bdcd8170SKalle Valo 
43bdcd8170SKalle Valo 		if ((ep_map == -1) && !ar->node_map[i].tx_pend)
44bdcd8170SKalle Valo 			ep_map = i;
45bdcd8170SKalle Valo 	}
46bdcd8170SKalle Valo 
47bdcd8170SKalle Valo 	if (ep_map == -1) {
48bdcd8170SKalle Valo 		ep_map = ar->node_num;
49bdcd8170SKalle Valo 		ar->node_num++;
50bdcd8170SKalle Valo 		if (ar->node_num > MAX_NODE_NUM)
51bdcd8170SKalle Valo 			return ENDPOINT_UNUSED;
52bdcd8170SKalle Valo 	}
53bdcd8170SKalle Valo 
54bdcd8170SKalle Valo 	memcpy(ar->node_map[ep_map].mac_addr, eth_hdr->h_dest, ETH_ALEN);
55bdcd8170SKalle Valo 
56bdcd8170SKalle Valo 	for (i = ENDPOINT_2; i <= ENDPOINT_5; i++) {
57bdcd8170SKalle Valo 		if (!ar->tx_pending[i]) {
58bdcd8170SKalle Valo 			ar->node_map[ep_map].ep_id = i;
59bdcd8170SKalle Valo 			break;
60bdcd8170SKalle Valo 		}
61bdcd8170SKalle Valo 
62bdcd8170SKalle Valo 		/*
63bdcd8170SKalle Valo 		 * No free endpoint is available, start redistribution on
64bdcd8170SKalle Valo 		 * the inuse endpoints.
65bdcd8170SKalle Valo 		 */
66bdcd8170SKalle Valo 		if (i == ENDPOINT_5) {
67bdcd8170SKalle Valo 			ar->node_map[ep_map].ep_id = ar->next_ep_id;
68bdcd8170SKalle Valo 			ar->next_ep_id++;
69bdcd8170SKalle Valo 			if (ar->next_ep_id > ENDPOINT_5)
70bdcd8170SKalle Valo 				ar->next_ep_id = ENDPOINT_2;
71bdcd8170SKalle Valo 		}
72bdcd8170SKalle Valo 	}
73bdcd8170SKalle Valo 
74bdcd8170SKalle Valo 	*map_no = ep_map + 1;
75bdcd8170SKalle Valo 	ar->node_map[ep_map].tx_pend++;
76bdcd8170SKalle Valo 
77bdcd8170SKalle Valo 	return ar->node_map[ep_map].ep_id;
78bdcd8170SKalle Valo }
79bdcd8170SKalle Valo 
806765d0aaSVasanthakumar Thiagarajan static bool ath6kl_powersave_ap(struct ath6kl_vif *vif, struct sk_buff *skb,
81bdcd8170SKalle Valo 				bool *more_data)
82bdcd8170SKalle Valo {
83bdcd8170SKalle Valo 	struct ethhdr *datap = (struct ethhdr *) skb->data;
84bdcd8170SKalle Valo 	struct ath6kl_sta *conn = NULL;
85bdcd8170SKalle Valo 	bool ps_queued = false, is_psq_empty = false;
866765d0aaSVasanthakumar Thiagarajan 	struct ath6kl *ar = vif->ar;
87bdcd8170SKalle Valo 
88bdcd8170SKalle Valo 	if (is_multicast_ether_addr(datap->h_dest)) {
89bdcd8170SKalle Valo 		u8 ctr = 0;
90bdcd8170SKalle Valo 		bool q_mcast = false;
91bdcd8170SKalle Valo 
92bdcd8170SKalle Valo 		for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) {
93bdcd8170SKalle Valo 			if (ar->sta_list[ctr].sta_flags & STA_PS_SLEEP) {
94bdcd8170SKalle Valo 				q_mcast = true;
95bdcd8170SKalle Valo 				break;
96bdcd8170SKalle Valo 			}
97bdcd8170SKalle Valo 		}
98bdcd8170SKalle Valo 
99bdcd8170SKalle Valo 		if (q_mcast) {
100bdcd8170SKalle Valo 			/*
101bdcd8170SKalle Valo 			 * If this transmit is not because of a Dtim Expiry
102bdcd8170SKalle Valo 			 * q it.
103bdcd8170SKalle Valo 			 */
10459c98449SVasanthakumar Thiagarajan 			if (!test_bit(DTIM_EXPIRED, &vif->flags)) {
105bdcd8170SKalle Valo 				bool is_mcastq_empty = false;
106bdcd8170SKalle Valo 
107bdcd8170SKalle Valo 				spin_lock_bh(&ar->mcastpsq_lock);
108bdcd8170SKalle Valo 				is_mcastq_empty =
109bdcd8170SKalle Valo 					skb_queue_empty(&ar->mcastpsq);
110bdcd8170SKalle Valo 				skb_queue_tail(&ar->mcastpsq, skb);
111bdcd8170SKalle Valo 				spin_unlock_bh(&ar->mcastpsq_lock);
112bdcd8170SKalle Valo 
113bdcd8170SKalle Valo 				/*
114bdcd8170SKalle Valo 				 * If this is the first Mcast pkt getting
115bdcd8170SKalle Valo 				 * queued indicate to the target to set the
116bdcd8170SKalle Valo 				 * BitmapControl LSB of the TIM IE.
117bdcd8170SKalle Valo 				 */
118bdcd8170SKalle Valo 				if (is_mcastq_empty)
119bdcd8170SKalle Valo 					ath6kl_wmi_set_pvb_cmd(ar->wmi,
120334234b5SVasanthakumar Thiagarajan 							       vif->fw_vif_idx,
121bdcd8170SKalle Valo 							       MCAST_AID, 1);
122bdcd8170SKalle Valo 
123bdcd8170SKalle Valo 				ps_queued = true;
124bdcd8170SKalle Valo 			} else {
125bdcd8170SKalle Valo 				/*
126bdcd8170SKalle Valo 				 * This transmit is because of Dtim expiry.
127bdcd8170SKalle Valo 				 * Determine if MoreData bit has to be set.
128bdcd8170SKalle Valo 				 */
129bdcd8170SKalle Valo 				spin_lock_bh(&ar->mcastpsq_lock);
130bdcd8170SKalle Valo 				if (!skb_queue_empty(&ar->mcastpsq))
131bdcd8170SKalle Valo 					*more_data = true;
132bdcd8170SKalle Valo 				spin_unlock_bh(&ar->mcastpsq_lock);
133bdcd8170SKalle Valo 			}
134bdcd8170SKalle Valo 		}
135bdcd8170SKalle Valo 	} else {
1366765d0aaSVasanthakumar Thiagarajan 		conn = ath6kl_find_sta(vif, datap->h_dest);
137bdcd8170SKalle Valo 		if (!conn) {
138bdcd8170SKalle Valo 			dev_kfree_skb(skb);
139bdcd8170SKalle Valo 
140bdcd8170SKalle Valo 			/* Inform the caller that the skb is consumed */
141bdcd8170SKalle Valo 			return true;
142bdcd8170SKalle Valo 		}
143bdcd8170SKalle Valo 
144bdcd8170SKalle Valo 		if (conn->sta_flags & STA_PS_SLEEP) {
145bdcd8170SKalle Valo 			if (!(conn->sta_flags & STA_PS_POLLED)) {
146bdcd8170SKalle Valo 				/* Queue the frames if the STA is sleeping */
147bdcd8170SKalle Valo 				spin_lock_bh(&conn->psq_lock);
148bdcd8170SKalle Valo 				is_psq_empty = skb_queue_empty(&conn->psq);
149bdcd8170SKalle Valo 				skb_queue_tail(&conn->psq, skb);
150bdcd8170SKalle Valo 				spin_unlock_bh(&conn->psq_lock);
151bdcd8170SKalle Valo 
152bdcd8170SKalle Valo 				/*
153bdcd8170SKalle Valo 				 * If this is the first pkt getting queued
154bdcd8170SKalle Valo 				 * for this STA, update the PVB for this
155bdcd8170SKalle Valo 				 * STA.
156bdcd8170SKalle Valo 				 */
157bdcd8170SKalle Valo 				if (is_psq_empty)
158bdcd8170SKalle Valo 					ath6kl_wmi_set_pvb_cmd(ar->wmi,
159334234b5SVasanthakumar Thiagarajan 							       vif->fw_vif_idx,
160bdcd8170SKalle Valo 							       conn->aid, 1);
161bdcd8170SKalle Valo 
162bdcd8170SKalle Valo 				ps_queued = true;
163bdcd8170SKalle Valo 			} else {
164bdcd8170SKalle Valo 				/*
165bdcd8170SKalle Valo 				 * This tx is because of a PsPoll.
166bdcd8170SKalle Valo 				 * Determine if MoreData bit has to be set.
167bdcd8170SKalle Valo 				 */
168bdcd8170SKalle Valo 				spin_lock_bh(&conn->psq_lock);
169bdcd8170SKalle Valo 				if (!skb_queue_empty(&conn->psq))
170bdcd8170SKalle Valo 					*more_data = true;
171bdcd8170SKalle Valo 				spin_unlock_bh(&conn->psq_lock);
172bdcd8170SKalle Valo 			}
173bdcd8170SKalle Valo 		}
174bdcd8170SKalle Valo 	}
175bdcd8170SKalle Valo 
176bdcd8170SKalle Valo 	return ps_queued;
177bdcd8170SKalle Valo }
178bdcd8170SKalle Valo 
179bdcd8170SKalle Valo /* Tx functions */
180bdcd8170SKalle Valo 
181bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb,
182bdcd8170SKalle Valo 		      enum htc_endpoint_id eid)
183bdcd8170SKalle Valo {
184bdcd8170SKalle Valo 	struct ath6kl *ar = devt;
185bdcd8170SKalle Valo 	int status = 0;
186bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie = NULL;
187bdcd8170SKalle Valo 
188bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
189bdcd8170SKalle Valo 
190bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_WLAN_TX,
191bdcd8170SKalle Valo 		   "%s: skb=0x%p, len=0x%x eid =%d\n", __func__,
192bdcd8170SKalle Valo 		   skb, skb->len, eid);
193bdcd8170SKalle Valo 
194bdcd8170SKalle Valo 	if (test_bit(WMI_CTRL_EP_FULL, &ar->flag) && (eid == ar->ctrl_ep)) {
195bdcd8170SKalle Valo 		/*
196bdcd8170SKalle Valo 		 * Control endpoint is full, don't allocate resources, we
197bdcd8170SKalle Valo 		 * are just going to drop this packet.
198bdcd8170SKalle Valo 		 */
199bdcd8170SKalle Valo 		cookie = NULL;
200bdcd8170SKalle Valo 		ath6kl_err("wmi ctrl ep full, dropping pkt : 0x%p, len:%d\n",
201bdcd8170SKalle Valo 			   skb, skb->len);
202bdcd8170SKalle Valo 	} else
203bdcd8170SKalle Valo 		cookie = ath6kl_alloc_cookie(ar);
204bdcd8170SKalle Valo 
205bdcd8170SKalle Valo 	if (cookie == NULL) {
206bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
207bdcd8170SKalle Valo 		status = -ENOMEM;
208bdcd8170SKalle Valo 		goto fail_ctrl_tx;
209bdcd8170SKalle Valo 	}
210bdcd8170SKalle Valo 
211bdcd8170SKalle Valo 	ar->tx_pending[eid]++;
212bdcd8170SKalle Valo 
213bdcd8170SKalle Valo 	if (eid != ar->ctrl_ep)
214bdcd8170SKalle Valo 		ar->total_tx_data_pend++;
215bdcd8170SKalle Valo 
216bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
217bdcd8170SKalle Valo 
218bdcd8170SKalle Valo 	cookie->skb = skb;
219bdcd8170SKalle Valo 	cookie->map_no = 0;
220bdcd8170SKalle Valo 	set_htc_pkt_info(&cookie->htc_pkt, cookie, skb->data, skb->len,
221bdcd8170SKalle Valo 			 eid, ATH6KL_CONTROL_PKT_TAG);
222bdcd8170SKalle Valo 
223bdcd8170SKalle Valo 	/*
224bdcd8170SKalle Valo 	 * This interface is asynchronous, if there is an error, cleanup
225bdcd8170SKalle Valo 	 * will happen in the TX completion callback.
226bdcd8170SKalle Valo 	 */
227ad226ec2SKalle Valo 	ath6kl_htc_tx(ar->htc_target, &cookie->htc_pkt);
228bdcd8170SKalle Valo 
229bdcd8170SKalle Valo 	return 0;
230bdcd8170SKalle Valo 
231bdcd8170SKalle Valo fail_ctrl_tx:
232bdcd8170SKalle Valo 	dev_kfree_skb(skb);
233bdcd8170SKalle Valo 	return status;
234bdcd8170SKalle Valo }
235bdcd8170SKalle Valo 
236bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev)
237bdcd8170SKalle Valo {
238bdcd8170SKalle Valo 	struct ath6kl *ar = ath6kl_priv(dev);
239bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie = NULL;
240bdcd8170SKalle Valo 	enum htc_endpoint_id eid = ENDPOINT_UNUSED;
24159c98449SVasanthakumar Thiagarajan 	struct ath6kl_vif *vif = netdev_priv(dev);
242bdcd8170SKalle Valo 	u32 map_no = 0;
243bdcd8170SKalle Valo 	u16 htc_tag = ATH6KL_DATA_PKT_TAG;
244bdcd8170SKalle Valo 	u8 ac = 99 ; /* initialize to unmapped ac */
245bdcd8170SKalle Valo 	bool chk_adhoc_ps_mapping = false, more_data = false;
246bdcd8170SKalle Valo 	int ret;
247*bc48ad31SRishi Panjwani 	struct wmi_tx_meta_v2 meta_v2;
248*bc48ad31SRishi Panjwani 	void *meta;
249*bc48ad31SRishi Panjwani 	u8 csum_start = 0, csum_dest = 0, csum = skb->ip_summed;
250*bc48ad31SRishi Panjwani 	u8 meta_ver = 0;
251bdcd8170SKalle Valo 
252bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_WLAN_TX,
253bdcd8170SKalle Valo 		   "%s: skb=0x%p, data=0x%p, len=0x%x\n", __func__,
254bdcd8170SKalle Valo 		   skb, skb->data, skb->len);
255bdcd8170SKalle Valo 
256bdcd8170SKalle Valo 	/* If target is not associated */
25759c98449SVasanthakumar Thiagarajan 	if (!test_bit(CONNECTED, &vif->flags)) {
258bdcd8170SKalle Valo 		dev_kfree_skb(skb);
259bdcd8170SKalle Valo 		return 0;
260bdcd8170SKalle Valo 	}
261bdcd8170SKalle Valo 
262bdcd8170SKalle Valo 	if (!test_bit(WMI_READY, &ar->flag))
263bdcd8170SKalle Valo 		goto fail_tx;
264bdcd8170SKalle Valo 
265bdcd8170SKalle Valo 	/* AP mode Power saving processing */
266f5938f24SVasanthakumar Thiagarajan 	if (vif->nw_type == AP_NETWORK) {
2676765d0aaSVasanthakumar Thiagarajan 		if (ath6kl_powersave_ap(vif, skb, &more_data))
268bdcd8170SKalle Valo 			return 0;
269bdcd8170SKalle Valo 	}
270bdcd8170SKalle Valo 
271bdcd8170SKalle Valo 	if (test_bit(WMI_ENABLED, &ar->flag)) {
272*bc48ad31SRishi Panjwani 		if ((dev->features & NETIF_F_IP_CSUM) &&
273*bc48ad31SRishi Panjwani 				(csum == CHECKSUM_PARTIAL)) {
274*bc48ad31SRishi Panjwani 			csum_start = skb->csum_start -
275*bc48ad31SRishi Panjwani 					(skb_network_header(skb) - skb->head) +
276*bc48ad31SRishi Panjwani 					sizeof(struct ath6kl_llc_snap_hdr);
277*bc48ad31SRishi Panjwani 			csum_dest = skb->csum_offset + csum_start;
278*bc48ad31SRishi Panjwani 		}
279*bc48ad31SRishi Panjwani 
280bdcd8170SKalle Valo 		if (skb_headroom(skb) < dev->needed_headroom) {
281a29517ceSVasanthakumar Thiagarajan 			struct sk_buff *tmp_skb = skb;
282a29517ceSVasanthakumar Thiagarajan 
283a29517ceSVasanthakumar Thiagarajan 			skb = skb_realloc_headroom(skb, dev->needed_headroom);
284a29517ceSVasanthakumar Thiagarajan 			kfree_skb(tmp_skb);
285a29517ceSVasanthakumar Thiagarajan 			if (skb == NULL) {
286a29517ceSVasanthakumar Thiagarajan 				vif->net_stats.tx_dropped++;
287a29517ceSVasanthakumar Thiagarajan 				return 0;
288a29517ceSVasanthakumar Thiagarajan 			}
289bdcd8170SKalle Valo 		}
290bdcd8170SKalle Valo 
291bdcd8170SKalle Valo 		if (ath6kl_wmi_dix_2_dot3(ar->wmi, skb)) {
292bdcd8170SKalle Valo 			ath6kl_err("ath6kl_wmi_dix_2_dot3 failed\n");
293bdcd8170SKalle Valo 			goto fail_tx;
294bdcd8170SKalle Valo 		}
295bdcd8170SKalle Valo 
296*bc48ad31SRishi Panjwani 		if ((dev->features & NETIF_F_IP_CSUM) &&
297*bc48ad31SRishi Panjwani 				(csum == CHECKSUM_PARTIAL)) {
298*bc48ad31SRishi Panjwani 			meta_v2.csum_start = csum_start;
299*bc48ad31SRishi Panjwani 			meta_v2.csum_dest = csum_dest;
300*bc48ad31SRishi Panjwani 
301*bc48ad31SRishi Panjwani 			/* instruct target to calculate checksum */
302*bc48ad31SRishi Panjwani 			meta_v2.csum_flags = WMI_META_V2_FLAG_CSUM_OFFLOAD;
303*bc48ad31SRishi Panjwani 			meta_ver = WMI_META_VERSION_2;
304*bc48ad31SRishi Panjwani 			meta = &meta_v2;
305*bc48ad31SRishi Panjwani 		} else {
306*bc48ad31SRishi Panjwani 			meta_ver = 0;
307*bc48ad31SRishi Panjwani 			meta = NULL;
308*bc48ad31SRishi Panjwani 		}
309*bc48ad31SRishi Panjwani 
310*bc48ad31SRishi Panjwani 		ret = ath6kl_wmi_data_hdr_add(ar->wmi, skb,
311*bc48ad31SRishi Panjwani 				DATA_MSGTYPE, more_data, 0,
312*bc48ad31SRishi Panjwani 				meta_ver,
313*bc48ad31SRishi Panjwani 				meta, vif->fw_vif_idx);
314*bc48ad31SRishi Panjwani 
315*bc48ad31SRishi Panjwani 		if (ret) {
316*bc48ad31SRishi Panjwani 			ath6kl_warn("failed to add wmi data header:%d\n"
317*bc48ad31SRishi Panjwani 				, ret);
318bdcd8170SKalle Valo 			goto fail_tx;
319bdcd8170SKalle Valo 		}
320bdcd8170SKalle Valo 
321f5938f24SVasanthakumar Thiagarajan 		if ((vif->nw_type == ADHOC_NETWORK) &&
32259c98449SVasanthakumar Thiagarajan 		     ar->ibss_ps_enable && test_bit(CONNECTED, &vif->flags))
323bdcd8170SKalle Valo 			chk_adhoc_ps_mapping = true;
324bdcd8170SKalle Valo 		else {
325bdcd8170SKalle Valo 			/* get the stream mapping */
326240d2799SVasanthakumar Thiagarajan 			ret = ath6kl_wmi_implicit_create_pstream(ar->wmi,
327240d2799SVasanthakumar Thiagarajan 				    vif->fw_vif_idx, skb,
32859c98449SVasanthakumar Thiagarajan 				    0, test_bit(WMM_ENABLED, &vif->flags), &ac);
329bdcd8170SKalle Valo 			if (ret)
330bdcd8170SKalle Valo 				goto fail_tx;
331bdcd8170SKalle Valo 		}
332bdcd8170SKalle Valo 	} else
333bdcd8170SKalle Valo 		goto fail_tx;
334bdcd8170SKalle Valo 
335bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
336bdcd8170SKalle Valo 
337bdcd8170SKalle Valo 	if (chk_adhoc_ps_mapping)
338bdcd8170SKalle Valo 		eid = ath6kl_ibss_map_epid(skb, dev, &map_no);
339bdcd8170SKalle Valo 	else
340bdcd8170SKalle Valo 		eid = ar->ac2ep_map[ac];
341bdcd8170SKalle Valo 
342bdcd8170SKalle Valo 	if (eid == 0 || eid == ENDPOINT_UNUSED) {
343bdcd8170SKalle Valo 		ath6kl_err("eid %d is not mapped!\n", eid);
344bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
345bdcd8170SKalle Valo 		goto fail_tx;
346bdcd8170SKalle Valo 	}
347bdcd8170SKalle Valo 
348bdcd8170SKalle Valo 	/* allocate resource for this packet */
349bdcd8170SKalle Valo 	cookie = ath6kl_alloc_cookie(ar);
350bdcd8170SKalle Valo 
351bdcd8170SKalle Valo 	if (!cookie) {
352bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
353bdcd8170SKalle Valo 		goto fail_tx;
354bdcd8170SKalle Valo 	}
355bdcd8170SKalle Valo 
356bdcd8170SKalle Valo 	/* update counts while the lock is held */
357bdcd8170SKalle Valo 	ar->tx_pending[eid]++;
358bdcd8170SKalle Valo 	ar->total_tx_data_pend++;
359bdcd8170SKalle Valo 
360bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
361bdcd8170SKalle Valo 
36200b1edf1SJouni Malinen 	if (!IS_ALIGNED((unsigned long) skb->data - HTC_HDR_LENGTH, 4) &&
36300b1edf1SJouni Malinen 	    skb_cloned(skb)) {
36400b1edf1SJouni Malinen 		/*
36500b1edf1SJouni Malinen 		 * We will touch (move the buffer data to align it. Since the
36600b1edf1SJouni Malinen 		 * skb buffer is cloned and not only the header is changed, we
36700b1edf1SJouni Malinen 		 * have to copy it to allow the changes. Since we are copying
36800b1edf1SJouni Malinen 		 * the data here, we may as well align it by reserving suitable
36900b1edf1SJouni Malinen 		 * headroom to avoid the memmove in ath6kl_htc_tx_buf_align().
37000b1edf1SJouni Malinen 		 */
37100b1edf1SJouni Malinen 		struct sk_buff *nskb;
37200b1edf1SJouni Malinen 
37300b1edf1SJouni Malinen 		nskb = skb_copy_expand(skb, HTC_HDR_LENGTH, 0, GFP_ATOMIC);
37400b1edf1SJouni Malinen 		if (nskb == NULL)
37500b1edf1SJouni Malinen 			goto fail_tx;
37600b1edf1SJouni Malinen 		kfree_skb(skb);
37700b1edf1SJouni Malinen 		skb = nskb;
37800b1edf1SJouni Malinen 	}
37900b1edf1SJouni Malinen 
380bdcd8170SKalle Valo 	cookie->skb = skb;
381bdcd8170SKalle Valo 	cookie->map_no = map_no;
382bdcd8170SKalle Valo 	set_htc_pkt_info(&cookie->htc_pkt, cookie, skb->data, skb->len,
383bdcd8170SKalle Valo 			 eid, htc_tag);
384bdcd8170SKalle Valo 
385ef094103SKalle Valo 	ath6kl_dbg_dump(ATH6KL_DBG_RAW_BYTES, __func__, "tx ",
386ef094103SKalle Valo 			skb->data, skb->len);
387bdcd8170SKalle Valo 
388bdcd8170SKalle Valo 	/*
389bdcd8170SKalle Valo 	 * HTC interface is asynchronous, if this fails, cleanup will
390bdcd8170SKalle Valo 	 * happen in the ath6kl_tx_complete callback.
391bdcd8170SKalle Valo 	 */
392ad226ec2SKalle Valo 	ath6kl_htc_tx(ar->htc_target, &cookie->htc_pkt);
393bdcd8170SKalle Valo 
394bdcd8170SKalle Valo 	return 0;
395bdcd8170SKalle Valo 
396bdcd8170SKalle Valo fail_tx:
397bdcd8170SKalle Valo 	dev_kfree_skb(skb);
398bdcd8170SKalle Valo 
399b95907a7SVasanthakumar Thiagarajan 	vif->net_stats.tx_dropped++;
400b95907a7SVasanthakumar Thiagarajan 	vif->net_stats.tx_aborted_errors++;
401bdcd8170SKalle Valo 
402bdcd8170SKalle Valo 	return 0;
403bdcd8170SKalle Valo }
404bdcd8170SKalle Valo 
405bdcd8170SKalle Valo /* indicate tx activity or inactivity on a WMI stream */
406bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active)
407bdcd8170SKalle Valo {
408bdcd8170SKalle Valo 	struct ath6kl *ar = devt;
409bdcd8170SKalle Valo 	enum htc_endpoint_id eid;
410bdcd8170SKalle Valo 	int i;
411bdcd8170SKalle Valo 
412bdcd8170SKalle Valo 	eid = ar->ac2ep_map[traffic_class];
413bdcd8170SKalle Valo 
414bdcd8170SKalle Valo 	if (!test_bit(WMI_ENABLED, &ar->flag))
415bdcd8170SKalle Valo 		goto notify_htc;
416bdcd8170SKalle Valo 
417bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
418bdcd8170SKalle Valo 
419bdcd8170SKalle Valo 	ar->ac_stream_active[traffic_class] = active;
420bdcd8170SKalle Valo 
421bdcd8170SKalle Valo 	if (active) {
422bdcd8170SKalle Valo 		/*
423bdcd8170SKalle Valo 		 * Keep track of the active stream with the highest
424bdcd8170SKalle Valo 		 * priority.
425bdcd8170SKalle Valo 		 */
426bdcd8170SKalle Valo 		if (ar->ac_stream_pri_map[traffic_class] >
427bdcd8170SKalle Valo 		    ar->hiac_stream_active_pri)
428bdcd8170SKalle Valo 			/* set the new highest active priority */
429bdcd8170SKalle Valo 			ar->hiac_stream_active_pri =
430bdcd8170SKalle Valo 					ar->ac_stream_pri_map[traffic_class];
431bdcd8170SKalle Valo 
432bdcd8170SKalle Valo 	} else {
433bdcd8170SKalle Valo 		/*
434bdcd8170SKalle Valo 		 * We may have to search for the next active stream
435bdcd8170SKalle Valo 		 * that is the highest priority.
436bdcd8170SKalle Valo 		 */
437bdcd8170SKalle Valo 		if (ar->hiac_stream_active_pri ==
438bdcd8170SKalle Valo 			ar->ac_stream_pri_map[traffic_class]) {
439bdcd8170SKalle Valo 			/*
440bdcd8170SKalle Valo 			 * The highest priority stream just went inactive
441bdcd8170SKalle Valo 			 * reset and search for the "next" highest "active"
442bdcd8170SKalle Valo 			 * priority stream.
443bdcd8170SKalle Valo 			 */
444bdcd8170SKalle Valo 			ar->hiac_stream_active_pri = 0;
445bdcd8170SKalle Valo 
446bdcd8170SKalle Valo 			for (i = 0; i < WMM_NUM_AC; i++) {
447bdcd8170SKalle Valo 				if (ar->ac_stream_active[i] &&
448bdcd8170SKalle Valo 				    (ar->ac_stream_pri_map[i] >
449bdcd8170SKalle Valo 				     ar->hiac_stream_active_pri))
450bdcd8170SKalle Valo 					/*
451bdcd8170SKalle Valo 					 * Set the new highest active
452bdcd8170SKalle Valo 					 * priority.
453bdcd8170SKalle Valo 					 */
454bdcd8170SKalle Valo 					ar->hiac_stream_active_pri =
455bdcd8170SKalle Valo 						ar->ac_stream_pri_map[i];
456bdcd8170SKalle Valo 			}
457bdcd8170SKalle Valo 		}
458bdcd8170SKalle Valo 	}
459bdcd8170SKalle Valo 
460bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
461bdcd8170SKalle Valo 
462bdcd8170SKalle Valo notify_htc:
463bdcd8170SKalle Valo 	/* notify HTC, this may cause credit distribution changes */
464ad226ec2SKalle Valo 	ath6kl_htc_indicate_activity_change(ar->htc_target, eid, active);
465bdcd8170SKalle Valo }
466bdcd8170SKalle Valo 
467bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
468bdcd8170SKalle Valo 					       struct htc_packet *packet)
469bdcd8170SKalle Valo {
470bdcd8170SKalle Valo 	struct ath6kl *ar = target->dev->ar;
471990bd915SVasanthakumar Thiagarajan 	struct ath6kl_vif *vif;
472bdcd8170SKalle Valo 	enum htc_endpoint_id endpoint = packet->endpoint;
473990bd915SVasanthakumar Thiagarajan 	enum htc_send_full_action action = HTC_SEND_FULL_KEEP;
474bdcd8170SKalle Valo 
475bdcd8170SKalle Valo 	if (endpoint == ar->ctrl_ep) {
476bdcd8170SKalle Valo 		/*
477bdcd8170SKalle Valo 		 * Under normal WMI if this is getting full, then something
478bdcd8170SKalle Valo 		 * is running rampant the host should not be exhausting the
479bdcd8170SKalle Valo 		 * WMI queue with too many commands the only exception to
480bdcd8170SKalle Valo 		 * this is during testing using endpointping.
481bdcd8170SKalle Valo 		 */
482bdcd8170SKalle Valo 		spin_lock_bh(&ar->lock);
483bdcd8170SKalle Valo 		set_bit(WMI_CTRL_EP_FULL, &ar->flag);
484bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
485bdcd8170SKalle Valo 		ath6kl_err("wmi ctrl ep is full\n");
486901db39cSVasanthakumar Thiagarajan 		return action;
487bdcd8170SKalle Valo 	}
488bdcd8170SKalle Valo 
489bdcd8170SKalle Valo 	if (packet->info.tx.tag == ATH6KL_CONTROL_PKT_TAG)
490901db39cSVasanthakumar Thiagarajan 		return action;
491bdcd8170SKalle Valo 
492bdcd8170SKalle Valo 	/*
493bdcd8170SKalle Valo 	 * The last MAX_HI_COOKIE_NUM "batch" of cookies are reserved for
494bdcd8170SKalle Valo 	 * the highest active stream.
495bdcd8170SKalle Valo 	 */
496bdcd8170SKalle Valo 	if (ar->ac_stream_pri_map[ar->ep2ac_map[endpoint]] <
497bdcd8170SKalle Valo 	    ar->hiac_stream_active_pri &&
498901db39cSVasanthakumar Thiagarajan 	    ar->cookie_count <= MAX_HI_COOKIE_NUM)
499bdcd8170SKalle Valo 		/*
500bdcd8170SKalle Valo 		 * Give preference to the highest priority stream by
501bdcd8170SKalle Valo 		 * dropping the packets which overflowed.
502bdcd8170SKalle Valo 		 */
503990bd915SVasanthakumar Thiagarajan 		action = HTC_SEND_FULL_DROP;
504bdcd8170SKalle Valo 
505990bd915SVasanthakumar Thiagarajan 	/* FIXME: Locking */
50611f6e40dSVasanthakumar Thiagarajan 	spin_lock_bh(&ar->list_lock);
507990bd915SVasanthakumar Thiagarajan 	list_for_each_entry(vif, &ar->vif_list, list) {
508901db39cSVasanthakumar Thiagarajan 		if (vif->nw_type == ADHOC_NETWORK ||
509901db39cSVasanthakumar Thiagarajan 		    action != HTC_SEND_FULL_DROP) {
51011f6e40dSVasanthakumar Thiagarajan 			spin_unlock_bh(&ar->list_lock);
511990bd915SVasanthakumar Thiagarajan 
512478ac027SVasanthakumar Thiagarajan 			spin_lock_bh(&vif->if_lock);
51359c98449SVasanthakumar Thiagarajan 			set_bit(NETQ_STOPPED, &vif->flags);
514478ac027SVasanthakumar Thiagarajan 			spin_unlock_bh(&vif->if_lock);
51528ae58ddSVasanthakumar Thiagarajan 			netif_stop_queue(vif->ndev);
516bdcd8170SKalle Valo 
517990bd915SVasanthakumar Thiagarajan 			return action;
518990bd915SVasanthakumar Thiagarajan 		}
519990bd915SVasanthakumar Thiagarajan 	}
52011f6e40dSVasanthakumar Thiagarajan 	spin_unlock_bh(&ar->list_lock);
521990bd915SVasanthakumar Thiagarajan 
522990bd915SVasanthakumar Thiagarajan 	return action;
523bdcd8170SKalle Valo }
524bdcd8170SKalle Valo 
525bdcd8170SKalle Valo /* TODO this needs to be looked at */
526990bd915SVasanthakumar Thiagarajan static void ath6kl_tx_clear_node_map(struct ath6kl_vif *vif,
527bdcd8170SKalle Valo 				     enum htc_endpoint_id eid, u32 map_no)
528bdcd8170SKalle Valo {
529990bd915SVasanthakumar Thiagarajan 	struct ath6kl *ar = vif->ar;
530bdcd8170SKalle Valo 	u32 i;
531bdcd8170SKalle Valo 
532f5938f24SVasanthakumar Thiagarajan 	if (vif->nw_type != ADHOC_NETWORK)
533bdcd8170SKalle Valo 		return;
534bdcd8170SKalle Valo 
535bdcd8170SKalle Valo 	if (!ar->ibss_ps_enable)
536bdcd8170SKalle Valo 		return;
537bdcd8170SKalle Valo 
538bdcd8170SKalle Valo 	if (eid == ar->ctrl_ep)
539bdcd8170SKalle Valo 		return;
540bdcd8170SKalle Valo 
541bdcd8170SKalle Valo 	if (map_no == 0)
542bdcd8170SKalle Valo 		return;
543bdcd8170SKalle Valo 
544bdcd8170SKalle Valo 	map_no--;
545bdcd8170SKalle Valo 	ar->node_map[map_no].tx_pend--;
546bdcd8170SKalle Valo 
547bdcd8170SKalle Valo 	if (ar->node_map[map_no].tx_pend)
548bdcd8170SKalle Valo 		return;
549bdcd8170SKalle Valo 
550bdcd8170SKalle Valo 	if (map_no != (ar->node_num - 1))
551bdcd8170SKalle Valo 		return;
552bdcd8170SKalle Valo 
553bdcd8170SKalle Valo 	for (i = ar->node_num; i > 0; i--) {
554bdcd8170SKalle Valo 		if (ar->node_map[i - 1].tx_pend)
555bdcd8170SKalle Valo 			break;
556bdcd8170SKalle Valo 
557bdcd8170SKalle Valo 		memset(&ar->node_map[i - 1], 0,
558bdcd8170SKalle Valo 		       sizeof(struct ath6kl_node_mapping));
559bdcd8170SKalle Valo 		ar->node_num--;
560bdcd8170SKalle Valo 	}
561bdcd8170SKalle Valo }
562bdcd8170SKalle Valo 
563bdcd8170SKalle Valo void ath6kl_tx_complete(void *context, struct list_head *packet_queue)
564bdcd8170SKalle Valo {
565bdcd8170SKalle Valo 	struct ath6kl *ar = context;
566bdcd8170SKalle Valo 	struct sk_buff_head skb_queue;
567bdcd8170SKalle Valo 	struct htc_packet *packet;
568bdcd8170SKalle Valo 	struct sk_buff *skb;
569bdcd8170SKalle Valo 	struct ath6kl_cookie *ath6kl_cookie;
570bdcd8170SKalle Valo 	u32 map_no = 0;
571bdcd8170SKalle Valo 	int status;
572bdcd8170SKalle Valo 	enum htc_endpoint_id eid;
573bdcd8170SKalle Valo 	bool wake_event = false;
57471f96ee6SKalle Valo 	bool flushing[ATH6KL_VIF_MAX] = {false};
5756765d0aaSVasanthakumar Thiagarajan 	u8 if_idx;
576990bd915SVasanthakumar Thiagarajan 	struct ath6kl_vif *vif;
577bdcd8170SKalle Valo 
578bdcd8170SKalle Valo 	skb_queue_head_init(&skb_queue);
579bdcd8170SKalle Valo 
580bdcd8170SKalle Valo 	/* lock the driver as we update internal state */
581bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
582bdcd8170SKalle Valo 
583bdcd8170SKalle Valo 	/* reap completed packets */
584bdcd8170SKalle Valo 	while (!list_empty(packet_queue)) {
585bdcd8170SKalle Valo 
586bdcd8170SKalle Valo 		packet = list_first_entry(packet_queue, struct htc_packet,
587bdcd8170SKalle Valo 					  list);
588bdcd8170SKalle Valo 		list_del(&packet->list);
589bdcd8170SKalle Valo 
590bdcd8170SKalle Valo 		ath6kl_cookie = (struct ath6kl_cookie *)packet->pkt_cntxt;
591bdcd8170SKalle Valo 		if (!ath6kl_cookie)
592bdcd8170SKalle Valo 			goto fatal;
593bdcd8170SKalle Valo 
594bdcd8170SKalle Valo 		status = packet->status;
595bdcd8170SKalle Valo 		skb = ath6kl_cookie->skb;
596bdcd8170SKalle Valo 		eid = packet->endpoint;
597bdcd8170SKalle Valo 		map_no = ath6kl_cookie->map_no;
598bdcd8170SKalle Valo 
599bdcd8170SKalle Valo 		if (!skb || !skb->data)
600bdcd8170SKalle Valo 			goto fatal;
601bdcd8170SKalle Valo 
602bdcd8170SKalle Valo 		__skb_queue_tail(&skb_queue, skb);
603bdcd8170SKalle Valo 
604bdcd8170SKalle Valo 		if (!status && (packet->act_len != skb->len))
605bdcd8170SKalle Valo 			goto fatal;
606bdcd8170SKalle Valo 
607bdcd8170SKalle Valo 		ar->tx_pending[eid]--;
608bdcd8170SKalle Valo 
609bdcd8170SKalle Valo 		if (eid != ar->ctrl_ep)
610bdcd8170SKalle Valo 			ar->total_tx_data_pend--;
611bdcd8170SKalle Valo 
612bdcd8170SKalle Valo 		if (eid == ar->ctrl_ep) {
613bdcd8170SKalle Valo 			if (test_bit(WMI_CTRL_EP_FULL, &ar->flag))
614bdcd8170SKalle Valo 				clear_bit(WMI_CTRL_EP_FULL, &ar->flag);
615bdcd8170SKalle Valo 
616bdcd8170SKalle Valo 			if (ar->tx_pending[eid] == 0)
617bdcd8170SKalle Valo 				wake_event = true;
618bdcd8170SKalle Valo 		}
619bdcd8170SKalle Valo 
6206765d0aaSVasanthakumar Thiagarajan 		if (eid == ar->ctrl_ep) {
6216765d0aaSVasanthakumar Thiagarajan 			if_idx = wmi_cmd_hdr_get_if_idx(
622f3803eb2SVasanthakumar Thiagarajan 				(struct wmi_cmd_hdr *) packet->buf);
6236765d0aaSVasanthakumar Thiagarajan 		} else {
6246765d0aaSVasanthakumar Thiagarajan 			if_idx = wmi_data_hdr_get_if_idx(
625f3803eb2SVasanthakumar Thiagarajan 				(struct wmi_data_hdr *) packet->buf);
6266765d0aaSVasanthakumar Thiagarajan 		}
6276765d0aaSVasanthakumar Thiagarajan 
6286765d0aaSVasanthakumar Thiagarajan 		vif = ath6kl_get_vif_by_index(ar, if_idx);
6296765d0aaSVasanthakumar Thiagarajan 		if (!vif) {
6306765d0aaSVasanthakumar Thiagarajan 			ath6kl_free_cookie(ar, ath6kl_cookie);
6316765d0aaSVasanthakumar Thiagarajan 			continue;
6326765d0aaSVasanthakumar Thiagarajan 		}
6336765d0aaSVasanthakumar Thiagarajan 
634bdcd8170SKalle Valo 		if (status) {
635bdcd8170SKalle Valo 			if (status == -ECANCELED)
636bdcd8170SKalle Valo 				/* a packet was flushed  */
637990bd915SVasanthakumar Thiagarajan 				flushing[if_idx] = true;
638bdcd8170SKalle Valo 
639b95907a7SVasanthakumar Thiagarajan 			vif->net_stats.tx_errors++;
640bdcd8170SKalle Valo 
641778e6502SKalle Valo 			if (status != -ENOSPC && status != -ECANCELED)
642778e6502SKalle Valo 				ath6kl_warn("tx complete error: %d\n", status);
643778e6502SKalle Valo 
644bdcd8170SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_WLAN_TX,
645bdcd8170SKalle Valo 				   "%s: skb=0x%p data=0x%p len=0x%x eid=%d %s\n",
646bdcd8170SKalle Valo 				   __func__, skb, packet->buf, packet->act_len,
647bdcd8170SKalle Valo 				   eid, "error!");
648bdcd8170SKalle Valo 		} else {
649bdcd8170SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_WLAN_TX,
650bdcd8170SKalle Valo 				   "%s: skb=0x%p data=0x%p len=0x%x eid=%d %s\n",
651bdcd8170SKalle Valo 				   __func__, skb, packet->buf, packet->act_len,
652bdcd8170SKalle Valo 				   eid, "OK");
653bdcd8170SKalle Valo 
654990bd915SVasanthakumar Thiagarajan 			flushing[if_idx] = false;
655b95907a7SVasanthakumar Thiagarajan 			vif->net_stats.tx_packets++;
656b95907a7SVasanthakumar Thiagarajan 			vif->net_stats.tx_bytes += skb->len;
657bdcd8170SKalle Valo 		}
658bdcd8170SKalle Valo 
659990bd915SVasanthakumar Thiagarajan 		ath6kl_tx_clear_node_map(vif, eid, map_no);
660bdcd8170SKalle Valo 
661bdcd8170SKalle Valo 		ath6kl_free_cookie(ar, ath6kl_cookie);
662bdcd8170SKalle Valo 
66359c98449SVasanthakumar Thiagarajan 		if (test_bit(NETQ_STOPPED, &vif->flags))
66459c98449SVasanthakumar Thiagarajan 			clear_bit(NETQ_STOPPED, &vif->flags);
665bdcd8170SKalle Valo 	}
666bdcd8170SKalle Valo 
667bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
668bdcd8170SKalle Valo 
669bdcd8170SKalle Valo 	__skb_queue_purge(&skb_queue);
670bdcd8170SKalle Valo 
671990bd915SVasanthakumar Thiagarajan 	/* FIXME: Locking */
67211f6e40dSVasanthakumar Thiagarajan 	spin_lock_bh(&ar->list_lock);
673990bd915SVasanthakumar Thiagarajan 	list_for_each_entry(vif, &ar->vif_list, list) {
674990bd915SVasanthakumar Thiagarajan 		if (test_bit(CONNECTED, &vif->flags) &&
675990bd915SVasanthakumar Thiagarajan 		    !flushing[vif->fw_vif_idx]) {
67611f6e40dSVasanthakumar Thiagarajan 			spin_unlock_bh(&ar->list_lock);
67728ae58ddSVasanthakumar Thiagarajan 			netif_wake_queue(vif->ndev);
67811f6e40dSVasanthakumar Thiagarajan 			spin_lock_bh(&ar->list_lock);
679bdcd8170SKalle Valo 		}
680990bd915SVasanthakumar Thiagarajan 	}
68111f6e40dSVasanthakumar Thiagarajan 	spin_unlock_bh(&ar->list_lock);
682bdcd8170SKalle Valo 
683bdcd8170SKalle Valo 	if (wake_event)
684bdcd8170SKalle Valo 		wake_up(&ar->event_wq);
685bdcd8170SKalle Valo 
686bdcd8170SKalle Valo 	return;
687bdcd8170SKalle Valo 
688bdcd8170SKalle Valo fatal:
689bdcd8170SKalle Valo 	WARN_ON(1);
690bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
691bdcd8170SKalle Valo 	return;
692bdcd8170SKalle Valo }
693bdcd8170SKalle Valo 
694bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar)
695bdcd8170SKalle Valo {
696bdcd8170SKalle Valo 	int i;
697bdcd8170SKalle Valo 
698bdcd8170SKalle Valo 	/* flush all the data (non-control) streams */
699bdcd8170SKalle Valo 	for (i = 0; i < WMM_NUM_AC; i++)
700ad226ec2SKalle Valo 		ath6kl_htc_flush_txep(ar->htc_target, ar->ac2ep_map[i],
701bdcd8170SKalle Valo 				      ATH6KL_DATA_PKT_TAG);
702bdcd8170SKalle Valo }
703bdcd8170SKalle Valo 
704bdcd8170SKalle Valo /* Rx functions */
705bdcd8170SKalle Valo 
706bdcd8170SKalle Valo static void ath6kl_deliver_frames_to_nw_stack(struct net_device *dev,
707bdcd8170SKalle Valo 					      struct sk_buff *skb)
708bdcd8170SKalle Valo {
709bdcd8170SKalle Valo 	if (!skb)
710bdcd8170SKalle Valo 		return;
711bdcd8170SKalle Valo 
712bdcd8170SKalle Valo 	skb->dev = dev;
713bdcd8170SKalle Valo 
714bdcd8170SKalle Valo 	if (!(skb->dev->flags & IFF_UP)) {
715bdcd8170SKalle Valo 		dev_kfree_skb(skb);
716bdcd8170SKalle Valo 		return;
717bdcd8170SKalle Valo 	}
718bdcd8170SKalle Valo 
719bdcd8170SKalle Valo 	skb->protocol = eth_type_trans(skb, skb->dev);
720bdcd8170SKalle Valo 
721bdcd8170SKalle Valo 	netif_rx_ni(skb);
722bdcd8170SKalle Valo }
723bdcd8170SKalle Valo 
724bdcd8170SKalle Valo static void ath6kl_alloc_netbufs(struct sk_buff_head *q, u16 num)
725bdcd8170SKalle Valo {
726bdcd8170SKalle Valo 	struct sk_buff *skb;
727bdcd8170SKalle Valo 
728bdcd8170SKalle Valo 	while (num) {
729bdcd8170SKalle Valo 		skb = ath6kl_buf_alloc(ATH6KL_BUFFER_SIZE);
730bdcd8170SKalle Valo 		if (!skb) {
731bdcd8170SKalle Valo 			ath6kl_err("netbuf allocation failed\n");
732bdcd8170SKalle Valo 			return;
733bdcd8170SKalle Valo 		}
734bdcd8170SKalle Valo 		skb_queue_tail(q, skb);
735bdcd8170SKalle Valo 		num--;
736bdcd8170SKalle Valo 	}
737bdcd8170SKalle Valo }
738bdcd8170SKalle Valo 
739bdcd8170SKalle Valo static struct sk_buff *aggr_get_free_skb(struct aggr_info *p_aggr)
740bdcd8170SKalle Valo {
741bdcd8170SKalle Valo 	struct sk_buff *skb = NULL;
742bdcd8170SKalle Valo 
743bdcd8170SKalle Valo 	if (skb_queue_len(&p_aggr->free_q) < (AGGR_NUM_OF_FREE_NETBUFS >> 2))
744bdcd8170SKalle Valo 		ath6kl_alloc_netbufs(&p_aggr->free_q, AGGR_NUM_OF_FREE_NETBUFS);
745bdcd8170SKalle Valo 
746bdcd8170SKalle Valo 	skb = skb_dequeue(&p_aggr->free_q);
747bdcd8170SKalle Valo 
748bdcd8170SKalle Valo 	return skb;
749bdcd8170SKalle Valo }
750bdcd8170SKalle Valo 
751bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, enum htc_endpoint_id endpoint)
752bdcd8170SKalle Valo {
753bdcd8170SKalle Valo 	struct ath6kl *ar = target->dev->ar;
754bdcd8170SKalle Valo 	struct sk_buff *skb;
755bdcd8170SKalle Valo 	int rx_buf;
756bdcd8170SKalle Valo 	int n_buf_refill;
757bdcd8170SKalle Valo 	struct htc_packet *packet;
758bdcd8170SKalle Valo 	struct list_head queue;
759bdcd8170SKalle Valo 
760bdcd8170SKalle Valo 	n_buf_refill = ATH6KL_MAX_RX_BUFFERS -
761ad226ec2SKalle Valo 			  ath6kl_htc_get_rxbuf_num(ar->htc_target, endpoint);
762bdcd8170SKalle Valo 
763bdcd8170SKalle Valo 	if (n_buf_refill <= 0)
764bdcd8170SKalle Valo 		return;
765bdcd8170SKalle Valo 
766bdcd8170SKalle Valo 	INIT_LIST_HEAD(&queue);
767bdcd8170SKalle Valo 
768bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_WLAN_RX,
769bdcd8170SKalle Valo 		   "%s: providing htc with %d buffers at eid=%d\n",
770bdcd8170SKalle Valo 		   __func__, n_buf_refill, endpoint);
771bdcd8170SKalle Valo 
772bdcd8170SKalle Valo 	for (rx_buf = 0; rx_buf < n_buf_refill; rx_buf++) {
773bdcd8170SKalle Valo 		skb = ath6kl_buf_alloc(ATH6KL_BUFFER_SIZE);
774bdcd8170SKalle Valo 		if (!skb)
775bdcd8170SKalle Valo 			break;
776bdcd8170SKalle Valo 
777bdcd8170SKalle Valo 		packet = (struct htc_packet *) skb->head;
77894e532d1SVasanthakumar Thiagarajan 		if (!IS_ALIGNED((unsigned long) skb->data, 4))
7791df94a85SVasanthakumar Thiagarajan 			skb->data = PTR_ALIGN(skb->data - 4, 4);
780bdcd8170SKalle Valo 		set_htc_rxpkt_info(packet, skb, skb->data,
781bdcd8170SKalle Valo 				ATH6KL_BUFFER_SIZE, endpoint);
782bdcd8170SKalle Valo 		list_add_tail(&packet->list, &queue);
783bdcd8170SKalle Valo 	}
784bdcd8170SKalle Valo 
785bdcd8170SKalle Valo 	if (!list_empty(&queue))
786ad226ec2SKalle Valo 		ath6kl_htc_add_rxbuf_multiple(ar->htc_target, &queue);
787bdcd8170SKalle Valo }
788bdcd8170SKalle Valo 
789bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count)
790bdcd8170SKalle Valo {
791bdcd8170SKalle Valo 	struct htc_packet *packet;
792bdcd8170SKalle Valo 	struct sk_buff *skb;
793bdcd8170SKalle Valo 
794bdcd8170SKalle Valo 	while (count) {
795bdcd8170SKalle Valo 		skb = ath6kl_buf_alloc(ATH6KL_AMSDU_BUFFER_SIZE);
796bdcd8170SKalle Valo 		if (!skb)
797bdcd8170SKalle Valo 			return;
798bdcd8170SKalle Valo 
799bdcd8170SKalle Valo 		packet = (struct htc_packet *) skb->head;
80094e532d1SVasanthakumar Thiagarajan 		if (!IS_ALIGNED((unsigned long) skb->data, 4))
8011df94a85SVasanthakumar Thiagarajan 			skb->data = PTR_ALIGN(skb->data - 4, 4);
802bdcd8170SKalle Valo 		set_htc_rxpkt_info(packet, skb, skb->data,
803bdcd8170SKalle Valo 				   ATH6KL_AMSDU_BUFFER_SIZE, 0);
804bdcd8170SKalle Valo 		spin_lock_bh(&ar->lock);
805bdcd8170SKalle Valo 		list_add_tail(&packet->list, &ar->amsdu_rx_buffer_queue);
806bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
807bdcd8170SKalle Valo 		count--;
808bdcd8170SKalle Valo 	}
809bdcd8170SKalle Valo }
810bdcd8170SKalle Valo 
811bdcd8170SKalle Valo /*
812bdcd8170SKalle Valo  * Callback to allocate a receive buffer for a pending packet. We use a
813bdcd8170SKalle Valo  * pre-allocated list of buffers of maximum AMSDU size (4K).
814bdcd8170SKalle Valo  */
815bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
816bdcd8170SKalle Valo 					    enum htc_endpoint_id endpoint,
817bdcd8170SKalle Valo 					    int len)
818bdcd8170SKalle Valo {
819bdcd8170SKalle Valo 	struct ath6kl *ar = target->dev->ar;
820bdcd8170SKalle Valo 	struct htc_packet *packet = NULL;
821bdcd8170SKalle Valo 	struct list_head *pkt_pos;
822bdcd8170SKalle Valo 	int refill_cnt = 0, depth = 0;
823bdcd8170SKalle Valo 
824bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_WLAN_RX, "%s: eid=%d, len:%d\n",
825bdcd8170SKalle Valo 		   __func__, endpoint, len);
826bdcd8170SKalle Valo 
827bdcd8170SKalle Valo 	if ((len <= ATH6KL_BUFFER_SIZE) ||
828bdcd8170SKalle Valo 	    (len > ATH6KL_AMSDU_BUFFER_SIZE))
829bdcd8170SKalle Valo 		return NULL;
830bdcd8170SKalle Valo 
831bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
832bdcd8170SKalle Valo 
833bdcd8170SKalle Valo 	if (list_empty(&ar->amsdu_rx_buffer_queue)) {
834bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
835bdcd8170SKalle Valo 		refill_cnt = ATH6KL_MAX_AMSDU_RX_BUFFERS;
836bdcd8170SKalle Valo 		goto refill_buf;
837bdcd8170SKalle Valo 	}
838bdcd8170SKalle Valo 
839bdcd8170SKalle Valo 	packet = list_first_entry(&ar->amsdu_rx_buffer_queue,
840bdcd8170SKalle Valo 				  struct htc_packet, list);
841bdcd8170SKalle Valo 	list_del(&packet->list);
842bdcd8170SKalle Valo 	list_for_each(pkt_pos, &ar->amsdu_rx_buffer_queue)
843bdcd8170SKalle Valo 		depth++;
844bdcd8170SKalle Valo 
845bdcd8170SKalle Valo 	refill_cnt = ATH6KL_MAX_AMSDU_RX_BUFFERS - depth;
846bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
847bdcd8170SKalle Valo 
848bdcd8170SKalle Valo 	/* set actual endpoint ID */
849bdcd8170SKalle Valo 	packet->endpoint = endpoint;
850bdcd8170SKalle Valo 
851bdcd8170SKalle Valo refill_buf:
852bdcd8170SKalle Valo 	if (refill_cnt >= ATH6KL_AMSDU_REFILL_THRESHOLD)
853bdcd8170SKalle Valo 		ath6kl_refill_amsdu_rxbufs(ar, refill_cnt);
854bdcd8170SKalle Valo 
855bdcd8170SKalle Valo 	return packet;
856bdcd8170SKalle Valo }
857bdcd8170SKalle Valo 
858bdcd8170SKalle Valo static void aggr_slice_amsdu(struct aggr_info *p_aggr,
859bdcd8170SKalle Valo 			     struct rxtid *rxtid, struct sk_buff *skb)
860bdcd8170SKalle Valo {
861bdcd8170SKalle Valo 	struct sk_buff *new_skb;
862bdcd8170SKalle Valo 	struct ethhdr *hdr;
863bdcd8170SKalle Valo 	u16 frame_8023_len, payload_8023_len, mac_hdr_len, amsdu_len;
864bdcd8170SKalle Valo 	u8 *framep;
865bdcd8170SKalle Valo 
866bdcd8170SKalle Valo 	mac_hdr_len = sizeof(struct ethhdr);
867bdcd8170SKalle Valo 	framep = skb->data + mac_hdr_len;
868bdcd8170SKalle Valo 	amsdu_len = skb->len - mac_hdr_len;
869bdcd8170SKalle Valo 
870bdcd8170SKalle Valo 	while (amsdu_len > mac_hdr_len) {
871bdcd8170SKalle Valo 		hdr = (struct ethhdr *) framep;
872bdcd8170SKalle Valo 		payload_8023_len = ntohs(hdr->h_proto);
873bdcd8170SKalle Valo 
874bdcd8170SKalle Valo 		if (payload_8023_len < MIN_MSDU_SUBFRAME_PAYLOAD_LEN ||
875bdcd8170SKalle Valo 		    payload_8023_len > MAX_MSDU_SUBFRAME_PAYLOAD_LEN) {
876bdcd8170SKalle Valo 			ath6kl_err("802.3 AMSDU frame bound check failed. len %d\n",
877bdcd8170SKalle Valo 				   payload_8023_len);
878bdcd8170SKalle Valo 			break;
879bdcd8170SKalle Valo 		}
880bdcd8170SKalle Valo 
881bdcd8170SKalle Valo 		frame_8023_len = payload_8023_len + mac_hdr_len;
882bdcd8170SKalle Valo 		new_skb = aggr_get_free_skb(p_aggr);
883bdcd8170SKalle Valo 		if (!new_skb) {
884bdcd8170SKalle Valo 			ath6kl_err("no buffer available\n");
885bdcd8170SKalle Valo 			break;
886bdcd8170SKalle Valo 		}
887bdcd8170SKalle Valo 
888bdcd8170SKalle Valo 		memcpy(new_skb->data, framep, frame_8023_len);
889bdcd8170SKalle Valo 		skb_put(new_skb, frame_8023_len);
890bdcd8170SKalle Valo 		if (ath6kl_wmi_dot3_2_dix(new_skb)) {
891bdcd8170SKalle Valo 			ath6kl_err("dot3_2_dix error\n");
892bdcd8170SKalle Valo 			dev_kfree_skb(new_skb);
893bdcd8170SKalle Valo 			break;
894bdcd8170SKalle Valo 		}
895bdcd8170SKalle Valo 
896bdcd8170SKalle Valo 		skb_queue_tail(&rxtid->q, new_skb);
897bdcd8170SKalle Valo 
898bdcd8170SKalle Valo 		/* Is this the last subframe within this aggregate ? */
899bdcd8170SKalle Valo 		if ((amsdu_len - frame_8023_len) == 0)
900bdcd8170SKalle Valo 			break;
901bdcd8170SKalle Valo 
902bdcd8170SKalle Valo 		/* Add the length of A-MSDU subframe padding bytes -
903bdcd8170SKalle Valo 		 * Round to nearest word.
904bdcd8170SKalle Valo 		 */
90513e34ea1SVasanthakumar Thiagarajan 		frame_8023_len = ALIGN(frame_8023_len, 4);
906bdcd8170SKalle Valo 
907bdcd8170SKalle Valo 		framep += frame_8023_len;
908bdcd8170SKalle Valo 		amsdu_len -= frame_8023_len;
909bdcd8170SKalle Valo 	}
910bdcd8170SKalle Valo 
911bdcd8170SKalle Valo 	dev_kfree_skb(skb);
912bdcd8170SKalle Valo }
913bdcd8170SKalle Valo 
914bdcd8170SKalle Valo static void aggr_deque_frms(struct aggr_info *p_aggr, u8 tid,
915bdcd8170SKalle Valo 			    u16 seq_no, u8 order)
916bdcd8170SKalle Valo {
917bdcd8170SKalle Valo 	struct sk_buff *skb;
918bdcd8170SKalle Valo 	struct rxtid *rxtid;
919bdcd8170SKalle Valo 	struct skb_hold_q *node;
920bdcd8170SKalle Valo 	u16 idx, idx_end, seq_end;
921bdcd8170SKalle Valo 	struct rxtid_stats *stats;
922bdcd8170SKalle Valo 
923bdcd8170SKalle Valo 	if (!p_aggr)
924bdcd8170SKalle Valo 		return;
925bdcd8170SKalle Valo 
926bdcd8170SKalle Valo 	rxtid = &p_aggr->rx_tid[tid];
927bdcd8170SKalle Valo 	stats = &p_aggr->stat[tid];
928bdcd8170SKalle Valo 
929bdcd8170SKalle Valo 	idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
930bdcd8170SKalle Valo 
931bdcd8170SKalle Valo 	/*
932bdcd8170SKalle Valo 	 * idx_end is typically the last possible frame in the window,
933bdcd8170SKalle Valo 	 * but changes to 'the' seq_no, when BAR comes. If seq_no
934bdcd8170SKalle Valo 	 * is non-zero, we will go up to that and stop.
935bdcd8170SKalle Valo 	 * Note: last seq no in current window will occupy the same
936bdcd8170SKalle Valo 	 * index position as index that is just previous to start.
937bdcd8170SKalle Valo 	 * An imp point : if win_sz is 7, for seq_no space of 4095,
938bdcd8170SKalle Valo 	 * then, there would be holes when sequence wrap around occurs.
939bdcd8170SKalle Valo 	 * Target should judiciously choose the win_sz, based on
940bdcd8170SKalle Valo 	 * this condition. For 4095, (TID_WINDOW_SZ = 2 x win_sz
941bdcd8170SKalle Valo 	 * 2, 4, 8, 16 win_sz works fine).
942bdcd8170SKalle Valo 	 * We must deque from "idx" to "idx_end", including both.
943bdcd8170SKalle Valo 	 */
944bdcd8170SKalle Valo 	seq_end = seq_no ? seq_no : rxtid->seq_next;
945bdcd8170SKalle Valo 	idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz);
946bdcd8170SKalle Valo 
947bdcd8170SKalle Valo 	spin_lock_bh(&rxtid->lock);
948bdcd8170SKalle Valo 
949bdcd8170SKalle Valo 	do {
950bdcd8170SKalle Valo 		node = &rxtid->hold_q[idx];
951bdcd8170SKalle Valo 		if ((order == 1) && (!node->skb))
952bdcd8170SKalle Valo 			break;
953bdcd8170SKalle Valo 
954bdcd8170SKalle Valo 		if (node->skb) {
955bdcd8170SKalle Valo 			if (node->is_amsdu)
956bdcd8170SKalle Valo 				aggr_slice_amsdu(p_aggr, rxtid, node->skb);
957bdcd8170SKalle Valo 			else
958bdcd8170SKalle Valo 				skb_queue_tail(&rxtid->q, node->skb);
959bdcd8170SKalle Valo 			node->skb = NULL;
960bdcd8170SKalle Valo 		} else
961bdcd8170SKalle Valo 			stats->num_hole++;
962bdcd8170SKalle Valo 
963bdcd8170SKalle Valo 		rxtid->seq_next = ATH6KL_NEXT_SEQ_NO(rxtid->seq_next);
964bdcd8170SKalle Valo 		idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
965bdcd8170SKalle Valo 	} while (idx != idx_end);
966bdcd8170SKalle Valo 
967bdcd8170SKalle Valo 	spin_unlock_bh(&rxtid->lock);
968bdcd8170SKalle Valo 
969bdcd8170SKalle Valo 	stats->num_delivered += skb_queue_len(&rxtid->q);
970bdcd8170SKalle Valo 
971bdcd8170SKalle Valo 	while ((skb = skb_dequeue(&rxtid->q)))
972bdcd8170SKalle Valo 		ath6kl_deliver_frames_to_nw_stack(p_aggr->dev, skb);
973bdcd8170SKalle Valo }
974bdcd8170SKalle Valo 
975bdcd8170SKalle Valo static bool aggr_process_recv_frm(struct aggr_info *agg_info, u8 tid,
976bdcd8170SKalle Valo 				  u16 seq_no,
977bdcd8170SKalle Valo 				  bool is_amsdu, struct sk_buff *frame)
978bdcd8170SKalle Valo {
979bdcd8170SKalle Valo 	struct rxtid *rxtid;
980bdcd8170SKalle Valo 	struct rxtid_stats *stats;
981bdcd8170SKalle Valo 	struct sk_buff *skb;
982bdcd8170SKalle Valo 	struct skb_hold_q *node;
983bdcd8170SKalle Valo 	u16 idx, st, cur, end;
984bdcd8170SKalle Valo 	bool is_queued = false;
985bdcd8170SKalle Valo 	u16 extended_end;
986bdcd8170SKalle Valo 
987bdcd8170SKalle Valo 	rxtid = &agg_info->rx_tid[tid];
988bdcd8170SKalle Valo 	stats = &agg_info->stat[tid];
989bdcd8170SKalle Valo 
990bdcd8170SKalle Valo 	stats->num_into_aggr++;
991bdcd8170SKalle Valo 
992bdcd8170SKalle Valo 	if (!rxtid->aggr) {
993bdcd8170SKalle Valo 		if (is_amsdu) {
994bdcd8170SKalle Valo 			aggr_slice_amsdu(agg_info, rxtid, frame);
995bdcd8170SKalle Valo 			is_queued = true;
996bdcd8170SKalle Valo 			stats->num_amsdu++;
997bdcd8170SKalle Valo 			while ((skb = skb_dequeue(&rxtid->q)))
998bdcd8170SKalle Valo 				ath6kl_deliver_frames_to_nw_stack(agg_info->dev,
999bdcd8170SKalle Valo 								  skb);
1000bdcd8170SKalle Valo 		}
1001bdcd8170SKalle Valo 		return is_queued;
1002bdcd8170SKalle Valo 	}
1003bdcd8170SKalle Valo 
1004bdcd8170SKalle Valo 	/* Check the incoming sequence no, if it's in the window */
1005bdcd8170SKalle Valo 	st = rxtid->seq_next;
1006bdcd8170SKalle Valo 	cur = seq_no;
1007bdcd8170SKalle Valo 	end = (st + rxtid->hold_q_sz-1) & ATH6KL_MAX_SEQ_NO;
1008bdcd8170SKalle Valo 
1009bdcd8170SKalle Valo 	if (((st < end) && (cur < st || cur > end)) ||
1010bdcd8170SKalle Valo 	    ((st > end) && (cur > end) && (cur < st))) {
1011bdcd8170SKalle Valo 		extended_end = (end + rxtid->hold_q_sz - 1) &
1012bdcd8170SKalle Valo 			ATH6KL_MAX_SEQ_NO;
1013bdcd8170SKalle Valo 
1014bdcd8170SKalle Valo 		if (((end < extended_end) &&
1015bdcd8170SKalle Valo 		     (cur < end || cur > extended_end)) ||
1016bdcd8170SKalle Valo 		    ((end > extended_end) && (cur > extended_end) &&
1017bdcd8170SKalle Valo 		     (cur < end))) {
1018bdcd8170SKalle Valo 			aggr_deque_frms(agg_info, tid, 0, 0);
1019bdcd8170SKalle Valo 			if (cur >= rxtid->hold_q_sz - 1)
1020bdcd8170SKalle Valo 				rxtid->seq_next = cur - (rxtid->hold_q_sz - 1);
1021bdcd8170SKalle Valo 			else
1022bdcd8170SKalle Valo 				rxtid->seq_next = ATH6KL_MAX_SEQ_NO -
1023bdcd8170SKalle Valo 						  (rxtid->hold_q_sz - 2 - cur);
1024bdcd8170SKalle Valo 		} else {
1025bdcd8170SKalle Valo 			/*
1026bdcd8170SKalle Valo 			 * Dequeue only those frames that are outside the
1027bdcd8170SKalle Valo 			 * new shifted window.
1028bdcd8170SKalle Valo 			 */
1029bdcd8170SKalle Valo 			if (cur >= rxtid->hold_q_sz - 1)
1030bdcd8170SKalle Valo 				st = cur - (rxtid->hold_q_sz - 1);
1031bdcd8170SKalle Valo 			else
1032bdcd8170SKalle Valo 				st = ATH6KL_MAX_SEQ_NO -
1033bdcd8170SKalle Valo 					(rxtid->hold_q_sz - 2 - cur);
1034bdcd8170SKalle Valo 
1035bdcd8170SKalle Valo 			aggr_deque_frms(agg_info, tid, st, 0);
1036bdcd8170SKalle Valo 		}
1037bdcd8170SKalle Valo 
1038bdcd8170SKalle Valo 		stats->num_oow++;
1039bdcd8170SKalle Valo 	}
1040bdcd8170SKalle Valo 
1041bdcd8170SKalle Valo 	idx = AGGR_WIN_IDX(seq_no, rxtid->hold_q_sz);
1042bdcd8170SKalle Valo 
1043bdcd8170SKalle Valo 	node = &rxtid->hold_q[idx];
1044bdcd8170SKalle Valo 
1045bdcd8170SKalle Valo 	spin_lock_bh(&rxtid->lock);
1046bdcd8170SKalle Valo 
1047bdcd8170SKalle Valo 	/*
1048bdcd8170SKalle Valo 	 * Is the cur frame duplicate or something beyond our window(hold_q
1049bdcd8170SKalle Valo 	 * -> which is 2x, already)?
1050bdcd8170SKalle Valo 	 *
1051bdcd8170SKalle Valo 	 * 1. Duplicate is easy - drop incoming frame.
1052bdcd8170SKalle Valo 	 * 2. Not falling in current sliding window.
1053bdcd8170SKalle Valo 	 *  2a. is the frame_seq_no preceding current tid_seq_no?
1054bdcd8170SKalle Valo 	 *      -> drop the frame. perhaps sender did not get our ACK.
1055bdcd8170SKalle Valo 	 *         this is taken care of above.
1056bdcd8170SKalle Valo 	 *  2b. is the frame_seq_no beyond window(st, TID_WINDOW_SZ);
1057bdcd8170SKalle Valo 	 *      -> Taken care of it above, by moving window forward.
1058bdcd8170SKalle Valo 	 */
1059bdcd8170SKalle Valo 	dev_kfree_skb(node->skb);
1060bdcd8170SKalle Valo 	stats->num_dups++;
1061bdcd8170SKalle Valo 
1062bdcd8170SKalle Valo 	node->skb = frame;
1063bdcd8170SKalle Valo 	is_queued = true;
1064bdcd8170SKalle Valo 	node->is_amsdu = is_amsdu;
1065bdcd8170SKalle Valo 	node->seq_no = seq_no;
1066bdcd8170SKalle Valo 
1067bdcd8170SKalle Valo 	if (node->is_amsdu)
1068bdcd8170SKalle Valo 		stats->num_amsdu++;
1069bdcd8170SKalle Valo 	else
1070bdcd8170SKalle Valo 		stats->num_mpdu++;
1071bdcd8170SKalle Valo 
1072bdcd8170SKalle Valo 	spin_unlock_bh(&rxtid->lock);
1073bdcd8170SKalle Valo 
1074bdcd8170SKalle Valo 	aggr_deque_frms(agg_info, tid, 0, 1);
1075bdcd8170SKalle Valo 
1076bdcd8170SKalle Valo 	if (agg_info->timer_scheduled)
1077bdcd8170SKalle Valo 		rxtid->progress = true;
1078bdcd8170SKalle Valo 	else
1079bdcd8170SKalle Valo 		for (idx = 0 ; idx < rxtid->hold_q_sz; idx++) {
1080bdcd8170SKalle Valo 			if (rxtid->hold_q[idx].skb) {
1081bdcd8170SKalle Valo 				/*
1082bdcd8170SKalle Valo 				 * There is a frame in the queue and no
1083bdcd8170SKalle Valo 				 * timer so start a timer to ensure that
1084bdcd8170SKalle Valo 				 * the frame doesn't remain stuck
1085bdcd8170SKalle Valo 				 * forever.
1086bdcd8170SKalle Valo 				 */
1087bdcd8170SKalle Valo 				agg_info->timer_scheduled = true;
1088bdcd8170SKalle Valo 				mod_timer(&agg_info->timer,
1089bdcd8170SKalle Valo 					  (jiffies +
1090bdcd8170SKalle Valo 					   HZ * (AGGR_RX_TIMEOUT) / 1000));
1091bdcd8170SKalle Valo 				rxtid->progress = false;
1092bdcd8170SKalle Valo 				rxtid->timer_mon = true;
1093bdcd8170SKalle Valo 				break;
1094bdcd8170SKalle Valo 			}
1095bdcd8170SKalle Valo 		}
1096bdcd8170SKalle Valo 
1097bdcd8170SKalle Valo 	return is_queued;
1098bdcd8170SKalle Valo }
1099bdcd8170SKalle Valo 
1100bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet)
1101bdcd8170SKalle Valo {
1102bdcd8170SKalle Valo 	struct ath6kl *ar = target->dev->ar;
1103bdcd8170SKalle Valo 	struct sk_buff *skb = packet->pkt_cntxt;
1104bdcd8170SKalle Valo 	struct wmi_rx_meta_v2 *meta;
1105bdcd8170SKalle Valo 	struct wmi_data_hdr *dhdr;
1106bdcd8170SKalle Valo 	int min_hdr_len;
1107bdcd8170SKalle Valo 	u8 meta_type, dot11_hdr = 0;
1108bdcd8170SKalle Valo 	int status = packet->status;
1109bdcd8170SKalle Valo 	enum htc_endpoint_id ept = packet->endpoint;
1110bdcd8170SKalle Valo 	bool is_amsdu, prev_ps, ps_state = false;
1111bdcd8170SKalle Valo 	struct ath6kl_sta *conn = NULL;
1112bdcd8170SKalle Valo 	struct sk_buff *skb1 = NULL;
1113bdcd8170SKalle Valo 	struct ethhdr *datap = NULL;
11146765d0aaSVasanthakumar Thiagarajan 	struct ath6kl_vif *vif;
1115bdcd8170SKalle Valo 	u16 seq_no, offset;
11166765d0aaSVasanthakumar Thiagarajan 	u8 tid, if_idx;
1117bdcd8170SKalle Valo 
1118bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_WLAN_RX,
1119bdcd8170SKalle Valo 		   "%s: ar=0x%p eid=%d, skb=0x%p, data=0x%p, len=0x%x status:%d",
1120bdcd8170SKalle Valo 		   __func__, ar, ept, skb, packet->buf,
1121bdcd8170SKalle Valo 		   packet->act_len, status);
1122bdcd8170SKalle Valo 
1123bdcd8170SKalle Valo 	if (status || !(skb->data + HTC_HDR_LENGTH)) {
11246765d0aaSVasanthakumar Thiagarajan 		dev_kfree_skb(skb);
11256765d0aaSVasanthakumar Thiagarajan 		return;
11266765d0aaSVasanthakumar Thiagarajan 	}
11276765d0aaSVasanthakumar Thiagarajan 
11286765d0aaSVasanthakumar Thiagarajan 	skb_put(skb, packet->act_len + HTC_HDR_LENGTH);
11296765d0aaSVasanthakumar Thiagarajan 	skb_pull(skb, HTC_HDR_LENGTH);
11306765d0aaSVasanthakumar Thiagarajan 
11316765d0aaSVasanthakumar Thiagarajan 	if (ept == ar->ctrl_ep) {
11326765d0aaSVasanthakumar Thiagarajan 		if_idx =
11336765d0aaSVasanthakumar Thiagarajan 		wmi_cmd_hdr_get_if_idx((struct wmi_cmd_hdr *) skb->data);
11346765d0aaSVasanthakumar Thiagarajan 	} else {
11356765d0aaSVasanthakumar Thiagarajan 		if_idx =
11366765d0aaSVasanthakumar Thiagarajan 		wmi_data_hdr_get_if_idx((struct wmi_data_hdr *) skb->data);
11376765d0aaSVasanthakumar Thiagarajan 	}
11386765d0aaSVasanthakumar Thiagarajan 
11396765d0aaSVasanthakumar Thiagarajan 	vif = ath6kl_get_vif_by_index(ar, if_idx);
11406765d0aaSVasanthakumar Thiagarajan 	if (!vif) {
1141bdcd8170SKalle Valo 		dev_kfree_skb(skb);
1142bdcd8170SKalle Valo 		return;
1143bdcd8170SKalle Valo 	}
1144bdcd8170SKalle Valo 
1145bdcd8170SKalle Valo 	/*
1146bdcd8170SKalle Valo 	 * Take lock to protect buffer counts and adaptive power throughput
1147bdcd8170SKalle Valo 	 * state.
1148bdcd8170SKalle Valo 	 */
1149478ac027SVasanthakumar Thiagarajan 	spin_lock_bh(&vif->if_lock);
1150bdcd8170SKalle Valo 
1151b95907a7SVasanthakumar Thiagarajan 	vif->net_stats.rx_packets++;
1152b95907a7SVasanthakumar Thiagarajan 	vif->net_stats.rx_bytes += packet->act_len;
1153bdcd8170SKalle Valo 
1154478ac027SVasanthakumar Thiagarajan 	spin_unlock_bh(&vif->if_lock);
115583dc5f2fSVasanthakumar Thiagarajan 
1156bdcd8170SKalle Valo 
1157ef094103SKalle Valo 	ath6kl_dbg_dump(ATH6KL_DBG_RAW_BYTES, __func__, "rx ",
1158ef094103SKalle Valo 			skb->data, skb->len);
1159bdcd8170SKalle Valo 
116028ae58ddSVasanthakumar Thiagarajan 	skb->dev = vif->ndev;
1161bdcd8170SKalle Valo 
1162bdcd8170SKalle Valo 	if (!test_bit(WMI_ENABLED, &ar->flag)) {
1163bdcd8170SKalle Valo 		if (EPPING_ALIGNMENT_PAD > 0)
1164bdcd8170SKalle Valo 			skb_pull(skb, EPPING_ALIGNMENT_PAD);
116528ae58ddSVasanthakumar Thiagarajan 		ath6kl_deliver_frames_to_nw_stack(vif->ndev, skb);
1166bdcd8170SKalle Valo 		return;
1167bdcd8170SKalle Valo 	}
1168bdcd8170SKalle Valo 
1169a918fb3cSRaja Mani 	ath6kl_check_wow_status(ar);
1170a918fb3cSRaja Mani 
1171bdcd8170SKalle Valo 	if (ept == ar->ctrl_ep) {
1172bdcd8170SKalle Valo 		ath6kl_wmi_control_rx(ar->wmi, skb);
1173bdcd8170SKalle Valo 		return;
1174bdcd8170SKalle Valo 	}
1175bdcd8170SKalle Valo 
117667f9178fSVasanthakumar Thiagarajan 	min_hdr_len = sizeof(struct ethhdr) + sizeof(struct wmi_data_hdr) +
1177bdcd8170SKalle Valo 		      sizeof(struct ath6kl_llc_snap_hdr);
1178bdcd8170SKalle Valo 
1179bdcd8170SKalle Valo 	dhdr = (struct wmi_data_hdr *) skb->data;
1180bdcd8170SKalle Valo 
1181bdcd8170SKalle Valo 	/*
1182bdcd8170SKalle Valo 	 * In the case of AP mode we may receive NULL data frames
1183bdcd8170SKalle Valo 	 * that do not have LLC hdr. They are 16 bytes in size.
1184bdcd8170SKalle Valo 	 * Allow these frames in the AP mode.
1185bdcd8170SKalle Valo 	 */
1186f5938f24SVasanthakumar Thiagarajan 	if (vif->nw_type != AP_NETWORK &&
1187bdcd8170SKalle Valo 	    ((packet->act_len < min_hdr_len) ||
1188bdcd8170SKalle Valo 	     (packet->act_len > WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH))) {
1189bdcd8170SKalle Valo 		ath6kl_info("frame len is too short or too long\n");
1190b95907a7SVasanthakumar Thiagarajan 		vif->net_stats.rx_errors++;
1191b95907a7SVasanthakumar Thiagarajan 		vif->net_stats.rx_length_errors++;
1192bdcd8170SKalle Valo 		dev_kfree_skb(skb);
1193bdcd8170SKalle Valo 		return;
1194bdcd8170SKalle Valo 	}
1195bdcd8170SKalle Valo 
1196bdcd8170SKalle Valo 	/* Get the Power save state of the STA */
1197f5938f24SVasanthakumar Thiagarajan 	if (vif->nw_type == AP_NETWORK) {
1198bdcd8170SKalle Valo 		meta_type = wmi_data_hdr_get_meta(dhdr);
1199bdcd8170SKalle Valo 
1200bdcd8170SKalle Valo 		ps_state = !!((dhdr->info >> WMI_DATA_HDR_PS_SHIFT) &
1201bdcd8170SKalle Valo 			      WMI_DATA_HDR_PS_MASK);
1202bdcd8170SKalle Valo 
1203bdcd8170SKalle Valo 		offset = sizeof(struct wmi_data_hdr);
1204bdcd8170SKalle Valo 
1205bdcd8170SKalle Valo 		switch (meta_type) {
1206bdcd8170SKalle Valo 		case 0:
1207bdcd8170SKalle Valo 			break;
1208bdcd8170SKalle Valo 		case WMI_META_VERSION_1:
1209bdcd8170SKalle Valo 			offset += sizeof(struct wmi_rx_meta_v1);
1210bdcd8170SKalle Valo 			break;
1211bdcd8170SKalle Valo 		case WMI_META_VERSION_2:
1212bdcd8170SKalle Valo 			offset += sizeof(struct wmi_rx_meta_v2);
1213bdcd8170SKalle Valo 			break;
1214bdcd8170SKalle Valo 		default:
1215bdcd8170SKalle Valo 			break;
1216bdcd8170SKalle Valo 		}
1217bdcd8170SKalle Valo 
1218bdcd8170SKalle Valo 		datap = (struct ethhdr *) (skb->data + offset);
12196765d0aaSVasanthakumar Thiagarajan 		conn = ath6kl_find_sta(vif, datap->h_source);
1220bdcd8170SKalle Valo 
1221bdcd8170SKalle Valo 		if (!conn) {
1222bdcd8170SKalle Valo 			dev_kfree_skb(skb);
1223bdcd8170SKalle Valo 			return;
1224bdcd8170SKalle Valo 		}
1225bdcd8170SKalle Valo 
1226bdcd8170SKalle Valo 		/*
1227bdcd8170SKalle Valo 		 * If there is a change in PS state of the STA,
1228bdcd8170SKalle Valo 		 * take appropriate steps:
1229bdcd8170SKalle Valo 		 *
1230bdcd8170SKalle Valo 		 * 1. If Sleep-->Awake, flush the psq for the STA
1231bdcd8170SKalle Valo 		 *    Clear the PVB for the STA.
1232bdcd8170SKalle Valo 		 * 2. If Awake-->Sleep, Starting queueing frames
1233bdcd8170SKalle Valo 		 *    the STA.
1234bdcd8170SKalle Valo 		 */
1235bdcd8170SKalle Valo 		prev_ps = !!(conn->sta_flags & STA_PS_SLEEP);
1236bdcd8170SKalle Valo 
1237bdcd8170SKalle Valo 		if (ps_state)
1238bdcd8170SKalle Valo 			conn->sta_flags |= STA_PS_SLEEP;
1239bdcd8170SKalle Valo 		else
1240bdcd8170SKalle Valo 			conn->sta_flags &= ~STA_PS_SLEEP;
1241bdcd8170SKalle Valo 
1242bdcd8170SKalle Valo 		if (prev_ps ^ !!(conn->sta_flags & STA_PS_SLEEP)) {
1243bdcd8170SKalle Valo 			if (!(conn->sta_flags & STA_PS_SLEEP)) {
1244bdcd8170SKalle Valo 				struct sk_buff *skbuff = NULL;
1245bdcd8170SKalle Valo 
1246bdcd8170SKalle Valo 				spin_lock_bh(&conn->psq_lock);
1247bdcd8170SKalle Valo 				while ((skbuff = skb_dequeue(&conn->psq))
1248bdcd8170SKalle Valo 				       != NULL) {
1249bdcd8170SKalle Valo 					spin_unlock_bh(&conn->psq_lock);
125028ae58ddSVasanthakumar Thiagarajan 					ath6kl_data_tx(skbuff, vif->ndev);
1251bdcd8170SKalle Valo 					spin_lock_bh(&conn->psq_lock);
1252bdcd8170SKalle Valo 				}
1253bdcd8170SKalle Valo 				spin_unlock_bh(&conn->psq_lock);
1254bdcd8170SKalle Valo 				/* Clear the PVB for this STA */
1255334234b5SVasanthakumar Thiagarajan 				ath6kl_wmi_set_pvb_cmd(ar->wmi, vif->fw_vif_idx,
1256334234b5SVasanthakumar Thiagarajan 						       conn->aid, 0);
1257bdcd8170SKalle Valo 			}
1258bdcd8170SKalle Valo 		}
1259bdcd8170SKalle Valo 
1260bdcd8170SKalle Valo 		/* drop NULL data frames here */
1261bdcd8170SKalle Valo 		if ((packet->act_len < min_hdr_len) ||
1262bdcd8170SKalle Valo 		    (packet->act_len >
1263bdcd8170SKalle Valo 		     WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH)) {
1264bdcd8170SKalle Valo 			dev_kfree_skb(skb);
1265bdcd8170SKalle Valo 			return;
1266bdcd8170SKalle Valo 		}
1267bdcd8170SKalle Valo 	}
1268bdcd8170SKalle Valo 
1269bdcd8170SKalle Valo 	is_amsdu = wmi_data_hdr_is_amsdu(dhdr) ? true : false;
1270bdcd8170SKalle Valo 	tid = wmi_data_hdr_get_up(dhdr);
1271bdcd8170SKalle Valo 	seq_no = wmi_data_hdr_get_seqno(dhdr);
1272bdcd8170SKalle Valo 	meta_type = wmi_data_hdr_get_meta(dhdr);
1273bdcd8170SKalle Valo 	dot11_hdr = wmi_data_hdr_get_dot11(dhdr);
1274594a0bc8SVasanthakumar Thiagarajan 	skb_pull(skb, sizeof(struct wmi_data_hdr));
1275bdcd8170SKalle Valo 
1276bdcd8170SKalle Valo 	switch (meta_type) {
1277bdcd8170SKalle Valo 	case WMI_META_VERSION_1:
1278bdcd8170SKalle Valo 		skb_pull(skb, sizeof(struct wmi_rx_meta_v1));
1279bdcd8170SKalle Valo 		break;
1280bdcd8170SKalle Valo 	case WMI_META_VERSION_2:
1281bdcd8170SKalle Valo 		meta = (struct wmi_rx_meta_v2 *) skb->data;
1282bdcd8170SKalle Valo 		if (meta->csum_flags & 0x1) {
1283bdcd8170SKalle Valo 			skb->ip_summed = CHECKSUM_COMPLETE;
1284bdcd8170SKalle Valo 			skb->csum = (__force __wsum) meta->csum;
1285bdcd8170SKalle Valo 		}
1286bdcd8170SKalle Valo 		skb_pull(skb, sizeof(struct wmi_rx_meta_v2));
1287bdcd8170SKalle Valo 		break;
1288bdcd8170SKalle Valo 	default:
1289bdcd8170SKalle Valo 		break;
1290bdcd8170SKalle Valo 	}
1291bdcd8170SKalle Valo 
1292bdcd8170SKalle Valo 	if (dot11_hdr)
1293bdcd8170SKalle Valo 		status = ath6kl_wmi_dot11_hdr_remove(ar->wmi, skb);
1294bdcd8170SKalle Valo 	else if (!is_amsdu)
1295bdcd8170SKalle Valo 		status = ath6kl_wmi_dot3_2_dix(skb);
1296bdcd8170SKalle Valo 
1297bdcd8170SKalle Valo 	if (status) {
1298bdcd8170SKalle Valo 		/*
1299bdcd8170SKalle Valo 		 * Drop frames that could not be processed (lack of
1300bdcd8170SKalle Valo 		 * memory, etc.)
1301bdcd8170SKalle Valo 		 */
1302bdcd8170SKalle Valo 		dev_kfree_skb(skb);
1303bdcd8170SKalle Valo 		return;
1304bdcd8170SKalle Valo 	}
1305bdcd8170SKalle Valo 
130628ae58ddSVasanthakumar Thiagarajan 	if (!(vif->ndev->flags & IFF_UP)) {
1307bdcd8170SKalle Valo 		dev_kfree_skb(skb);
1308bdcd8170SKalle Valo 		return;
1309bdcd8170SKalle Valo 	}
1310bdcd8170SKalle Valo 
1311f5938f24SVasanthakumar Thiagarajan 	if (vif->nw_type == AP_NETWORK) {
1312bdcd8170SKalle Valo 		datap = (struct ethhdr *) skb->data;
1313bdcd8170SKalle Valo 		if (is_multicast_ether_addr(datap->h_dest))
1314bdcd8170SKalle Valo 			/*
1315bdcd8170SKalle Valo 			 * Bcast/Mcast frames should be sent to the
1316bdcd8170SKalle Valo 			 * OS stack as well as on the air.
1317bdcd8170SKalle Valo 			 */
1318bdcd8170SKalle Valo 			skb1 = skb_copy(skb, GFP_ATOMIC);
1319bdcd8170SKalle Valo 		else {
1320bdcd8170SKalle Valo 			/*
1321bdcd8170SKalle Valo 			 * Search for a connected STA with dstMac
1322bdcd8170SKalle Valo 			 * as the Mac address. If found send the
1323bdcd8170SKalle Valo 			 * frame to it on the air else send the
1324bdcd8170SKalle Valo 			 * frame up the stack.
1325bdcd8170SKalle Valo 			 */
13266765d0aaSVasanthakumar Thiagarajan 			conn = ath6kl_find_sta(vif, datap->h_dest);
1327bdcd8170SKalle Valo 
1328bdcd8170SKalle Valo 			if (conn && ar->intra_bss) {
1329bdcd8170SKalle Valo 				skb1 = skb;
1330bdcd8170SKalle Valo 				skb = NULL;
1331bdcd8170SKalle Valo 			} else if (conn && !ar->intra_bss) {
1332bdcd8170SKalle Valo 				dev_kfree_skb(skb);
1333bdcd8170SKalle Valo 				skb = NULL;
1334bdcd8170SKalle Valo 			}
1335bdcd8170SKalle Valo 		}
1336bdcd8170SKalle Valo 		if (skb1)
133728ae58ddSVasanthakumar Thiagarajan 			ath6kl_data_tx(skb1, vif->ndev);
1338ad3f78b9SKalle Valo 
1339ad3f78b9SKalle Valo 		if (skb == NULL) {
1340ad3f78b9SKalle Valo 			/* nothing to deliver up the stack */
1341ad3f78b9SKalle Valo 			return;
1342ad3f78b9SKalle Valo 		}
1343bdcd8170SKalle Valo 	}
1344bdcd8170SKalle Valo 
13455694f962SKalle Valo 	datap = (struct ethhdr *) skb->data;
13465694f962SKalle Valo 
13475694f962SKalle Valo 	if (is_unicast_ether_addr(datap->h_dest) &&
13482132c69cSVasanthakumar Thiagarajan 	    aggr_process_recv_frm(vif->aggr_cntxt, tid, seq_no,
1349bdcd8170SKalle Valo 				  is_amsdu, skb))
13505694f962SKalle Valo 		/* aggregation code will handle the skb */
13515694f962SKalle Valo 		return;
13525694f962SKalle Valo 
135328ae58ddSVasanthakumar Thiagarajan 	ath6kl_deliver_frames_to_nw_stack(vif->ndev, skb);
1354bdcd8170SKalle Valo }
1355bdcd8170SKalle Valo 
1356bdcd8170SKalle Valo static void aggr_timeout(unsigned long arg)
1357bdcd8170SKalle Valo {
1358bdcd8170SKalle Valo 	u8 i, j;
1359bdcd8170SKalle Valo 	struct aggr_info *p_aggr = (struct aggr_info *) arg;
1360bdcd8170SKalle Valo 	struct rxtid *rxtid;
1361bdcd8170SKalle Valo 	struct rxtid_stats *stats;
1362bdcd8170SKalle Valo 
1363bdcd8170SKalle Valo 	for (i = 0; i < NUM_OF_TIDS; i++) {
1364bdcd8170SKalle Valo 		rxtid = &p_aggr->rx_tid[i];
1365bdcd8170SKalle Valo 		stats = &p_aggr->stat[i];
1366bdcd8170SKalle Valo 
1367bdcd8170SKalle Valo 		if (!rxtid->aggr || !rxtid->timer_mon || rxtid->progress)
1368bdcd8170SKalle Valo 			continue;
1369bdcd8170SKalle Valo 
1370bdcd8170SKalle Valo 		stats->num_timeouts++;
137137ca6335SKalle Valo 		ath6kl_dbg(ATH6KL_DBG_AGGR,
137237ca6335SKalle Valo 			   "aggr timeout (st %d end %d)\n",
1373bdcd8170SKalle Valo 			   rxtid->seq_next,
1374bdcd8170SKalle Valo 			   ((rxtid->seq_next + rxtid->hold_q_sz-1) &
1375bdcd8170SKalle Valo 			    ATH6KL_MAX_SEQ_NO));
1376bdcd8170SKalle Valo 		aggr_deque_frms(p_aggr, i, 0, 0);
1377bdcd8170SKalle Valo 	}
1378bdcd8170SKalle Valo 
1379bdcd8170SKalle Valo 	p_aggr->timer_scheduled = false;
1380bdcd8170SKalle Valo 
1381bdcd8170SKalle Valo 	for (i = 0; i < NUM_OF_TIDS; i++) {
1382bdcd8170SKalle Valo 		rxtid = &p_aggr->rx_tid[i];
1383bdcd8170SKalle Valo 
1384bdcd8170SKalle Valo 		if (rxtid->aggr && rxtid->hold_q) {
1385bdcd8170SKalle Valo 			for (j = 0; j < rxtid->hold_q_sz; j++) {
1386bdcd8170SKalle Valo 				if (rxtid->hold_q[j].skb) {
1387bdcd8170SKalle Valo 					p_aggr->timer_scheduled = true;
1388bdcd8170SKalle Valo 					rxtid->timer_mon = true;
1389bdcd8170SKalle Valo 					rxtid->progress = false;
1390bdcd8170SKalle Valo 					break;
1391bdcd8170SKalle Valo 				}
1392bdcd8170SKalle Valo 			}
1393bdcd8170SKalle Valo 
1394bdcd8170SKalle Valo 			if (j >= rxtid->hold_q_sz)
1395bdcd8170SKalle Valo 				rxtid->timer_mon = false;
1396bdcd8170SKalle Valo 		}
1397bdcd8170SKalle Valo 	}
1398bdcd8170SKalle Valo 
1399bdcd8170SKalle Valo 	if (p_aggr->timer_scheduled)
1400bdcd8170SKalle Valo 		mod_timer(&p_aggr->timer,
1401bdcd8170SKalle Valo 			  jiffies + msecs_to_jiffies(AGGR_RX_TIMEOUT));
1402bdcd8170SKalle Valo }
1403bdcd8170SKalle Valo 
1404bdcd8170SKalle Valo static void aggr_delete_tid_state(struct aggr_info *p_aggr, u8 tid)
1405bdcd8170SKalle Valo {
1406bdcd8170SKalle Valo 	struct rxtid *rxtid;
1407bdcd8170SKalle Valo 	struct rxtid_stats *stats;
1408bdcd8170SKalle Valo 
1409bdcd8170SKalle Valo 	if (!p_aggr || tid >= NUM_OF_TIDS)
1410bdcd8170SKalle Valo 		return;
1411bdcd8170SKalle Valo 
1412bdcd8170SKalle Valo 	rxtid = &p_aggr->rx_tid[tid];
1413bdcd8170SKalle Valo 	stats = &p_aggr->stat[tid];
1414bdcd8170SKalle Valo 
1415bdcd8170SKalle Valo 	if (rxtid->aggr)
1416bdcd8170SKalle Valo 		aggr_deque_frms(p_aggr, tid, 0, 0);
1417bdcd8170SKalle Valo 
1418bdcd8170SKalle Valo 	rxtid->aggr = false;
1419bdcd8170SKalle Valo 	rxtid->progress = false;
1420bdcd8170SKalle Valo 	rxtid->timer_mon = false;
1421bdcd8170SKalle Valo 	rxtid->win_sz = 0;
1422bdcd8170SKalle Valo 	rxtid->seq_next = 0;
1423bdcd8170SKalle Valo 	rxtid->hold_q_sz = 0;
1424bdcd8170SKalle Valo 
1425bdcd8170SKalle Valo 	kfree(rxtid->hold_q);
1426bdcd8170SKalle Valo 	rxtid->hold_q = NULL;
1427bdcd8170SKalle Valo 
1428bdcd8170SKalle Valo 	memset(stats, 0, sizeof(struct rxtid_stats));
1429bdcd8170SKalle Valo }
1430bdcd8170SKalle Valo 
1431240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
1432240d2799SVasanthakumar Thiagarajan 			     u8 win_sz)
1433bdcd8170SKalle Valo {
14342132c69cSVasanthakumar Thiagarajan 	struct aggr_info *p_aggr = vif->aggr_cntxt;
1435bdcd8170SKalle Valo 	struct rxtid *rxtid;
1436bdcd8170SKalle Valo 	struct rxtid_stats *stats;
1437bdcd8170SKalle Valo 	u16 hold_q_size;
1438bdcd8170SKalle Valo 
1439bdcd8170SKalle Valo 	if (!p_aggr)
1440bdcd8170SKalle Valo 		return;
1441bdcd8170SKalle Valo 
1442bdcd8170SKalle Valo 	rxtid = &p_aggr->rx_tid[tid];
1443bdcd8170SKalle Valo 	stats = &p_aggr->stat[tid];
1444bdcd8170SKalle Valo 
1445bdcd8170SKalle Valo 	if (win_sz < AGGR_WIN_SZ_MIN || win_sz > AGGR_WIN_SZ_MAX)
1446bdcd8170SKalle Valo 		ath6kl_dbg(ATH6KL_DBG_WLAN_RX, "%s: win_sz %d, tid %d\n",
1447bdcd8170SKalle Valo 			   __func__, win_sz, tid);
1448bdcd8170SKalle Valo 
1449bdcd8170SKalle Valo 	if (rxtid->aggr)
1450bdcd8170SKalle Valo 		aggr_delete_tid_state(p_aggr, tid);
1451bdcd8170SKalle Valo 
1452bdcd8170SKalle Valo 	rxtid->seq_next = seq_no;
1453bdcd8170SKalle Valo 	hold_q_size = TID_WINDOW_SZ(win_sz) * sizeof(struct skb_hold_q);
1454bdcd8170SKalle Valo 	rxtid->hold_q = kzalloc(hold_q_size, GFP_KERNEL);
1455bdcd8170SKalle Valo 	if (!rxtid->hold_q)
1456bdcd8170SKalle Valo 		return;
1457bdcd8170SKalle Valo 
1458bdcd8170SKalle Valo 	rxtid->win_sz = win_sz;
1459bdcd8170SKalle Valo 	rxtid->hold_q_sz = TID_WINDOW_SZ(win_sz);
1460bdcd8170SKalle Valo 	if (!skb_queue_empty(&rxtid->q))
1461bdcd8170SKalle Valo 		return;
1462bdcd8170SKalle Valo 
1463bdcd8170SKalle Valo 	rxtid->aggr = true;
1464bdcd8170SKalle Valo }
1465bdcd8170SKalle Valo 
1466bdcd8170SKalle Valo struct aggr_info *aggr_init(struct net_device *dev)
1467bdcd8170SKalle Valo {
1468bdcd8170SKalle Valo 	struct aggr_info *p_aggr = NULL;
1469bdcd8170SKalle Valo 	struct rxtid *rxtid;
1470bdcd8170SKalle Valo 	u8 i;
1471bdcd8170SKalle Valo 
1472bdcd8170SKalle Valo 	p_aggr = kzalloc(sizeof(struct aggr_info), GFP_KERNEL);
1473bdcd8170SKalle Valo 	if (!p_aggr) {
1474bdcd8170SKalle Valo 		ath6kl_err("failed to alloc memory for aggr_node\n");
1475bdcd8170SKalle Valo 		return NULL;
1476bdcd8170SKalle Valo 	}
1477bdcd8170SKalle Valo 
1478bdcd8170SKalle Valo 	p_aggr->aggr_sz = AGGR_SZ_DEFAULT;
1479bdcd8170SKalle Valo 	p_aggr->dev = dev;
1480bdcd8170SKalle Valo 	init_timer(&p_aggr->timer);
1481bdcd8170SKalle Valo 	p_aggr->timer.function = aggr_timeout;
1482bdcd8170SKalle Valo 	p_aggr->timer.data = (unsigned long) p_aggr;
1483bdcd8170SKalle Valo 
1484bdcd8170SKalle Valo 	p_aggr->timer_scheduled = false;
1485bdcd8170SKalle Valo 	skb_queue_head_init(&p_aggr->free_q);
1486bdcd8170SKalle Valo 
1487bdcd8170SKalle Valo 	ath6kl_alloc_netbufs(&p_aggr->free_q, AGGR_NUM_OF_FREE_NETBUFS);
1488bdcd8170SKalle Valo 
1489bdcd8170SKalle Valo 	for (i = 0; i < NUM_OF_TIDS; i++) {
1490bdcd8170SKalle Valo 		rxtid = &p_aggr->rx_tid[i];
1491bdcd8170SKalle Valo 		rxtid->aggr = false;
1492bdcd8170SKalle Valo 		rxtid->progress = false;
1493bdcd8170SKalle Valo 		rxtid->timer_mon = false;
1494bdcd8170SKalle Valo 		skb_queue_head_init(&rxtid->q);
1495bdcd8170SKalle Valo 		spin_lock_init(&rxtid->lock);
1496bdcd8170SKalle Valo 	}
1497bdcd8170SKalle Valo 
1498bdcd8170SKalle Valo 	return p_aggr;
1499bdcd8170SKalle Valo }
1500bdcd8170SKalle Valo 
1501240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid)
1502bdcd8170SKalle Valo {
15032132c69cSVasanthakumar Thiagarajan 	struct aggr_info *p_aggr = vif->aggr_cntxt;
1504bdcd8170SKalle Valo 	struct rxtid *rxtid;
1505bdcd8170SKalle Valo 
1506bdcd8170SKalle Valo 	if (!p_aggr)
1507bdcd8170SKalle Valo 		return;
1508bdcd8170SKalle Valo 
1509bdcd8170SKalle Valo 	rxtid = &p_aggr->rx_tid[tid];
1510bdcd8170SKalle Valo 
1511bdcd8170SKalle Valo 	if (rxtid->aggr)
1512bdcd8170SKalle Valo 		aggr_delete_tid_state(p_aggr, tid);
1513bdcd8170SKalle Valo }
1514bdcd8170SKalle Valo 
1515bdcd8170SKalle Valo void aggr_reset_state(struct aggr_info *aggr_info)
1516bdcd8170SKalle Valo {
1517bdcd8170SKalle Valo 	u8 tid;
1518bdcd8170SKalle Valo 
1519bdcd8170SKalle Valo 	for (tid = 0; tid < NUM_OF_TIDS; tid++)
1520bdcd8170SKalle Valo 		aggr_delete_tid_state(aggr_info, tid);
1521bdcd8170SKalle Valo }
1522bdcd8170SKalle Valo 
1523bdcd8170SKalle Valo /* clean up our amsdu buffer list */
1524bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar)
1525bdcd8170SKalle Valo {
1526bdcd8170SKalle Valo 	struct htc_packet *packet, *tmp_pkt;
1527bdcd8170SKalle Valo 
1528bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
1529bdcd8170SKalle Valo 	if (list_empty(&ar->amsdu_rx_buffer_queue)) {
1530bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
1531bdcd8170SKalle Valo 		return;
1532bdcd8170SKalle Valo 	}
1533bdcd8170SKalle Valo 
1534bdcd8170SKalle Valo 	list_for_each_entry_safe(packet, tmp_pkt, &ar->amsdu_rx_buffer_queue,
1535bdcd8170SKalle Valo 				 list) {
1536bdcd8170SKalle Valo 		list_del(&packet->list);
1537bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
1538bdcd8170SKalle Valo 		dev_kfree_skb(packet->pkt_cntxt);
1539bdcd8170SKalle Valo 		spin_lock_bh(&ar->lock);
1540bdcd8170SKalle Valo 	}
1541bdcd8170SKalle Valo 
1542bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
1543bdcd8170SKalle Valo }
1544bdcd8170SKalle Valo 
1545bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info)
1546bdcd8170SKalle Valo {
1547bdcd8170SKalle Valo 	struct rxtid *rxtid;
1548bdcd8170SKalle Valo 	u8 i, k;
1549bdcd8170SKalle Valo 
1550bdcd8170SKalle Valo 	if (!aggr_info)
1551bdcd8170SKalle Valo 		return;
1552bdcd8170SKalle Valo 
1553bdcd8170SKalle Valo 	if (aggr_info->timer_scheduled) {
1554bdcd8170SKalle Valo 		del_timer(&aggr_info->timer);
1555bdcd8170SKalle Valo 		aggr_info->timer_scheduled = false;
1556bdcd8170SKalle Valo 	}
1557bdcd8170SKalle Valo 
1558bdcd8170SKalle Valo 	for (i = 0; i < NUM_OF_TIDS; i++) {
1559bdcd8170SKalle Valo 		rxtid = &aggr_info->rx_tid[i];
1560bdcd8170SKalle Valo 		if (rxtid->hold_q) {
1561bdcd8170SKalle Valo 			for (k = 0; k < rxtid->hold_q_sz; k++)
1562bdcd8170SKalle Valo 				dev_kfree_skb(rxtid->hold_q[k].skb);
1563bdcd8170SKalle Valo 			kfree(rxtid->hold_q);
1564bdcd8170SKalle Valo 		}
1565bdcd8170SKalle Valo 
1566bdcd8170SKalle Valo 		skb_queue_purge(&rxtid->q);
1567bdcd8170SKalle Valo 	}
1568bdcd8170SKalle Valo 
1569bdcd8170SKalle Valo 	skb_queue_purge(&aggr_info->free_q);
1570bdcd8170SKalle Valo 	kfree(aggr_info);
1571bdcd8170SKalle Valo }
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