1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 3bdcd8170SKalle Valo * 4bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd8170SKalle Valo * 8bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd8170SKalle Valo */ 16bdcd8170SKalle Valo 17bdcd8170SKalle Valo #include "core.h" 18bdcd8170SKalle Valo #include "debug.h" 19bdcd8170SKalle Valo 20bdcd8170SKalle Valo static u8 ath6kl_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, 21bdcd8170SKalle Valo u32 *map_no) 22bdcd8170SKalle Valo { 23bdcd8170SKalle Valo struct ath6kl *ar = ath6kl_priv(dev); 24bdcd8170SKalle Valo struct ethhdr *eth_hdr; 25bdcd8170SKalle Valo u32 i, ep_map = -1; 26bdcd8170SKalle Valo u8 *datap; 27bdcd8170SKalle Valo 28bdcd8170SKalle Valo *map_no = 0; 29bdcd8170SKalle Valo datap = skb->data; 30bdcd8170SKalle Valo eth_hdr = (struct ethhdr *) (datap + sizeof(struct wmi_data_hdr)); 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo if (is_multicast_ether_addr(eth_hdr->h_dest)) 33bdcd8170SKalle Valo return ENDPOINT_2; 34bdcd8170SKalle Valo 35bdcd8170SKalle Valo for (i = 0; i < ar->node_num; i++) { 36bdcd8170SKalle Valo if (memcmp(eth_hdr->h_dest, ar->node_map[i].mac_addr, 37bdcd8170SKalle Valo ETH_ALEN) == 0) { 38bdcd8170SKalle Valo *map_no = i + 1; 39bdcd8170SKalle Valo ar->node_map[i].tx_pend++; 40bdcd8170SKalle Valo return ar->node_map[i].ep_id; 41bdcd8170SKalle Valo } 42bdcd8170SKalle Valo 43bdcd8170SKalle Valo if ((ep_map == -1) && !ar->node_map[i].tx_pend) 44bdcd8170SKalle Valo ep_map = i; 45bdcd8170SKalle Valo } 46bdcd8170SKalle Valo 47bdcd8170SKalle Valo if (ep_map == -1) { 48bdcd8170SKalle Valo ep_map = ar->node_num; 49bdcd8170SKalle Valo ar->node_num++; 50bdcd8170SKalle Valo if (ar->node_num > MAX_NODE_NUM) 51bdcd8170SKalle Valo return ENDPOINT_UNUSED; 52bdcd8170SKalle Valo } 53bdcd8170SKalle Valo 54bdcd8170SKalle Valo memcpy(ar->node_map[ep_map].mac_addr, eth_hdr->h_dest, ETH_ALEN); 55bdcd8170SKalle Valo 56bdcd8170SKalle Valo for (i = ENDPOINT_2; i <= ENDPOINT_5; i++) { 57bdcd8170SKalle Valo if (!ar->tx_pending[i]) { 58bdcd8170SKalle Valo ar->node_map[ep_map].ep_id = i; 59bdcd8170SKalle Valo break; 60bdcd8170SKalle Valo } 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo /* 63bdcd8170SKalle Valo * No free endpoint is available, start redistribution on 64bdcd8170SKalle Valo * the inuse endpoints. 65bdcd8170SKalle Valo */ 66bdcd8170SKalle Valo if (i == ENDPOINT_5) { 67bdcd8170SKalle Valo ar->node_map[ep_map].ep_id = ar->next_ep_id; 68bdcd8170SKalle Valo ar->next_ep_id++; 69bdcd8170SKalle Valo if (ar->next_ep_id > ENDPOINT_5) 70bdcd8170SKalle Valo ar->next_ep_id = ENDPOINT_2; 71bdcd8170SKalle Valo } 72bdcd8170SKalle Valo } 73bdcd8170SKalle Valo 74bdcd8170SKalle Valo *map_no = ep_map + 1; 75bdcd8170SKalle Valo ar->node_map[ep_map].tx_pend++; 76bdcd8170SKalle Valo 77bdcd8170SKalle Valo return ar->node_map[ep_map].ep_id; 78bdcd8170SKalle Valo } 79bdcd8170SKalle Valo 80c1762a3fSThirumalai Pachamuthu static bool ath6kl_process_uapsdq(struct ath6kl_sta *conn, 81c1762a3fSThirumalai Pachamuthu struct ath6kl_vif *vif, 82c1762a3fSThirumalai Pachamuthu struct sk_buff *skb, 83c1762a3fSThirumalai Pachamuthu u32 *flags) 84c1762a3fSThirumalai Pachamuthu { 85c1762a3fSThirumalai Pachamuthu struct ath6kl *ar = vif->ar; 86c1762a3fSThirumalai Pachamuthu bool is_apsdq_empty = false; 87c1762a3fSThirumalai Pachamuthu struct ethhdr *datap = (struct ethhdr *) skb->data; 88e5726028SKalle Valo u8 up = 0, traffic_class, *ip_hdr; 89c1762a3fSThirumalai Pachamuthu u16 ether_type; 90c1762a3fSThirumalai Pachamuthu struct ath6kl_llc_snap_hdr *llc_hdr; 91c1762a3fSThirumalai Pachamuthu 92c1762a3fSThirumalai Pachamuthu if (conn->sta_flags & STA_PS_APSD_TRIGGER) { 93c1762a3fSThirumalai Pachamuthu /* 94c1762a3fSThirumalai Pachamuthu * This tx is because of a uAPSD trigger, determine 95c1762a3fSThirumalai Pachamuthu * more and EOSP bit. Set EOSP if queue is empty 96c1762a3fSThirumalai Pachamuthu * or sufficient frames are delivered for this trigger. 97c1762a3fSThirumalai Pachamuthu */ 98c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 99c1762a3fSThirumalai Pachamuthu if (!skb_queue_empty(&conn->apsdq)) 100c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_MORE; 101c1762a3fSThirumalai Pachamuthu else if (conn->sta_flags & STA_PS_APSD_EOSP) 102c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_EOSP; 103c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_UAPSD; 104c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 105c1762a3fSThirumalai Pachamuthu return false; 106c1762a3fSThirumalai Pachamuthu } else if (!conn->apsd_info) 107c1762a3fSThirumalai Pachamuthu return false; 108c1762a3fSThirumalai Pachamuthu 109c1762a3fSThirumalai Pachamuthu if (test_bit(WMM_ENABLED, &vif->flags)) { 110c1762a3fSThirumalai Pachamuthu ether_type = be16_to_cpu(datap->h_proto); 111c1762a3fSThirumalai Pachamuthu if (is_ethertype(ether_type)) { 112c1762a3fSThirumalai Pachamuthu /* packet is in DIX format */ 113c1762a3fSThirumalai Pachamuthu ip_hdr = (u8 *)(datap + 1); 114c1762a3fSThirumalai Pachamuthu } else { 115c1762a3fSThirumalai Pachamuthu /* packet is in 802.3 format */ 116c1762a3fSThirumalai Pachamuthu llc_hdr = (struct ath6kl_llc_snap_hdr *) 117c1762a3fSThirumalai Pachamuthu (datap + 1); 118c1762a3fSThirumalai Pachamuthu ether_type = be16_to_cpu(llc_hdr->eth_type); 119c1762a3fSThirumalai Pachamuthu ip_hdr = (u8 *)(llc_hdr + 1); 120c1762a3fSThirumalai Pachamuthu } 121c1762a3fSThirumalai Pachamuthu 122c1762a3fSThirumalai Pachamuthu if (ether_type == IP_ETHERTYPE) 123c1762a3fSThirumalai Pachamuthu up = ath6kl_wmi_determine_user_priority( 124c1762a3fSThirumalai Pachamuthu ip_hdr, 0); 125c1762a3fSThirumalai Pachamuthu } 126c1762a3fSThirumalai Pachamuthu 127c1762a3fSThirumalai Pachamuthu traffic_class = ath6kl_wmi_get_traffic_class(up); 128c1762a3fSThirumalai Pachamuthu 129c1762a3fSThirumalai Pachamuthu if ((conn->apsd_info & (1 << traffic_class)) == 0) 130c1762a3fSThirumalai Pachamuthu return false; 131c1762a3fSThirumalai Pachamuthu 132c1762a3fSThirumalai Pachamuthu /* Queue the frames if the STA is sleeping */ 133c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 134c1762a3fSThirumalai Pachamuthu is_apsdq_empty = skb_queue_empty(&conn->apsdq); 135c1762a3fSThirumalai Pachamuthu skb_queue_tail(&conn->apsdq, skb); 136c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 137c1762a3fSThirumalai Pachamuthu 138c1762a3fSThirumalai Pachamuthu /* 139c1762a3fSThirumalai Pachamuthu * If this is the first pkt getting queued 140c1762a3fSThirumalai Pachamuthu * for this STA, update the PVB for this STA 141c1762a3fSThirumalai Pachamuthu */ 142c1762a3fSThirumalai Pachamuthu if (is_apsdq_empty) { 143c1762a3fSThirumalai Pachamuthu ath6kl_wmi_set_apsd_bfrd_traf(ar->wmi, 144c1762a3fSThirumalai Pachamuthu vif->fw_vif_idx, 145c1762a3fSThirumalai Pachamuthu conn->aid, 1, 0); 146c1762a3fSThirumalai Pachamuthu } 147c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_UAPSD; 148c1762a3fSThirumalai Pachamuthu 149c1762a3fSThirumalai Pachamuthu return true; 150c1762a3fSThirumalai Pachamuthu } 151c1762a3fSThirumalai Pachamuthu 152c1762a3fSThirumalai Pachamuthu static bool ath6kl_process_psq(struct ath6kl_sta *conn, 153c1762a3fSThirumalai Pachamuthu struct ath6kl_vif *vif, 154c1762a3fSThirumalai Pachamuthu struct sk_buff *skb, 155c1762a3fSThirumalai Pachamuthu u32 *flags) 156c1762a3fSThirumalai Pachamuthu { 157c1762a3fSThirumalai Pachamuthu bool is_psq_empty = false; 158c1762a3fSThirumalai Pachamuthu struct ath6kl *ar = vif->ar; 159c1762a3fSThirumalai Pachamuthu 160c1762a3fSThirumalai Pachamuthu if (conn->sta_flags & STA_PS_POLLED) { 161c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 162c1762a3fSThirumalai Pachamuthu if (!skb_queue_empty(&conn->psq)) 163c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_MORE; 164c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 165c1762a3fSThirumalai Pachamuthu return false; 166c1762a3fSThirumalai Pachamuthu } 167c1762a3fSThirumalai Pachamuthu 168c1762a3fSThirumalai Pachamuthu /* Queue the frames if the STA is sleeping */ 169c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 170c1762a3fSThirumalai Pachamuthu is_psq_empty = skb_queue_empty(&conn->psq); 171c1762a3fSThirumalai Pachamuthu skb_queue_tail(&conn->psq, skb); 172c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 173c1762a3fSThirumalai Pachamuthu 174c1762a3fSThirumalai Pachamuthu /* 175c1762a3fSThirumalai Pachamuthu * If this is the first pkt getting queued 176c1762a3fSThirumalai Pachamuthu * for this STA, update the PVB for this 177c1762a3fSThirumalai Pachamuthu * STA. 178c1762a3fSThirumalai Pachamuthu */ 179c1762a3fSThirumalai Pachamuthu if (is_psq_empty) 180c1762a3fSThirumalai Pachamuthu ath6kl_wmi_set_pvb_cmd(ar->wmi, 181c1762a3fSThirumalai Pachamuthu vif->fw_vif_idx, 182c1762a3fSThirumalai Pachamuthu conn->aid, 1); 183c1762a3fSThirumalai Pachamuthu return true; 184c1762a3fSThirumalai Pachamuthu } 185c1762a3fSThirumalai Pachamuthu 1866765d0aaSVasanthakumar Thiagarajan static bool ath6kl_powersave_ap(struct ath6kl_vif *vif, struct sk_buff *skb, 187c1762a3fSThirumalai Pachamuthu u32 *flags) 188bdcd8170SKalle Valo { 189bdcd8170SKalle Valo struct ethhdr *datap = (struct ethhdr *) skb->data; 190bdcd8170SKalle Valo struct ath6kl_sta *conn = NULL; 191c1762a3fSThirumalai Pachamuthu bool ps_queued = false; 1926765d0aaSVasanthakumar Thiagarajan struct ath6kl *ar = vif->ar; 193bdcd8170SKalle Valo 194bdcd8170SKalle Valo if (is_multicast_ether_addr(datap->h_dest)) { 195bdcd8170SKalle Valo u8 ctr = 0; 196bdcd8170SKalle Valo bool q_mcast = false; 197bdcd8170SKalle Valo 198bdcd8170SKalle Valo for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { 199bdcd8170SKalle Valo if (ar->sta_list[ctr].sta_flags & STA_PS_SLEEP) { 200bdcd8170SKalle Valo q_mcast = true; 201bdcd8170SKalle Valo break; 202bdcd8170SKalle Valo } 203bdcd8170SKalle Valo } 204bdcd8170SKalle Valo 205bdcd8170SKalle Valo if (q_mcast) { 206bdcd8170SKalle Valo /* 207bdcd8170SKalle Valo * If this transmit is not because of a Dtim Expiry 208bdcd8170SKalle Valo * q it. 209bdcd8170SKalle Valo */ 21059c98449SVasanthakumar Thiagarajan if (!test_bit(DTIM_EXPIRED, &vif->flags)) { 211bdcd8170SKalle Valo bool is_mcastq_empty = false; 212bdcd8170SKalle Valo 213bdcd8170SKalle Valo spin_lock_bh(&ar->mcastpsq_lock); 214bdcd8170SKalle Valo is_mcastq_empty = 215bdcd8170SKalle Valo skb_queue_empty(&ar->mcastpsq); 216bdcd8170SKalle Valo skb_queue_tail(&ar->mcastpsq, skb); 217bdcd8170SKalle Valo spin_unlock_bh(&ar->mcastpsq_lock); 218bdcd8170SKalle Valo 219bdcd8170SKalle Valo /* 220bdcd8170SKalle Valo * If this is the first Mcast pkt getting 221bdcd8170SKalle Valo * queued indicate to the target to set the 222bdcd8170SKalle Valo * BitmapControl LSB of the TIM IE. 223bdcd8170SKalle Valo */ 224bdcd8170SKalle Valo if (is_mcastq_empty) 225bdcd8170SKalle Valo ath6kl_wmi_set_pvb_cmd(ar->wmi, 226334234b5SVasanthakumar Thiagarajan vif->fw_vif_idx, 227bdcd8170SKalle Valo MCAST_AID, 1); 228bdcd8170SKalle Valo 229bdcd8170SKalle Valo ps_queued = true; 230bdcd8170SKalle Valo } else { 231bdcd8170SKalle Valo /* 232bdcd8170SKalle Valo * This transmit is because of Dtim expiry. 233bdcd8170SKalle Valo * Determine if MoreData bit has to be set. 234bdcd8170SKalle Valo */ 235bdcd8170SKalle Valo spin_lock_bh(&ar->mcastpsq_lock); 236bdcd8170SKalle Valo if (!skb_queue_empty(&ar->mcastpsq)) 237c1762a3fSThirumalai Pachamuthu *flags |= WMI_DATA_HDR_FLAGS_MORE; 238bdcd8170SKalle Valo spin_unlock_bh(&ar->mcastpsq_lock); 239bdcd8170SKalle Valo } 240bdcd8170SKalle Valo } 241bdcd8170SKalle Valo } else { 2426765d0aaSVasanthakumar Thiagarajan conn = ath6kl_find_sta(vif, datap->h_dest); 243bdcd8170SKalle Valo if (!conn) { 244bdcd8170SKalle Valo dev_kfree_skb(skb); 245bdcd8170SKalle Valo 246bdcd8170SKalle Valo /* Inform the caller that the skb is consumed */ 247bdcd8170SKalle Valo return true; 248bdcd8170SKalle Valo } 249bdcd8170SKalle Valo 250bdcd8170SKalle Valo if (conn->sta_flags & STA_PS_SLEEP) { 251c1762a3fSThirumalai Pachamuthu ps_queued = ath6kl_process_uapsdq(conn, 252c1762a3fSThirumalai Pachamuthu vif, skb, flags); 253c1762a3fSThirumalai Pachamuthu if (!(*flags & WMI_DATA_HDR_FLAGS_UAPSD)) 254c1762a3fSThirumalai Pachamuthu ps_queued = ath6kl_process_psq(conn, 255c1762a3fSThirumalai Pachamuthu vif, skb, flags); 256bdcd8170SKalle Valo } 257bdcd8170SKalle Valo } 258bdcd8170SKalle Valo return ps_queued; 259bdcd8170SKalle Valo } 260bdcd8170SKalle Valo 261bdcd8170SKalle Valo /* Tx functions */ 262bdcd8170SKalle Valo 263bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 264bdcd8170SKalle Valo enum htc_endpoint_id eid) 265bdcd8170SKalle Valo { 266bdcd8170SKalle Valo struct ath6kl *ar = devt; 267bdcd8170SKalle Valo int status = 0; 268bdcd8170SKalle Valo struct ath6kl_cookie *cookie = NULL; 269bdcd8170SKalle Valo 270bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 271bdcd8170SKalle Valo 272bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 273bdcd8170SKalle Valo "%s: skb=0x%p, len=0x%x eid =%d\n", __func__, 274bdcd8170SKalle Valo skb, skb->len, eid); 275bdcd8170SKalle Valo 276bdcd8170SKalle Valo if (test_bit(WMI_CTRL_EP_FULL, &ar->flag) && (eid == ar->ctrl_ep)) { 277bdcd8170SKalle Valo /* 278bdcd8170SKalle Valo * Control endpoint is full, don't allocate resources, we 279bdcd8170SKalle Valo * are just going to drop this packet. 280bdcd8170SKalle Valo */ 281bdcd8170SKalle Valo cookie = NULL; 282bdcd8170SKalle Valo ath6kl_err("wmi ctrl ep full, dropping pkt : 0x%p, len:%d\n", 283bdcd8170SKalle Valo skb, skb->len); 284bdcd8170SKalle Valo } else 285bdcd8170SKalle Valo cookie = ath6kl_alloc_cookie(ar); 286bdcd8170SKalle Valo 287bdcd8170SKalle Valo if (cookie == NULL) { 288bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 289bdcd8170SKalle Valo status = -ENOMEM; 290bdcd8170SKalle Valo goto fail_ctrl_tx; 291bdcd8170SKalle Valo } 292bdcd8170SKalle Valo 293bdcd8170SKalle Valo ar->tx_pending[eid]++; 294bdcd8170SKalle Valo 295bdcd8170SKalle Valo if (eid != ar->ctrl_ep) 296bdcd8170SKalle Valo ar->total_tx_data_pend++; 297bdcd8170SKalle Valo 298bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 299bdcd8170SKalle Valo 300bdcd8170SKalle Valo cookie->skb = skb; 301bdcd8170SKalle Valo cookie->map_no = 0; 302bdcd8170SKalle Valo set_htc_pkt_info(&cookie->htc_pkt, cookie, skb->data, skb->len, 303bdcd8170SKalle Valo eid, ATH6KL_CONTROL_PKT_TAG); 304bdcd8170SKalle Valo 305bdcd8170SKalle Valo /* 306bdcd8170SKalle Valo * This interface is asynchronous, if there is an error, cleanup 307bdcd8170SKalle Valo * will happen in the TX completion callback. 308bdcd8170SKalle Valo */ 309ad226ec2SKalle Valo ath6kl_htc_tx(ar->htc_target, &cookie->htc_pkt); 310bdcd8170SKalle Valo 311bdcd8170SKalle Valo return 0; 312bdcd8170SKalle Valo 313bdcd8170SKalle Valo fail_ctrl_tx: 314bdcd8170SKalle Valo dev_kfree_skb(skb); 315bdcd8170SKalle Valo return status; 316bdcd8170SKalle Valo } 317bdcd8170SKalle Valo 318bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev) 319bdcd8170SKalle Valo { 320bdcd8170SKalle Valo struct ath6kl *ar = ath6kl_priv(dev); 321bdcd8170SKalle Valo struct ath6kl_cookie *cookie = NULL; 322bdcd8170SKalle Valo enum htc_endpoint_id eid = ENDPOINT_UNUSED; 32359c98449SVasanthakumar Thiagarajan struct ath6kl_vif *vif = netdev_priv(dev); 324bdcd8170SKalle Valo u32 map_no = 0; 325bdcd8170SKalle Valo u16 htc_tag = ATH6KL_DATA_PKT_TAG; 326bdcd8170SKalle Valo u8 ac = 99 ; /* initialize to unmapped ac */ 327c1762a3fSThirumalai Pachamuthu bool chk_adhoc_ps_mapping = false; 328bdcd8170SKalle Valo int ret; 329bc48ad31SRishi Panjwani struct wmi_tx_meta_v2 meta_v2; 330bc48ad31SRishi Panjwani void *meta; 331bc48ad31SRishi Panjwani u8 csum_start = 0, csum_dest = 0, csum = skb->ip_summed; 332bc48ad31SRishi Panjwani u8 meta_ver = 0; 333c1762a3fSThirumalai Pachamuthu u32 flags = 0; 334bdcd8170SKalle Valo 335bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 336bdcd8170SKalle Valo "%s: skb=0x%p, data=0x%p, len=0x%x\n", __func__, 337bdcd8170SKalle Valo skb, skb->data, skb->len); 338bdcd8170SKalle Valo 339bdcd8170SKalle Valo /* If target is not associated */ 34059c98449SVasanthakumar Thiagarajan if (!test_bit(CONNECTED, &vif->flags)) { 341bdcd8170SKalle Valo dev_kfree_skb(skb); 342bdcd8170SKalle Valo return 0; 343bdcd8170SKalle Valo } 344bdcd8170SKalle Valo 345bdcd8170SKalle Valo if (!test_bit(WMI_READY, &ar->flag)) 346bdcd8170SKalle Valo goto fail_tx; 347bdcd8170SKalle Valo 348bdcd8170SKalle Valo /* AP mode Power saving processing */ 349f5938f24SVasanthakumar Thiagarajan if (vif->nw_type == AP_NETWORK) { 350c1762a3fSThirumalai Pachamuthu if (ath6kl_powersave_ap(vif, skb, &flags)) 351bdcd8170SKalle Valo return 0; 352bdcd8170SKalle Valo } 353bdcd8170SKalle Valo 354bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) { 355bc48ad31SRishi Panjwani if ((dev->features & NETIF_F_IP_CSUM) && 356bc48ad31SRishi Panjwani (csum == CHECKSUM_PARTIAL)) { 357bc48ad31SRishi Panjwani csum_start = skb->csum_start - 358bc48ad31SRishi Panjwani (skb_network_header(skb) - skb->head) + 359bc48ad31SRishi Panjwani sizeof(struct ath6kl_llc_snap_hdr); 360bc48ad31SRishi Panjwani csum_dest = skb->csum_offset + csum_start; 361bc48ad31SRishi Panjwani } 362bc48ad31SRishi Panjwani 363bdcd8170SKalle Valo if (skb_headroom(skb) < dev->needed_headroom) { 364a29517ceSVasanthakumar Thiagarajan struct sk_buff *tmp_skb = skb; 365a29517ceSVasanthakumar Thiagarajan 366a29517ceSVasanthakumar Thiagarajan skb = skb_realloc_headroom(skb, dev->needed_headroom); 367a29517ceSVasanthakumar Thiagarajan kfree_skb(tmp_skb); 368a29517ceSVasanthakumar Thiagarajan if (skb == NULL) { 369a29517ceSVasanthakumar Thiagarajan vif->net_stats.tx_dropped++; 370a29517ceSVasanthakumar Thiagarajan return 0; 371a29517ceSVasanthakumar Thiagarajan } 372bdcd8170SKalle Valo } 373bdcd8170SKalle Valo 374bdcd8170SKalle Valo if (ath6kl_wmi_dix_2_dot3(ar->wmi, skb)) { 375bdcd8170SKalle Valo ath6kl_err("ath6kl_wmi_dix_2_dot3 failed\n"); 376bdcd8170SKalle Valo goto fail_tx; 377bdcd8170SKalle Valo } 378bdcd8170SKalle Valo 379bc48ad31SRishi Panjwani if ((dev->features & NETIF_F_IP_CSUM) && 380bc48ad31SRishi Panjwani (csum == CHECKSUM_PARTIAL)) { 381bc48ad31SRishi Panjwani meta_v2.csum_start = csum_start; 382bc48ad31SRishi Panjwani meta_v2.csum_dest = csum_dest; 383bc48ad31SRishi Panjwani 384bc48ad31SRishi Panjwani /* instruct target to calculate checksum */ 385bc48ad31SRishi Panjwani meta_v2.csum_flags = WMI_META_V2_FLAG_CSUM_OFFLOAD; 386bc48ad31SRishi Panjwani meta_ver = WMI_META_VERSION_2; 387bc48ad31SRishi Panjwani meta = &meta_v2; 388bc48ad31SRishi Panjwani } else { 389bc48ad31SRishi Panjwani meta_ver = 0; 390bc48ad31SRishi Panjwani meta = NULL; 391bc48ad31SRishi Panjwani } 392bc48ad31SRishi Panjwani 393bc48ad31SRishi Panjwani ret = ath6kl_wmi_data_hdr_add(ar->wmi, skb, 394c1762a3fSThirumalai Pachamuthu DATA_MSGTYPE, flags, 0, 395bc48ad31SRishi Panjwani meta_ver, 396bc48ad31SRishi Panjwani meta, vif->fw_vif_idx); 397bc48ad31SRishi Panjwani 398bc48ad31SRishi Panjwani if (ret) { 399bc48ad31SRishi Panjwani ath6kl_warn("failed to add wmi data header:%d\n" 400bc48ad31SRishi Panjwani , ret); 401bdcd8170SKalle Valo goto fail_tx; 402bdcd8170SKalle Valo } 403bdcd8170SKalle Valo 404f5938f24SVasanthakumar Thiagarajan if ((vif->nw_type == ADHOC_NETWORK) && 40559c98449SVasanthakumar Thiagarajan ar->ibss_ps_enable && test_bit(CONNECTED, &vif->flags)) 406bdcd8170SKalle Valo chk_adhoc_ps_mapping = true; 407bdcd8170SKalle Valo else { 408bdcd8170SKalle Valo /* get the stream mapping */ 409240d2799SVasanthakumar Thiagarajan ret = ath6kl_wmi_implicit_create_pstream(ar->wmi, 410240d2799SVasanthakumar Thiagarajan vif->fw_vif_idx, skb, 41159c98449SVasanthakumar Thiagarajan 0, test_bit(WMM_ENABLED, &vif->flags), &ac); 412bdcd8170SKalle Valo if (ret) 413bdcd8170SKalle Valo goto fail_tx; 414bdcd8170SKalle Valo } 415bdcd8170SKalle Valo } else 416bdcd8170SKalle Valo goto fail_tx; 417bdcd8170SKalle Valo 418bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 419bdcd8170SKalle Valo 420bdcd8170SKalle Valo if (chk_adhoc_ps_mapping) 421bdcd8170SKalle Valo eid = ath6kl_ibss_map_epid(skb, dev, &map_no); 422bdcd8170SKalle Valo else 423bdcd8170SKalle Valo eid = ar->ac2ep_map[ac]; 424bdcd8170SKalle Valo 425bdcd8170SKalle Valo if (eid == 0 || eid == ENDPOINT_UNUSED) { 426bdcd8170SKalle Valo ath6kl_err("eid %d is not mapped!\n", eid); 427bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 428bdcd8170SKalle Valo goto fail_tx; 429bdcd8170SKalle Valo } 430bdcd8170SKalle Valo 431bdcd8170SKalle Valo /* allocate resource for this packet */ 432bdcd8170SKalle Valo cookie = ath6kl_alloc_cookie(ar); 433bdcd8170SKalle Valo 434bdcd8170SKalle Valo if (!cookie) { 435bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 436bdcd8170SKalle Valo goto fail_tx; 437bdcd8170SKalle Valo } 438bdcd8170SKalle Valo 439bdcd8170SKalle Valo /* update counts while the lock is held */ 440bdcd8170SKalle Valo ar->tx_pending[eid]++; 441bdcd8170SKalle Valo ar->total_tx_data_pend++; 442bdcd8170SKalle Valo 443bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 444bdcd8170SKalle Valo 44500b1edf1SJouni Malinen if (!IS_ALIGNED((unsigned long) skb->data - HTC_HDR_LENGTH, 4) && 44600b1edf1SJouni Malinen skb_cloned(skb)) { 44700b1edf1SJouni Malinen /* 44800b1edf1SJouni Malinen * We will touch (move the buffer data to align it. Since the 44900b1edf1SJouni Malinen * skb buffer is cloned and not only the header is changed, we 45000b1edf1SJouni Malinen * have to copy it to allow the changes. Since we are copying 45100b1edf1SJouni Malinen * the data here, we may as well align it by reserving suitable 45200b1edf1SJouni Malinen * headroom to avoid the memmove in ath6kl_htc_tx_buf_align(). 45300b1edf1SJouni Malinen */ 45400b1edf1SJouni Malinen struct sk_buff *nskb; 45500b1edf1SJouni Malinen 45600b1edf1SJouni Malinen nskb = skb_copy_expand(skb, HTC_HDR_LENGTH, 0, GFP_ATOMIC); 45700b1edf1SJouni Malinen if (nskb == NULL) 45800b1edf1SJouni Malinen goto fail_tx; 45900b1edf1SJouni Malinen kfree_skb(skb); 46000b1edf1SJouni Malinen skb = nskb; 46100b1edf1SJouni Malinen } 46200b1edf1SJouni Malinen 463bdcd8170SKalle Valo cookie->skb = skb; 464bdcd8170SKalle Valo cookie->map_no = map_no; 465bdcd8170SKalle Valo set_htc_pkt_info(&cookie->htc_pkt, cookie, skb->data, skb->len, 466bdcd8170SKalle Valo eid, htc_tag); 467bdcd8170SKalle Valo 468ef094103SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_RAW_BYTES, __func__, "tx ", 469ef094103SKalle Valo skb->data, skb->len); 470bdcd8170SKalle Valo 471bdcd8170SKalle Valo /* 472bdcd8170SKalle Valo * HTC interface is asynchronous, if this fails, cleanup will 473bdcd8170SKalle Valo * happen in the ath6kl_tx_complete callback. 474bdcd8170SKalle Valo */ 475ad226ec2SKalle Valo ath6kl_htc_tx(ar->htc_target, &cookie->htc_pkt); 476bdcd8170SKalle Valo 477bdcd8170SKalle Valo return 0; 478bdcd8170SKalle Valo 479bdcd8170SKalle Valo fail_tx: 480bdcd8170SKalle Valo dev_kfree_skb(skb); 481bdcd8170SKalle Valo 482b95907a7SVasanthakumar Thiagarajan vif->net_stats.tx_dropped++; 483b95907a7SVasanthakumar Thiagarajan vif->net_stats.tx_aborted_errors++; 484bdcd8170SKalle Valo 485bdcd8170SKalle Valo return 0; 486bdcd8170SKalle Valo } 487bdcd8170SKalle Valo 488bdcd8170SKalle Valo /* indicate tx activity or inactivity on a WMI stream */ 489bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active) 490bdcd8170SKalle Valo { 491bdcd8170SKalle Valo struct ath6kl *ar = devt; 492bdcd8170SKalle Valo enum htc_endpoint_id eid; 493bdcd8170SKalle Valo int i; 494bdcd8170SKalle Valo 495bdcd8170SKalle Valo eid = ar->ac2ep_map[traffic_class]; 496bdcd8170SKalle Valo 497bdcd8170SKalle Valo if (!test_bit(WMI_ENABLED, &ar->flag)) 498bdcd8170SKalle Valo goto notify_htc; 499bdcd8170SKalle Valo 500bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 501bdcd8170SKalle Valo 502bdcd8170SKalle Valo ar->ac_stream_active[traffic_class] = active; 503bdcd8170SKalle Valo 504bdcd8170SKalle Valo if (active) { 505bdcd8170SKalle Valo /* 506bdcd8170SKalle Valo * Keep track of the active stream with the highest 507bdcd8170SKalle Valo * priority. 508bdcd8170SKalle Valo */ 509bdcd8170SKalle Valo if (ar->ac_stream_pri_map[traffic_class] > 510bdcd8170SKalle Valo ar->hiac_stream_active_pri) 511bdcd8170SKalle Valo /* set the new highest active priority */ 512bdcd8170SKalle Valo ar->hiac_stream_active_pri = 513bdcd8170SKalle Valo ar->ac_stream_pri_map[traffic_class]; 514bdcd8170SKalle Valo 515bdcd8170SKalle Valo } else { 516bdcd8170SKalle Valo /* 517bdcd8170SKalle Valo * We may have to search for the next active stream 518bdcd8170SKalle Valo * that is the highest priority. 519bdcd8170SKalle Valo */ 520bdcd8170SKalle Valo if (ar->hiac_stream_active_pri == 521bdcd8170SKalle Valo ar->ac_stream_pri_map[traffic_class]) { 522bdcd8170SKalle Valo /* 523bdcd8170SKalle Valo * The highest priority stream just went inactive 524bdcd8170SKalle Valo * reset and search for the "next" highest "active" 525bdcd8170SKalle Valo * priority stream. 526bdcd8170SKalle Valo */ 527bdcd8170SKalle Valo ar->hiac_stream_active_pri = 0; 528bdcd8170SKalle Valo 529bdcd8170SKalle Valo for (i = 0; i < WMM_NUM_AC; i++) { 530bdcd8170SKalle Valo if (ar->ac_stream_active[i] && 531bdcd8170SKalle Valo (ar->ac_stream_pri_map[i] > 532bdcd8170SKalle Valo ar->hiac_stream_active_pri)) 533bdcd8170SKalle Valo /* 534bdcd8170SKalle Valo * Set the new highest active 535bdcd8170SKalle Valo * priority. 536bdcd8170SKalle Valo */ 537bdcd8170SKalle Valo ar->hiac_stream_active_pri = 538bdcd8170SKalle Valo ar->ac_stream_pri_map[i]; 539bdcd8170SKalle Valo } 540bdcd8170SKalle Valo } 541bdcd8170SKalle Valo } 542bdcd8170SKalle Valo 543bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 544bdcd8170SKalle Valo 545bdcd8170SKalle Valo notify_htc: 546bdcd8170SKalle Valo /* notify HTC, this may cause credit distribution changes */ 547ad226ec2SKalle Valo ath6kl_htc_indicate_activity_change(ar->htc_target, eid, active); 548bdcd8170SKalle Valo } 549bdcd8170SKalle Valo 550bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 551bdcd8170SKalle Valo struct htc_packet *packet) 552bdcd8170SKalle Valo { 553bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 554990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif; 555bdcd8170SKalle Valo enum htc_endpoint_id endpoint = packet->endpoint; 556990bd915SVasanthakumar Thiagarajan enum htc_send_full_action action = HTC_SEND_FULL_KEEP; 557bdcd8170SKalle Valo 558bdcd8170SKalle Valo if (endpoint == ar->ctrl_ep) { 559bdcd8170SKalle Valo /* 560bdcd8170SKalle Valo * Under normal WMI if this is getting full, then something 561bdcd8170SKalle Valo * is running rampant the host should not be exhausting the 562bdcd8170SKalle Valo * WMI queue with too many commands the only exception to 563bdcd8170SKalle Valo * this is during testing using endpointping. 564bdcd8170SKalle Valo */ 565bdcd8170SKalle Valo set_bit(WMI_CTRL_EP_FULL, &ar->flag); 566bdcd8170SKalle Valo ath6kl_err("wmi ctrl ep is full\n"); 567901db39cSVasanthakumar Thiagarajan return action; 568bdcd8170SKalle Valo } 569bdcd8170SKalle Valo 570bdcd8170SKalle Valo if (packet->info.tx.tag == ATH6KL_CONTROL_PKT_TAG) 571901db39cSVasanthakumar Thiagarajan return action; 572bdcd8170SKalle Valo 573bdcd8170SKalle Valo /* 574bdcd8170SKalle Valo * The last MAX_HI_COOKIE_NUM "batch" of cookies are reserved for 575bdcd8170SKalle Valo * the highest active stream. 576bdcd8170SKalle Valo */ 577bdcd8170SKalle Valo if (ar->ac_stream_pri_map[ar->ep2ac_map[endpoint]] < 578bdcd8170SKalle Valo ar->hiac_stream_active_pri && 579901db39cSVasanthakumar Thiagarajan ar->cookie_count <= MAX_HI_COOKIE_NUM) 580bdcd8170SKalle Valo /* 581bdcd8170SKalle Valo * Give preference to the highest priority stream by 582bdcd8170SKalle Valo * dropping the packets which overflowed. 583bdcd8170SKalle Valo */ 584990bd915SVasanthakumar Thiagarajan action = HTC_SEND_FULL_DROP; 585bdcd8170SKalle Valo 586990bd915SVasanthakumar Thiagarajan /* FIXME: Locking */ 58711f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 588990bd915SVasanthakumar Thiagarajan list_for_each_entry(vif, &ar->vif_list, list) { 589901db39cSVasanthakumar Thiagarajan if (vif->nw_type == ADHOC_NETWORK || 590901db39cSVasanthakumar Thiagarajan action != HTC_SEND_FULL_DROP) { 59111f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 592990bd915SVasanthakumar Thiagarajan 59359c98449SVasanthakumar Thiagarajan set_bit(NETQ_STOPPED, &vif->flags); 59428ae58ddSVasanthakumar Thiagarajan netif_stop_queue(vif->ndev); 595bdcd8170SKalle Valo 596990bd915SVasanthakumar Thiagarajan return action; 597990bd915SVasanthakumar Thiagarajan } 598990bd915SVasanthakumar Thiagarajan } 59911f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 600990bd915SVasanthakumar Thiagarajan 601990bd915SVasanthakumar Thiagarajan return action; 602bdcd8170SKalle Valo } 603bdcd8170SKalle Valo 604bdcd8170SKalle Valo /* TODO this needs to be looked at */ 605990bd915SVasanthakumar Thiagarajan static void ath6kl_tx_clear_node_map(struct ath6kl_vif *vif, 606bdcd8170SKalle Valo enum htc_endpoint_id eid, u32 map_no) 607bdcd8170SKalle Valo { 608990bd915SVasanthakumar Thiagarajan struct ath6kl *ar = vif->ar; 609bdcd8170SKalle Valo u32 i; 610bdcd8170SKalle Valo 611f5938f24SVasanthakumar Thiagarajan if (vif->nw_type != ADHOC_NETWORK) 612bdcd8170SKalle Valo return; 613bdcd8170SKalle Valo 614bdcd8170SKalle Valo if (!ar->ibss_ps_enable) 615bdcd8170SKalle Valo return; 616bdcd8170SKalle Valo 617bdcd8170SKalle Valo if (eid == ar->ctrl_ep) 618bdcd8170SKalle Valo return; 619bdcd8170SKalle Valo 620bdcd8170SKalle Valo if (map_no == 0) 621bdcd8170SKalle Valo return; 622bdcd8170SKalle Valo 623bdcd8170SKalle Valo map_no--; 624bdcd8170SKalle Valo ar->node_map[map_no].tx_pend--; 625bdcd8170SKalle Valo 626bdcd8170SKalle Valo if (ar->node_map[map_no].tx_pend) 627bdcd8170SKalle Valo return; 628bdcd8170SKalle Valo 629bdcd8170SKalle Valo if (map_no != (ar->node_num - 1)) 630bdcd8170SKalle Valo return; 631bdcd8170SKalle Valo 632bdcd8170SKalle Valo for (i = ar->node_num; i > 0; i--) { 633bdcd8170SKalle Valo if (ar->node_map[i - 1].tx_pend) 634bdcd8170SKalle Valo break; 635bdcd8170SKalle Valo 636bdcd8170SKalle Valo memset(&ar->node_map[i - 1], 0, 637bdcd8170SKalle Valo sizeof(struct ath6kl_node_mapping)); 638bdcd8170SKalle Valo ar->node_num--; 639bdcd8170SKalle Valo } 640bdcd8170SKalle Valo } 641bdcd8170SKalle Valo 642bdcd8170SKalle Valo void ath6kl_tx_complete(void *context, struct list_head *packet_queue) 643bdcd8170SKalle Valo { 644bdcd8170SKalle Valo struct ath6kl *ar = context; 645bdcd8170SKalle Valo struct sk_buff_head skb_queue; 646bdcd8170SKalle Valo struct htc_packet *packet; 647bdcd8170SKalle Valo struct sk_buff *skb; 648bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_cookie; 649bdcd8170SKalle Valo u32 map_no = 0; 650bdcd8170SKalle Valo int status; 651bdcd8170SKalle Valo enum htc_endpoint_id eid; 652bdcd8170SKalle Valo bool wake_event = false; 65371f96ee6SKalle Valo bool flushing[ATH6KL_VIF_MAX] = {false}; 6546765d0aaSVasanthakumar Thiagarajan u8 if_idx; 655990bd915SVasanthakumar Thiagarajan struct ath6kl_vif *vif; 656bdcd8170SKalle Valo 657bdcd8170SKalle Valo skb_queue_head_init(&skb_queue); 658bdcd8170SKalle Valo 659bdcd8170SKalle Valo /* lock the driver as we update internal state */ 660bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 661bdcd8170SKalle Valo 662bdcd8170SKalle Valo /* reap completed packets */ 663bdcd8170SKalle Valo while (!list_empty(packet_queue)) { 664bdcd8170SKalle Valo 665bdcd8170SKalle Valo packet = list_first_entry(packet_queue, struct htc_packet, 666bdcd8170SKalle Valo list); 667bdcd8170SKalle Valo list_del(&packet->list); 668bdcd8170SKalle Valo 669bdcd8170SKalle Valo ath6kl_cookie = (struct ath6kl_cookie *)packet->pkt_cntxt; 670bdcd8170SKalle Valo if (!ath6kl_cookie) 671bdcd8170SKalle Valo goto fatal; 672bdcd8170SKalle Valo 673bdcd8170SKalle Valo status = packet->status; 674bdcd8170SKalle Valo skb = ath6kl_cookie->skb; 675bdcd8170SKalle Valo eid = packet->endpoint; 676bdcd8170SKalle Valo map_no = ath6kl_cookie->map_no; 677bdcd8170SKalle Valo 678bdcd8170SKalle Valo if (!skb || !skb->data) 679bdcd8170SKalle Valo goto fatal; 680bdcd8170SKalle Valo 681bdcd8170SKalle Valo __skb_queue_tail(&skb_queue, skb); 682bdcd8170SKalle Valo 683bdcd8170SKalle Valo if (!status && (packet->act_len != skb->len)) 684bdcd8170SKalle Valo goto fatal; 685bdcd8170SKalle Valo 686bdcd8170SKalle Valo ar->tx_pending[eid]--; 687bdcd8170SKalle Valo 688bdcd8170SKalle Valo if (eid != ar->ctrl_ep) 689bdcd8170SKalle Valo ar->total_tx_data_pend--; 690bdcd8170SKalle Valo 691bdcd8170SKalle Valo if (eid == ar->ctrl_ep) { 692bdcd8170SKalle Valo if (test_bit(WMI_CTRL_EP_FULL, &ar->flag)) 693bdcd8170SKalle Valo clear_bit(WMI_CTRL_EP_FULL, &ar->flag); 694bdcd8170SKalle Valo 695bdcd8170SKalle Valo if (ar->tx_pending[eid] == 0) 696bdcd8170SKalle Valo wake_event = true; 697bdcd8170SKalle Valo } 698bdcd8170SKalle Valo 6996765d0aaSVasanthakumar Thiagarajan if (eid == ar->ctrl_ep) { 7006765d0aaSVasanthakumar Thiagarajan if_idx = wmi_cmd_hdr_get_if_idx( 701f3803eb2SVasanthakumar Thiagarajan (struct wmi_cmd_hdr *) packet->buf); 7026765d0aaSVasanthakumar Thiagarajan } else { 7036765d0aaSVasanthakumar Thiagarajan if_idx = wmi_data_hdr_get_if_idx( 704f3803eb2SVasanthakumar Thiagarajan (struct wmi_data_hdr *) packet->buf); 7056765d0aaSVasanthakumar Thiagarajan } 7066765d0aaSVasanthakumar Thiagarajan 7076765d0aaSVasanthakumar Thiagarajan vif = ath6kl_get_vif_by_index(ar, if_idx); 7086765d0aaSVasanthakumar Thiagarajan if (!vif) { 7096765d0aaSVasanthakumar Thiagarajan ath6kl_free_cookie(ar, ath6kl_cookie); 7106765d0aaSVasanthakumar Thiagarajan continue; 7116765d0aaSVasanthakumar Thiagarajan } 7126765d0aaSVasanthakumar Thiagarajan 713bdcd8170SKalle Valo if (status) { 714bdcd8170SKalle Valo if (status == -ECANCELED) 715bdcd8170SKalle Valo /* a packet was flushed */ 716990bd915SVasanthakumar Thiagarajan flushing[if_idx] = true; 717bdcd8170SKalle Valo 718b95907a7SVasanthakumar Thiagarajan vif->net_stats.tx_errors++; 719bdcd8170SKalle Valo 720778e6502SKalle Valo if (status != -ENOSPC && status != -ECANCELED) 721778e6502SKalle Valo ath6kl_warn("tx complete error: %d\n", status); 722778e6502SKalle Valo 723bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 724bdcd8170SKalle Valo "%s: skb=0x%p data=0x%p len=0x%x eid=%d %s\n", 725bdcd8170SKalle Valo __func__, skb, packet->buf, packet->act_len, 726bdcd8170SKalle Valo eid, "error!"); 727bdcd8170SKalle Valo } else { 728bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 729bdcd8170SKalle Valo "%s: skb=0x%p data=0x%p len=0x%x eid=%d %s\n", 730bdcd8170SKalle Valo __func__, skb, packet->buf, packet->act_len, 731bdcd8170SKalle Valo eid, "OK"); 732bdcd8170SKalle Valo 733990bd915SVasanthakumar Thiagarajan flushing[if_idx] = false; 734b95907a7SVasanthakumar Thiagarajan vif->net_stats.tx_packets++; 735b95907a7SVasanthakumar Thiagarajan vif->net_stats.tx_bytes += skb->len; 736bdcd8170SKalle Valo } 737bdcd8170SKalle Valo 738990bd915SVasanthakumar Thiagarajan ath6kl_tx_clear_node_map(vif, eid, map_no); 739bdcd8170SKalle Valo 740bdcd8170SKalle Valo ath6kl_free_cookie(ar, ath6kl_cookie); 741bdcd8170SKalle Valo 74259c98449SVasanthakumar Thiagarajan if (test_bit(NETQ_STOPPED, &vif->flags)) 74359c98449SVasanthakumar Thiagarajan clear_bit(NETQ_STOPPED, &vif->flags); 744bdcd8170SKalle Valo } 745bdcd8170SKalle Valo 746bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 747bdcd8170SKalle Valo 748bdcd8170SKalle Valo __skb_queue_purge(&skb_queue); 749bdcd8170SKalle Valo 750990bd915SVasanthakumar Thiagarajan /* FIXME: Locking */ 75111f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 752990bd915SVasanthakumar Thiagarajan list_for_each_entry(vif, &ar->vif_list, list) { 753990bd915SVasanthakumar Thiagarajan if (test_bit(CONNECTED, &vif->flags) && 754990bd915SVasanthakumar Thiagarajan !flushing[vif->fw_vif_idx]) { 75511f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 75628ae58ddSVasanthakumar Thiagarajan netif_wake_queue(vif->ndev); 75711f6e40dSVasanthakumar Thiagarajan spin_lock_bh(&ar->list_lock); 758bdcd8170SKalle Valo } 759990bd915SVasanthakumar Thiagarajan } 76011f6e40dSVasanthakumar Thiagarajan spin_unlock_bh(&ar->list_lock); 761bdcd8170SKalle Valo 762bdcd8170SKalle Valo if (wake_event) 763bdcd8170SKalle Valo wake_up(&ar->event_wq); 764bdcd8170SKalle Valo 765bdcd8170SKalle Valo return; 766bdcd8170SKalle Valo 767bdcd8170SKalle Valo fatal: 768bdcd8170SKalle Valo WARN_ON(1); 769bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 770bdcd8170SKalle Valo return; 771bdcd8170SKalle Valo } 772bdcd8170SKalle Valo 773bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar) 774bdcd8170SKalle Valo { 775bdcd8170SKalle Valo int i; 776bdcd8170SKalle Valo 777bdcd8170SKalle Valo /* flush all the data (non-control) streams */ 778bdcd8170SKalle Valo for (i = 0; i < WMM_NUM_AC; i++) 779ad226ec2SKalle Valo ath6kl_htc_flush_txep(ar->htc_target, ar->ac2ep_map[i], 780bdcd8170SKalle Valo ATH6KL_DATA_PKT_TAG); 781bdcd8170SKalle Valo } 782bdcd8170SKalle Valo 783bdcd8170SKalle Valo /* Rx functions */ 784bdcd8170SKalle Valo 785bdcd8170SKalle Valo static void ath6kl_deliver_frames_to_nw_stack(struct net_device *dev, 786bdcd8170SKalle Valo struct sk_buff *skb) 787bdcd8170SKalle Valo { 788bdcd8170SKalle Valo if (!skb) 789bdcd8170SKalle Valo return; 790bdcd8170SKalle Valo 791bdcd8170SKalle Valo skb->dev = dev; 792bdcd8170SKalle Valo 793bdcd8170SKalle Valo if (!(skb->dev->flags & IFF_UP)) { 794bdcd8170SKalle Valo dev_kfree_skb(skb); 795bdcd8170SKalle Valo return; 796bdcd8170SKalle Valo } 797bdcd8170SKalle Valo 798bdcd8170SKalle Valo skb->protocol = eth_type_trans(skb, skb->dev); 799bdcd8170SKalle Valo 800bdcd8170SKalle Valo netif_rx_ni(skb); 801bdcd8170SKalle Valo } 802bdcd8170SKalle Valo 803bdcd8170SKalle Valo static void ath6kl_alloc_netbufs(struct sk_buff_head *q, u16 num) 804bdcd8170SKalle Valo { 805bdcd8170SKalle Valo struct sk_buff *skb; 806bdcd8170SKalle Valo 807bdcd8170SKalle Valo while (num) { 808bdcd8170SKalle Valo skb = ath6kl_buf_alloc(ATH6KL_BUFFER_SIZE); 809bdcd8170SKalle Valo if (!skb) { 810bdcd8170SKalle Valo ath6kl_err("netbuf allocation failed\n"); 811bdcd8170SKalle Valo return; 812bdcd8170SKalle Valo } 813bdcd8170SKalle Valo skb_queue_tail(q, skb); 814bdcd8170SKalle Valo num--; 815bdcd8170SKalle Valo } 816bdcd8170SKalle Valo } 817bdcd8170SKalle Valo 818bdcd8170SKalle Valo static struct sk_buff *aggr_get_free_skb(struct aggr_info *p_aggr) 819bdcd8170SKalle Valo { 820bdcd8170SKalle Valo struct sk_buff *skb = NULL; 821bdcd8170SKalle Valo 822bdcd8170SKalle Valo if (skb_queue_len(&p_aggr->free_q) < (AGGR_NUM_OF_FREE_NETBUFS >> 2)) 823bdcd8170SKalle Valo ath6kl_alloc_netbufs(&p_aggr->free_q, AGGR_NUM_OF_FREE_NETBUFS); 824bdcd8170SKalle Valo 825bdcd8170SKalle Valo skb = skb_dequeue(&p_aggr->free_q); 826bdcd8170SKalle Valo 827bdcd8170SKalle Valo return skb; 828bdcd8170SKalle Valo } 829bdcd8170SKalle Valo 830bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, enum htc_endpoint_id endpoint) 831bdcd8170SKalle Valo { 832bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 833bdcd8170SKalle Valo struct sk_buff *skb; 834bdcd8170SKalle Valo int rx_buf; 835bdcd8170SKalle Valo int n_buf_refill; 836bdcd8170SKalle Valo struct htc_packet *packet; 837bdcd8170SKalle Valo struct list_head queue; 838bdcd8170SKalle Valo 839bdcd8170SKalle Valo n_buf_refill = ATH6KL_MAX_RX_BUFFERS - 840ad226ec2SKalle Valo ath6kl_htc_get_rxbuf_num(ar->htc_target, endpoint); 841bdcd8170SKalle Valo 842bdcd8170SKalle Valo if (n_buf_refill <= 0) 843bdcd8170SKalle Valo return; 844bdcd8170SKalle Valo 845bdcd8170SKalle Valo INIT_LIST_HEAD(&queue); 846bdcd8170SKalle Valo 847bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, 848bdcd8170SKalle Valo "%s: providing htc with %d buffers at eid=%d\n", 849bdcd8170SKalle Valo __func__, n_buf_refill, endpoint); 850bdcd8170SKalle Valo 851bdcd8170SKalle Valo for (rx_buf = 0; rx_buf < n_buf_refill; rx_buf++) { 852bdcd8170SKalle Valo skb = ath6kl_buf_alloc(ATH6KL_BUFFER_SIZE); 853bdcd8170SKalle Valo if (!skb) 854bdcd8170SKalle Valo break; 855bdcd8170SKalle Valo 856bdcd8170SKalle Valo packet = (struct htc_packet *) skb->head; 85794e532d1SVasanthakumar Thiagarajan if (!IS_ALIGNED((unsigned long) skb->data, 4)) 8581df94a85SVasanthakumar Thiagarajan skb->data = PTR_ALIGN(skb->data - 4, 4); 859bdcd8170SKalle Valo set_htc_rxpkt_info(packet, skb, skb->data, 860bdcd8170SKalle Valo ATH6KL_BUFFER_SIZE, endpoint); 861bdcd8170SKalle Valo list_add_tail(&packet->list, &queue); 862bdcd8170SKalle Valo } 863bdcd8170SKalle Valo 864bdcd8170SKalle Valo if (!list_empty(&queue)) 865ad226ec2SKalle Valo ath6kl_htc_add_rxbuf_multiple(ar->htc_target, &queue); 866bdcd8170SKalle Valo } 867bdcd8170SKalle Valo 868bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count) 869bdcd8170SKalle Valo { 870bdcd8170SKalle Valo struct htc_packet *packet; 871bdcd8170SKalle Valo struct sk_buff *skb; 872bdcd8170SKalle Valo 873bdcd8170SKalle Valo while (count) { 874bdcd8170SKalle Valo skb = ath6kl_buf_alloc(ATH6KL_AMSDU_BUFFER_SIZE); 875bdcd8170SKalle Valo if (!skb) 876bdcd8170SKalle Valo return; 877bdcd8170SKalle Valo 878bdcd8170SKalle Valo packet = (struct htc_packet *) skb->head; 87994e532d1SVasanthakumar Thiagarajan if (!IS_ALIGNED((unsigned long) skb->data, 4)) 8801df94a85SVasanthakumar Thiagarajan skb->data = PTR_ALIGN(skb->data - 4, 4); 881bdcd8170SKalle Valo set_htc_rxpkt_info(packet, skb, skb->data, 882bdcd8170SKalle Valo ATH6KL_AMSDU_BUFFER_SIZE, 0); 883bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 884bdcd8170SKalle Valo list_add_tail(&packet->list, &ar->amsdu_rx_buffer_queue); 885bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 886bdcd8170SKalle Valo count--; 887bdcd8170SKalle Valo } 888bdcd8170SKalle Valo } 889bdcd8170SKalle Valo 890bdcd8170SKalle Valo /* 891bdcd8170SKalle Valo * Callback to allocate a receive buffer for a pending packet. We use a 892bdcd8170SKalle Valo * pre-allocated list of buffers of maximum AMSDU size (4K). 893bdcd8170SKalle Valo */ 894bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 895bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 896bdcd8170SKalle Valo int len) 897bdcd8170SKalle Valo { 898bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 899bdcd8170SKalle Valo struct htc_packet *packet = NULL; 900bdcd8170SKalle Valo struct list_head *pkt_pos; 901bdcd8170SKalle Valo int refill_cnt = 0, depth = 0; 902bdcd8170SKalle Valo 903bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, "%s: eid=%d, len:%d\n", 904bdcd8170SKalle Valo __func__, endpoint, len); 905bdcd8170SKalle Valo 906bdcd8170SKalle Valo if ((len <= ATH6KL_BUFFER_SIZE) || 907bdcd8170SKalle Valo (len > ATH6KL_AMSDU_BUFFER_SIZE)) 908bdcd8170SKalle Valo return NULL; 909bdcd8170SKalle Valo 910bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 911bdcd8170SKalle Valo 912bdcd8170SKalle Valo if (list_empty(&ar->amsdu_rx_buffer_queue)) { 913bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 914bdcd8170SKalle Valo refill_cnt = ATH6KL_MAX_AMSDU_RX_BUFFERS; 915bdcd8170SKalle Valo goto refill_buf; 916bdcd8170SKalle Valo } 917bdcd8170SKalle Valo 918bdcd8170SKalle Valo packet = list_first_entry(&ar->amsdu_rx_buffer_queue, 919bdcd8170SKalle Valo struct htc_packet, list); 920bdcd8170SKalle Valo list_del(&packet->list); 921bdcd8170SKalle Valo list_for_each(pkt_pos, &ar->amsdu_rx_buffer_queue) 922bdcd8170SKalle Valo depth++; 923bdcd8170SKalle Valo 924bdcd8170SKalle Valo refill_cnt = ATH6KL_MAX_AMSDU_RX_BUFFERS - depth; 925bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 926bdcd8170SKalle Valo 927bdcd8170SKalle Valo /* set actual endpoint ID */ 928bdcd8170SKalle Valo packet->endpoint = endpoint; 929bdcd8170SKalle Valo 930bdcd8170SKalle Valo refill_buf: 931bdcd8170SKalle Valo if (refill_cnt >= ATH6KL_AMSDU_REFILL_THRESHOLD) 932bdcd8170SKalle Valo ath6kl_refill_amsdu_rxbufs(ar, refill_cnt); 933bdcd8170SKalle Valo 934bdcd8170SKalle Valo return packet; 935bdcd8170SKalle Valo } 936bdcd8170SKalle Valo 937bdcd8170SKalle Valo static void aggr_slice_amsdu(struct aggr_info *p_aggr, 938bdcd8170SKalle Valo struct rxtid *rxtid, struct sk_buff *skb) 939bdcd8170SKalle Valo { 940bdcd8170SKalle Valo struct sk_buff *new_skb; 941bdcd8170SKalle Valo struct ethhdr *hdr; 942bdcd8170SKalle Valo u16 frame_8023_len, payload_8023_len, mac_hdr_len, amsdu_len; 943bdcd8170SKalle Valo u8 *framep; 944bdcd8170SKalle Valo 945bdcd8170SKalle Valo mac_hdr_len = sizeof(struct ethhdr); 946bdcd8170SKalle Valo framep = skb->data + mac_hdr_len; 947bdcd8170SKalle Valo amsdu_len = skb->len - mac_hdr_len; 948bdcd8170SKalle Valo 949bdcd8170SKalle Valo while (amsdu_len > mac_hdr_len) { 950bdcd8170SKalle Valo hdr = (struct ethhdr *) framep; 951bdcd8170SKalle Valo payload_8023_len = ntohs(hdr->h_proto); 952bdcd8170SKalle Valo 953bdcd8170SKalle Valo if (payload_8023_len < MIN_MSDU_SUBFRAME_PAYLOAD_LEN || 954bdcd8170SKalle Valo payload_8023_len > MAX_MSDU_SUBFRAME_PAYLOAD_LEN) { 955bdcd8170SKalle Valo ath6kl_err("802.3 AMSDU frame bound check failed. len %d\n", 956bdcd8170SKalle Valo payload_8023_len); 957bdcd8170SKalle Valo break; 958bdcd8170SKalle Valo } 959bdcd8170SKalle Valo 960bdcd8170SKalle Valo frame_8023_len = payload_8023_len + mac_hdr_len; 961bdcd8170SKalle Valo new_skb = aggr_get_free_skb(p_aggr); 962bdcd8170SKalle Valo if (!new_skb) { 963bdcd8170SKalle Valo ath6kl_err("no buffer available\n"); 964bdcd8170SKalle Valo break; 965bdcd8170SKalle Valo } 966bdcd8170SKalle Valo 967bdcd8170SKalle Valo memcpy(new_skb->data, framep, frame_8023_len); 968bdcd8170SKalle Valo skb_put(new_skb, frame_8023_len); 969bdcd8170SKalle Valo if (ath6kl_wmi_dot3_2_dix(new_skb)) { 970bdcd8170SKalle Valo ath6kl_err("dot3_2_dix error\n"); 971bdcd8170SKalle Valo dev_kfree_skb(new_skb); 972bdcd8170SKalle Valo break; 973bdcd8170SKalle Valo } 974bdcd8170SKalle Valo 975bdcd8170SKalle Valo skb_queue_tail(&rxtid->q, new_skb); 976bdcd8170SKalle Valo 977bdcd8170SKalle Valo /* Is this the last subframe within this aggregate ? */ 978bdcd8170SKalle Valo if ((amsdu_len - frame_8023_len) == 0) 979bdcd8170SKalle Valo break; 980bdcd8170SKalle Valo 981bdcd8170SKalle Valo /* Add the length of A-MSDU subframe padding bytes - 982bdcd8170SKalle Valo * Round to nearest word. 983bdcd8170SKalle Valo */ 98413e34ea1SVasanthakumar Thiagarajan frame_8023_len = ALIGN(frame_8023_len, 4); 985bdcd8170SKalle Valo 986bdcd8170SKalle Valo framep += frame_8023_len; 987bdcd8170SKalle Valo amsdu_len -= frame_8023_len; 988bdcd8170SKalle Valo } 989bdcd8170SKalle Valo 990bdcd8170SKalle Valo dev_kfree_skb(skb); 991bdcd8170SKalle Valo } 992bdcd8170SKalle Valo 993bdcd8170SKalle Valo static void aggr_deque_frms(struct aggr_info *p_aggr, u8 tid, 994bdcd8170SKalle Valo u16 seq_no, u8 order) 995bdcd8170SKalle Valo { 996bdcd8170SKalle Valo struct sk_buff *skb; 997bdcd8170SKalle Valo struct rxtid *rxtid; 998bdcd8170SKalle Valo struct skb_hold_q *node; 999bdcd8170SKalle Valo u16 idx, idx_end, seq_end; 1000bdcd8170SKalle Valo struct rxtid_stats *stats; 1001bdcd8170SKalle Valo 1002bdcd8170SKalle Valo if (!p_aggr) 1003bdcd8170SKalle Valo return; 1004bdcd8170SKalle Valo 1005bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1006bdcd8170SKalle Valo stats = &p_aggr->stat[tid]; 1007bdcd8170SKalle Valo 1008bdcd8170SKalle Valo idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz); 1009bdcd8170SKalle Valo 1010bdcd8170SKalle Valo /* 1011bdcd8170SKalle Valo * idx_end is typically the last possible frame in the window, 1012bdcd8170SKalle Valo * but changes to 'the' seq_no, when BAR comes. If seq_no 1013bdcd8170SKalle Valo * is non-zero, we will go up to that and stop. 1014bdcd8170SKalle Valo * Note: last seq no in current window will occupy the same 1015bdcd8170SKalle Valo * index position as index that is just previous to start. 1016bdcd8170SKalle Valo * An imp point : if win_sz is 7, for seq_no space of 4095, 1017bdcd8170SKalle Valo * then, there would be holes when sequence wrap around occurs. 1018bdcd8170SKalle Valo * Target should judiciously choose the win_sz, based on 1019bdcd8170SKalle Valo * this condition. For 4095, (TID_WINDOW_SZ = 2 x win_sz 1020bdcd8170SKalle Valo * 2, 4, 8, 16 win_sz works fine). 1021bdcd8170SKalle Valo * We must deque from "idx" to "idx_end", including both. 1022bdcd8170SKalle Valo */ 1023bdcd8170SKalle Valo seq_end = seq_no ? seq_no : rxtid->seq_next; 1024bdcd8170SKalle Valo idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz); 1025bdcd8170SKalle Valo 1026bdcd8170SKalle Valo spin_lock_bh(&rxtid->lock); 1027bdcd8170SKalle Valo 1028bdcd8170SKalle Valo do { 1029bdcd8170SKalle Valo node = &rxtid->hold_q[idx]; 1030bdcd8170SKalle Valo if ((order == 1) && (!node->skb)) 1031bdcd8170SKalle Valo break; 1032bdcd8170SKalle Valo 1033bdcd8170SKalle Valo if (node->skb) { 1034bdcd8170SKalle Valo if (node->is_amsdu) 1035bdcd8170SKalle Valo aggr_slice_amsdu(p_aggr, rxtid, node->skb); 1036bdcd8170SKalle Valo else 1037bdcd8170SKalle Valo skb_queue_tail(&rxtid->q, node->skb); 1038bdcd8170SKalle Valo node->skb = NULL; 1039bdcd8170SKalle Valo } else 1040bdcd8170SKalle Valo stats->num_hole++; 1041bdcd8170SKalle Valo 1042bdcd8170SKalle Valo rxtid->seq_next = ATH6KL_NEXT_SEQ_NO(rxtid->seq_next); 1043bdcd8170SKalle Valo idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz); 1044bdcd8170SKalle Valo } while (idx != idx_end); 1045bdcd8170SKalle Valo 1046bdcd8170SKalle Valo spin_unlock_bh(&rxtid->lock); 1047bdcd8170SKalle Valo 1048bdcd8170SKalle Valo stats->num_delivered += skb_queue_len(&rxtid->q); 1049bdcd8170SKalle Valo 1050bdcd8170SKalle Valo while ((skb = skb_dequeue(&rxtid->q))) 1051bdcd8170SKalle Valo ath6kl_deliver_frames_to_nw_stack(p_aggr->dev, skb); 1052bdcd8170SKalle Valo } 1053bdcd8170SKalle Valo 1054bdcd8170SKalle Valo static bool aggr_process_recv_frm(struct aggr_info *agg_info, u8 tid, 1055bdcd8170SKalle Valo u16 seq_no, 1056bdcd8170SKalle Valo bool is_amsdu, struct sk_buff *frame) 1057bdcd8170SKalle Valo { 1058bdcd8170SKalle Valo struct rxtid *rxtid; 1059bdcd8170SKalle Valo struct rxtid_stats *stats; 1060bdcd8170SKalle Valo struct sk_buff *skb; 1061bdcd8170SKalle Valo struct skb_hold_q *node; 1062bdcd8170SKalle Valo u16 idx, st, cur, end; 1063bdcd8170SKalle Valo bool is_queued = false; 1064bdcd8170SKalle Valo u16 extended_end; 1065bdcd8170SKalle Valo 1066bdcd8170SKalle Valo rxtid = &agg_info->rx_tid[tid]; 1067bdcd8170SKalle Valo stats = &agg_info->stat[tid]; 1068bdcd8170SKalle Valo 1069bdcd8170SKalle Valo stats->num_into_aggr++; 1070bdcd8170SKalle Valo 1071bdcd8170SKalle Valo if (!rxtid->aggr) { 1072bdcd8170SKalle Valo if (is_amsdu) { 1073bdcd8170SKalle Valo aggr_slice_amsdu(agg_info, rxtid, frame); 1074bdcd8170SKalle Valo is_queued = true; 1075bdcd8170SKalle Valo stats->num_amsdu++; 1076bdcd8170SKalle Valo while ((skb = skb_dequeue(&rxtid->q))) 1077bdcd8170SKalle Valo ath6kl_deliver_frames_to_nw_stack(agg_info->dev, 1078bdcd8170SKalle Valo skb); 1079bdcd8170SKalle Valo } 1080bdcd8170SKalle Valo return is_queued; 1081bdcd8170SKalle Valo } 1082bdcd8170SKalle Valo 1083bdcd8170SKalle Valo /* Check the incoming sequence no, if it's in the window */ 1084bdcd8170SKalle Valo st = rxtid->seq_next; 1085bdcd8170SKalle Valo cur = seq_no; 1086bdcd8170SKalle Valo end = (st + rxtid->hold_q_sz-1) & ATH6KL_MAX_SEQ_NO; 1087bdcd8170SKalle Valo 1088bdcd8170SKalle Valo if (((st < end) && (cur < st || cur > end)) || 1089bdcd8170SKalle Valo ((st > end) && (cur > end) && (cur < st))) { 1090bdcd8170SKalle Valo extended_end = (end + rxtid->hold_q_sz - 1) & 1091bdcd8170SKalle Valo ATH6KL_MAX_SEQ_NO; 1092bdcd8170SKalle Valo 1093bdcd8170SKalle Valo if (((end < extended_end) && 1094bdcd8170SKalle Valo (cur < end || cur > extended_end)) || 1095bdcd8170SKalle Valo ((end > extended_end) && (cur > extended_end) && 1096bdcd8170SKalle Valo (cur < end))) { 1097bdcd8170SKalle Valo aggr_deque_frms(agg_info, tid, 0, 0); 1098bdcd8170SKalle Valo if (cur >= rxtid->hold_q_sz - 1) 1099bdcd8170SKalle Valo rxtid->seq_next = cur - (rxtid->hold_q_sz - 1); 1100bdcd8170SKalle Valo else 1101bdcd8170SKalle Valo rxtid->seq_next = ATH6KL_MAX_SEQ_NO - 1102bdcd8170SKalle Valo (rxtid->hold_q_sz - 2 - cur); 1103bdcd8170SKalle Valo } else { 1104bdcd8170SKalle Valo /* 1105bdcd8170SKalle Valo * Dequeue only those frames that are outside the 1106bdcd8170SKalle Valo * new shifted window. 1107bdcd8170SKalle Valo */ 1108bdcd8170SKalle Valo if (cur >= rxtid->hold_q_sz - 1) 1109bdcd8170SKalle Valo st = cur - (rxtid->hold_q_sz - 1); 1110bdcd8170SKalle Valo else 1111bdcd8170SKalle Valo st = ATH6KL_MAX_SEQ_NO - 1112bdcd8170SKalle Valo (rxtid->hold_q_sz - 2 - cur); 1113bdcd8170SKalle Valo 1114bdcd8170SKalle Valo aggr_deque_frms(agg_info, tid, st, 0); 1115bdcd8170SKalle Valo } 1116bdcd8170SKalle Valo 1117bdcd8170SKalle Valo stats->num_oow++; 1118bdcd8170SKalle Valo } 1119bdcd8170SKalle Valo 1120bdcd8170SKalle Valo idx = AGGR_WIN_IDX(seq_no, rxtid->hold_q_sz); 1121bdcd8170SKalle Valo 1122bdcd8170SKalle Valo node = &rxtid->hold_q[idx]; 1123bdcd8170SKalle Valo 1124bdcd8170SKalle Valo spin_lock_bh(&rxtid->lock); 1125bdcd8170SKalle Valo 1126bdcd8170SKalle Valo /* 1127bdcd8170SKalle Valo * Is the cur frame duplicate or something beyond our window(hold_q 1128bdcd8170SKalle Valo * -> which is 2x, already)? 1129bdcd8170SKalle Valo * 1130bdcd8170SKalle Valo * 1. Duplicate is easy - drop incoming frame. 1131bdcd8170SKalle Valo * 2. Not falling in current sliding window. 1132bdcd8170SKalle Valo * 2a. is the frame_seq_no preceding current tid_seq_no? 1133bdcd8170SKalle Valo * -> drop the frame. perhaps sender did not get our ACK. 1134bdcd8170SKalle Valo * this is taken care of above. 1135bdcd8170SKalle Valo * 2b. is the frame_seq_no beyond window(st, TID_WINDOW_SZ); 1136bdcd8170SKalle Valo * -> Taken care of it above, by moving window forward. 1137bdcd8170SKalle Valo */ 1138bdcd8170SKalle Valo dev_kfree_skb(node->skb); 1139bdcd8170SKalle Valo stats->num_dups++; 1140bdcd8170SKalle Valo 1141bdcd8170SKalle Valo node->skb = frame; 1142bdcd8170SKalle Valo is_queued = true; 1143bdcd8170SKalle Valo node->is_amsdu = is_amsdu; 1144bdcd8170SKalle Valo node->seq_no = seq_no; 1145bdcd8170SKalle Valo 1146bdcd8170SKalle Valo if (node->is_amsdu) 1147bdcd8170SKalle Valo stats->num_amsdu++; 1148bdcd8170SKalle Valo else 1149bdcd8170SKalle Valo stats->num_mpdu++; 1150bdcd8170SKalle Valo 1151bdcd8170SKalle Valo spin_unlock_bh(&rxtid->lock); 1152bdcd8170SKalle Valo 1153bdcd8170SKalle Valo aggr_deque_frms(agg_info, tid, 0, 1); 1154bdcd8170SKalle Valo 1155bdcd8170SKalle Valo if (agg_info->timer_scheduled) 1156bdcd8170SKalle Valo rxtid->progress = true; 1157bdcd8170SKalle Valo else 1158bdcd8170SKalle Valo for (idx = 0 ; idx < rxtid->hold_q_sz; idx++) { 1159bdcd8170SKalle Valo if (rxtid->hold_q[idx].skb) { 1160bdcd8170SKalle Valo /* 1161bdcd8170SKalle Valo * There is a frame in the queue and no 1162bdcd8170SKalle Valo * timer so start a timer to ensure that 1163bdcd8170SKalle Valo * the frame doesn't remain stuck 1164bdcd8170SKalle Valo * forever. 1165bdcd8170SKalle Valo */ 1166bdcd8170SKalle Valo agg_info->timer_scheduled = true; 1167bdcd8170SKalle Valo mod_timer(&agg_info->timer, 1168bdcd8170SKalle Valo (jiffies + 1169bdcd8170SKalle Valo HZ * (AGGR_RX_TIMEOUT) / 1000)); 1170bdcd8170SKalle Valo rxtid->progress = false; 1171bdcd8170SKalle Valo rxtid->timer_mon = true; 1172bdcd8170SKalle Valo break; 1173bdcd8170SKalle Valo } 1174bdcd8170SKalle Valo } 1175bdcd8170SKalle Valo 1176bdcd8170SKalle Valo return is_queued; 1177bdcd8170SKalle Valo } 1178bdcd8170SKalle Valo 1179c1762a3fSThirumalai Pachamuthu static void ath6kl_uapsd_trigger_frame_rx(struct ath6kl_vif *vif, 1180c1762a3fSThirumalai Pachamuthu struct ath6kl_sta *conn) 1181c1762a3fSThirumalai Pachamuthu { 1182c1762a3fSThirumalai Pachamuthu struct ath6kl *ar = vif->ar; 1183c1762a3fSThirumalai Pachamuthu bool is_apsdq_empty, is_apsdq_empty_at_start; 1184c1762a3fSThirumalai Pachamuthu u32 num_frames_to_deliver, flags; 1185c1762a3fSThirumalai Pachamuthu struct sk_buff *skb = NULL; 1186c1762a3fSThirumalai Pachamuthu 1187c1762a3fSThirumalai Pachamuthu /* 1188c1762a3fSThirumalai Pachamuthu * If the APSD q for this STA is not empty, dequeue and 1189c1762a3fSThirumalai Pachamuthu * send a pkt from the head of the q. Also update the 1190c1762a3fSThirumalai Pachamuthu * More data bit in the WMI_DATA_HDR if there are 1191c1762a3fSThirumalai Pachamuthu * more pkts for this STA in the APSD q. 1192c1762a3fSThirumalai Pachamuthu * If there are no more pkts for this STA, 1193c1762a3fSThirumalai Pachamuthu * update the APSD bitmap for this STA. 1194c1762a3fSThirumalai Pachamuthu */ 1195c1762a3fSThirumalai Pachamuthu 1196c1762a3fSThirumalai Pachamuthu num_frames_to_deliver = (conn->apsd_info >> ATH6KL_APSD_NUM_OF_AC) & 1197c1762a3fSThirumalai Pachamuthu ATH6KL_APSD_FRAME_MASK; 1198c1762a3fSThirumalai Pachamuthu /* 1199c1762a3fSThirumalai Pachamuthu * Number of frames to send in a service period is 1200c1762a3fSThirumalai Pachamuthu * indicated by the station 1201c1762a3fSThirumalai Pachamuthu * in the QOS_INFO of the association request 1202c1762a3fSThirumalai Pachamuthu * If it is zero, send all frames 1203c1762a3fSThirumalai Pachamuthu */ 1204c1762a3fSThirumalai Pachamuthu if (!num_frames_to_deliver) 1205c1762a3fSThirumalai Pachamuthu num_frames_to_deliver = ATH6KL_APSD_ALL_FRAME; 1206c1762a3fSThirumalai Pachamuthu 1207c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 1208c1762a3fSThirumalai Pachamuthu is_apsdq_empty = skb_queue_empty(&conn->apsdq); 1209c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 1210c1762a3fSThirumalai Pachamuthu is_apsdq_empty_at_start = is_apsdq_empty; 1211c1762a3fSThirumalai Pachamuthu 1212c1762a3fSThirumalai Pachamuthu while ((!is_apsdq_empty) && (num_frames_to_deliver)) { 1213c1762a3fSThirumalai Pachamuthu 1214c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 1215c1762a3fSThirumalai Pachamuthu skb = skb_dequeue(&conn->apsdq); 1216c1762a3fSThirumalai Pachamuthu is_apsdq_empty = skb_queue_empty(&conn->apsdq); 1217c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 1218c1762a3fSThirumalai Pachamuthu 1219c1762a3fSThirumalai Pachamuthu /* 1220c1762a3fSThirumalai Pachamuthu * Set the STA flag to Trigger delivery, 1221c1762a3fSThirumalai Pachamuthu * so that the frame will go out 1222c1762a3fSThirumalai Pachamuthu */ 1223c1762a3fSThirumalai Pachamuthu conn->sta_flags |= STA_PS_APSD_TRIGGER; 1224c1762a3fSThirumalai Pachamuthu num_frames_to_deliver--; 1225c1762a3fSThirumalai Pachamuthu 1226c1762a3fSThirumalai Pachamuthu /* Last frame in the service period, set EOSP or queue empty */ 1227c1762a3fSThirumalai Pachamuthu if ((is_apsdq_empty) || (!num_frames_to_deliver)) 1228c1762a3fSThirumalai Pachamuthu conn->sta_flags |= STA_PS_APSD_EOSP; 1229c1762a3fSThirumalai Pachamuthu 1230c1762a3fSThirumalai Pachamuthu ath6kl_data_tx(skb, vif->ndev); 1231c1762a3fSThirumalai Pachamuthu conn->sta_flags &= ~(STA_PS_APSD_TRIGGER); 1232c1762a3fSThirumalai Pachamuthu conn->sta_flags &= ~(STA_PS_APSD_EOSP); 1233c1762a3fSThirumalai Pachamuthu } 1234c1762a3fSThirumalai Pachamuthu 1235c1762a3fSThirumalai Pachamuthu if (is_apsdq_empty) { 1236c1762a3fSThirumalai Pachamuthu if (is_apsdq_empty_at_start) 1237c1762a3fSThirumalai Pachamuthu flags = WMI_AP_APSD_NO_DELIVERY_FRAMES; 1238c1762a3fSThirumalai Pachamuthu else 1239c1762a3fSThirumalai Pachamuthu flags = 0; 1240c1762a3fSThirumalai Pachamuthu 1241c1762a3fSThirumalai Pachamuthu ath6kl_wmi_set_apsd_bfrd_traf(ar->wmi, 1242c1762a3fSThirumalai Pachamuthu vif->fw_vif_idx, 1243c1762a3fSThirumalai Pachamuthu conn->aid, 0, flags); 1244c1762a3fSThirumalai Pachamuthu } 1245c1762a3fSThirumalai Pachamuthu 1246c1762a3fSThirumalai Pachamuthu return; 1247c1762a3fSThirumalai Pachamuthu } 1248c1762a3fSThirumalai Pachamuthu 1249bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet) 1250bdcd8170SKalle Valo { 1251bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 1252bdcd8170SKalle Valo struct sk_buff *skb = packet->pkt_cntxt; 1253bdcd8170SKalle Valo struct wmi_rx_meta_v2 *meta; 1254bdcd8170SKalle Valo struct wmi_data_hdr *dhdr; 1255bdcd8170SKalle Valo int min_hdr_len; 1256bdcd8170SKalle Valo u8 meta_type, dot11_hdr = 0; 1257bdcd8170SKalle Valo int status = packet->status; 1258bdcd8170SKalle Valo enum htc_endpoint_id ept = packet->endpoint; 1259bdcd8170SKalle Valo bool is_amsdu, prev_ps, ps_state = false; 1260c1762a3fSThirumalai Pachamuthu bool trig_state = false; 1261bdcd8170SKalle Valo struct ath6kl_sta *conn = NULL; 1262bdcd8170SKalle Valo struct sk_buff *skb1 = NULL; 1263bdcd8170SKalle Valo struct ethhdr *datap = NULL; 12646765d0aaSVasanthakumar Thiagarajan struct ath6kl_vif *vif; 1265bdcd8170SKalle Valo u16 seq_no, offset; 12666765d0aaSVasanthakumar Thiagarajan u8 tid, if_idx; 1267bdcd8170SKalle Valo 1268bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, 1269bdcd8170SKalle Valo "%s: ar=0x%p eid=%d, skb=0x%p, data=0x%p, len=0x%x status:%d", 1270bdcd8170SKalle Valo __func__, ar, ept, skb, packet->buf, 1271bdcd8170SKalle Valo packet->act_len, status); 1272bdcd8170SKalle Valo 1273bdcd8170SKalle Valo if (status || !(skb->data + HTC_HDR_LENGTH)) { 12746765d0aaSVasanthakumar Thiagarajan dev_kfree_skb(skb); 12756765d0aaSVasanthakumar Thiagarajan return; 12766765d0aaSVasanthakumar Thiagarajan } 12776765d0aaSVasanthakumar Thiagarajan 12786765d0aaSVasanthakumar Thiagarajan skb_put(skb, packet->act_len + HTC_HDR_LENGTH); 12796765d0aaSVasanthakumar Thiagarajan skb_pull(skb, HTC_HDR_LENGTH); 12806765d0aaSVasanthakumar Thiagarajan 12816765d0aaSVasanthakumar Thiagarajan if (ept == ar->ctrl_ep) { 12826765d0aaSVasanthakumar Thiagarajan if_idx = 12836765d0aaSVasanthakumar Thiagarajan wmi_cmd_hdr_get_if_idx((struct wmi_cmd_hdr *) skb->data); 12846765d0aaSVasanthakumar Thiagarajan } else { 12856765d0aaSVasanthakumar Thiagarajan if_idx = 12866765d0aaSVasanthakumar Thiagarajan wmi_data_hdr_get_if_idx((struct wmi_data_hdr *) skb->data); 12876765d0aaSVasanthakumar Thiagarajan } 12886765d0aaSVasanthakumar Thiagarajan 12896765d0aaSVasanthakumar Thiagarajan vif = ath6kl_get_vif_by_index(ar, if_idx); 12906765d0aaSVasanthakumar Thiagarajan if (!vif) { 1291bdcd8170SKalle Valo dev_kfree_skb(skb); 1292bdcd8170SKalle Valo return; 1293bdcd8170SKalle Valo } 1294bdcd8170SKalle Valo 1295bdcd8170SKalle Valo /* 1296bdcd8170SKalle Valo * Take lock to protect buffer counts and adaptive power throughput 1297bdcd8170SKalle Valo * state. 1298bdcd8170SKalle Valo */ 1299478ac027SVasanthakumar Thiagarajan spin_lock_bh(&vif->if_lock); 1300bdcd8170SKalle Valo 1301b95907a7SVasanthakumar Thiagarajan vif->net_stats.rx_packets++; 1302b95907a7SVasanthakumar Thiagarajan vif->net_stats.rx_bytes += packet->act_len; 1303bdcd8170SKalle Valo 1304478ac027SVasanthakumar Thiagarajan spin_unlock_bh(&vif->if_lock); 130583dc5f2fSVasanthakumar Thiagarajan 1306bdcd8170SKalle Valo 1307ef094103SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_RAW_BYTES, __func__, "rx ", 1308ef094103SKalle Valo skb->data, skb->len); 1309bdcd8170SKalle Valo 131028ae58ddSVasanthakumar Thiagarajan skb->dev = vif->ndev; 1311bdcd8170SKalle Valo 1312bdcd8170SKalle Valo if (!test_bit(WMI_ENABLED, &ar->flag)) { 1313bdcd8170SKalle Valo if (EPPING_ALIGNMENT_PAD > 0) 1314bdcd8170SKalle Valo skb_pull(skb, EPPING_ALIGNMENT_PAD); 131528ae58ddSVasanthakumar Thiagarajan ath6kl_deliver_frames_to_nw_stack(vif->ndev, skb); 1316bdcd8170SKalle Valo return; 1317bdcd8170SKalle Valo } 1318bdcd8170SKalle Valo 1319a918fb3cSRaja Mani ath6kl_check_wow_status(ar); 1320a918fb3cSRaja Mani 1321bdcd8170SKalle Valo if (ept == ar->ctrl_ep) { 1322bdcd8170SKalle Valo ath6kl_wmi_control_rx(ar->wmi, skb); 1323bdcd8170SKalle Valo return; 1324bdcd8170SKalle Valo } 1325bdcd8170SKalle Valo 132667f9178fSVasanthakumar Thiagarajan min_hdr_len = sizeof(struct ethhdr) + sizeof(struct wmi_data_hdr) + 1327bdcd8170SKalle Valo sizeof(struct ath6kl_llc_snap_hdr); 1328bdcd8170SKalle Valo 1329bdcd8170SKalle Valo dhdr = (struct wmi_data_hdr *) skb->data; 1330bdcd8170SKalle Valo 1331bdcd8170SKalle Valo /* 1332bdcd8170SKalle Valo * In the case of AP mode we may receive NULL data frames 1333bdcd8170SKalle Valo * that do not have LLC hdr. They are 16 bytes in size. 1334bdcd8170SKalle Valo * Allow these frames in the AP mode. 1335bdcd8170SKalle Valo */ 1336f5938f24SVasanthakumar Thiagarajan if (vif->nw_type != AP_NETWORK && 1337bdcd8170SKalle Valo ((packet->act_len < min_hdr_len) || 1338bdcd8170SKalle Valo (packet->act_len > WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH))) { 1339bdcd8170SKalle Valo ath6kl_info("frame len is too short or too long\n"); 1340b95907a7SVasanthakumar Thiagarajan vif->net_stats.rx_errors++; 1341b95907a7SVasanthakumar Thiagarajan vif->net_stats.rx_length_errors++; 1342bdcd8170SKalle Valo dev_kfree_skb(skb); 1343bdcd8170SKalle Valo return; 1344bdcd8170SKalle Valo } 1345bdcd8170SKalle Valo 1346bdcd8170SKalle Valo /* Get the Power save state of the STA */ 1347f5938f24SVasanthakumar Thiagarajan if (vif->nw_type == AP_NETWORK) { 1348bdcd8170SKalle Valo meta_type = wmi_data_hdr_get_meta(dhdr); 1349bdcd8170SKalle Valo 1350bdcd8170SKalle Valo ps_state = !!((dhdr->info >> WMI_DATA_HDR_PS_SHIFT) & 1351bdcd8170SKalle Valo WMI_DATA_HDR_PS_MASK); 1352bdcd8170SKalle Valo 1353bdcd8170SKalle Valo offset = sizeof(struct wmi_data_hdr); 1354c1762a3fSThirumalai Pachamuthu trig_state = !!(le16_to_cpu(dhdr->info3) & WMI_DATA_HDR_TRIG); 1355bdcd8170SKalle Valo 1356bdcd8170SKalle Valo switch (meta_type) { 1357bdcd8170SKalle Valo case 0: 1358bdcd8170SKalle Valo break; 1359bdcd8170SKalle Valo case WMI_META_VERSION_1: 1360bdcd8170SKalle Valo offset += sizeof(struct wmi_rx_meta_v1); 1361bdcd8170SKalle Valo break; 1362bdcd8170SKalle Valo case WMI_META_VERSION_2: 1363bdcd8170SKalle Valo offset += sizeof(struct wmi_rx_meta_v2); 1364bdcd8170SKalle Valo break; 1365bdcd8170SKalle Valo default: 1366bdcd8170SKalle Valo break; 1367bdcd8170SKalle Valo } 1368bdcd8170SKalle Valo 1369bdcd8170SKalle Valo datap = (struct ethhdr *) (skb->data + offset); 13706765d0aaSVasanthakumar Thiagarajan conn = ath6kl_find_sta(vif, datap->h_source); 1371bdcd8170SKalle Valo 1372bdcd8170SKalle Valo if (!conn) { 1373bdcd8170SKalle Valo dev_kfree_skb(skb); 1374bdcd8170SKalle Valo return; 1375bdcd8170SKalle Valo } 1376bdcd8170SKalle Valo 1377bdcd8170SKalle Valo /* 1378bdcd8170SKalle Valo * If there is a change in PS state of the STA, 1379bdcd8170SKalle Valo * take appropriate steps: 1380bdcd8170SKalle Valo * 1381bdcd8170SKalle Valo * 1. If Sleep-->Awake, flush the psq for the STA 1382bdcd8170SKalle Valo * Clear the PVB for the STA. 1383bdcd8170SKalle Valo * 2. If Awake-->Sleep, Starting queueing frames 1384bdcd8170SKalle Valo * the STA. 1385bdcd8170SKalle Valo */ 1386bdcd8170SKalle Valo prev_ps = !!(conn->sta_flags & STA_PS_SLEEP); 1387bdcd8170SKalle Valo 1388bdcd8170SKalle Valo if (ps_state) 1389bdcd8170SKalle Valo conn->sta_flags |= STA_PS_SLEEP; 1390bdcd8170SKalle Valo else 1391bdcd8170SKalle Valo conn->sta_flags &= ~STA_PS_SLEEP; 1392bdcd8170SKalle Valo 1393c1762a3fSThirumalai Pachamuthu /* Accept trigger only when the station is in sleep */ 1394c1762a3fSThirumalai Pachamuthu if ((conn->sta_flags & STA_PS_SLEEP) && trig_state) 1395c1762a3fSThirumalai Pachamuthu ath6kl_uapsd_trigger_frame_rx(vif, conn); 1396c1762a3fSThirumalai Pachamuthu 1397bdcd8170SKalle Valo if (prev_ps ^ !!(conn->sta_flags & STA_PS_SLEEP)) { 1398bdcd8170SKalle Valo if (!(conn->sta_flags & STA_PS_SLEEP)) { 1399bdcd8170SKalle Valo struct sk_buff *skbuff = NULL; 1400c1762a3fSThirumalai Pachamuthu bool is_apsdq_empty; 1401bdcd8170SKalle Valo 1402bdcd8170SKalle Valo spin_lock_bh(&conn->psq_lock); 1403c1762a3fSThirumalai Pachamuthu while ((skbuff = skb_dequeue(&conn->psq))) { 1404c1762a3fSThirumalai Pachamuthu spin_unlock_bh(&conn->psq_lock); 1405c1762a3fSThirumalai Pachamuthu ath6kl_data_tx(skbuff, vif->ndev); 1406c1762a3fSThirumalai Pachamuthu spin_lock_bh(&conn->psq_lock); 1407c1762a3fSThirumalai Pachamuthu } 1408c1762a3fSThirumalai Pachamuthu 1409c1762a3fSThirumalai Pachamuthu is_apsdq_empty = skb_queue_empty(&conn->apsdq); 1410c1762a3fSThirumalai Pachamuthu while ((skbuff = skb_dequeue(&conn->apsdq))) { 1411bdcd8170SKalle Valo spin_unlock_bh(&conn->psq_lock); 141228ae58ddSVasanthakumar Thiagarajan ath6kl_data_tx(skbuff, vif->ndev); 1413bdcd8170SKalle Valo spin_lock_bh(&conn->psq_lock); 1414bdcd8170SKalle Valo } 1415bdcd8170SKalle Valo spin_unlock_bh(&conn->psq_lock); 1416c1762a3fSThirumalai Pachamuthu 1417c1762a3fSThirumalai Pachamuthu if (!is_apsdq_empty) 1418c1762a3fSThirumalai Pachamuthu ath6kl_wmi_set_apsd_bfrd_traf( 1419c1762a3fSThirumalai Pachamuthu ar->wmi, 1420c1762a3fSThirumalai Pachamuthu vif->fw_vif_idx, 1421c1762a3fSThirumalai Pachamuthu conn->aid, 0, 0); 1422c1762a3fSThirumalai Pachamuthu 1423bdcd8170SKalle Valo /* Clear the PVB for this STA */ 1424334234b5SVasanthakumar Thiagarajan ath6kl_wmi_set_pvb_cmd(ar->wmi, vif->fw_vif_idx, 1425334234b5SVasanthakumar Thiagarajan conn->aid, 0); 1426bdcd8170SKalle Valo } 1427bdcd8170SKalle Valo } 1428bdcd8170SKalle Valo 1429bdcd8170SKalle Valo /* drop NULL data frames here */ 1430bdcd8170SKalle Valo if ((packet->act_len < min_hdr_len) || 1431bdcd8170SKalle Valo (packet->act_len > 1432bdcd8170SKalle Valo WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH)) { 1433bdcd8170SKalle Valo dev_kfree_skb(skb); 1434bdcd8170SKalle Valo return; 1435bdcd8170SKalle Valo } 1436bdcd8170SKalle Valo } 1437bdcd8170SKalle Valo 1438bdcd8170SKalle Valo is_amsdu = wmi_data_hdr_is_amsdu(dhdr) ? true : false; 1439bdcd8170SKalle Valo tid = wmi_data_hdr_get_up(dhdr); 1440bdcd8170SKalle Valo seq_no = wmi_data_hdr_get_seqno(dhdr); 1441bdcd8170SKalle Valo meta_type = wmi_data_hdr_get_meta(dhdr); 1442bdcd8170SKalle Valo dot11_hdr = wmi_data_hdr_get_dot11(dhdr); 1443594a0bc8SVasanthakumar Thiagarajan skb_pull(skb, sizeof(struct wmi_data_hdr)); 1444bdcd8170SKalle Valo 1445bdcd8170SKalle Valo switch (meta_type) { 1446bdcd8170SKalle Valo case WMI_META_VERSION_1: 1447bdcd8170SKalle Valo skb_pull(skb, sizeof(struct wmi_rx_meta_v1)); 1448bdcd8170SKalle Valo break; 1449bdcd8170SKalle Valo case WMI_META_VERSION_2: 1450bdcd8170SKalle Valo meta = (struct wmi_rx_meta_v2 *) skb->data; 1451bdcd8170SKalle Valo if (meta->csum_flags & 0x1) { 1452bdcd8170SKalle Valo skb->ip_summed = CHECKSUM_COMPLETE; 1453bdcd8170SKalle Valo skb->csum = (__force __wsum) meta->csum; 1454bdcd8170SKalle Valo } 1455bdcd8170SKalle Valo skb_pull(skb, sizeof(struct wmi_rx_meta_v2)); 1456bdcd8170SKalle Valo break; 1457bdcd8170SKalle Valo default: 1458bdcd8170SKalle Valo break; 1459bdcd8170SKalle Valo } 1460bdcd8170SKalle Valo 1461bdcd8170SKalle Valo if (dot11_hdr) 1462bdcd8170SKalle Valo status = ath6kl_wmi_dot11_hdr_remove(ar->wmi, skb); 1463bdcd8170SKalle Valo else if (!is_amsdu) 1464bdcd8170SKalle Valo status = ath6kl_wmi_dot3_2_dix(skb); 1465bdcd8170SKalle Valo 1466bdcd8170SKalle Valo if (status) { 1467bdcd8170SKalle Valo /* 1468bdcd8170SKalle Valo * Drop frames that could not be processed (lack of 1469bdcd8170SKalle Valo * memory, etc.) 1470bdcd8170SKalle Valo */ 1471bdcd8170SKalle Valo dev_kfree_skb(skb); 1472bdcd8170SKalle Valo return; 1473bdcd8170SKalle Valo } 1474bdcd8170SKalle Valo 147528ae58ddSVasanthakumar Thiagarajan if (!(vif->ndev->flags & IFF_UP)) { 1476bdcd8170SKalle Valo dev_kfree_skb(skb); 1477bdcd8170SKalle Valo return; 1478bdcd8170SKalle Valo } 1479bdcd8170SKalle Valo 1480f5938f24SVasanthakumar Thiagarajan if (vif->nw_type == AP_NETWORK) { 1481bdcd8170SKalle Valo datap = (struct ethhdr *) skb->data; 1482bdcd8170SKalle Valo if (is_multicast_ether_addr(datap->h_dest)) 1483bdcd8170SKalle Valo /* 1484bdcd8170SKalle Valo * Bcast/Mcast frames should be sent to the 1485bdcd8170SKalle Valo * OS stack as well as on the air. 1486bdcd8170SKalle Valo */ 1487bdcd8170SKalle Valo skb1 = skb_copy(skb, GFP_ATOMIC); 1488bdcd8170SKalle Valo else { 1489bdcd8170SKalle Valo /* 1490bdcd8170SKalle Valo * Search for a connected STA with dstMac 1491bdcd8170SKalle Valo * as the Mac address. If found send the 1492bdcd8170SKalle Valo * frame to it on the air else send the 1493bdcd8170SKalle Valo * frame up the stack. 1494bdcd8170SKalle Valo */ 14956765d0aaSVasanthakumar Thiagarajan conn = ath6kl_find_sta(vif, datap->h_dest); 1496bdcd8170SKalle Valo 1497bdcd8170SKalle Valo if (conn && ar->intra_bss) { 1498bdcd8170SKalle Valo skb1 = skb; 1499bdcd8170SKalle Valo skb = NULL; 1500bdcd8170SKalle Valo } else if (conn && !ar->intra_bss) { 1501bdcd8170SKalle Valo dev_kfree_skb(skb); 1502bdcd8170SKalle Valo skb = NULL; 1503bdcd8170SKalle Valo } 1504bdcd8170SKalle Valo } 1505bdcd8170SKalle Valo if (skb1) 150628ae58ddSVasanthakumar Thiagarajan ath6kl_data_tx(skb1, vif->ndev); 1507ad3f78b9SKalle Valo 1508ad3f78b9SKalle Valo if (skb == NULL) { 1509ad3f78b9SKalle Valo /* nothing to deliver up the stack */ 1510ad3f78b9SKalle Valo return; 1511ad3f78b9SKalle Valo } 1512bdcd8170SKalle Valo } 1513bdcd8170SKalle Valo 15145694f962SKalle Valo datap = (struct ethhdr *) skb->data; 15155694f962SKalle Valo 15165694f962SKalle Valo if (is_unicast_ether_addr(datap->h_dest) && 15172132c69cSVasanthakumar Thiagarajan aggr_process_recv_frm(vif->aggr_cntxt, tid, seq_no, 1518bdcd8170SKalle Valo is_amsdu, skb)) 15195694f962SKalle Valo /* aggregation code will handle the skb */ 15205694f962SKalle Valo return; 15215694f962SKalle Valo 152228ae58ddSVasanthakumar Thiagarajan ath6kl_deliver_frames_to_nw_stack(vif->ndev, skb); 1523bdcd8170SKalle Valo } 1524bdcd8170SKalle Valo 1525bdcd8170SKalle Valo static void aggr_timeout(unsigned long arg) 1526bdcd8170SKalle Valo { 1527bdcd8170SKalle Valo u8 i, j; 1528bdcd8170SKalle Valo struct aggr_info *p_aggr = (struct aggr_info *) arg; 1529bdcd8170SKalle Valo struct rxtid *rxtid; 1530bdcd8170SKalle Valo struct rxtid_stats *stats; 1531bdcd8170SKalle Valo 1532bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1533bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[i]; 1534bdcd8170SKalle Valo stats = &p_aggr->stat[i]; 1535bdcd8170SKalle Valo 1536bdcd8170SKalle Valo if (!rxtid->aggr || !rxtid->timer_mon || rxtid->progress) 1537bdcd8170SKalle Valo continue; 1538bdcd8170SKalle Valo 1539bdcd8170SKalle Valo stats->num_timeouts++; 154037ca6335SKalle Valo ath6kl_dbg(ATH6KL_DBG_AGGR, 154137ca6335SKalle Valo "aggr timeout (st %d end %d)\n", 1542bdcd8170SKalle Valo rxtid->seq_next, 1543bdcd8170SKalle Valo ((rxtid->seq_next + rxtid->hold_q_sz-1) & 1544bdcd8170SKalle Valo ATH6KL_MAX_SEQ_NO)); 1545bdcd8170SKalle Valo aggr_deque_frms(p_aggr, i, 0, 0); 1546bdcd8170SKalle Valo } 1547bdcd8170SKalle Valo 1548bdcd8170SKalle Valo p_aggr->timer_scheduled = false; 1549bdcd8170SKalle Valo 1550bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1551bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[i]; 1552bdcd8170SKalle Valo 1553bdcd8170SKalle Valo if (rxtid->aggr && rxtid->hold_q) { 1554bdcd8170SKalle Valo for (j = 0; j < rxtid->hold_q_sz; j++) { 1555bdcd8170SKalle Valo if (rxtid->hold_q[j].skb) { 1556bdcd8170SKalle Valo p_aggr->timer_scheduled = true; 1557bdcd8170SKalle Valo rxtid->timer_mon = true; 1558bdcd8170SKalle Valo rxtid->progress = false; 1559bdcd8170SKalle Valo break; 1560bdcd8170SKalle Valo } 1561bdcd8170SKalle Valo } 1562bdcd8170SKalle Valo 1563bdcd8170SKalle Valo if (j >= rxtid->hold_q_sz) 1564bdcd8170SKalle Valo rxtid->timer_mon = false; 1565bdcd8170SKalle Valo } 1566bdcd8170SKalle Valo } 1567bdcd8170SKalle Valo 1568bdcd8170SKalle Valo if (p_aggr->timer_scheduled) 1569bdcd8170SKalle Valo mod_timer(&p_aggr->timer, 1570bdcd8170SKalle Valo jiffies + msecs_to_jiffies(AGGR_RX_TIMEOUT)); 1571bdcd8170SKalle Valo } 1572bdcd8170SKalle Valo 1573bdcd8170SKalle Valo static void aggr_delete_tid_state(struct aggr_info *p_aggr, u8 tid) 1574bdcd8170SKalle Valo { 1575bdcd8170SKalle Valo struct rxtid *rxtid; 1576bdcd8170SKalle Valo struct rxtid_stats *stats; 1577bdcd8170SKalle Valo 1578bdcd8170SKalle Valo if (!p_aggr || tid >= NUM_OF_TIDS) 1579bdcd8170SKalle Valo return; 1580bdcd8170SKalle Valo 1581bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1582bdcd8170SKalle Valo stats = &p_aggr->stat[tid]; 1583bdcd8170SKalle Valo 1584bdcd8170SKalle Valo if (rxtid->aggr) 1585bdcd8170SKalle Valo aggr_deque_frms(p_aggr, tid, 0, 0); 1586bdcd8170SKalle Valo 1587bdcd8170SKalle Valo rxtid->aggr = false; 1588bdcd8170SKalle Valo rxtid->progress = false; 1589bdcd8170SKalle Valo rxtid->timer_mon = false; 1590bdcd8170SKalle Valo rxtid->win_sz = 0; 1591bdcd8170SKalle Valo rxtid->seq_next = 0; 1592bdcd8170SKalle Valo rxtid->hold_q_sz = 0; 1593bdcd8170SKalle Valo 1594bdcd8170SKalle Valo kfree(rxtid->hold_q); 1595bdcd8170SKalle Valo rxtid->hold_q = NULL; 1596bdcd8170SKalle Valo 1597bdcd8170SKalle Valo memset(stats, 0, sizeof(struct rxtid_stats)); 1598bdcd8170SKalle Valo } 1599bdcd8170SKalle Valo 1600240d2799SVasanthakumar Thiagarajan void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no, 1601240d2799SVasanthakumar Thiagarajan u8 win_sz) 1602bdcd8170SKalle Valo { 16032132c69cSVasanthakumar Thiagarajan struct aggr_info *p_aggr = vif->aggr_cntxt; 1604bdcd8170SKalle Valo struct rxtid *rxtid; 1605bdcd8170SKalle Valo struct rxtid_stats *stats; 1606bdcd8170SKalle Valo u16 hold_q_size; 1607bdcd8170SKalle Valo 1608bdcd8170SKalle Valo if (!p_aggr) 1609bdcd8170SKalle Valo return; 1610bdcd8170SKalle Valo 1611bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1612bdcd8170SKalle Valo stats = &p_aggr->stat[tid]; 1613bdcd8170SKalle Valo 1614bdcd8170SKalle Valo if (win_sz < AGGR_WIN_SZ_MIN || win_sz > AGGR_WIN_SZ_MAX) 1615bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, "%s: win_sz %d, tid %d\n", 1616bdcd8170SKalle Valo __func__, win_sz, tid); 1617bdcd8170SKalle Valo 1618bdcd8170SKalle Valo if (rxtid->aggr) 1619bdcd8170SKalle Valo aggr_delete_tid_state(p_aggr, tid); 1620bdcd8170SKalle Valo 1621bdcd8170SKalle Valo rxtid->seq_next = seq_no; 1622bdcd8170SKalle Valo hold_q_size = TID_WINDOW_SZ(win_sz) * sizeof(struct skb_hold_q); 1623bdcd8170SKalle Valo rxtid->hold_q = kzalloc(hold_q_size, GFP_KERNEL); 1624bdcd8170SKalle Valo if (!rxtid->hold_q) 1625bdcd8170SKalle Valo return; 1626bdcd8170SKalle Valo 1627bdcd8170SKalle Valo rxtid->win_sz = win_sz; 1628bdcd8170SKalle Valo rxtid->hold_q_sz = TID_WINDOW_SZ(win_sz); 1629bdcd8170SKalle Valo if (!skb_queue_empty(&rxtid->q)) 1630bdcd8170SKalle Valo return; 1631bdcd8170SKalle Valo 1632bdcd8170SKalle Valo rxtid->aggr = true; 1633bdcd8170SKalle Valo } 1634bdcd8170SKalle Valo 1635bdcd8170SKalle Valo struct aggr_info *aggr_init(struct net_device *dev) 1636bdcd8170SKalle Valo { 1637bdcd8170SKalle Valo struct aggr_info *p_aggr = NULL; 1638bdcd8170SKalle Valo struct rxtid *rxtid; 1639bdcd8170SKalle Valo u8 i; 1640bdcd8170SKalle Valo 1641bdcd8170SKalle Valo p_aggr = kzalloc(sizeof(struct aggr_info), GFP_KERNEL); 1642bdcd8170SKalle Valo if (!p_aggr) { 1643bdcd8170SKalle Valo ath6kl_err("failed to alloc memory for aggr_node\n"); 1644bdcd8170SKalle Valo return NULL; 1645bdcd8170SKalle Valo } 1646bdcd8170SKalle Valo 1647bdcd8170SKalle Valo p_aggr->aggr_sz = AGGR_SZ_DEFAULT; 1648bdcd8170SKalle Valo p_aggr->dev = dev; 1649bdcd8170SKalle Valo init_timer(&p_aggr->timer); 1650bdcd8170SKalle Valo p_aggr->timer.function = aggr_timeout; 1651bdcd8170SKalle Valo p_aggr->timer.data = (unsigned long) p_aggr; 1652bdcd8170SKalle Valo 1653bdcd8170SKalle Valo p_aggr->timer_scheduled = false; 1654bdcd8170SKalle Valo skb_queue_head_init(&p_aggr->free_q); 1655bdcd8170SKalle Valo 1656bdcd8170SKalle Valo ath6kl_alloc_netbufs(&p_aggr->free_q, AGGR_NUM_OF_FREE_NETBUFS); 1657bdcd8170SKalle Valo 1658bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1659bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[i]; 1660bdcd8170SKalle Valo rxtid->aggr = false; 1661bdcd8170SKalle Valo rxtid->progress = false; 1662bdcd8170SKalle Valo rxtid->timer_mon = false; 1663bdcd8170SKalle Valo skb_queue_head_init(&rxtid->q); 1664bdcd8170SKalle Valo spin_lock_init(&rxtid->lock); 1665bdcd8170SKalle Valo } 1666bdcd8170SKalle Valo 1667bdcd8170SKalle Valo return p_aggr; 1668bdcd8170SKalle Valo } 1669bdcd8170SKalle Valo 1670240d2799SVasanthakumar Thiagarajan void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid) 1671bdcd8170SKalle Valo { 16722132c69cSVasanthakumar Thiagarajan struct aggr_info *p_aggr = vif->aggr_cntxt; 1673bdcd8170SKalle Valo struct rxtid *rxtid; 1674bdcd8170SKalle Valo 1675bdcd8170SKalle Valo if (!p_aggr) 1676bdcd8170SKalle Valo return; 1677bdcd8170SKalle Valo 1678bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1679bdcd8170SKalle Valo 1680bdcd8170SKalle Valo if (rxtid->aggr) 1681bdcd8170SKalle Valo aggr_delete_tid_state(p_aggr, tid); 1682bdcd8170SKalle Valo } 1683bdcd8170SKalle Valo 1684bdcd8170SKalle Valo void aggr_reset_state(struct aggr_info *aggr_info) 1685bdcd8170SKalle Valo { 1686bdcd8170SKalle Valo u8 tid; 1687bdcd8170SKalle Valo 1688*7a950ea8SVasanthakumar Thiagarajan if (aggr_info->timer_scheduled) { 1689*7a950ea8SVasanthakumar Thiagarajan del_timer(&aggr_info->timer); 1690*7a950ea8SVasanthakumar Thiagarajan aggr_info->timer_scheduled = false; 1691*7a950ea8SVasanthakumar Thiagarajan } 1692*7a950ea8SVasanthakumar Thiagarajan 1693bdcd8170SKalle Valo for (tid = 0; tid < NUM_OF_TIDS; tid++) 1694bdcd8170SKalle Valo aggr_delete_tid_state(aggr_info, tid); 1695bdcd8170SKalle Valo } 1696bdcd8170SKalle Valo 1697bdcd8170SKalle Valo /* clean up our amsdu buffer list */ 1698bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar) 1699bdcd8170SKalle Valo { 1700bdcd8170SKalle Valo struct htc_packet *packet, *tmp_pkt; 1701bdcd8170SKalle Valo 1702bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 1703bdcd8170SKalle Valo if (list_empty(&ar->amsdu_rx_buffer_queue)) { 1704bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 1705bdcd8170SKalle Valo return; 1706bdcd8170SKalle Valo } 1707bdcd8170SKalle Valo 1708bdcd8170SKalle Valo list_for_each_entry_safe(packet, tmp_pkt, &ar->amsdu_rx_buffer_queue, 1709bdcd8170SKalle Valo list) { 1710bdcd8170SKalle Valo list_del(&packet->list); 1711bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 1712bdcd8170SKalle Valo dev_kfree_skb(packet->pkt_cntxt); 1713bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 1714bdcd8170SKalle Valo } 1715bdcd8170SKalle Valo 1716bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 1717bdcd8170SKalle Valo } 1718bdcd8170SKalle Valo 1719bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info) 1720bdcd8170SKalle Valo { 1721bdcd8170SKalle Valo struct rxtid *rxtid; 1722bdcd8170SKalle Valo u8 i, k; 1723bdcd8170SKalle Valo 1724bdcd8170SKalle Valo if (!aggr_info) 1725bdcd8170SKalle Valo return; 1726bdcd8170SKalle Valo 1727bdcd8170SKalle Valo if (aggr_info->timer_scheduled) { 1728bdcd8170SKalle Valo del_timer(&aggr_info->timer); 1729bdcd8170SKalle Valo aggr_info->timer_scheduled = false; 1730bdcd8170SKalle Valo } 1731bdcd8170SKalle Valo 1732bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1733bdcd8170SKalle Valo rxtid = &aggr_info->rx_tid[i]; 1734bdcd8170SKalle Valo if (rxtid->hold_q) { 1735bdcd8170SKalle Valo for (k = 0; k < rxtid->hold_q_sz; k++) 1736bdcd8170SKalle Valo dev_kfree_skb(rxtid->hold_q[k].skb); 1737bdcd8170SKalle Valo kfree(rxtid->hold_q); 1738bdcd8170SKalle Valo } 1739bdcd8170SKalle Valo 1740bdcd8170SKalle Valo skb_queue_purge(&rxtid->q); 1741bdcd8170SKalle Valo } 1742bdcd8170SKalle Valo 1743bdcd8170SKalle Valo skb_queue_purge(&aggr_info->free_q); 1744bdcd8170SKalle Valo kfree(aggr_info); 1745bdcd8170SKalle Valo } 1746