xref: /openbmc/linux/drivers/net/wireless/ath/ath6kl/txrx.c (revision 5694f962964c5162f6b49ddb5d517180bd7d1d98)
1bdcd8170SKalle Valo /*
2bdcd8170SKalle Valo  * Copyright (c) 2004-2011 Atheros Communications Inc.
3bdcd8170SKalle Valo  *
4bdcd8170SKalle Valo  * Permission to use, copy, modify, and/or distribute this software for any
5bdcd8170SKalle Valo  * purpose with or without fee is hereby granted, provided that the above
6bdcd8170SKalle Valo  * copyright notice and this permission notice appear in all copies.
7bdcd8170SKalle Valo  *
8bdcd8170SKalle Valo  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9bdcd8170SKalle Valo  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10bdcd8170SKalle Valo  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11bdcd8170SKalle Valo  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12bdcd8170SKalle Valo  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13bdcd8170SKalle Valo  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14bdcd8170SKalle Valo  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15bdcd8170SKalle Valo  */
16bdcd8170SKalle Valo 
17bdcd8170SKalle Valo #include "core.h"
18bdcd8170SKalle Valo #include "debug.h"
19bdcd8170SKalle Valo 
20bdcd8170SKalle Valo static u8 ath6kl_ibss_map_epid(struct sk_buff *skb, struct net_device *dev,
21bdcd8170SKalle Valo 			       u32 *map_no)
22bdcd8170SKalle Valo {
23bdcd8170SKalle Valo 	struct ath6kl *ar = ath6kl_priv(dev);
24bdcd8170SKalle Valo 	struct ethhdr *eth_hdr;
25bdcd8170SKalle Valo 	u32 i, ep_map = -1;
26bdcd8170SKalle Valo 	u8 *datap;
27bdcd8170SKalle Valo 
28bdcd8170SKalle Valo 	*map_no = 0;
29bdcd8170SKalle Valo 	datap = skb->data;
30bdcd8170SKalle Valo 	eth_hdr = (struct ethhdr *) (datap + sizeof(struct wmi_data_hdr));
31bdcd8170SKalle Valo 
32bdcd8170SKalle Valo 	if (is_multicast_ether_addr(eth_hdr->h_dest))
33bdcd8170SKalle Valo 		return ENDPOINT_2;
34bdcd8170SKalle Valo 
35bdcd8170SKalle Valo 	for (i = 0; i < ar->node_num; i++) {
36bdcd8170SKalle Valo 		if (memcmp(eth_hdr->h_dest, ar->node_map[i].mac_addr,
37bdcd8170SKalle Valo 			   ETH_ALEN) == 0) {
38bdcd8170SKalle Valo 			*map_no = i + 1;
39bdcd8170SKalle Valo 			ar->node_map[i].tx_pend++;
40bdcd8170SKalle Valo 			return ar->node_map[i].ep_id;
41bdcd8170SKalle Valo 		}
42bdcd8170SKalle Valo 
43bdcd8170SKalle Valo 		if ((ep_map == -1) && !ar->node_map[i].tx_pend)
44bdcd8170SKalle Valo 			ep_map = i;
45bdcd8170SKalle Valo 	}
46bdcd8170SKalle Valo 
47bdcd8170SKalle Valo 	if (ep_map == -1) {
48bdcd8170SKalle Valo 		ep_map = ar->node_num;
49bdcd8170SKalle Valo 		ar->node_num++;
50bdcd8170SKalle Valo 		if (ar->node_num > MAX_NODE_NUM)
51bdcd8170SKalle Valo 			return ENDPOINT_UNUSED;
52bdcd8170SKalle Valo 	}
53bdcd8170SKalle Valo 
54bdcd8170SKalle Valo 	memcpy(ar->node_map[ep_map].mac_addr, eth_hdr->h_dest, ETH_ALEN);
55bdcd8170SKalle Valo 
56bdcd8170SKalle Valo 	for (i = ENDPOINT_2; i <= ENDPOINT_5; i++) {
57bdcd8170SKalle Valo 		if (!ar->tx_pending[i]) {
58bdcd8170SKalle Valo 			ar->node_map[ep_map].ep_id = i;
59bdcd8170SKalle Valo 			break;
60bdcd8170SKalle Valo 		}
61bdcd8170SKalle Valo 
62bdcd8170SKalle Valo 		/*
63bdcd8170SKalle Valo 		 * No free endpoint is available, start redistribution on
64bdcd8170SKalle Valo 		 * the inuse endpoints.
65bdcd8170SKalle Valo 		 */
66bdcd8170SKalle Valo 		if (i == ENDPOINT_5) {
67bdcd8170SKalle Valo 			ar->node_map[ep_map].ep_id = ar->next_ep_id;
68bdcd8170SKalle Valo 			ar->next_ep_id++;
69bdcd8170SKalle Valo 			if (ar->next_ep_id > ENDPOINT_5)
70bdcd8170SKalle Valo 				ar->next_ep_id = ENDPOINT_2;
71bdcd8170SKalle Valo 		}
72bdcd8170SKalle Valo 	}
73bdcd8170SKalle Valo 
74bdcd8170SKalle Valo 	*map_no = ep_map + 1;
75bdcd8170SKalle Valo 	ar->node_map[ep_map].tx_pend++;
76bdcd8170SKalle Valo 
77bdcd8170SKalle Valo 	return ar->node_map[ep_map].ep_id;
78bdcd8170SKalle Valo }
79bdcd8170SKalle Valo 
80bdcd8170SKalle Valo static bool ath6kl_powersave_ap(struct ath6kl *ar, struct sk_buff *skb,
81bdcd8170SKalle Valo 				bool *more_data)
82bdcd8170SKalle Valo {
83bdcd8170SKalle Valo 	struct ethhdr *datap = (struct ethhdr *) skb->data;
84bdcd8170SKalle Valo 	struct ath6kl_sta *conn = NULL;
85bdcd8170SKalle Valo 	bool ps_queued = false, is_psq_empty = false;
86bdcd8170SKalle Valo 
87bdcd8170SKalle Valo 	if (is_multicast_ether_addr(datap->h_dest)) {
88bdcd8170SKalle Valo 		u8 ctr = 0;
89bdcd8170SKalle Valo 		bool q_mcast = false;
90bdcd8170SKalle Valo 
91bdcd8170SKalle Valo 		for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) {
92bdcd8170SKalle Valo 			if (ar->sta_list[ctr].sta_flags & STA_PS_SLEEP) {
93bdcd8170SKalle Valo 				q_mcast = true;
94bdcd8170SKalle Valo 				break;
95bdcd8170SKalle Valo 			}
96bdcd8170SKalle Valo 		}
97bdcd8170SKalle Valo 
98bdcd8170SKalle Valo 		if (q_mcast) {
99bdcd8170SKalle Valo 			/*
100bdcd8170SKalle Valo 			 * If this transmit is not because of a Dtim Expiry
101bdcd8170SKalle Valo 			 * q it.
102bdcd8170SKalle Valo 			 */
103bdcd8170SKalle Valo 			if (!test_bit(DTIM_EXPIRED, &ar->flag)) {
104bdcd8170SKalle Valo 				bool is_mcastq_empty = false;
105bdcd8170SKalle Valo 
106bdcd8170SKalle Valo 				spin_lock_bh(&ar->mcastpsq_lock);
107bdcd8170SKalle Valo 				is_mcastq_empty =
108bdcd8170SKalle Valo 					skb_queue_empty(&ar->mcastpsq);
109bdcd8170SKalle Valo 				skb_queue_tail(&ar->mcastpsq, skb);
110bdcd8170SKalle Valo 				spin_unlock_bh(&ar->mcastpsq_lock);
111bdcd8170SKalle Valo 
112bdcd8170SKalle Valo 				/*
113bdcd8170SKalle Valo 				 * If this is the first Mcast pkt getting
114bdcd8170SKalle Valo 				 * queued indicate to the target to set the
115bdcd8170SKalle Valo 				 * BitmapControl LSB of the TIM IE.
116bdcd8170SKalle Valo 				 */
117bdcd8170SKalle Valo 				if (is_mcastq_empty)
118bdcd8170SKalle Valo 					ath6kl_wmi_set_pvb_cmd(ar->wmi,
119bdcd8170SKalle Valo 							       MCAST_AID, 1);
120bdcd8170SKalle Valo 
121bdcd8170SKalle Valo 				ps_queued = true;
122bdcd8170SKalle Valo 			} else {
123bdcd8170SKalle Valo 				/*
124bdcd8170SKalle Valo 				 * This transmit is because of Dtim expiry.
125bdcd8170SKalle Valo 				 * Determine if MoreData bit has to be set.
126bdcd8170SKalle Valo 				 */
127bdcd8170SKalle Valo 				spin_lock_bh(&ar->mcastpsq_lock);
128bdcd8170SKalle Valo 				if (!skb_queue_empty(&ar->mcastpsq))
129bdcd8170SKalle Valo 					*more_data = true;
130bdcd8170SKalle Valo 				spin_unlock_bh(&ar->mcastpsq_lock);
131bdcd8170SKalle Valo 			}
132bdcd8170SKalle Valo 		}
133bdcd8170SKalle Valo 	} else {
134bdcd8170SKalle Valo 		conn = ath6kl_find_sta(ar, datap->h_dest);
135bdcd8170SKalle Valo 		if (!conn) {
136bdcd8170SKalle Valo 			dev_kfree_skb(skb);
137bdcd8170SKalle Valo 
138bdcd8170SKalle Valo 			/* Inform the caller that the skb is consumed */
139bdcd8170SKalle Valo 			return true;
140bdcd8170SKalle Valo 		}
141bdcd8170SKalle Valo 
142bdcd8170SKalle Valo 		if (conn->sta_flags & STA_PS_SLEEP) {
143bdcd8170SKalle Valo 			if (!(conn->sta_flags & STA_PS_POLLED)) {
144bdcd8170SKalle Valo 				/* Queue the frames if the STA is sleeping */
145bdcd8170SKalle Valo 				spin_lock_bh(&conn->psq_lock);
146bdcd8170SKalle Valo 				is_psq_empty = skb_queue_empty(&conn->psq);
147bdcd8170SKalle Valo 				skb_queue_tail(&conn->psq, skb);
148bdcd8170SKalle Valo 				spin_unlock_bh(&conn->psq_lock);
149bdcd8170SKalle Valo 
150bdcd8170SKalle Valo 				/*
151bdcd8170SKalle Valo 				 * If this is the first pkt getting queued
152bdcd8170SKalle Valo 				 * for this STA, update the PVB for this
153bdcd8170SKalle Valo 				 * STA.
154bdcd8170SKalle Valo 				 */
155bdcd8170SKalle Valo 				if (is_psq_empty)
156bdcd8170SKalle Valo 					ath6kl_wmi_set_pvb_cmd(ar->wmi,
157bdcd8170SKalle Valo 							       conn->aid, 1);
158bdcd8170SKalle Valo 
159bdcd8170SKalle Valo 				ps_queued = true;
160bdcd8170SKalle Valo 			} else {
161bdcd8170SKalle Valo 				/*
162bdcd8170SKalle Valo 				 * This tx is because of a PsPoll.
163bdcd8170SKalle Valo 				 * Determine if MoreData bit has to be set.
164bdcd8170SKalle Valo 				 */
165bdcd8170SKalle Valo 				spin_lock_bh(&conn->psq_lock);
166bdcd8170SKalle Valo 				if (!skb_queue_empty(&conn->psq))
167bdcd8170SKalle Valo 					*more_data = true;
168bdcd8170SKalle Valo 				spin_unlock_bh(&conn->psq_lock);
169bdcd8170SKalle Valo 			}
170bdcd8170SKalle Valo 		}
171bdcd8170SKalle Valo 	}
172bdcd8170SKalle Valo 
173bdcd8170SKalle Valo 	return ps_queued;
174bdcd8170SKalle Valo }
175bdcd8170SKalle Valo 
176bdcd8170SKalle Valo /* Tx functions */
177bdcd8170SKalle Valo 
178bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb,
179bdcd8170SKalle Valo 		      enum htc_endpoint_id eid)
180bdcd8170SKalle Valo {
181bdcd8170SKalle Valo 	struct ath6kl *ar = devt;
182bdcd8170SKalle Valo 	int status = 0;
183bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie = NULL;
184bdcd8170SKalle Valo 
185bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
186bdcd8170SKalle Valo 
187bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_WLAN_TX,
188bdcd8170SKalle Valo 		   "%s: skb=0x%p, len=0x%x eid =%d\n", __func__,
189bdcd8170SKalle Valo 		   skb, skb->len, eid);
190bdcd8170SKalle Valo 
191bdcd8170SKalle Valo 	if (test_bit(WMI_CTRL_EP_FULL, &ar->flag) && (eid == ar->ctrl_ep)) {
192bdcd8170SKalle Valo 		/*
193bdcd8170SKalle Valo 		 * Control endpoint is full, don't allocate resources, we
194bdcd8170SKalle Valo 		 * are just going to drop this packet.
195bdcd8170SKalle Valo 		 */
196bdcd8170SKalle Valo 		cookie = NULL;
197bdcd8170SKalle Valo 		ath6kl_err("wmi ctrl ep full, dropping pkt : 0x%p, len:%d\n",
198bdcd8170SKalle Valo 			   skb, skb->len);
199bdcd8170SKalle Valo 	} else
200bdcd8170SKalle Valo 		cookie = ath6kl_alloc_cookie(ar);
201bdcd8170SKalle Valo 
202bdcd8170SKalle Valo 	if (cookie == NULL) {
203bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
204bdcd8170SKalle Valo 		status = -ENOMEM;
205bdcd8170SKalle Valo 		goto fail_ctrl_tx;
206bdcd8170SKalle Valo 	}
207bdcd8170SKalle Valo 
208bdcd8170SKalle Valo 	ar->tx_pending[eid]++;
209bdcd8170SKalle Valo 
210bdcd8170SKalle Valo 	if (eid != ar->ctrl_ep)
211bdcd8170SKalle Valo 		ar->total_tx_data_pend++;
212bdcd8170SKalle Valo 
213bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
214bdcd8170SKalle Valo 
215bdcd8170SKalle Valo 	cookie->skb = skb;
216bdcd8170SKalle Valo 	cookie->map_no = 0;
217bdcd8170SKalle Valo 	set_htc_pkt_info(&cookie->htc_pkt, cookie, skb->data, skb->len,
218bdcd8170SKalle Valo 			 eid, ATH6KL_CONTROL_PKT_TAG);
219bdcd8170SKalle Valo 
220bdcd8170SKalle Valo 	/*
221bdcd8170SKalle Valo 	 * This interface is asynchronous, if there is an error, cleanup
222bdcd8170SKalle Valo 	 * will happen in the TX completion callback.
223bdcd8170SKalle Valo 	 */
224ad226ec2SKalle Valo 	ath6kl_htc_tx(ar->htc_target, &cookie->htc_pkt);
225bdcd8170SKalle Valo 
226bdcd8170SKalle Valo 	return 0;
227bdcd8170SKalle Valo 
228bdcd8170SKalle Valo fail_ctrl_tx:
229bdcd8170SKalle Valo 	dev_kfree_skb(skb);
230bdcd8170SKalle Valo 	return status;
231bdcd8170SKalle Valo }
232bdcd8170SKalle Valo 
233bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev)
234bdcd8170SKalle Valo {
235bdcd8170SKalle Valo 	struct ath6kl *ar = ath6kl_priv(dev);
236bdcd8170SKalle Valo 	struct ath6kl_cookie *cookie = NULL;
237bdcd8170SKalle Valo 	enum htc_endpoint_id eid = ENDPOINT_UNUSED;
238bdcd8170SKalle Valo 	u32 map_no = 0;
239bdcd8170SKalle Valo 	u16 htc_tag = ATH6KL_DATA_PKT_TAG;
240bdcd8170SKalle Valo 	u8 ac = 99 ; /* initialize to unmapped ac */
241bdcd8170SKalle Valo 	bool chk_adhoc_ps_mapping = false, more_data = false;
242bdcd8170SKalle Valo 	int ret;
243bdcd8170SKalle Valo 
244bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_WLAN_TX,
245bdcd8170SKalle Valo 		   "%s: skb=0x%p, data=0x%p, len=0x%x\n", __func__,
246bdcd8170SKalle Valo 		   skb, skb->data, skb->len);
247bdcd8170SKalle Valo 
248bdcd8170SKalle Valo 	/* If target is not associated */
249bdcd8170SKalle Valo 	if (!test_bit(CONNECTED, &ar->flag)) {
250bdcd8170SKalle Valo 		dev_kfree_skb(skb);
251bdcd8170SKalle Valo 		return 0;
252bdcd8170SKalle Valo 	}
253bdcd8170SKalle Valo 
254bdcd8170SKalle Valo 	if (!test_bit(WMI_READY, &ar->flag))
255bdcd8170SKalle Valo 		goto fail_tx;
256bdcd8170SKalle Valo 
257bdcd8170SKalle Valo 	/* AP mode Power saving processing */
258bdcd8170SKalle Valo 	if (ar->nw_type == AP_NETWORK) {
259bdcd8170SKalle Valo 		if (ath6kl_powersave_ap(ar, skb, &more_data))
260bdcd8170SKalle Valo 			return 0;
261bdcd8170SKalle Valo 	}
262bdcd8170SKalle Valo 
263bdcd8170SKalle Valo 	if (test_bit(WMI_ENABLED, &ar->flag)) {
264bdcd8170SKalle Valo 		if (skb_headroom(skb) < dev->needed_headroom) {
265bdcd8170SKalle Valo 			WARN_ON(1);
266bdcd8170SKalle Valo 			goto fail_tx;
267bdcd8170SKalle Valo 		}
268bdcd8170SKalle Valo 
269bdcd8170SKalle Valo 		if (ath6kl_wmi_dix_2_dot3(ar->wmi, skb)) {
270bdcd8170SKalle Valo 			ath6kl_err("ath6kl_wmi_dix_2_dot3 failed\n");
271bdcd8170SKalle Valo 			goto fail_tx;
272bdcd8170SKalle Valo 		}
273bdcd8170SKalle Valo 
274bdcd8170SKalle Valo 		if (ath6kl_wmi_data_hdr_add(ar->wmi, skb, DATA_MSGTYPE,
275bdcd8170SKalle Valo 					    more_data, 0, 0, NULL)) {
276bdcd8170SKalle Valo 			ath6kl_err("wmi_data_hdr_add failed\n");
277bdcd8170SKalle Valo 			goto fail_tx;
278bdcd8170SKalle Valo 		}
279bdcd8170SKalle Valo 
280bdcd8170SKalle Valo 		if ((ar->nw_type == ADHOC_NETWORK) &&
281bdcd8170SKalle Valo 		     ar->ibss_ps_enable && test_bit(CONNECTED, &ar->flag))
282bdcd8170SKalle Valo 			chk_adhoc_ps_mapping = true;
283bdcd8170SKalle Valo 		else {
284bdcd8170SKalle Valo 			/* get the stream mapping */
285bdcd8170SKalle Valo 			ret = ath6kl_wmi_implicit_create_pstream(ar->wmi, skb,
286bdcd8170SKalle Valo 				    0, test_bit(WMM_ENABLED, &ar->flag), &ac);
287bdcd8170SKalle Valo 			if (ret)
288bdcd8170SKalle Valo 				goto fail_tx;
289bdcd8170SKalle Valo 		}
290bdcd8170SKalle Valo 	} else
291bdcd8170SKalle Valo 		goto fail_tx;
292bdcd8170SKalle Valo 
293bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
294bdcd8170SKalle Valo 
295bdcd8170SKalle Valo 	if (chk_adhoc_ps_mapping)
296bdcd8170SKalle Valo 		eid = ath6kl_ibss_map_epid(skb, dev, &map_no);
297bdcd8170SKalle Valo 	else
298bdcd8170SKalle Valo 		eid = ar->ac2ep_map[ac];
299bdcd8170SKalle Valo 
300bdcd8170SKalle Valo 	if (eid == 0 || eid == ENDPOINT_UNUSED) {
301bdcd8170SKalle Valo 		ath6kl_err("eid %d is not mapped!\n", eid);
302bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
303bdcd8170SKalle Valo 		goto fail_tx;
304bdcd8170SKalle Valo 	}
305bdcd8170SKalle Valo 
306bdcd8170SKalle Valo 	/* allocate resource for this packet */
307bdcd8170SKalle Valo 	cookie = ath6kl_alloc_cookie(ar);
308bdcd8170SKalle Valo 
309bdcd8170SKalle Valo 	if (!cookie) {
310bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
311bdcd8170SKalle Valo 		goto fail_tx;
312bdcd8170SKalle Valo 	}
313bdcd8170SKalle Valo 
314bdcd8170SKalle Valo 	/* update counts while the lock is held */
315bdcd8170SKalle Valo 	ar->tx_pending[eid]++;
316bdcd8170SKalle Valo 	ar->total_tx_data_pend++;
317bdcd8170SKalle Valo 
318bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
319bdcd8170SKalle Valo 
320bdcd8170SKalle Valo 	cookie->skb = skb;
321bdcd8170SKalle Valo 	cookie->map_no = map_no;
322bdcd8170SKalle Valo 	set_htc_pkt_info(&cookie->htc_pkt, cookie, skb->data, skb->len,
323bdcd8170SKalle Valo 			 eid, htc_tag);
324bdcd8170SKalle Valo 
325bdcd8170SKalle Valo 	ath6kl_dbg_dump(ATH6KL_DBG_RAW_BYTES, __func__, skb->data, skb->len);
326bdcd8170SKalle Valo 
327bdcd8170SKalle Valo 	/*
328bdcd8170SKalle Valo 	 * HTC interface is asynchronous, if this fails, cleanup will
329bdcd8170SKalle Valo 	 * happen in the ath6kl_tx_complete callback.
330bdcd8170SKalle Valo 	 */
331ad226ec2SKalle Valo 	ath6kl_htc_tx(ar->htc_target, &cookie->htc_pkt);
332bdcd8170SKalle Valo 
333bdcd8170SKalle Valo 	return 0;
334bdcd8170SKalle Valo 
335bdcd8170SKalle Valo fail_tx:
336bdcd8170SKalle Valo 	dev_kfree_skb(skb);
337bdcd8170SKalle Valo 
338bdcd8170SKalle Valo 	ar->net_stats.tx_dropped++;
339bdcd8170SKalle Valo 	ar->net_stats.tx_aborted_errors++;
340bdcd8170SKalle Valo 
341bdcd8170SKalle Valo 	return 0;
342bdcd8170SKalle Valo }
343bdcd8170SKalle Valo 
344bdcd8170SKalle Valo /* indicate tx activity or inactivity on a WMI stream */
345bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active)
346bdcd8170SKalle Valo {
347bdcd8170SKalle Valo 	struct ath6kl *ar = devt;
348bdcd8170SKalle Valo 	enum htc_endpoint_id eid;
349bdcd8170SKalle Valo 	int i;
350bdcd8170SKalle Valo 
351bdcd8170SKalle Valo 	eid = ar->ac2ep_map[traffic_class];
352bdcd8170SKalle Valo 
353bdcd8170SKalle Valo 	if (!test_bit(WMI_ENABLED, &ar->flag))
354bdcd8170SKalle Valo 		goto notify_htc;
355bdcd8170SKalle Valo 
356bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
357bdcd8170SKalle Valo 
358bdcd8170SKalle Valo 	ar->ac_stream_active[traffic_class] = active;
359bdcd8170SKalle Valo 
360bdcd8170SKalle Valo 	if (active) {
361bdcd8170SKalle Valo 		/*
362bdcd8170SKalle Valo 		 * Keep track of the active stream with the highest
363bdcd8170SKalle Valo 		 * priority.
364bdcd8170SKalle Valo 		 */
365bdcd8170SKalle Valo 		if (ar->ac_stream_pri_map[traffic_class] >
366bdcd8170SKalle Valo 		    ar->hiac_stream_active_pri)
367bdcd8170SKalle Valo 			/* set the new highest active priority */
368bdcd8170SKalle Valo 			ar->hiac_stream_active_pri =
369bdcd8170SKalle Valo 					ar->ac_stream_pri_map[traffic_class];
370bdcd8170SKalle Valo 
371bdcd8170SKalle Valo 	} else {
372bdcd8170SKalle Valo 		/*
373bdcd8170SKalle Valo 		 * We may have to search for the next active stream
374bdcd8170SKalle Valo 		 * that is the highest priority.
375bdcd8170SKalle Valo 		 */
376bdcd8170SKalle Valo 		if (ar->hiac_stream_active_pri ==
377bdcd8170SKalle Valo 			ar->ac_stream_pri_map[traffic_class]) {
378bdcd8170SKalle Valo 			/*
379bdcd8170SKalle Valo 			 * The highest priority stream just went inactive
380bdcd8170SKalle Valo 			 * reset and search for the "next" highest "active"
381bdcd8170SKalle Valo 			 * priority stream.
382bdcd8170SKalle Valo 			 */
383bdcd8170SKalle Valo 			ar->hiac_stream_active_pri = 0;
384bdcd8170SKalle Valo 
385bdcd8170SKalle Valo 			for (i = 0; i < WMM_NUM_AC; i++) {
386bdcd8170SKalle Valo 				if (ar->ac_stream_active[i] &&
387bdcd8170SKalle Valo 				    (ar->ac_stream_pri_map[i] >
388bdcd8170SKalle Valo 				     ar->hiac_stream_active_pri))
389bdcd8170SKalle Valo 					/*
390bdcd8170SKalle Valo 					 * Set the new highest active
391bdcd8170SKalle Valo 					 * priority.
392bdcd8170SKalle Valo 					 */
393bdcd8170SKalle Valo 					ar->hiac_stream_active_pri =
394bdcd8170SKalle Valo 						ar->ac_stream_pri_map[i];
395bdcd8170SKalle Valo 			}
396bdcd8170SKalle Valo 		}
397bdcd8170SKalle Valo 	}
398bdcd8170SKalle Valo 
399bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
400bdcd8170SKalle Valo 
401bdcd8170SKalle Valo notify_htc:
402bdcd8170SKalle Valo 	/* notify HTC, this may cause credit distribution changes */
403ad226ec2SKalle Valo 	ath6kl_htc_indicate_activity_change(ar->htc_target, eid, active);
404bdcd8170SKalle Valo }
405bdcd8170SKalle Valo 
406bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
407bdcd8170SKalle Valo 					       struct htc_packet *packet)
408bdcd8170SKalle Valo {
409bdcd8170SKalle Valo 	struct ath6kl *ar = target->dev->ar;
410bdcd8170SKalle Valo 	enum htc_endpoint_id endpoint = packet->endpoint;
411bdcd8170SKalle Valo 
412bdcd8170SKalle Valo 	if (endpoint == ar->ctrl_ep) {
413bdcd8170SKalle Valo 		/*
414bdcd8170SKalle Valo 		 * Under normal WMI if this is getting full, then something
415bdcd8170SKalle Valo 		 * is running rampant the host should not be exhausting the
416bdcd8170SKalle Valo 		 * WMI queue with too many commands the only exception to
417bdcd8170SKalle Valo 		 * this is during testing using endpointping.
418bdcd8170SKalle Valo 		 */
419bdcd8170SKalle Valo 		spin_lock_bh(&ar->lock);
420bdcd8170SKalle Valo 		set_bit(WMI_CTRL_EP_FULL, &ar->flag);
421bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
422bdcd8170SKalle Valo 		ath6kl_err("wmi ctrl ep is full\n");
423bdcd8170SKalle Valo 		return HTC_SEND_FULL_KEEP;
424bdcd8170SKalle Valo 	}
425bdcd8170SKalle Valo 
426bdcd8170SKalle Valo 	if (packet->info.tx.tag == ATH6KL_CONTROL_PKT_TAG)
427bdcd8170SKalle Valo 		return HTC_SEND_FULL_KEEP;
428bdcd8170SKalle Valo 
429bdcd8170SKalle Valo 	if (ar->nw_type == ADHOC_NETWORK)
430bdcd8170SKalle Valo 		/*
431bdcd8170SKalle Valo 		 * In adhoc mode, we cannot differentiate traffic
432bdcd8170SKalle Valo 		 * priorities so there is no need to continue, however we
433bdcd8170SKalle Valo 		 * should stop the network.
434bdcd8170SKalle Valo 		 */
435bdcd8170SKalle Valo 		goto stop_net_queues;
436bdcd8170SKalle Valo 
437bdcd8170SKalle Valo 	/*
438bdcd8170SKalle Valo 	 * The last MAX_HI_COOKIE_NUM "batch" of cookies are reserved for
439bdcd8170SKalle Valo 	 * the highest active stream.
440bdcd8170SKalle Valo 	 */
441bdcd8170SKalle Valo 	if (ar->ac_stream_pri_map[ar->ep2ac_map[endpoint]] <
442bdcd8170SKalle Valo 	    ar->hiac_stream_active_pri &&
443bdcd8170SKalle Valo 	    ar->cookie_count <= MAX_HI_COOKIE_NUM)
444bdcd8170SKalle Valo 		/*
445bdcd8170SKalle Valo 		 * Give preference to the highest priority stream by
446bdcd8170SKalle Valo 		 * dropping the packets which overflowed.
447bdcd8170SKalle Valo 		 */
448bdcd8170SKalle Valo 		return HTC_SEND_FULL_DROP;
449bdcd8170SKalle Valo 
450bdcd8170SKalle Valo stop_net_queues:
451bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
452bdcd8170SKalle Valo 	set_bit(NETQ_STOPPED, &ar->flag);
453bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
454bdcd8170SKalle Valo 	netif_stop_queue(ar->net_dev);
455bdcd8170SKalle Valo 
456bdcd8170SKalle Valo 	return HTC_SEND_FULL_KEEP;
457bdcd8170SKalle Valo }
458bdcd8170SKalle Valo 
459bdcd8170SKalle Valo /* TODO this needs to be looked at */
460bdcd8170SKalle Valo static void ath6kl_tx_clear_node_map(struct ath6kl *ar,
461bdcd8170SKalle Valo 				     enum htc_endpoint_id eid, u32 map_no)
462bdcd8170SKalle Valo {
463bdcd8170SKalle Valo 	u32 i;
464bdcd8170SKalle Valo 
465bdcd8170SKalle Valo 	if (ar->nw_type != ADHOC_NETWORK)
466bdcd8170SKalle Valo 		return;
467bdcd8170SKalle Valo 
468bdcd8170SKalle Valo 	if (!ar->ibss_ps_enable)
469bdcd8170SKalle Valo 		return;
470bdcd8170SKalle Valo 
471bdcd8170SKalle Valo 	if (eid == ar->ctrl_ep)
472bdcd8170SKalle Valo 		return;
473bdcd8170SKalle Valo 
474bdcd8170SKalle Valo 	if (map_no == 0)
475bdcd8170SKalle Valo 		return;
476bdcd8170SKalle Valo 
477bdcd8170SKalle Valo 	map_no--;
478bdcd8170SKalle Valo 	ar->node_map[map_no].tx_pend--;
479bdcd8170SKalle Valo 
480bdcd8170SKalle Valo 	if (ar->node_map[map_no].tx_pend)
481bdcd8170SKalle Valo 		return;
482bdcd8170SKalle Valo 
483bdcd8170SKalle Valo 	if (map_no != (ar->node_num - 1))
484bdcd8170SKalle Valo 		return;
485bdcd8170SKalle Valo 
486bdcd8170SKalle Valo 	for (i = ar->node_num; i > 0; i--) {
487bdcd8170SKalle Valo 		if (ar->node_map[i - 1].tx_pend)
488bdcd8170SKalle Valo 			break;
489bdcd8170SKalle Valo 
490bdcd8170SKalle Valo 		memset(&ar->node_map[i - 1], 0,
491bdcd8170SKalle Valo 		       sizeof(struct ath6kl_node_mapping));
492bdcd8170SKalle Valo 		ar->node_num--;
493bdcd8170SKalle Valo 	}
494bdcd8170SKalle Valo }
495bdcd8170SKalle Valo 
496bdcd8170SKalle Valo void ath6kl_tx_complete(void *context, struct list_head *packet_queue)
497bdcd8170SKalle Valo {
498bdcd8170SKalle Valo 	struct ath6kl *ar = context;
499bdcd8170SKalle Valo 	struct sk_buff_head skb_queue;
500bdcd8170SKalle Valo 	struct htc_packet *packet;
501bdcd8170SKalle Valo 	struct sk_buff *skb;
502bdcd8170SKalle Valo 	struct ath6kl_cookie *ath6kl_cookie;
503bdcd8170SKalle Valo 	u32 map_no = 0;
504bdcd8170SKalle Valo 	int status;
505bdcd8170SKalle Valo 	enum htc_endpoint_id eid;
506bdcd8170SKalle Valo 	bool wake_event = false;
507bdcd8170SKalle Valo 	bool flushing = false;
508bdcd8170SKalle Valo 
509bdcd8170SKalle Valo 	skb_queue_head_init(&skb_queue);
510bdcd8170SKalle Valo 
511bdcd8170SKalle Valo 	/* lock the driver as we update internal state */
512bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
513bdcd8170SKalle Valo 
514bdcd8170SKalle Valo 	/* reap completed packets */
515bdcd8170SKalle Valo 	while (!list_empty(packet_queue)) {
516bdcd8170SKalle Valo 
517bdcd8170SKalle Valo 		packet = list_first_entry(packet_queue, struct htc_packet,
518bdcd8170SKalle Valo 					  list);
519bdcd8170SKalle Valo 		list_del(&packet->list);
520bdcd8170SKalle Valo 
521bdcd8170SKalle Valo 		ath6kl_cookie = (struct ath6kl_cookie *)packet->pkt_cntxt;
522bdcd8170SKalle Valo 		if (!ath6kl_cookie)
523bdcd8170SKalle Valo 			goto fatal;
524bdcd8170SKalle Valo 
525bdcd8170SKalle Valo 		status = packet->status;
526bdcd8170SKalle Valo 		skb = ath6kl_cookie->skb;
527bdcd8170SKalle Valo 		eid = packet->endpoint;
528bdcd8170SKalle Valo 		map_no = ath6kl_cookie->map_no;
529bdcd8170SKalle Valo 
530bdcd8170SKalle Valo 		if (!skb || !skb->data)
531bdcd8170SKalle Valo 			goto fatal;
532bdcd8170SKalle Valo 
533bdcd8170SKalle Valo 		packet->buf = skb->data;
534bdcd8170SKalle Valo 
535bdcd8170SKalle Valo 		__skb_queue_tail(&skb_queue, skb);
536bdcd8170SKalle Valo 
537bdcd8170SKalle Valo 		if (!status && (packet->act_len != skb->len))
538bdcd8170SKalle Valo 			goto fatal;
539bdcd8170SKalle Valo 
540bdcd8170SKalle Valo 		ar->tx_pending[eid]--;
541bdcd8170SKalle Valo 
542bdcd8170SKalle Valo 		if (eid != ar->ctrl_ep)
543bdcd8170SKalle Valo 			ar->total_tx_data_pend--;
544bdcd8170SKalle Valo 
545bdcd8170SKalle Valo 		if (eid == ar->ctrl_ep) {
546bdcd8170SKalle Valo 			if (test_bit(WMI_CTRL_EP_FULL, &ar->flag))
547bdcd8170SKalle Valo 				clear_bit(WMI_CTRL_EP_FULL, &ar->flag);
548bdcd8170SKalle Valo 
549bdcd8170SKalle Valo 			if (ar->tx_pending[eid] == 0)
550bdcd8170SKalle Valo 				wake_event = true;
551bdcd8170SKalle Valo 		}
552bdcd8170SKalle Valo 
553bdcd8170SKalle Valo 		if (status) {
554bdcd8170SKalle Valo 			if (status == -ECANCELED)
555bdcd8170SKalle Valo 				/* a packet was flushed  */
556bdcd8170SKalle Valo 				flushing = true;
557bdcd8170SKalle Valo 
558bdcd8170SKalle Valo 			ar->net_stats.tx_errors++;
559bdcd8170SKalle Valo 
560bdcd8170SKalle Valo 			if (status != -ENOSPC)
561bdcd8170SKalle Valo 				ath6kl_err("tx error, status: 0x%x\n", status);
562bdcd8170SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_WLAN_TX,
563bdcd8170SKalle Valo 				   "%s: skb=0x%p data=0x%p len=0x%x eid=%d %s\n",
564bdcd8170SKalle Valo 				   __func__, skb, packet->buf, packet->act_len,
565bdcd8170SKalle Valo 				   eid, "error!");
566bdcd8170SKalle Valo 		} else {
567bdcd8170SKalle Valo 			ath6kl_dbg(ATH6KL_DBG_WLAN_TX,
568bdcd8170SKalle Valo 				   "%s: skb=0x%p data=0x%p len=0x%x eid=%d %s\n",
569bdcd8170SKalle Valo 				   __func__, skb, packet->buf, packet->act_len,
570bdcd8170SKalle Valo 				   eid, "OK");
571bdcd8170SKalle Valo 
572bdcd8170SKalle Valo 			flushing = false;
573bdcd8170SKalle Valo 			ar->net_stats.tx_packets++;
574bdcd8170SKalle Valo 			ar->net_stats.tx_bytes += skb->len;
575bdcd8170SKalle Valo 		}
576bdcd8170SKalle Valo 
577bdcd8170SKalle Valo 		ath6kl_tx_clear_node_map(ar, eid, map_no);
578bdcd8170SKalle Valo 
579bdcd8170SKalle Valo 		ath6kl_free_cookie(ar, ath6kl_cookie);
580bdcd8170SKalle Valo 
581bdcd8170SKalle Valo 		if (test_bit(NETQ_STOPPED, &ar->flag))
582bdcd8170SKalle Valo 			clear_bit(NETQ_STOPPED, &ar->flag);
583bdcd8170SKalle Valo 	}
584bdcd8170SKalle Valo 
585bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
586bdcd8170SKalle Valo 
587bdcd8170SKalle Valo 	__skb_queue_purge(&skb_queue);
588bdcd8170SKalle Valo 
589bdcd8170SKalle Valo 	if (test_bit(CONNECTED, &ar->flag)) {
590bdcd8170SKalle Valo 		if (!flushing)
591bdcd8170SKalle Valo 			netif_wake_queue(ar->net_dev);
592bdcd8170SKalle Valo 	}
593bdcd8170SKalle Valo 
594bdcd8170SKalle Valo 	if (wake_event)
595bdcd8170SKalle Valo 		wake_up(&ar->event_wq);
596bdcd8170SKalle Valo 
597bdcd8170SKalle Valo 	return;
598bdcd8170SKalle Valo 
599bdcd8170SKalle Valo fatal:
600bdcd8170SKalle Valo 	WARN_ON(1);
601bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
602bdcd8170SKalle Valo 	return;
603bdcd8170SKalle Valo }
604bdcd8170SKalle Valo 
605bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar)
606bdcd8170SKalle Valo {
607bdcd8170SKalle Valo 	int i;
608bdcd8170SKalle Valo 
609bdcd8170SKalle Valo 	/* flush all the data (non-control) streams */
610bdcd8170SKalle Valo 	for (i = 0; i < WMM_NUM_AC; i++)
611ad226ec2SKalle Valo 		ath6kl_htc_flush_txep(ar->htc_target, ar->ac2ep_map[i],
612bdcd8170SKalle Valo 				      ATH6KL_DATA_PKT_TAG);
613bdcd8170SKalle Valo }
614bdcd8170SKalle Valo 
615bdcd8170SKalle Valo /* Rx functions */
616bdcd8170SKalle Valo 
617bdcd8170SKalle Valo static void ath6kl_deliver_frames_to_nw_stack(struct net_device *dev,
618bdcd8170SKalle Valo 					      struct sk_buff *skb)
619bdcd8170SKalle Valo {
620bdcd8170SKalle Valo 	if (!skb)
621bdcd8170SKalle Valo 		return;
622bdcd8170SKalle Valo 
623bdcd8170SKalle Valo 	skb->dev = dev;
624bdcd8170SKalle Valo 
625bdcd8170SKalle Valo 	if (!(skb->dev->flags & IFF_UP)) {
626bdcd8170SKalle Valo 		dev_kfree_skb(skb);
627bdcd8170SKalle Valo 		return;
628bdcd8170SKalle Valo 	}
629bdcd8170SKalle Valo 
630bdcd8170SKalle Valo 	skb->protocol = eth_type_trans(skb, skb->dev);
631bdcd8170SKalle Valo 
632bdcd8170SKalle Valo 	netif_rx_ni(skb);
633bdcd8170SKalle Valo }
634bdcd8170SKalle Valo 
635bdcd8170SKalle Valo static void ath6kl_alloc_netbufs(struct sk_buff_head *q, u16 num)
636bdcd8170SKalle Valo {
637bdcd8170SKalle Valo 	struct sk_buff *skb;
638bdcd8170SKalle Valo 
639bdcd8170SKalle Valo 	while (num) {
640bdcd8170SKalle Valo 		skb = ath6kl_buf_alloc(ATH6KL_BUFFER_SIZE);
641bdcd8170SKalle Valo 		if (!skb) {
642bdcd8170SKalle Valo 			ath6kl_err("netbuf allocation failed\n");
643bdcd8170SKalle Valo 			return;
644bdcd8170SKalle Valo 		}
645bdcd8170SKalle Valo 		skb_queue_tail(q, skb);
646bdcd8170SKalle Valo 		num--;
647bdcd8170SKalle Valo 	}
648bdcd8170SKalle Valo }
649bdcd8170SKalle Valo 
650bdcd8170SKalle Valo static struct sk_buff *aggr_get_free_skb(struct aggr_info *p_aggr)
651bdcd8170SKalle Valo {
652bdcd8170SKalle Valo 	struct sk_buff *skb = NULL;
653bdcd8170SKalle Valo 
654bdcd8170SKalle Valo 	if (skb_queue_len(&p_aggr->free_q) < (AGGR_NUM_OF_FREE_NETBUFS >> 2))
655bdcd8170SKalle Valo 		ath6kl_alloc_netbufs(&p_aggr->free_q, AGGR_NUM_OF_FREE_NETBUFS);
656bdcd8170SKalle Valo 
657bdcd8170SKalle Valo 	skb = skb_dequeue(&p_aggr->free_q);
658bdcd8170SKalle Valo 
659bdcd8170SKalle Valo 	return skb;
660bdcd8170SKalle Valo }
661bdcd8170SKalle Valo 
662bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, enum htc_endpoint_id endpoint)
663bdcd8170SKalle Valo {
664bdcd8170SKalle Valo 	struct ath6kl *ar = target->dev->ar;
665bdcd8170SKalle Valo 	struct sk_buff *skb;
666bdcd8170SKalle Valo 	int rx_buf;
667bdcd8170SKalle Valo 	int n_buf_refill;
668bdcd8170SKalle Valo 	struct htc_packet *packet;
669bdcd8170SKalle Valo 	struct list_head queue;
670bdcd8170SKalle Valo 
671bdcd8170SKalle Valo 	n_buf_refill = ATH6KL_MAX_RX_BUFFERS -
672ad226ec2SKalle Valo 			  ath6kl_htc_get_rxbuf_num(ar->htc_target, endpoint);
673bdcd8170SKalle Valo 
674bdcd8170SKalle Valo 	if (n_buf_refill <= 0)
675bdcd8170SKalle Valo 		return;
676bdcd8170SKalle Valo 
677bdcd8170SKalle Valo 	INIT_LIST_HEAD(&queue);
678bdcd8170SKalle Valo 
679bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_WLAN_RX,
680bdcd8170SKalle Valo 		   "%s: providing htc with %d buffers at eid=%d\n",
681bdcd8170SKalle Valo 		   __func__, n_buf_refill, endpoint);
682bdcd8170SKalle Valo 
683bdcd8170SKalle Valo 	for (rx_buf = 0; rx_buf < n_buf_refill; rx_buf++) {
684bdcd8170SKalle Valo 		skb = ath6kl_buf_alloc(ATH6KL_BUFFER_SIZE);
685bdcd8170SKalle Valo 		if (!skb)
686bdcd8170SKalle Valo 			break;
687bdcd8170SKalle Valo 
688bdcd8170SKalle Valo 		packet = (struct htc_packet *) skb->head;
68994e532d1SVasanthakumar Thiagarajan 		if (!IS_ALIGNED((unsigned long) skb->data, 4))
6901df94a85SVasanthakumar Thiagarajan 			skb->data = PTR_ALIGN(skb->data - 4, 4);
691bdcd8170SKalle Valo 		set_htc_rxpkt_info(packet, skb, skb->data,
692bdcd8170SKalle Valo 				ATH6KL_BUFFER_SIZE, endpoint);
693bdcd8170SKalle Valo 		list_add_tail(&packet->list, &queue);
694bdcd8170SKalle Valo 	}
695bdcd8170SKalle Valo 
696bdcd8170SKalle Valo 	if (!list_empty(&queue))
697ad226ec2SKalle Valo 		ath6kl_htc_add_rxbuf_multiple(ar->htc_target, &queue);
698bdcd8170SKalle Valo }
699bdcd8170SKalle Valo 
700bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count)
701bdcd8170SKalle Valo {
702bdcd8170SKalle Valo 	struct htc_packet *packet;
703bdcd8170SKalle Valo 	struct sk_buff *skb;
704bdcd8170SKalle Valo 
705bdcd8170SKalle Valo 	while (count) {
706bdcd8170SKalle Valo 		skb = ath6kl_buf_alloc(ATH6KL_AMSDU_BUFFER_SIZE);
707bdcd8170SKalle Valo 		if (!skb)
708bdcd8170SKalle Valo 			return;
709bdcd8170SKalle Valo 
710bdcd8170SKalle Valo 		packet = (struct htc_packet *) skb->head;
71194e532d1SVasanthakumar Thiagarajan 		if (!IS_ALIGNED((unsigned long) skb->data, 4))
7121df94a85SVasanthakumar Thiagarajan 			skb->data = PTR_ALIGN(skb->data - 4, 4);
713bdcd8170SKalle Valo 		set_htc_rxpkt_info(packet, skb, skb->data,
714bdcd8170SKalle Valo 				   ATH6KL_AMSDU_BUFFER_SIZE, 0);
715bdcd8170SKalle Valo 		spin_lock_bh(&ar->lock);
716bdcd8170SKalle Valo 		list_add_tail(&packet->list, &ar->amsdu_rx_buffer_queue);
717bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
718bdcd8170SKalle Valo 		count--;
719bdcd8170SKalle Valo 	}
720bdcd8170SKalle Valo }
721bdcd8170SKalle Valo 
722bdcd8170SKalle Valo /*
723bdcd8170SKalle Valo  * Callback to allocate a receive buffer for a pending packet. We use a
724bdcd8170SKalle Valo  * pre-allocated list of buffers of maximum AMSDU size (4K).
725bdcd8170SKalle Valo  */
726bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
727bdcd8170SKalle Valo 					    enum htc_endpoint_id endpoint,
728bdcd8170SKalle Valo 					    int len)
729bdcd8170SKalle Valo {
730bdcd8170SKalle Valo 	struct ath6kl *ar = target->dev->ar;
731bdcd8170SKalle Valo 	struct htc_packet *packet = NULL;
732bdcd8170SKalle Valo 	struct list_head *pkt_pos;
733bdcd8170SKalle Valo 	int refill_cnt = 0, depth = 0;
734bdcd8170SKalle Valo 
735bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_WLAN_RX, "%s: eid=%d, len:%d\n",
736bdcd8170SKalle Valo 		   __func__, endpoint, len);
737bdcd8170SKalle Valo 
738bdcd8170SKalle Valo 	if ((len <= ATH6KL_BUFFER_SIZE) ||
739bdcd8170SKalle Valo 	    (len > ATH6KL_AMSDU_BUFFER_SIZE))
740bdcd8170SKalle Valo 		return NULL;
741bdcd8170SKalle Valo 
742bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
743bdcd8170SKalle Valo 
744bdcd8170SKalle Valo 	if (list_empty(&ar->amsdu_rx_buffer_queue)) {
745bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
746bdcd8170SKalle Valo 		refill_cnt = ATH6KL_MAX_AMSDU_RX_BUFFERS;
747bdcd8170SKalle Valo 		goto refill_buf;
748bdcd8170SKalle Valo 	}
749bdcd8170SKalle Valo 
750bdcd8170SKalle Valo 	packet = list_first_entry(&ar->amsdu_rx_buffer_queue,
751bdcd8170SKalle Valo 				  struct htc_packet, list);
752bdcd8170SKalle Valo 	list_del(&packet->list);
753bdcd8170SKalle Valo 	list_for_each(pkt_pos, &ar->amsdu_rx_buffer_queue)
754bdcd8170SKalle Valo 		depth++;
755bdcd8170SKalle Valo 
756bdcd8170SKalle Valo 	refill_cnt = ATH6KL_MAX_AMSDU_RX_BUFFERS - depth;
757bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
758bdcd8170SKalle Valo 
759bdcd8170SKalle Valo 	/* set actual endpoint ID */
760bdcd8170SKalle Valo 	packet->endpoint = endpoint;
761bdcd8170SKalle Valo 
762bdcd8170SKalle Valo refill_buf:
763bdcd8170SKalle Valo 	if (refill_cnt >= ATH6KL_AMSDU_REFILL_THRESHOLD)
764bdcd8170SKalle Valo 		ath6kl_refill_amsdu_rxbufs(ar, refill_cnt);
765bdcd8170SKalle Valo 
766bdcd8170SKalle Valo 	return packet;
767bdcd8170SKalle Valo }
768bdcd8170SKalle Valo 
769bdcd8170SKalle Valo static void aggr_slice_amsdu(struct aggr_info *p_aggr,
770bdcd8170SKalle Valo 			     struct rxtid *rxtid, struct sk_buff *skb)
771bdcd8170SKalle Valo {
772bdcd8170SKalle Valo 	struct sk_buff *new_skb;
773bdcd8170SKalle Valo 	struct ethhdr *hdr;
774bdcd8170SKalle Valo 	u16 frame_8023_len, payload_8023_len, mac_hdr_len, amsdu_len;
775bdcd8170SKalle Valo 	u8 *framep;
776bdcd8170SKalle Valo 
777bdcd8170SKalle Valo 	mac_hdr_len = sizeof(struct ethhdr);
778bdcd8170SKalle Valo 	framep = skb->data + mac_hdr_len;
779bdcd8170SKalle Valo 	amsdu_len = skb->len - mac_hdr_len;
780bdcd8170SKalle Valo 
781bdcd8170SKalle Valo 	while (amsdu_len > mac_hdr_len) {
782bdcd8170SKalle Valo 		hdr = (struct ethhdr *) framep;
783bdcd8170SKalle Valo 		payload_8023_len = ntohs(hdr->h_proto);
784bdcd8170SKalle Valo 
785bdcd8170SKalle Valo 		if (payload_8023_len < MIN_MSDU_SUBFRAME_PAYLOAD_LEN ||
786bdcd8170SKalle Valo 		    payload_8023_len > MAX_MSDU_SUBFRAME_PAYLOAD_LEN) {
787bdcd8170SKalle Valo 			ath6kl_err("802.3 AMSDU frame bound check failed. len %d\n",
788bdcd8170SKalle Valo 				   payload_8023_len);
789bdcd8170SKalle Valo 			break;
790bdcd8170SKalle Valo 		}
791bdcd8170SKalle Valo 
792bdcd8170SKalle Valo 		frame_8023_len = payload_8023_len + mac_hdr_len;
793bdcd8170SKalle Valo 		new_skb = aggr_get_free_skb(p_aggr);
794bdcd8170SKalle Valo 		if (!new_skb) {
795bdcd8170SKalle Valo 			ath6kl_err("no buffer available\n");
796bdcd8170SKalle Valo 			break;
797bdcd8170SKalle Valo 		}
798bdcd8170SKalle Valo 
799bdcd8170SKalle Valo 		memcpy(new_skb->data, framep, frame_8023_len);
800bdcd8170SKalle Valo 		skb_put(new_skb, frame_8023_len);
801bdcd8170SKalle Valo 		if (ath6kl_wmi_dot3_2_dix(new_skb)) {
802bdcd8170SKalle Valo 			ath6kl_err("dot3_2_dix error\n");
803bdcd8170SKalle Valo 			dev_kfree_skb(new_skb);
804bdcd8170SKalle Valo 			break;
805bdcd8170SKalle Valo 		}
806bdcd8170SKalle Valo 
807bdcd8170SKalle Valo 		skb_queue_tail(&rxtid->q, new_skb);
808bdcd8170SKalle Valo 
809bdcd8170SKalle Valo 		/* Is this the last subframe within this aggregate ? */
810bdcd8170SKalle Valo 		if ((amsdu_len - frame_8023_len) == 0)
811bdcd8170SKalle Valo 			break;
812bdcd8170SKalle Valo 
813bdcd8170SKalle Valo 		/* Add the length of A-MSDU subframe padding bytes -
814bdcd8170SKalle Valo 		 * Round to nearest word.
815bdcd8170SKalle Valo 		 */
81613e34ea1SVasanthakumar Thiagarajan 		frame_8023_len = ALIGN(frame_8023_len, 4);
817bdcd8170SKalle Valo 
818bdcd8170SKalle Valo 		framep += frame_8023_len;
819bdcd8170SKalle Valo 		amsdu_len -= frame_8023_len;
820bdcd8170SKalle Valo 	}
821bdcd8170SKalle Valo 
822bdcd8170SKalle Valo 	dev_kfree_skb(skb);
823bdcd8170SKalle Valo }
824bdcd8170SKalle Valo 
825bdcd8170SKalle Valo static void aggr_deque_frms(struct aggr_info *p_aggr, u8 tid,
826bdcd8170SKalle Valo 			    u16 seq_no, u8 order)
827bdcd8170SKalle Valo {
828bdcd8170SKalle Valo 	struct sk_buff *skb;
829bdcd8170SKalle Valo 	struct rxtid *rxtid;
830bdcd8170SKalle Valo 	struct skb_hold_q *node;
831bdcd8170SKalle Valo 	u16 idx, idx_end, seq_end;
832bdcd8170SKalle Valo 	struct rxtid_stats *stats;
833bdcd8170SKalle Valo 
834bdcd8170SKalle Valo 	if (!p_aggr)
835bdcd8170SKalle Valo 		return;
836bdcd8170SKalle Valo 
837bdcd8170SKalle Valo 	rxtid = &p_aggr->rx_tid[tid];
838bdcd8170SKalle Valo 	stats = &p_aggr->stat[tid];
839bdcd8170SKalle Valo 
840bdcd8170SKalle Valo 	idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
841bdcd8170SKalle Valo 
842bdcd8170SKalle Valo 	/*
843bdcd8170SKalle Valo 	 * idx_end is typically the last possible frame in the window,
844bdcd8170SKalle Valo 	 * but changes to 'the' seq_no, when BAR comes. If seq_no
845bdcd8170SKalle Valo 	 * is non-zero, we will go up to that and stop.
846bdcd8170SKalle Valo 	 * Note: last seq no in current window will occupy the same
847bdcd8170SKalle Valo 	 * index position as index that is just previous to start.
848bdcd8170SKalle Valo 	 * An imp point : if win_sz is 7, for seq_no space of 4095,
849bdcd8170SKalle Valo 	 * then, there would be holes when sequence wrap around occurs.
850bdcd8170SKalle Valo 	 * Target should judiciously choose the win_sz, based on
851bdcd8170SKalle Valo 	 * this condition. For 4095, (TID_WINDOW_SZ = 2 x win_sz
852bdcd8170SKalle Valo 	 * 2, 4, 8, 16 win_sz works fine).
853bdcd8170SKalle Valo 	 * We must deque from "idx" to "idx_end", including both.
854bdcd8170SKalle Valo 	 */
855bdcd8170SKalle Valo 	seq_end = seq_no ? seq_no : rxtid->seq_next;
856bdcd8170SKalle Valo 	idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz);
857bdcd8170SKalle Valo 
858bdcd8170SKalle Valo 	spin_lock_bh(&rxtid->lock);
859bdcd8170SKalle Valo 
860bdcd8170SKalle Valo 	do {
861bdcd8170SKalle Valo 		node = &rxtid->hold_q[idx];
862bdcd8170SKalle Valo 		if ((order == 1) && (!node->skb))
863bdcd8170SKalle Valo 			break;
864bdcd8170SKalle Valo 
865bdcd8170SKalle Valo 		if (node->skb) {
866bdcd8170SKalle Valo 			if (node->is_amsdu)
867bdcd8170SKalle Valo 				aggr_slice_amsdu(p_aggr, rxtid, node->skb);
868bdcd8170SKalle Valo 			else
869bdcd8170SKalle Valo 				skb_queue_tail(&rxtid->q, node->skb);
870bdcd8170SKalle Valo 			node->skb = NULL;
871bdcd8170SKalle Valo 		} else
872bdcd8170SKalle Valo 			stats->num_hole++;
873bdcd8170SKalle Valo 
874bdcd8170SKalle Valo 		rxtid->seq_next = ATH6KL_NEXT_SEQ_NO(rxtid->seq_next);
875bdcd8170SKalle Valo 		idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz);
876bdcd8170SKalle Valo 	} while (idx != idx_end);
877bdcd8170SKalle Valo 
878bdcd8170SKalle Valo 	spin_unlock_bh(&rxtid->lock);
879bdcd8170SKalle Valo 
880bdcd8170SKalle Valo 	stats->num_delivered += skb_queue_len(&rxtid->q);
881bdcd8170SKalle Valo 
882bdcd8170SKalle Valo 	while ((skb = skb_dequeue(&rxtid->q)))
883bdcd8170SKalle Valo 		ath6kl_deliver_frames_to_nw_stack(p_aggr->dev, skb);
884bdcd8170SKalle Valo }
885bdcd8170SKalle Valo 
886bdcd8170SKalle Valo static bool aggr_process_recv_frm(struct aggr_info *agg_info, u8 tid,
887bdcd8170SKalle Valo 				  u16 seq_no,
888bdcd8170SKalle Valo 				  bool is_amsdu, struct sk_buff *frame)
889bdcd8170SKalle Valo {
890bdcd8170SKalle Valo 	struct rxtid *rxtid;
891bdcd8170SKalle Valo 	struct rxtid_stats *stats;
892bdcd8170SKalle Valo 	struct sk_buff *skb;
893bdcd8170SKalle Valo 	struct skb_hold_q *node;
894bdcd8170SKalle Valo 	u16 idx, st, cur, end;
895bdcd8170SKalle Valo 	bool is_queued = false;
896bdcd8170SKalle Valo 	u16 extended_end;
897bdcd8170SKalle Valo 
898bdcd8170SKalle Valo 	rxtid = &agg_info->rx_tid[tid];
899bdcd8170SKalle Valo 	stats = &agg_info->stat[tid];
900bdcd8170SKalle Valo 
901bdcd8170SKalle Valo 	stats->num_into_aggr++;
902bdcd8170SKalle Valo 
903bdcd8170SKalle Valo 	if (!rxtid->aggr) {
904bdcd8170SKalle Valo 		if (is_amsdu) {
905bdcd8170SKalle Valo 			aggr_slice_amsdu(agg_info, rxtid, frame);
906bdcd8170SKalle Valo 			is_queued = true;
907bdcd8170SKalle Valo 			stats->num_amsdu++;
908bdcd8170SKalle Valo 			while ((skb = skb_dequeue(&rxtid->q)))
909bdcd8170SKalle Valo 				ath6kl_deliver_frames_to_nw_stack(agg_info->dev,
910bdcd8170SKalle Valo 								  skb);
911bdcd8170SKalle Valo 		}
912bdcd8170SKalle Valo 		return is_queued;
913bdcd8170SKalle Valo 	}
914bdcd8170SKalle Valo 
915bdcd8170SKalle Valo 	/* Check the incoming sequence no, if it's in the window */
916bdcd8170SKalle Valo 	st = rxtid->seq_next;
917bdcd8170SKalle Valo 	cur = seq_no;
918bdcd8170SKalle Valo 	end = (st + rxtid->hold_q_sz-1) & ATH6KL_MAX_SEQ_NO;
919bdcd8170SKalle Valo 
920bdcd8170SKalle Valo 	if (((st < end) && (cur < st || cur > end)) ||
921bdcd8170SKalle Valo 	    ((st > end) && (cur > end) && (cur < st))) {
922bdcd8170SKalle Valo 		extended_end = (end + rxtid->hold_q_sz - 1) &
923bdcd8170SKalle Valo 			ATH6KL_MAX_SEQ_NO;
924bdcd8170SKalle Valo 
925bdcd8170SKalle Valo 		if (((end < extended_end) &&
926bdcd8170SKalle Valo 		     (cur < end || cur > extended_end)) ||
927bdcd8170SKalle Valo 		    ((end > extended_end) && (cur > extended_end) &&
928bdcd8170SKalle Valo 		     (cur < end))) {
929bdcd8170SKalle Valo 			aggr_deque_frms(agg_info, tid, 0, 0);
930bdcd8170SKalle Valo 			if (cur >= rxtid->hold_q_sz - 1)
931bdcd8170SKalle Valo 				rxtid->seq_next = cur - (rxtid->hold_q_sz - 1);
932bdcd8170SKalle Valo 			else
933bdcd8170SKalle Valo 				rxtid->seq_next = ATH6KL_MAX_SEQ_NO -
934bdcd8170SKalle Valo 						  (rxtid->hold_q_sz - 2 - cur);
935bdcd8170SKalle Valo 		} else {
936bdcd8170SKalle Valo 			/*
937bdcd8170SKalle Valo 			 * Dequeue only those frames that are outside the
938bdcd8170SKalle Valo 			 * new shifted window.
939bdcd8170SKalle Valo 			 */
940bdcd8170SKalle Valo 			if (cur >= rxtid->hold_q_sz - 1)
941bdcd8170SKalle Valo 				st = cur - (rxtid->hold_q_sz - 1);
942bdcd8170SKalle Valo 			else
943bdcd8170SKalle Valo 				st = ATH6KL_MAX_SEQ_NO -
944bdcd8170SKalle Valo 					(rxtid->hold_q_sz - 2 - cur);
945bdcd8170SKalle Valo 
946bdcd8170SKalle Valo 			aggr_deque_frms(agg_info, tid, st, 0);
947bdcd8170SKalle Valo 		}
948bdcd8170SKalle Valo 
949bdcd8170SKalle Valo 		stats->num_oow++;
950bdcd8170SKalle Valo 	}
951bdcd8170SKalle Valo 
952bdcd8170SKalle Valo 	idx = AGGR_WIN_IDX(seq_no, rxtid->hold_q_sz);
953bdcd8170SKalle Valo 
954bdcd8170SKalle Valo 	node = &rxtid->hold_q[idx];
955bdcd8170SKalle Valo 
956bdcd8170SKalle Valo 	spin_lock_bh(&rxtid->lock);
957bdcd8170SKalle Valo 
958bdcd8170SKalle Valo 	/*
959bdcd8170SKalle Valo 	 * Is the cur frame duplicate or something beyond our window(hold_q
960bdcd8170SKalle Valo 	 * -> which is 2x, already)?
961bdcd8170SKalle Valo 	 *
962bdcd8170SKalle Valo 	 * 1. Duplicate is easy - drop incoming frame.
963bdcd8170SKalle Valo 	 * 2. Not falling in current sliding window.
964bdcd8170SKalle Valo 	 *  2a. is the frame_seq_no preceding current tid_seq_no?
965bdcd8170SKalle Valo 	 *      -> drop the frame. perhaps sender did not get our ACK.
966bdcd8170SKalle Valo 	 *         this is taken care of above.
967bdcd8170SKalle Valo 	 *  2b. is the frame_seq_no beyond window(st, TID_WINDOW_SZ);
968bdcd8170SKalle Valo 	 *      -> Taken care of it above, by moving window forward.
969bdcd8170SKalle Valo 	 */
970bdcd8170SKalle Valo 	dev_kfree_skb(node->skb);
971bdcd8170SKalle Valo 	stats->num_dups++;
972bdcd8170SKalle Valo 
973bdcd8170SKalle Valo 	node->skb = frame;
974bdcd8170SKalle Valo 	is_queued = true;
975bdcd8170SKalle Valo 	node->is_amsdu = is_amsdu;
976bdcd8170SKalle Valo 	node->seq_no = seq_no;
977bdcd8170SKalle Valo 
978bdcd8170SKalle Valo 	if (node->is_amsdu)
979bdcd8170SKalle Valo 		stats->num_amsdu++;
980bdcd8170SKalle Valo 	else
981bdcd8170SKalle Valo 		stats->num_mpdu++;
982bdcd8170SKalle Valo 
983bdcd8170SKalle Valo 	spin_unlock_bh(&rxtid->lock);
984bdcd8170SKalle Valo 
985bdcd8170SKalle Valo 	aggr_deque_frms(agg_info, tid, 0, 1);
986bdcd8170SKalle Valo 
987bdcd8170SKalle Valo 	if (agg_info->timer_scheduled)
988bdcd8170SKalle Valo 		rxtid->progress = true;
989bdcd8170SKalle Valo 	else
990bdcd8170SKalle Valo 		for (idx = 0 ; idx < rxtid->hold_q_sz; idx++) {
991bdcd8170SKalle Valo 			if (rxtid->hold_q[idx].skb) {
992bdcd8170SKalle Valo 				/*
993bdcd8170SKalle Valo 				 * There is a frame in the queue and no
994bdcd8170SKalle Valo 				 * timer so start a timer to ensure that
995bdcd8170SKalle Valo 				 * the frame doesn't remain stuck
996bdcd8170SKalle Valo 				 * forever.
997bdcd8170SKalle Valo 				 */
998bdcd8170SKalle Valo 				agg_info->timer_scheduled = true;
999bdcd8170SKalle Valo 				mod_timer(&agg_info->timer,
1000bdcd8170SKalle Valo 					  (jiffies +
1001bdcd8170SKalle Valo 					   HZ * (AGGR_RX_TIMEOUT) / 1000));
1002bdcd8170SKalle Valo 				rxtid->progress = false;
1003bdcd8170SKalle Valo 				rxtid->timer_mon = true;
1004bdcd8170SKalle Valo 				break;
1005bdcd8170SKalle Valo 			}
1006bdcd8170SKalle Valo 		}
1007bdcd8170SKalle Valo 
1008bdcd8170SKalle Valo 	return is_queued;
1009bdcd8170SKalle Valo }
1010bdcd8170SKalle Valo 
1011bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet)
1012bdcd8170SKalle Valo {
1013bdcd8170SKalle Valo 	struct ath6kl *ar = target->dev->ar;
1014bdcd8170SKalle Valo 	struct sk_buff *skb = packet->pkt_cntxt;
1015bdcd8170SKalle Valo 	struct wmi_rx_meta_v2 *meta;
1016bdcd8170SKalle Valo 	struct wmi_data_hdr *dhdr;
1017bdcd8170SKalle Valo 	int min_hdr_len;
1018bdcd8170SKalle Valo 	u8 meta_type, dot11_hdr = 0;
1019bdcd8170SKalle Valo 	int status = packet->status;
1020bdcd8170SKalle Valo 	enum htc_endpoint_id ept = packet->endpoint;
1021bdcd8170SKalle Valo 	bool is_amsdu, prev_ps, ps_state = false;
1022bdcd8170SKalle Valo 	struct ath6kl_sta *conn = NULL;
1023bdcd8170SKalle Valo 	struct sk_buff *skb1 = NULL;
1024bdcd8170SKalle Valo 	struct ethhdr *datap = NULL;
1025bdcd8170SKalle Valo 	u16 seq_no, offset;
1026bdcd8170SKalle Valo 	u8 tid;
1027bdcd8170SKalle Valo 
1028bdcd8170SKalle Valo 	ath6kl_dbg(ATH6KL_DBG_WLAN_RX,
1029bdcd8170SKalle Valo 		   "%s: ar=0x%p eid=%d, skb=0x%p, data=0x%p, len=0x%x status:%d",
1030bdcd8170SKalle Valo 		   __func__, ar, ept, skb, packet->buf,
1031bdcd8170SKalle Valo 		   packet->act_len, status);
1032bdcd8170SKalle Valo 
1033bdcd8170SKalle Valo 	if (status || !(skb->data + HTC_HDR_LENGTH)) {
1034bdcd8170SKalle Valo 		ar->net_stats.rx_errors++;
1035bdcd8170SKalle Valo 		dev_kfree_skb(skb);
1036bdcd8170SKalle Valo 		return;
1037bdcd8170SKalle Valo 	}
1038bdcd8170SKalle Valo 
1039bdcd8170SKalle Valo 	/*
1040bdcd8170SKalle Valo 	 * Take lock to protect buffer counts and adaptive power throughput
1041bdcd8170SKalle Valo 	 * state.
1042bdcd8170SKalle Valo 	 */
1043bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
1044bdcd8170SKalle Valo 
1045bdcd8170SKalle Valo 	ar->net_stats.rx_packets++;
1046bdcd8170SKalle Valo 	ar->net_stats.rx_bytes += packet->act_len;
1047bdcd8170SKalle Valo 
104883dc5f2fSVasanthakumar Thiagarajan 	spin_unlock_bh(&ar->lock);
104983dc5f2fSVasanthakumar Thiagarajan 
1050bdcd8170SKalle Valo 	skb_put(skb, packet->act_len + HTC_HDR_LENGTH);
1051bdcd8170SKalle Valo 	skb_pull(skb, HTC_HDR_LENGTH);
1052bdcd8170SKalle Valo 
1053bdcd8170SKalle Valo 	ath6kl_dbg_dump(ATH6KL_DBG_RAW_BYTES, __func__, skb->data, skb->len);
1054bdcd8170SKalle Valo 
1055bdcd8170SKalle Valo 	skb->dev = ar->net_dev;
1056bdcd8170SKalle Valo 
1057bdcd8170SKalle Valo 	if (!test_bit(WMI_ENABLED, &ar->flag)) {
1058bdcd8170SKalle Valo 		if (EPPING_ALIGNMENT_PAD > 0)
1059bdcd8170SKalle Valo 			skb_pull(skb, EPPING_ALIGNMENT_PAD);
1060bdcd8170SKalle Valo 		ath6kl_deliver_frames_to_nw_stack(ar->net_dev, skb);
1061bdcd8170SKalle Valo 		return;
1062bdcd8170SKalle Valo 	}
1063bdcd8170SKalle Valo 
1064bdcd8170SKalle Valo 	if (ept == ar->ctrl_ep) {
1065bdcd8170SKalle Valo 		ath6kl_wmi_control_rx(ar->wmi, skb);
1066bdcd8170SKalle Valo 		return;
1067bdcd8170SKalle Valo 	}
1068bdcd8170SKalle Valo 
106967f9178fSVasanthakumar Thiagarajan 	min_hdr_len = sizeof(struct ethhdr) + sizeof(struct wmi_data_hdr) +
1070bdcd8170SKalle Valo 		      sizeof(struct ath6kl_llc_snap_hdr);
1071bdcd8170SKalle Valo 
1072bdcd8170SKalle Valo 	dhdr = (struct wmi_data_hdr *) skb->data;
1073bdcd8170SKalle Valo 
1074bdcd8170SKalle Valo 	/*
1075bdcd8170SKalle Valo 	 * In the case of AP mode we may receive NULL data frames
1076bdcd8170SKalle Valo 	 * that do not have LLC hdr. They are 16 bytes in size.
1077bdcd8170SKalle Valo 	 * Allow these frames in the AP mode.
1078bdcd8170SKalle Valo 	 */
1079bdcd8170SKalle Valo 	if (ar->nw_type != AP_NETWORK &&
1080bdcd8170SKalle Valo 	    ((packet->act_len < min_hdr_len) ||
1081bdcd8170SKalle Valo 	     (packet->act_len > WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH))) {
1082bdcd8170SKalle Valo 		ath6kl_info("frame len is too short or too long\n");
1083bdcd8170SKalle Valo 		ar->net_stats.rx_errors++;
1084bdcd8170SKalle Valo 		ar->net_stats.rx_length_errors++;
1085bdcd8170SKalle Valo 		dev_kfree_skb(skb);
1086bdcd8170SKalle Valo 		return;
1087bdcd8170SKalle Valo 	}
1088bdcd8170SKalle Valo 
1089bdcd8170SKalle Valo 	/* Get the Power save state of the STA */
1090bdcd8170SKalle Valo 	if (ar->nw_type == AP_NETWORK) {
1091bdcd8170SKalle Valo 		meta_type = wmi_data_hdr_get_meta(dhdr);
1092bdcd8170SKalle Valo 
1093bdcd8170SKalle Valo 		ps_state = !!((dhdr->info >> WMI_DATA_HDR_PS_SHIFT) &
1094bdcd8170SKalle Valo 			      WMI_DATA_HDR_PS_MASK);
1095bdcd8170SKalle Valo 
1096bdcd8170SKalle Valo 		offset = sizeof(struct wmi_data_hdr);
1097bdcd8170SKalle Valo 
1098bdcd8170SKalle Valo 		switch (meta_type) {
1099bdcd8170SKalle Valo 		case 0:
1100bdcd8170SKalle Valo 			break;
1101bdcd8170SKalle Valo 		case WMI_META_VERSION_1:
1102bdcd8170SKalle Valo 			offset += sizeof(struct wmi_rx_meta_v1);
1103bdcd8170SKalle Valo 			break;
1104bdcd8170SKalle Valo 		case WMI_META_VERSION_2:
1105bdcd8170SKalle Valo 			offset += sizeof(struct wmi_rx_meta_v2);
1106bdcd8170SKalle Valo 			break;
1107bdcd8170SKalle Valo 		default:
1108bdcd8170SKalle Valo 			break;
1109bdcd8170SKalle Valo 		}
1110bdcd8170SKalle Valo 
1111bdcd8170SKalle Valo 		datap = (struct ethhdr *) (skb->data + offset);
1112bdcd8170SKalle Valo 		conn = ath6kl_find_sta(ar, datap->h_source);
1113bdcd8170SKalle Valo 
1114bdcd8170SKalle Valo 		if (!conn) {
1115bdcd8170SKalle Valo 			dev_kfree_skb(skb);
1116bdcd8170SKalle Valo 			return;
1117bdcd8170SKalle Valo 		}
1118bdcd8170SKalle Valo 
1119bdcd8170SKalle Valo 		/*
1120bdcd8170SKalle Valo 		 * If there is a change in PS state of the STA,
1121bdcd8170SKalle Valo 		 * take appropriate steps:
1122bdcd8170SKalle Valo 		 *
1123bdcd8170SKalle Valo 		 * 1. If Sleep-->Awake, flush the psq for the STA
1124bdcd8170SKalle Valo 		 *    Clear the PVB for the STA.
1125bdcd8170SKalle Valo 		 * 2. If Awake-->Sleep, Starting queueing frames
1126bdcd8170SKalle Valo 		 *    the STA.
1127bdcd8170SKalle Valo 		 */
1128bdcd8170SKalle Valo 		prev_ps = !!(conn->sta_flags & STA_PS_SLEEP);
1129bdcd8170SKalle Valo 
1130bdcd8170SKalle Valo 		if (ps_state)
1131bdcd8170SKalle Valo 			conn->sta_flags |= STA_PS_SLEEP;
1132bdcd8170SKalle Valo 		else
1133bdcd8170SKalle Valo 			conn->sta_flags &= ~STA_PS_SLEEP;
1134bdcd8170SKalle Valo 
1135bdcd8170SKalle Valo 		if (prev_ps ^ !!(conn->sta_flags & STA_PS_SLEEP)) {
1136bdcd8170SKalle Valo 			if (!(conn->sta_flags & STA_PS_SLEEP)) {
1137bdcd8170SKalle Valo 				struct sk_buff *skbuff = NULL;
1138bdcd8170SKalle Valo 
1139bdcd8170SKalle Valo 				spin_lock_bh(&conn->psq_lock);
1140bdcd8170SKalle Valo 				while ((skbuff = skb_dequeue(&conn->psq))
1141bdcd8170SKalle Valo 				       != NULL) {
1142bdcd8170SKalle Valo 					spin_unlock_bh(&conn->psq_lock);
1143bdcd8170SKalle Valo 					ath6kl_data_tx(skbuff, ar->net_dev);
1144bdcd8170SKalle Valo 					spin_lock_bh(&conn->psq_lock);
1145bdcd8170SKalle Valo 				}
1146bdcd8170SKalle Valo 				spin_unlock_bh(&conn->psq_lock);
1147bdcd8170SKalle Valo 				/* Clear the PVB for this STA */
1148bdcd8170SKalle Valo 				ath6kl_wmi_set_pvb_cmd(ar->wmi, conn->aid, 0);
1149bdcd8170SKalle Valo 			}
1150bdcd8170SKalle Valo 		}
1151bdcd8170SKalle Valo 
1152bdcd8170SKalle Valo 		/* drop NULL data frames here */
1153bdcd8170SKalle Valo 		if ((packet->act_len < min_hdr_len) ||
1154bdcd8170SKalle Valo 		    (packet->act_len >
1155bdcd8170SKalle Valo 		     WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH)) {
1156bdcd8170SKalle Valo 			dev_kfree_skb(skb);
1157bdcd8170SKalle Valo 			return;
1158bdcd8170SKalle Valo 		}
1159bdcd8170SKalle Valo 	}
1160bdcd8170SKalle Valo 
1161bdcd8170SKalle Valo 	is_amsdu = wmi_data_hdr_is_amsdu(dhdr) ? true : false;
1162bdcd8170SKalle Valo 	tid = wmi_data_hdr_get_up(dhdr);
1163bdcd8170SKalle Valo 	seq_no = wmi_data_hdr_get_seqno(dhdr);
1164bdcd8170SKalle Valo 	meta_type = wmi_data_hdr_get_meta(dhdr);
1165bdcd8170SKalle Valo 	dot11_hdr = wmi_data_hdr_get_dot11(dhdr);
1166594a0bc8SVasanthakumar Thiagarajan 	skb_pull(skb, sizeof(struct wmi_data_hdr));
1167bdcd8170SKalle Valo 
1168bdcd8170SKalle Valo 	switch (meta_type) {
1169bdcd8170SKalle Valo 	case WMI_META_VERSION_1:
1170bdcd8170SKalle Valo 		skb_pull(skb, sizeof(struct wmi_rx_meta_v1));
1171bdcd8170SKalle Valo 		break;
1172bdcd8170SKalle Valo 	case WMI_META_VERSION_2:
1173bdcd8170SKalle Valo 		meta = (struct wmi_rx_meta_v2 *) skb->data;
1174bdcd8170SKalle Valo 		if (meta->csum_flags & 0x1) {
1175bdcd8170SKalle Valo 			skb->ip_summed = CHECKSUM_COMPLETE;
1176bdcd8170SKalle Valo 			skb->csum = (__force __wsum) meta->csum;
1177bdcd8170SKalle Valo 		}
1178bdcd8170SKalle Valo 		skb_pull(skb, sizeof(struct wmi_rx_meta_v2));
1179bdcd8170SKalle Valo 		break;
1180bdcd8170SKalle Valo 	default:
1181bdcd8170SKalle Valo 		break;
1182bdcd8170SKalle Valo 	}
1183bdcd8170SKalle Valo 
1184bdcd8170SKalle Valo 	if (dot11_hdr)
1185bdcd8170SKalle Valo 		status = ath6kl_wmi_dot11_hdr_remove(ar->wmi, skb);
1186bdcd8170SKalle Valo 	else if (!is_amsdu)
1187bdcd8170SKalle Valo 		status = ath6kl_wmi_dot3_2_dix(skb);
1188bdcd8170SKalle Valo 
1189bdcd8170SKalle Valo 	if (status) {
1190bdcd8170SKalle Valo 		/*
1191bdcd8170SKalle Valo 		 * Drop frames that could not be processed (lack of
1192bdcd8170SKalle Valo 		 * memory, etc.)
1193bdcd8170SKalle Valo 		 */
1194bdcd8170SKalle Valo 		dev_kfree_skb(skb);
1195bdcd8170SKalle Valo 		return;
1196bdcd8170SKalle Valo 	}
1197bdcd8170SKalle Valo 
1198bdcd8170SKalle Valo 	if (!(ar->net_dev->flags & IFF_UP)) {
1199bdcd8170SKalle Valo 		dev_kfree_skb(skb);
1200bdcd8170SKalle Valo 		return;
1201bdcd8170SKalle Valo 	}
1202bdcd8170SKalle Valo 
1203bdcd8170SKalle Valo 	if (ar->nw_type == AP_NETWORK) {
1204bdcd8170SKalle Valo 		datap = (struct ethhdr *) skb->data;
1205bdcd8170SKalle Valo 		if (is_multicast_ether_addr(datap->h_dest))
1206bdcd8170SKalle Valo 			/*
1207bdcd8170SKalle Valo 			 * Bcast/Mcast frames should be sent to the
1208bdcd8170SKalle Valo 			 * OS stack as well as on the air.
1209bdcd8170SKalle Valo 			 */
1210bdcd8170SKalle Valo 			skb1 = skb_copy(skb, GFP_ATOMIC);
1211bdcd8170SKalle Valo 		else {
1212bdcd8170SKalle Valo 			/*
1213bdcd8170SKalle Valo 			 * Search for a connected STA with dstMac
1214bdcd8170SKalle Valo 			 * as the Mac address. If found send the
1215bdcd8170SKalle Valo 			 * frame to it on the air else send the
1216bdcd8170SKalle Valo 			 * frame up the stack.
1217bdcd8170SKalle Valo 			 */
1218bdcd8170SKalle Valo 			struct ath6kl_sta *conn = NULL;
1219bdcd8170SKalle Valo 			conn = ath6kl_find_sta(ar, datap->h_dest);
1220bdcd8170SKalle Valo 
1221bdcd8170SKalle Valo 			if (conn && ar->intra_bss) {
1222bdcd8170SKalle Valo 				skb1 = skb;
1223bdcd8170SKalle Valo 				skb = NULL;
1224bdcd8170SKalle Valo 			} else if (conn && !ar->intra_bss) {
1225bdcd8170SKalle Valo 				dev_kfree_skb(skb);
1226bdcd8170SKalle Valo 				skb = NULL;
1227bdcd8170SKalle Valo 			}
1228bdcd8170SKalle Valo 		}
1229bdcd8170SKalle Valo 		if (skb1)
1230bdcd8170SKalle Valo 			ath6kl_data_tx(skb1, ar->net_dev);
1231bdcd8170SKalle Valo 	}
1232bdcd8170SKalle Valo 
1233*5694f962SKalle Valo 	datap = (struct ethhdr *) skb->data;
1234*5694f962SKalle Valo 
1235*5694f962SKalle Valo 	if (is_unicast_ether_addr(datap->h_dest) &&
1236*5694f962SKalle Valo 	    aggr_process_recv_frm(ar->aggr_cntxt, tid, seq_no,
1237bdcd8170SKalle Valo 				  is_amsdu, skb))
1238*5694f962SKalle Valo 		/* aggregation code will handle the skb */
1239*5694f962SKalle Valo 		return;
1240*5694f962SKalle Valo 
1241bdcd8170SKalle Valo 	ath6kl_deliver_frames_to_nw_stack(ar->net_dev, skb);
1242bdcd8170SKalle Valo }
1243bdcd8170SKalle Valo 
1244bdcd8170SKalle Valo static void aggr_timeout(unsigned long arg)
1245bdcd8170SKalle Valo {
1246bdcd8170SKalle Valo 	u8 i, j;
1247bdcd8170SKalle Valo 	struct aggr_info *p_aggr = (struct aggr_info *) arg;
1248bdcd8170SKalle Valo 	struct rxtid *rxtid;
1249bdcd8170SKalle Valo 	struct rxtid_stats *stats;
1250bdcd8170SKalle Valo 
1251bdcd8170SKalle Valo 	for (i = 0; i < NUM_OF_TIDS; i++) {
1252bdcd8170SKalle Valo 		rxtid = &p_aggr->rx_tid[i];
1253bdcd8170SKalle Valo 		stats = &p_aggr->stat[i];
1254bdcd8170SKalle Valo 
1255bdcd8170SKalle Valo 		if (!rxtid->aggr || !rxtid->timer_mon || rxtid->progress)
1256bdcd8170SKalle Valo 			continue;
1257bdcd8170SKalle Valo 
1258bdcd8170SKalle Valo 		stats->num_timeouts++;
125937ca6335SKalle Valo 		ath6kl_dbg(ATH6KL_DBG_AGGR,
126037ca6335SKalle Valo 			   "aggr timeout (st %d end %d)\n",
1261bdcd8170SKalle Valo 			   rxtid->seq_next,
1262bdcd8170SKalle Valo 			   ((rxtid->seq_next + rxtid->hold_q_sz-1) &
1263bdcd8170SKalle Valo 			    ATH6KL_MAX_SEQ_NO));
1264bdcd8170SKalle Valo 		aggr_deque_frms(p_aggr, i, 0, 0);
1265bdcd8170SKalle Valo 	}
1266bdcd8170SKalle Valo 
1267bdcd8170SKalle Valo 	p_aggr->timer_scheduled = false;
1268bdcd8170SKalle Valo 
1269bdcd8170SKalle Valo 	for (i = 0; i < NUM_OF_TIDS; i++) {
1270bdcd8170SKalle Valo 		rxtid = &p_aggr->rx_tid[i];
1271bdcd8170SKalle Valo 
1272bdcd8170SKalle Valo 		if (rxtid->aggr && rxtid->hold_q) {
1273bdcd8170SKalle Valo 			for (j = 0; j < rxtid->hold_q_sz; j++) {
1274bdcd8170SKalle Valo 				if (rxtid->hold_q[j].skb) {
1275bdcd8170SKalle Valo 					p_aggr->timer_scheduled = true;
1276bdcd8170SKalle Valo 					rxtid->timer_mon = true;
1277bdcd8170SKalle Valo 					rxtid->progress = false;
1278bdcd8170SKalle Valo 					break;
1279bdcd8170SKalle Valo 				}
1280bdcd8170SKalle Valo 			}
1281bdcd8170SKalle Valo 
1282bdcd8170SKalle Valo 			if (j >= rxtid->hold_q_sz)
1283bdcd8170SKalle Valo 				rxtid->timer_mon = false;
1284bdcd8170SKalle Valo 		}
1285bdcd8170SKalle Valo 	}
1286bdcd8170SKalle Valo 
1287bdcd8170SKalle Valo 	if (p_aggr->timer_scheduled)
1288bdcd8170SKalle Valo 		mod_timer(&p_aggr->timer,
1289bdcd8170SKalle Valo 			  jiffies + msecs_to_jiffies(AGGR_RX_TIMEOUT));
1290bdcd8170SKalle Valo }
1291bdcd8170SKalle Valo 
1292bdcd8170SKalle Valo static void aggr_delete_tid_state(struct aggr_info *p_aggr, u8 tid)
1293bdcd8170SKalle Valo {
1294bdcd8170SKalle Valo 	struct rxtid *rxtid;
1295bdcd8170SKalle Valo 	struct rxtid_stats *stats;
1296bdcd8170SKalle Valo 
1297bdcd8170SKalle Valo 	if (!p_aggr || tid >= NUM_OF_TIDS)
1298bdcd8170SKalle Valo 		return;
1299bdcd8170SKalle Valo 
1300bdcd8170SKalle Valo 	rxtid = &p_aggr->rx_tid[tid];
1301bdcd8170SKalle Valo 	stats = &p_aggr->stat[tid];
1302bdcd8170SKalle Valo 
1303bdcd8170SKalle Valo 	if (rxtid->aggr)
1304bdcd8170SKalle Valo 		aggr_deque_frms(p_aggr, tid, 0, 0);
1305bdcd8170SKalle Valo 
1306bdcd8170SKalle Valo 	rxtid->aggr = false;
1307bdcd8170SKalle Valo 	rxtid->progress = false;
1308bdcd8170SKalle Valo 	rxtid->timer_mon = false;
1309bdcd8170SKalle Valo 	rxtid->win_sz = 0;
1310bdcd8170SKalle Valo 	rxtid->seq_next = 0;
1311bdcd8170SKalle Valo 	rxtid->hold_q_sz = 0;
1312bdcd8170SKalle Valo 
1313bdcd8170SKalle Valo 	kfree(rxtid->hold_q);
1314bdcd8170SKalle Valo 	rxtid->hold_q = NULL;
1315bdcd8170SKalle Valo 
1316bdcd8170SKalle Valo 	memset(stats, 0, sizeof(struct rxtid_stats));
1317bdcd8170SKalle Valo }
1318bdcd8170SKalle Valo 
1319bdcd8170SKalle Valo void aggr_recv_addba_req_evt(struct ath6kl *ar, u8 tid, u16 seq_no, u8 win_sz)
1320bdcd8170SKalle Valo {
1321bdcd8170SKalle Valo 	struct aggr_info *p_aggr = ar->aggr_cntxt;
1322bdcd8170SKalle Valo 	struct rxtid *rxtid;
1323bdcd8170SKalle Valo 	struct rxtid_stats *stats;
1324bdcd8170SKalle Valo 	u16 hold_q_size;
1325bdcd8170SKalle Valo 
1326bdcd8170SKalle Valo 	if (!p_aggr)
1327bdcd8170SKalle Valo 		return;
1328bdcd8170SKalle Valo 
1329bdcd8170SKalle Valo 	rxtid = &p_aggr->rx_tid[tid];
1330bdcd8170SKalle Valo 	stats = &p_aggr->stat[tid];
1331bdcd8170SKalle Valo 
1332bdcd8170SKalle Valo 	if (win_sz < AGGR_WIN_SZ_MIN || win_sz > AGGR_WIN_SZ_MAX)
1333bdcd8170SKalle Valo 		ath6kl_dbg(ATH6KL_DBG_WLAN_RX, "%s: win_sz %d, tid %d\n",
1334bdcd8170SKalle Valo 			   __func__, win_sz, tid);
1335bdcd8170SKalle Valo 
1336bdcd8170SKalle Valo 	if (rxtid->aggr)
1337bdcd8170SKalle Valo 		aggr_delete_tid_state(p_aggr, tid);
1338bdcd8170SKalle Valo 
1339bdcd8170SKalle Valo 	rxtid->seq_next = seq_no;
1340bdcd8170SKalle Valo 	hold_q_size = TID_WINDOW_SZ(win_sz) * sizeof(struct skb_hold_q);
1341bdcd8170SKalle Valo 	rxtid->hold_q = kzalloc(hold_q_size, GFP_KERNEL);
1342bdcd8170SKalle Valo 	if (!rxtid->hold_q)
1343bdcd8170SKalle Valo 		return;
1344bdcd8170SKalle Valo 
1345bdcd8170SKalle Valo 	rxtid->win_sz = win_sz;
1346bdcd8170SKalle Valo 	rxtid->hold_q_sz = TID_WINDOW_SZ(win_sz);
1347bdcd8170SKalle Valo 	if (!skb_queue_empty(&rxtid->q))
1348bdcd8170SKalle Valo 		return;
1349bdcd8170SKalle Valo 
1350bdcd8170SKalle Valo 	rxtid->aggr = true;
1351bdcd8170SKalle Valo }
1352bdcd8170SKalle Valo 
1353bdcd8170SKalle Valo struct aggr_info *aggr_init(struct net_device *dev)
1354bdcd8170SKalle Valo {
1355bdcd8170SKalle Valo 	struct aggr_info *p_aggr = NULL;
1356bdcd8170SKalle Valo 	struct rxtid *rxtid;
1357bdcd8170SKalle Valo 	u8 i;
1358bdcd8170SKalle Valo 
1359bdcd8170SKalle Valo 	p_aggr = kzalloc(sizeof(struct aggr_info), GFP_KERNEL);
1360bdcd8170SKalle Valo 	if (!p_aggr) {
1361bdcd8170SKalle Valo 		ath6kl_err("failed to alloc memory for aggr_node\n");
1362bdcd8170SKalle Valo 		return NULL;
1363bdcd8170SKalle Valo 	}
1364bdcd8170SKalle Valo 
1365bdcd8170SKalle Valo 	p_aggr->aggr_sz = AGGR_SZ_DEFAULT;
1366bdcd8170SKalle Valo 	p_aggr->dev = dev;
1367bdcd8170SKalle Valo 	init_timer(&p_aggr->timer);
1368bdcd8170SKalle Valo 	p_aggr->timer.function = aggr_timeout;
1369bdcd8170SKalle Valo 	p_aggr->timer.data = (unsigned long) p_aggr;
1370bdcd8170SKalle Valo 
1371bdcd8170SKalle Valo 	p_aggr->timer_scheduled = false;
1372bdcd8170SKalle Valo 	skb_queue_head_init(&p_aggr->free_q);
1373bdcd8170SKalle Valo 
1374bdcd8170SKalle Valo 	ath6kl_alloc_netbufs(&p_aggr->free_q, AGGR_NUM_OF_FREE_NETBUFS);
1375bdcd8170SKalle Valo 
1376bdcd8170SKalle Valo 	for (i = 0; i < NUM_OF_TIDS; i++) {
1377bdcd8170SKalle Valo 		rxtid = &p_aggr->rx_tid[i];
1378bdcd8170SKalle Valo 		rxtid->aggr = false;
1379bdcd8170SKalle Valo 		rxtid->progress = false;
1380bdcd8170SKalle Valo 		rxtid->timer_mon = false;
1381bdcd8170SKalle Valo 		skb_queue_head_init(&rxtid->q);
1382bdcd8170SKalle Valo 		spin_lock_init(&rxtid->lock);
1383bdcd8170SKalle Valo 	}
1384bdcd8170SKalle Valo 
1385bdcd8170SKalle Valo 	return p_aggr;
1386bdcd8170SKalle Valo }
1387bdcd8170SKalle Valo 
1388bdcd8170SKalle Valo void aggr_recv_delba_req_evt(struct ath6kl *ar, u8 tid)
1389bdcd8170SKalle Valo {
1390bdcd8170SKalle Valo 	struct aggr_info *p_aggr = ar->aggr_cntxt;
1391bdcd8170SKalle Valo 	struct rxtid *rxtid;
1392bdcd8170SKalle Valo 
1393bdcd8170SKalle Valo 	if (!p_aggr)
1394bdcd8170SKalle Valo 		return;
1395bdcd8170SKalle Valo 
1396bdcd8170SKalle Valo 	rxtid = &p_aggr->rx_tid[tid];
1397bdcd8170SKalle Valo 
1398bdcd8170SKalle Valo 	if (rxtid->aggr)
1399bdcd8170SKalle Valo 		aggr_delete_tid_state(p_aggr, tid);
1400bdcd8170SKalle Valo }
1401bdcd8170SKalle Valo 
1402bdcd8170SKalle Valo void aggr_reset_state(struct aggr_info *aggr_info)
1403bdcd8170SKalle Valo {
1404bdcd8170SKalle Valo 	u8 tid;
1405bdcd8170SKalle Valo 
1406bdcd8170SKalle Valo 	for (tid = 0; tid < NUM_OF_TIDS; tid++)
1407bdcd8170SKalle Valo 		aggr_delete_tid_state(aggr_info, tid);
1408bdcd8170SKalle Valo }
1409bdcd8170SKalle Valo 
1410bdcd8170SKalle Valo /* clean up our amsdu buffer list */
1411bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar)
1412bdcd8170SKalle Valo {
1413bdcd8170SKalle Valo 	struct htc_packet *packet, *tmp_pkt;
1414bdcd8170SKalle Valo 
1415bdcd8170SKalle Valo 	spin_lock_bh(&ar->lock);
1416bdcd8170SKalle Valo 	if (list_empty(&ar->amsdu_rx_buffer_queue)) {
1417bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
1418bdcd8170SKalle Valo 		return;
1419bdcd8170SKalle Valo 	}
1420bdcd8170SKalle Valo 
1421bdcd8170SKalle Valo 	list_for_each_entry_safe(packet, tmp_pkt, &ar->amsdu_rx_buffer_queue,
1422bdcd8170SKalle Valo 				 list) {
1423bdcd8170SKalle Valo 		list_del(&packet->list);
1424bdcd8170SKalle Valo 		spin_unlock_bh(&ar->lock);
1425bdcd8170SKalle Valo 		dev_kfree_skb(packet->pkt_cntxt);
1426bdcd8170SKalle Valo 		spin_lock_bh(&ar->lock);
1427bdcd8170SKalle Valo 	}
1428bdcd8170SKalle Valo 
1429bdcd8170SKalle Valo 	spin_unlock_bh(&ar->lock);
1430bdcd8170SKalle Valo }
1431bdcd8170SKalle Valo 
1432bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info)
1433bdcd8170SKalle Valo {
1434bdcd8170SKalle Valo 	struct rxtid *rxtid;
1435bdcd8170SKalle Valo 	u8 i, k;
1436bdcd8170SKalle Valo 
1437bdcd8170SKalle Valo 	if (!aggr_info)
1438bdcd8170SKalle Valo 		return;
1439bdcd8170SKalle Valo 
1440bdcd8170SKalle Valo 	if (aggr_info->timer_scheduled) {
1441bdcd8170SKalle Valo 		del_timer(&aggr_info->timer);
1442bdcd8170SKalle Valo 		aggr_info->timer_scheduled = false;
1443bdcd8170SKalle Valo 	}
1444bdcd8170SKalle Valo 
1445bdcd8170SKalle Valo 	for (i = 0; i < NUM_OF_TIDS; i++) {
1446bdcd8170SKalle Valo 		rxtid = &aggr_info->rx_tid[i];
1447bdcd8170SKalle Valo 		if (rxtid->hold_q) {
1448bdcd8170SKalle Valo 			for (k = 0; k < rxtid->hold_q_sz; k++)
1449bdcd8170SKalle Valo 				dev_kfree_skb(rxtid->hold_q[k].skb);
1450bdcd8170SKalle Valo 			kfree(rxtid->hold_q);
1451bdcd8170SKalle Valo 		}
1452bdcd8170SKalle Valo 
1453bdcd8170SKalle Valo 		skb_queue_purge(&rxtid->q);
1454bdcd8170SKalle Valo 	}
1455bdcd8170SKalle Valo 
1456bdcd8170SKalle Valo 	skb_queue_purge(&aggr_info->free_q);
1457bdcd8170SKalle Valo 	kfree(aggr_info);
1458bdcd8170SKalle Valo }
1459