1bdcd8170SKalle Valo /* 2bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 3bdcd8170SKalle Valo * 4bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7bdcd8170SKalle Valo * 8bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15bdcd8170SKalle Valo */ 16bdcd8170SKalle Valo 17bdcd8170SKalle Valo #include "core.h" 18bdcd8170SKalle Valo #include "debug.h" 19bdcd8170SKalle Valo 20bdcd8170SKalle Valo static u8 ath6kl_ibss_map_epid(struct sk_buff *skb, struct net_device *dev, 21bdcd8170SKalle Valo u32 *map_no) 22bdcd8170SKalle Valo { 23bdcd8170SKalle Valo struct ath6kl *ar = ath6kl_priv(dev); 24bdcd8170SKalle Valo struct ethhdr *eth_hdr; 25bdcd8170SKalle Valo u32 i, ep_map = -1; 26bdcd8170SKalle Valo u8 *datap; 27bdcd8170SKalle Valo 28bdcd8170SKalle Valo *map_no = 0; 29bdcd8170SKalle Valo datap = skb->data; 30bdcd8170SKalle Valo eth_hdr = (struct ethhdr *) (datap + sizeof(struct wmi_data_hdr)); 31bdcd8170SKalle Valo 32bdcd8170SKalle Valo if (is_multicast_ether_addr(eth_hdr->h_dest)) 33bdcd8170SKalle Valo return ENDPOINT_2; 34bdcd8170SKalle Valo 35bdcd8170SKalle Valo for (i = 0; i < ar->node_num; i++) { 36bdcd8170SKalle Valo if (memcmp(eth_hdr->h_dest, ar->node_map[i].mac_addr, 37bdcd8170SKalle Valo ETH_ALEN) == 0) { 38bdcd8170SKalle Valo *map_no = i + 1; 39bdcd8170SKalle Valo ar->node_map[i].tx_pend++; 40bdcd8170SKalle Valo return ar->node_map[i].ep_id; 41bdcd8170SKalle Valo } 42bdcd8170SKalle Valo 43bdcd8170SKalle Valo if ((ep_map == -1) && !ar->node_map[i].tx_pend) 44bdcd8170SKalle Valo ep_map = i; 45bdcd8170SKalle Valo } 46bdcd8170SKalle Valo 47bdcd8170SKalle Valo if (ep_map == -1) { 48bdcd8170SKalle Valo ep_map = ar->node_num; 49bdcd8170SKalle Valo ar->node_num++; 50bdcd8170SKalle Valo if (ar->node_num > MAX_NODE_NUM) 51bdcd8170SKalle Valo return ENDPOINT_UNUSED; 52bdcd8170SKalle Valo } 53bdcd8170SKalle Valo 54bdcd8170SKalle Valo memcpy(ar->node_map[ep_map].mac_addr, eth_hdr->h_dest, ETH_ALEN); 55bdcd8170SKalle Valo 56bdcd8170SKalle Valo for (i = ENDPOINT_2; i <= ENDPOINT_5; i++) { 57bdcd8170SKalle Valo if (!ar->tx_pending[i]) { 58bdcd8170SKalle Valo ar->node_map[ep_map].ep_id = i; 59bdcd8170SKalle Valo break; 60bdcd8170SKalle Valo } 61bdcd8170SKalle Valo 62bdcd8170SKalle Valo /* 63bdcd8170SKalle Valo * No free endpoint is available, start redistribution on 64bdcd8170SKalle Valo * the inuse endpoints. 65bdcd8170SKalle Valo */ 66bdcd8170SKalle Valo if (i == ENDPOINT_5) { 67bdcd8170SKalle Valo ar->node_map[ep_map].ep_id = ar->next_ep_id; 68bdcd8170SKalle Valo ar->next_ep_id++; 69bdcd8170SKalle Valo if (ar->next_ep_id > ENDPOINT_5) 70bdcd8170SKalle Valo ar->next_ep_id = ENDPOINT_2; 71bdcd8170SKalle Valo } 72bdcd8170SKalle Valo } 73bdcd8170SKalle Valo 74bdcd8170SKalle Valo *map_no = ep_map + 1; 75bdcd8170SKalle Valo ar->node_map[ep_map].tx_pend++; 76bdcd8170SKalle Valo 77bdcd8170SKalle Valo return ar->node_map[ep_map].ep_id; 78bdcd8170SKalle Valo } 79bdcd8170SKalle Valo 80bdcd8170SKalle Valo static bool ath6kl_powersave_ap(struct ath6kl *ar, struct sk_buff *skb, 81bdcd8170SKalle Valo bool *more_data) 82bdcd8170SKalle Valo { 83bdcd8170SKalle Valo struct ethhdr *datap = (struct ethhdr *) skb->data; 84bdcd8170SKalle Valo struct ath6kl_sta *conn = NULL; 85bdcd8170SKalle Valo bool ps_queued = false, is_psq_empty = false; 86bdcd8170SKalle Valo 87bdcd8170SKalle Valo if (is_multicast_ether_addr(datap->h_dest)) { 88bdcd8170SKalle Valo u8 ctr = 0; 89bdcd8170SKalle Valo bool q_mcast = false; 90bdcd8170SKalle Valo 91bdcd8170SKalle Valo for (ctr = 0; ctr < AP_MAX_NUM_STA; ctr++) { 92bdcd8170SKalle Valo if (ar->sta_list[ctr].sta_flags & STA_PS_SLEEP) { 93bdcd8170SKalle Valo q_mcast = true; 94bdcd8170SKalle Valo break; 95bdcd8170SKalle Valo } 96bdcd8170SKalle Valo } 97bdcd8170SKalle Valo 98bdcd8170SKalle Valo if (q_mcast) { 99bdcd8170SKalle Valo /* 100bdcd8170SKalle Valo * If this transmit is not because of a Dtim Expiry 101bdcd8170SKalle Valo * q it. 102bdcd8170SKalle Valo */ 103bdcd8170SKalle Valo if (!test_bit(DTIM_EXPIRED, &ar->flag)) { 104bdcd8170SKalle Valo bool is_mcastq_empty = false; 105bdcd8170SKalle Valo 106bdcd8170SKalle Valo spin_lock_bh(&ar->mcastpsq_lock); 107bdcd8170SKalle Valo is_mcastq_empty = 108bdcd8170SKalle Valo skb_queue_empty(&ar->mcastpsq); 109bdcd8170SKalle Valo skb_queue_tail(&ar->mcastpsq, skb); 110bdcd8170SKalle Valo spin_unlock_bh(&ar->mcastpsq_lock); 111bdcd8170SKalle Valo 112bdcd8170SKalle Valo /* 113bdcd8170SKalle Valo * If this is the first Mcast pkt getting 114bdcd8170SKalle Valo * queued indicate to the target to set the 115bdcd8170SKalle Valo * BitmapControl LSB of the TIM IE. 116bdcd8170SKalle Valo */ 117bdcd8170SKalle Valo if (is_mcastq_empty) 118bdcd8170SKalle Valo ath6kl_wmi_set_pvb_cmd(ar->wmi, 119bdcd8170SKalle Valo MCAST_AID, 1); 120bdcd8170SKalle Valo 121bdcd8170SKalle Valo ps_queued = true; 122bdcd8170SKalle Valo } else { 123bdcd8170SKalle Valo /* 124bdcd8170SKalle Valo * This transmit is because of Dtim expiry. 125bdcd8170SKalle Valo * Determine if MoreData bit has to be set. 126bdcd8170SKalle Valo */ 127bdcd8170SKalle Valo spin_lock_bh(&ar->mcastpsq_lock); 128bdcd8170SKalle Valo if (!skb_queue_empty(&ar->mcastpsq)) 129bdcd8170SKalle Valo *more_data = true; 130bdcd8170SKalle Valo spin_unlock_bh(&ar->mcastpsq_lock); 131bdcd8170SKalle Valo } 132bdcd8170SKalle Valo } 133bdcd8170SKalle Valo } else { 134bdcd8170SKalle Valo conn = ath6kl_find_sta(ar, datap->h_dest); 135bdcd8170SKalle Valo if (!conn) { 136bdcd8170SKalle Valo dev_kfree_skb(skb); 137bdcd8170SKalle Valo 138bdcd8170SKalle Valo /* Inform the caller that the skb is consumed */ 139bdcd8170SKalle Valo return true; 140bdcd8170SKalle Valo } 141bdcd8170SKalle Valo 142bdcd8170SKalle Valo if (conn->sta_flags & STA_PS_SLEEP) { 143bdcd8170SKalle Valo if (!(conn->sta_flags & STA_PS_POLLED)) { 144bdcd8170SKalle Valo /* Queue the frames if the STA is sleeping */ 145bdcd8170SKalle Valo spin_lock_bh(&conn->psq_lock); 146bdcd8170SKalle Valo is_psq_empty = skb_queue_empty(&conn->psq); 147bdcd8170SKalle Valo skb_queue_tail(&conn->psq, skb); 148bdcd8170SKalle Valo spin_unlock_bh(&conn->psq_lock); 149bdcd8170SKalle Valo 150bdcd8170SKalle Valo /* 151bdcd8170SKalle Valo * If this is the first pkt getting queued 152bdcd8170SKalle Valo * for this STA, update the PVB for this 153bdcd8170SKalle Valo * STA. 154bdcd8170SKalle Valo */ 155bdcd8170SKalle Valo if (is_psq_empty) 156bdcd8170SKalle Valo ath6kl_wmi_set_pvb_cmd(ar->wmi, 157bdcd8170SKalle Valo conn->aid, 1); 158bdcd8170SKalle Valo 159bdcd8170SKalle Valo ps_queued = true; 160bdcd8170SKalle Valo } else { 161bdcd8170SKalle Valo /* 162bdcd8170SKalle Valo * This tx is because of a PsPoll. 163bdcd8170SKalle Valo * Determine if MoreData bit has to be set. 164bdcd8170SKalle Valo */ 165bdcd8170SKalle Valo spin_lock_bh(&conn->psq_lock); 166bdcd8170SKalle Valo if (!skb_queue_empty(&conn->psq)) 167bdcd8170SKalle Valo *more_data = true; 168bdcd8170SKalle Valo spin_unlock_bh(&conn->psq_lock); 169bdcd8170SKalle Valo } 170bdcd8170SKalle Valo } 171bdcd8170SKalle Valo } 172bdcd8170SKalle Valo 173bdcd8170SKalle Valo return ps_queued; 174bdcd8170SKalle Valo } 175bdcd8170SKalle Valo 176bdcd8170SKalle Valo /* Tx functions */ 177bdcd8170SKalle Valo 178bdcd8170SKalle Valo int ath6kl_control_tx(void *devt, struct sk_buff *skb, 179bdcd8170SKalle Valo enum htc_endpoint_id eid) 180bdcd8170SKalle Valo { 181bdcd8170SKalle Valo struct ath6kl *ar = devt; 182bdcd8170SKalle Valo int status = 0; 183bdcd8170SKalle Valo struct ath6kl_cookie *cookie = NULL; 184bdcd8170SKalle Valo 185bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 186bdcd8170SKalle Valo 187bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 188bdcd8170SKalle Valo "%s: skb=0x%p, len=0x%x eid =%d\n", __func__, 189bdcd8170SKalle Valo skb, skb->len, eid); 190bdcd8170SKalle Valo 191bdcd8170SKalle Valo if (test_bit(WMI_CTRL_EP_FULL, &ar->flag) && (eid == ar->ctrl_ep)) { 192bdcd8170SKalle Valo /* 193bdcd8170SKalle Valo * Control endpoint is full, don't allocate resources, we 194bdcd8170SKalle Valo * are just going to drop this packet. 195bdcd8170SKalle Valo */ 196bdcd8170SKalle Valo cookie = NULL; 197bdcd8170SKalle Valo ath6kl_err("wmi ctrl ep full, dropping pkt : 0x%p, len:%d\n", 198bdcd8170SKalle Valo skb, skb->len); 199bdcd8170SKalle Valo } else 200bdcd8170SKalle Valo cookie = ath6kl_alloc_cookie(ar); 201bdcd8170SKalle Valo 202bdcd8170SKalle Valo if (cookie == NULL) { 203bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 204bdcd8170SKalle Valo status = -ENOMEM; 205bdcd8170SKalle Valo goto fail_ctrl_tx; 206bdcd8170SKalle Valo } 207bdcd8170SKalle Valo 208bdcd8170SKalle Valo ar->tx_pending[eid]++; 209bdcd8170SKalle Valo 210bdcd8170SKalle Valo if (eid != ar->ctrl_ep) 211bdcd8170SKalle Valo ar->total_tx_data_pend++; 212bdcd8170SKalle Valo 213bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 214bdcd8170SKalle Valo 215bdcd8170SKalle Valo cookie->skb = skb; 216bdcd8170SKalle Valo cookie->map_no = 0; 217bdcd8170SKalle Valo set_htc_pkt_info(&cookie->htc_pkt, cookie, skb->data, skb->len, 218bdcd8170SKalle Valo eid, ATH6KL_CONTROL_PKT_TAG); 219bdcd8170SKalle Valo 220bdcd8170SKalle Valo /* 221bdcd8170SKalle Valo * This interface is asynchronous, if there is an error, cleanup 222bdcd8170SKalle Valo * will happen in the TX completion callback. 223bdcd8170SKalle Valo */ 224ad226ec2SKalle Valo ath6kl_htc_tx(ar->htc_target, &cookie->htc_pkt); 225bdcd8170SKalle Valo 226bdcd8170SKalle Valo return 0; 227bdcd8170SKalle Valo 228bdcd8170SKalle Valo fail_ctrl_tx: 229bdcd8170SKalle Valo dev_kfree_skb(skb); 230bdcd8170SKalle Valo return status; 231bdcd8170SKalle Valo } 232bdcd8170SKalle Valo 233bdcd8170SKalle Valo int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev) 234bdcd8170SKalle Valo { 235bdcd8170SKalle Valo struct ath6kl *ar = ath6kl_priv(dev); 236bdcd8170SKalle Valo struct ath6kl_cookie *cookie = NULL; 237bdcd8170SKalle Valo enum htc_endpoint_id eid = ENDPOINT_UNUSED; 238bdcd8170SKalle Valo u32 map_no = 0; 239bdcd8170SKalle Valo u16 htc_tag = ATH6KL_DATA_PKT_TAG; 240bdcd8170SKalle Valo u8 ac = 99 ; /* initialize to unmapped ac */ 241bdcd8170SKalle Valo bool chk_adhoc_ps_mapping = false, more_data = false; 242bdcd8170SKalle Valo int ret; 243bdcd8170SKalle Valo 244bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 245bdcd8170SKalle Valo "%s: skb=0x%p, data=0x%p, len=0x%x\n", __func__, 246bdcd8170SKalle Valo skb, skb->data, skb->len); 247bdcd8170SKalle Valo 248bdcd8170SKalle Valo /* If target is not associated */ 249bdcd8170SKalle Valo if (!test_bit(CONNECTED, &ar->flag)) { 250bdcd8170SKalle Valo dev_kfree_skb(skb); 251bdcd8170SKalle Valo return 0; 252bdcd8170SKalle Valo } 253bdcd8170SKalle Valo 254bdcd8170SKalle Valo if (!test_bit(WMI_READY, &ar->flag)) 255bdcd8170SKalle Valo goto fail_tx; 256bdcd8170SKalle Valo 257bdcd8170SKalle Valo /* AP mode Power saving processing */ 258bdcd8170SKalle Valo if (ar->nw_type == AP_NETWORK) { 259bdcd8170SKalle Valo if (ath6kl_powersave_ap(ar, skb, &more_data)) 260bdcd8170SKalle Valo return 0; 261bdcd8170SKalle Valo } 262bdcd8170SKalle Valo 263bdcd8170SKalle Valo if (test_bit(WMI_ENABLED, &ar->flag)) { 264bdcd8170SKalle Valo if (skb_headroom(skb) < dev->needed_headroom) { 265bdcd8170SKalle Valo WARN_ON(1); 266bdcd8170SKalle Valo goto fail_tx; 267bdcd8170SKalle Valo } 268bdcd8170SKalle Valo 269bdcd8170SKalle Valo if (ath6kl_wmi_dix_2_dot3(ar->wmi, skb)) { 270bdcd8170SKalle Valo ath6kl_err("ath6kl_wmi_dix_2_dot3 failed\n"); 271bdcd8170SKalle Valo goto fail_tx; 272bdcd8170SKalle Valo } 273bdcd8170SKalle Valo 274bdcd8170SKalle Valo if (ath6kl_wmi_data_hdr_add(ar->wmi, skb, DATA_MSGTYPE, 275bdcd8170SKalle Valo more_data, 0, 0, NULL)) { 276bdcd8170SKalle Valo ath6kl_err("wmi_data_hdr_add failed\n"); 277bdcd8170SKalle Valo goto fail_tx; 278bdcd8170SKalle Valo } 279bdcd8170SKalle Valo 280bdcd8170SKalle Valo if ((ar->nw_type == ADHOC_NETWORK) && 281bdcd8170SKalle Valo ar->ibss_ps_enable && test_bit(CONNECTED, &ar->flag)) 282bdcd8170SKalle Valo chk_adhoc_ps_mapping = true; 283bdcd8170SKalle Valo else { 284bdcd8170SKalle Valo /* get the stream mapping */ 285bdcd8170SKalle Valo ret = ath6kl_wmi_implicit_create_pstream(ar->wmi, skb, 286bdcd8170SKalle Valo 0, test_bit(WMM_ENABLED, &ar->flag), &ac); 287bdcd8170SKalle Valo if (ret) 288bdcd8170SKalle Valo goto fail_tx; 289bdcd8170SKalle Valo } 290bdcd8170SKalle Valo } else 291bdcd8170SKalle Valo goto fail_tx; 292bdcd8170SKalle Valo 293bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 294bdcd8170SKalle Valo 295bdcd8170SKalle Valo if (chk_adhoc_ps_mapping) 296bdcd8170SKalle Valo eid = ath6kl_ibss_map_epid(skb, dev, &map_no); 297bdcd8170SKalle Valo else 298bdcd8170SKalle Valo eid = ar->ac2ep_map[ac]; 299bdcd8170SKalle Valo 300bdcd8170SKalle Valo if (eid == 0 || eid == ENDPOINT_UNUSED) { 301bdcd8170SKalle Valo ath6kl_err("eid %d is not mapped!\n", eid); 302bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 303bdcd8170SKalle Valo goto fail_tx; 304bdcd8170SKalle Valo } 305bdcd8170SKalle Valo 306bdcd8170SKalle Valo /* allocate resource for this packet */ 307bdcd8170SKalle Valo cookie = ath6kl_alloc_cookie(ar); 308bdcd8170SKalle Valo 309bdcd8170SKalle Valo if (!cookie) { 310bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 311bdcd8170SKalle Valo goto fail_tx; 312bdcd8170SKalle Valo } 313bdcd8170SKalle Valo 314bdcd8170SKalle Valo /* update counts while the lock is held */ 315bdcd8170SKalle Valo ar->tx_pending[eid]++; 316bdcd8170SKalle Valo ar->total_tx_data_pend++; 317bdcd8170SKalle Valo 318bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 319bdcd8170SKalle Valo 320*00b1edf1SJouni Malinen if (!IS_ALIGNED((unsigned long) skb->data - HTC_HDR_LENGTH, 4) && 321*00b1edf1SJouni Malinen skb_cloned(skb)) { 322*00b1edf1SJouni Malinen /* 323*00b1edf1SJouni Malinen * We will touch (move the buffer data to align it. Since the 324*00b1edf1SJouni Malinen * skb buffer is cloned and not only the header is changed, we 325*00b1edf1SJouni Malinen * have to copy it to allow the changes. Since we are copying 326*00b1edf1SJouni Malinen * the data here, we may as well align it by reserving suitable 327*00b1edf1SJouni Malinen * headroom to avoid the memmove in ath6kl_htc_tx_buf_align(). 328*00b1edf1SJouni Malinen */ 329*00b1edf1SJouni Malinen struct sk_buff *nskb; 330*00b1edf1SJouni Malinen 331*00b1edf1SJouni Malinen nskb = skb_copy_expand(skb, HTC_HDR_LENGTH, 0, GFP_ATOMIC); 332*00b1edf1SJouni Malinen if (nskb == NULL) 333*00b1edf1SJouni Malinen goto fail_tx; 334*00b1edf1SJouni Malinen kfree_skb(skb); 335*00b1edf1SJouni Malinen skb = nskb; 336*00b1edf1SJouni Malinen } 337*00b1edf1SJouni Malinen 338bdcd8170SKalle Valo cookie->skb = skb; 339bdcd8170SKalle Valo cookie->map_no = map_no; 340bdcd8170SKalle Valo set_htc_pkt_info(&cookie->htc_pkt, cookie, skb->data, skb->len, 341bdcd8170SKalle Valo eid, htc_tag); 342bdcd8170SKalle Valo 343bdcd8170SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_RAW_BYTES, __func__, skb->data, skb->len); 344bdcd8170SKalle Valo 345bdcd8170SKalle Valo /* 346bdcd8170SKalle Valo * HTC interface is asynchronous, if this fails, cleanup will 347bdcd8170SKalle Valo * happen in the ath6kl_tx_complete callback. 348bdcd8170SKalle Valo */ 349ad226ec2SKalle Valo ath6kl_htc_tx(ar->htc_target, &cookie->htc_pkt); 350bdcd8170SKalle Valo 351bdcd8170SKalle Valo return 0; 352bdcd8170SKalle Valo 353bdcd8170SKalle Valo fail_tx: 354bdcd8170SKalle Valo dev_kfree_skb(skb); 355bdcd8170SKalle Valo 356bdcd8170SKalle Valo ar->net_stats.tx_dropped++; 357bdcd8170SKalle Valo ar->net_stats.tx_aborted_errors++; 358bdcd8170SKalle Valo 359bdcd8170SKalle Valo return 0; 360bdcd8170SKalle Valo } 361bdcd8170SKalle Valo 362bdcd8170SKalle Valo /* indicate tx activity or inactivity on a WMI stream */ 363bdcd8170SKalle Valo void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active) 364bdcd8170SKalle Valo { 365bdcd8170SKalle Valo struct ath6kl *ar = devt; 366bdcd8170SKalle Valo enum htc_endpoint_id eid; 367bdcd8170SKalle Valo int i; 368bdcd8170SKalle Valo 369bdcd8170SKalle Valo eid = ar->ac2ep_map[traffic_class]; 370bdcd8170SKalle Valo 371bdcd8170SKalle Valo if (!test_bit(WMI_ENABLED, &ar->flag)) 372bdcd8170SKalle Valo goto notify_htc; 373bdcd8170SKalle Valo 374bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 375bdcd8170SKalle Valo 376bdcd8170SKalle Valo ar->ac_stream_active[traffic_class] = active; 377bdcd8170SKalle Valo 378bdcd8170SKalle Valo if (active) { 379bdcd8170SKalle Valo /* 380bdcd8170SKalle Valo * Keep track of the active stream with the highest 381bdcd8170SKalle Valo * priority. 382bdcd8170SKalle Valo */ 383bdcd8170SKalle Valo if (ar->ac_stream_pri_map[traffic_class] > 384bdcd8170SKalle Valo ar->hiac_stream_active_pri) 385bdcd8170SKalle Valo /* set the new highest active priority */ 386bdcd8170SKalle Valo ar->hiac_stream_active_pri = 387bdcd8170SKalle Valo ar->ac_stream_pri_map[traffic_class]; 388bdcd8170SKalle Valo 389bdcd8170SKalle Valo } else { 390bdcd8170SKalle Valo /* 391bdcd8170SKalle Valo * We may have to search for the next active stream 392bdcd8170SKalle Valo * that is the highest priority. 393bdcd8170SKalle Valo */ 394bdcd8170SKalle Valo if (ar->hiac_stream_active_pri == 395bdcd8170SKalle Valo ar->ac_stream_pri_map[traffic_class]) { 396bdcd8170SKalle Valo /* 397bdcd8170SKalle Valo * The highest priority stream just went inactive 398bdcd8170SKalle Valo * reset and search for the "next" highest "active" 399bdcd8170SKalle Valo * priority stream. 400bdcd8170SKalle Valo */ 401bdcd8170SKalle Valo ar->hiac_stream_active_pri = 0; 402bdcd8170SKalle Valo 403bdcd8170SKalle Valo for (i = 0; i < WMM_NUM_AC; i++) { 404bdcd8170SKalle Valo if (ar->ac_stream_active[i] && 405bdcd8170SKalle Valo (ar->ac_stream_pri_map[i] > 406bdcd8170SKalle Valo ar->hiac_stream_active_pri)) 407bdcd8170SKalle Valo /* 408bdcd8170SKalle Valo * Set the new highest active 409bdcd8170SKalle Valo * priority. 410bdcd8170SKalle Valo */ 411bdcd8170SKalle Valo ar->hiac_stream_active_pri = 412bdcd8170SKalle Valo ar->ac_stream_pri_map[i]; 413bdcd8170SKalle Valo } 414bdcd8170SKalle Valo } 415bdcd8170SKalle Valo } 416bdcd8170SKalle Valo 417bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 418bdcd8170SKalle Valo 419bdcd8170SKalle Valo notify_htc: 420bdcd8170SKalle Valo /* notify HTC, this may cause credit distribution changes */ 421ad226ec2SKalle Valo ath6kl_htc_indicate_activity_change(ar->htc_target, eid, active); 422bdcd8170SKalle Valo } 423bdcd8170SKalle Valo 424bdcd8170SKalle Valo enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target, 425bdcd8170SKalle Valo struct htc_packet *packet) 426bdcd8170SKalle Valo { 427bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 428bdcd8170SKalle Valo enum htc_endpoint_id endpoint = packet->endpoint; 429bdcd8170SKalle Valo 430bdcd8170SKalle Valo if (endpoint == ar->ctrl_ep) { 431bdcd8170SKalle Valo /* 432bdcd8170SKalle Valo * Under normal WMI if this is getting full, then something 433bdcd8170SKalle Valo * is running rampant the host should not be exhausting the 434bdcd8170SKalle Valo * WMI queue with too many commands the only exception to 435bdcd8170SKalle Valo * this is during testing using endpointping. 436bdcd8170SKalle Valo */ 437bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 438bdcd8170SKalle Valo set_bit(WMI_CTRL_EP_FULL, &ar->flag); 439bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 440bdcd8170SKalle Valo ath6kl_err("wmi ctrl ep is full\n"); 441bdcd8170SKalle Valo return HTC_SEND_FULL_KEEP; 442bdcd8170SKalle Valo } 443bdcd8170SKalle Valo 444bdcd8170SKalle Valo if (packet->info.tx.tag == ATH6KL_CONTROL_PKT_TAG) 445bdcd8170SKalle Valo return HTC_SEND_FULL_KEEP; 446bdcd8170SKalle Valo 447bdcd8170SKalle Valo if (ar->nw_type == ADHOC_NETWORK) 448bdcd8170SKalle Valo /* 449bdcd8170SKalle Valo * In adhoc mode, we cannot differentiate traffic 450bdcd8170SKalle Valo * priorities so there is no need to continue, however we 451bdcd8170SKalle Valo * should stop the network. 452bdcd8170SKalle Valo */ 453bdcd8170SKalle Valo goto stop_net_queues; 454bdcd8170SKalle Valo 455bdcd8170SKalle Valo /* 456bdcd8170SKalle Valo * The last MAX_HI_COOKIE_NUM "batch" of cookies are reserved for 457bdcd8170SKalle Valo * the highest active stream. 458bdcd8170SKalle Valo */ 459bdcd8170SKalle Valo if (ar->ac_stream_pri_map[ar->ep2ac_map[endpoint]] < 460bdcd8170SKalle Valo ar->hiac_stream_active_pri && 461bdcd8170SKalle Valo ar->cookie_count <= MAX_HI_COOKIE_NUM) 462bdcd8170SKalle Valo /* 463bdcd8170SKalle Valo * Give preference to the highest priority stream by 464bdcd8170SKalle Valo * dropping the packets which overflowed. 465bdcd8170SKalle Valo */ 466bdcd8170SKalle Valo return HTC_SEND_FULL_DROP; 467bdcd8170SKalle Valo 468bdcd8170SKalle Valo stop_net_queues: 469bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 470bdcd8170SKalle Valo set_bit(NETQ_STOPPED, &ar->flag); 471bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 472bdcd8170SKalle Valo netif_stop_queue(ar->net_dev); 473bdcd8170SKalle Valo 474bdcd8170SKalle Valo return HTC_SEND_FULL_KEEP; 475bdcd8170SKalle Valo } 476bdcd8170SKalle Valo 477bdcd8170SKalle Valo /* TODO this needs to be looked at */ 478bdcd8170SKalle Valo static void ath6kl_tx_clear_node_map(struct ath6kl *ar, 479bdcd8170SKalle Valo enum htc_endpoint_id eid, u32 map_no) 480bdcd8170SKalle Valo { 481bdcd8170SKalle Valo u32 i; 482bdcd8170SKalle Valo 483bdcd8170SKalle Valo if (ar->nw_type != ADHOC_NETWORK) 484bdcd8170SKalle Valo return; 485bdcd8170SKalle Valo 486bdcd8170SKalle Valo if (!ar->ibss_ps_enable) 487bdcd8170SKalle Valo return; 488bdcd8170SKalle Valo 489bdcd8170SKalle Valo if (eid == ar->ctrl_ep) 490bdcd8170SKalle Valo return; 491bdcd8170SKalle Valo 492bdcd8170SKalle Valo if (map_no == 0) 493bdcd8170SKalle Valo return; 494bdcd8170SKalle Valo 495bdcd8170SKalle Valo map_no--; 496bdcd8170SKalle Valo ar->node_map[map_no].tx_pend--; 497bdcd8170SKalle Valo 498bdcd8170SKalle Valo if (ar->node_map[map_no].tx_pend) 499bdcd8170SKalle Valo return; 500bdcd8170SKalle Valo 501bdcd8170SKalle Valo if (map_no != (ar->node_num - 1)) 502bdcd8170SKalle Valo return; 503bdcd8170SKalle Valo 504bdcd8170SKalle Valo for (i = ar->node_num; i > 0; i--) { 505bdcd8170SKalle Valo if (ar->node_map[i - 1].tx_pend) 506bdcd8170SKalle Valo break; 507bdcd8170SKalle Valo 508bdcd8170SKalle Valo memset(&ar->node_map[i - 1], 0, 509bdcd8170SKalle Valo sizeof(struct ath6kl_node_mapping)); 510bdcd8170SKalle Valo ar->node_num--; 511bdcd8170SKalle Valo } 512bdcd8170SKalle Valo } 513bdcd8170SKalle Valo 514bdcd8170SKalle Valo void ath6kl_tx_complete(void *context, struct list_head *packet_queue) 515bdcd8170SKalle Valo { 516bdcd8170SKalle Valo struct ath6kl *ar = context; 517bdcd8170SKalle Valo struct sk_buff_head skb_queue; 518bdcd8170SKalle Valo struct htc_packet *packet; 519bdcd8170SKalle Valo struct sk_buff *skb; 520bdcd8170SKalle Valo struct ath6kl_cookie *ath6kl_cookie; 521bdcd8170SKalle Valo u32 map_no = 0; 522bdcd8170SKalle Valo int status; 523bdcd8170SKalle Valo enum htc_endpoint_id eid; 524bdcd8170SKalle Valo bool wake_event = false; 525bdcd8170SKalle Valo bool flushing = false; 526bdcd8170SKalle Valo 527bdcd8170SKalle Valo skb_queue_head_init(&skb_queue); 528bdcd8170SKalle Valo 529bdcd8170SKalle Valo /* lock the driver as we update internal state */ 530bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 531bdcd8170SKalle Valo 532bdcd8170SKalle Valo /* reap completed packets */ 533bdcd8170SKalle Valo while (!list_empty(packet_queue)) { 534bdcd8170SKalle Valo 535bdcd8170SKalle Valo packet = list_first_entry(packet_queue, struct htc_packet, 536bdcd8170SKalle Valo list); 537bdcd8170SKalle Valo list_del(&packet->list); 538bdcd8170SKalle Valo 539bdcd8170SKalle Valo ath6kl_cookie = (struct ath6kl_cookie *)packet->pkt_cntxt; 540bdcd8170SKalle Valo if (!ath6kl_cookie) 541bdcd8170SKalle Valo goto fatal; 542bdcd8170SKalle Valo 543bdcd8170SKalle Valo status = packet->status; 544bdcd8170SKalle Valo skb = ath6kl_cookie->skb; 545bdcd8170SKalle Valo eid = packet->endpoint; 546bdcd8170SKalle Valo map_no = ath6kl_cookie->map_no; 547bdcd8170SKalle Valo 548bdcd8170SKalle Valo if (!skb || !skb->data) 549bdcd8170SKalle Valo goto fatal; 550bdcd8170SKalle Valo 551bdcd8170SKalle Valo packet->buf = skb->data; 552bdcd8170SKalle Valo 553bdcd8170SKalle Valo __skb_queue_tail(&skb_queue, skb); 554bdcd8170SKalle Valo 555bdcd8170SKalle Valo if (!status && (packet->act_len != skb->len)) 556bdcd8170SKalle Valo goto fatal; 557bdcd8170SKalle Valo 558bdcd8170SKalle Valo ar->tx_pending[eid]--; 559bdcd8170SKalle Valo 560bdcd8170SKalle Valo if (eid != ar->ctrl_ep) 561bdcd8170SKalle Valo ar->total_tx_data_pend--; 562bdcd8170SKalle Valo 563bdcd8170SKalle Valo if (eid == ar->ctrl_ep) { 564bdcd8170SKalle Valo if (test_bit(WMI_CTRL_EP_FULL, &ar->flag)) 565bdcd8170SKalle Valo clear_bit(WMI_CTRL_EP_FULL, &ar->flag); 566bdcd8170SKalle Valo 567bdcd8170SKalle Valo if (ar->tx_pending[eid] == 0) 568bdcd8170SKalle Valo wake_event = true; 569bdcd8170SKalle Valo } 570bdcd8170SKalle Valo 571bdcd8170SKalle Valo if (status) { 572bdcd8170SKalle Valo if (status == -ECANCELED) 573bdcd8170SKalle Valo /* a packet was flushed */ 574bdcd8170SKalle Valo flushing = true; 575bdcd8170SKalle Valo 576bdcd8170SKalle Valo ar->net_stats.tx_errors++; 577bdcd8170SKalle Valo 578bdcd8170SKalle Valo if (status != -ENOSPC) 579bdcd8170SKalle Valo ath6kl_err("tx error, status: 0x%x\n", status); 580bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 581bdcd8170SKalle Valo "%s: skb=0x%p data=0x%p len=0x%x eid=%d %s\n", 582bdcd8170SKalle Valo __func__, skb, packet->buf, packet->act_len, 583bdcd8170SKalle Valo eid, "error!"); 584bdcd8170SKalle Valo } else { 585bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_TX, 586bdcd8170SKalle Valo "%s: skb=0x%p data=0x%p len=0x%x eid=%d %s\n", 587bdcd8170SKalle Valo __func__, skb, packet->buf, packet->act_len, 588bdcd8170SKalle Valo eid, "OK"); 589bdcd8170SKalle Valo 590bdcd8170SKalle Valo flushing = false; 591bdcd8170SKalle Valo ar->net_stats.tx_packets++; 592bdcd8170SKalle Valo ar->net_stats.tx_bytes += skb->len; 593bdcd8170SKalle Valo } 594bdcd8170SKalle Valo 595bdcd8170SKalle Valo ath6kl_tx_clear_node_map(ar, eid, map_no); 596bdcd8170SKalle Valo 597bdcd8170SKalle Valo ath6kl_free_cookie(ar, ath6kl_cookie); 598bdcd8170SKalle Valo 599bdcd8170SKalle Valo if (test_bit(NETQ_STOPPED, &ar->flag)) 600bdcd8170SKalle Valo clear_bit(NETQ_STOPPED, &ar->flag); 601bdcd8170SKalle Valo } 602bdcd8170SKalle Valo 603bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 604bdcd8170SKalle Valo 605bdcd8170SKalle Valo __skb_queue_purge(&skb_queue); 606bdcd8170SKalle Valo 607bdcd8170SKalle Valo if (test_bit(CONNECTED, &ar->flag)) { 608bdcd8170SKalle Valo if (!flushing) 609bdcd8170SKalle Valo netif_wake_queue(ar->net_dev); 610bdcd8170SKalle Valo } 611bdcd8170SKalle Valo 612bdcd8170SKalle Valo if (wake_event) 613bdcd8170SKalle Valo wake_up(&ar->event_wq); 614bdcd8170SKalle Valo 615bdcd8170SKalle Valo return; 616bdcd8170SKalle Valo 617bdcd8170SKalle Valo fatal: 618bdcd8170SKalle Valo WARN_ON(1); 619bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 620bdcd8170SKalle Valo return; 621bdcd8170SKalle Valo } 622bdcd8170SKalle Valo 623bdcd8170SKalle Valo void ath6kl_tx_data_cleanup(struct ath6kl *ar) 624bdcd8170SKalle Valo { 625bdcd8170SKalle Valo int i; 626bdcd8170SKalle Valo 627bdcd8170SKalle Valo /* flush all the data (non-control) streams */ 628bdcd8170SKalle Valo for (i = 0; i < WMM_NUM_AC; i++) 629ad226ec2SKalle Valo ath6kl_htc_flush_txep(ar->htc_target, ar->ac2ep_map[i], 630bdcd8170SKalle Valo ATH6KL_DATA_PKT_TAG); 631bdcd8170SKalle Valo } 632bdcd8170SKalle Valo 633bdcd8170SKalle Valo /* Rx functions */ 634bdcd8170SKalle Valo 635bdcd8170SKalle Valo static void ath6kl_deliver_frames_to_nw_stack(struct net_device *dev, 636bdcd8170SKalle Valo struct sk_buff *skb) 637bdcd8170SKalle Valo { 638bdcd8170SKalle Valo if (!skb) 639bdcd8170SKalle Valo return; 640bdcd8170SKalle Valo 641bdcd8170SKalle Valo skb->dev = dev; 642bdcd8170SKalle Valo 643bdcd8170SKalle Valo if (!(skb->dev->flags & IFF_UP)) { 644bdcd8170SKalle Valo dev_kfree_skb(skb); 645bdcd8170SKalle Valo return; 646bdcd8170SKalle Valo } 647bdcd8170SKalle Valo 648bdcd8170SKalle Valo skb->protocol = eth_type_trans(skb, skb->dev); 649bdcd8170SKalle Valo 650bdcd8170SKalle Valo netif_rx_ni(skb); 651bdcd8170SKalle Valo } 652bdcd8170SKalle Valo 653bdcd8170SKalle Valo static void ath6kl_alloc_netbufs(struct sk_buff_head *q, u16 num) 654bdcd8170SKalle Valo { 655bdcd8170SKalle Valo struct sk_buff *skb; 656bdcd8170SKalle Valo 657bdcd8170SKalle Valo while (num) { 658bdcd8170SKalle Valo skb = ath6kl_buf_alloc(ATH6KL_BUFFER_SIZE); 659bdcd8170SKalle Valo if (!skb) { 660bdcd8170SKalle Valo ath6kl_err("netbuf allocation failed\n"); 661bdcd8170SKalle Valo return; 662bdcd8170SKalle Valo } 663bdcd8170SKalle Valo skb_queue_tail(q, skb); 664bdcd8170SKalle Valo num--; 665bdcd8170SKalle Valo } 666bdcd8170SKalle Valo } 667bdcd8170SKalle Valo 668bdcd8170SKalle Valo static struct sk_buff *aggr_get_free_skb(struct aggr_info *p_aggr) 669bdcd8170SKalle Valo { 670bdcd8170SKalle Valo struct sk_buff *skb = NULL; 671bdcd8170SKalle Valo 672bdcd8170SKalle Valo if (skb_queue_len(&p_aggr->free_q) < (AGGR_NUM_OF_FREE_NETBUFS >> 2)) 673bdcd8170SKalle Valo ath6kl_alloc_netbufs(&p_aggr->free_q, AGGR_NUM_OF_FREE_NETBUFS); 674bdcd8170SKalle Valo 675bdcd8170SKalle Valo skb = skb_dequeue(&p_aggr->free_q); 676bdcd8170SKalle Valo 677bdcd8170SKalle Valo return skb; 678bdcd8170SKalle Valo } 679bdcd8170SKalle Valo 680bdcd8170SKalle Valo void ath6kl_rx_refill(struct htc_target *target, enum htc_endpoint_id endpoint) 681bdcd8170SKalle Valo { 682bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 683bdcd8170SKalle Valo struct sk_buff *skb; 684bdcd8170SKalle Valo int rx_buf; 685bdcd8170SKalle Valo int n_buf_refill; 686bdcd8170SKalle Valo struct htc_packet *packet; 687bdcd8170SKalle Valo struct list_head queue; 688bdcd8170SKalle Valo 689bdcd8170SKalle Valo n_buf_refill = ATH6KL_MAX_RX_BUFFERS - 690ad226ec2SKalle Valo ath6kl_htc_get_rxbuf_num(ar->htc_target, endpoint); 691bdcd8170SKalle Valo 692bdcd8170SKalle Valo if (n_buf_refill <= 0) 693bdcd8170SKalle Valo return; 694bdcd8170SKalle Valo 695bdcd8170SKalle Valo INIT_LIST_HEAD(&queue); 696bdcd8170SKalle Valo 697bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, 698bdcd8170SKalle Valo "%s: providing htc with %d buffers at eid=%d\n", 699bdcd8170SKalle Valo __func__, n_buf_refill, endpoint); 700bdcd8170SKalle Valo 701bdcd8170SKalle Valo for (rx_buf = 0; rx_buf < n_buf_refill; rx_buf++) { 702bdcd8170SKalle Valo skb = ath6kl_buf_alloc(ATH6KL_BUFFER_SIZE); 703bdcd8170SKalle Valo if (!skb) 704bdcd8170SKalle Valo break; 705bdcd8170SKalle Valo 706bdcd8170SKalle Valo packet = (struct htc_packet *) skb->head; 70794e532d1SVasanthakumar Thiagarajan if (!IS_ALIGNED((unsigned long) skb->data, 4)) 7081df94a85SVasanthakumar Thiagarajan skb->data = PTR_ALIGN(skb->data - 4, 4); 709bdcd8170SKalle Valo set_htc_rxpkt_info(packet, skb, skb->data, 710bdcd8170SKalle Valo ATH6KL_BUFFER_SIZE, endpoint); 711bdcd8170SKalle Valo list_add_tail(&packet->list, &queue); 712bdcd8170SKalle Valo } 713bdcd8170SKalle Valo 714bdcd8170SKalle Valo if (!list_empty(&queue)) 715ad226ec2SKalle Valo ath6kl_htc_add_rxbuf_multiple(ar->htc_target, &queue); 716bdcd8170SKalle Valo } 717bdcd8170SKalle Valo 718bdcd8170SKalle Valo void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count) 719bdcd8170SKalle Valo { 720bdcd8170SKalle Valo struct htc_packet *packet; 721bdcd8170SKalle Valo struct sk_buff *skb; 722bdcd8170SKalle Valo 723bdcd8170SKalle Valo while (count) { 724bdcd8170SKalle Valo skb = ath6kl_buf_alloc(ATH6KL_AMSDU_BUFFER_SIZE); 725bdcd8170SKalle Valo if (!skb) 726bdcd8170SKalle Valo return; 727bdcd8170SKalle Valo 728bdcd8170SKalle Valo packet = (struct htc_packet *) skb->head; 72994e532d1SVasanthakumar Thiagarajan if (!IS_ALIGNED((unsigned long) skb->data, 4)) 7301df94a85SVasanthakumar Thiagarajan skb->data = PTR_ALIGN(skb->data - 4, 4); 731bdcd8170SKalle Valo set_htc_rxpkt_info(packet, skb, skb->data, 732bdcd8170SKalle Valo ATH6KL_AMSDU_BUFFER_SIZE, 0); 733bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 734bdcd8170SKalle Valo list_add_tail(&packet->list, &ar->amsdu_rx_buffer_queue); 735bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 736bdcd8170SKalle Valo count--; 737bdcd8170SKalle Valo } 738bdcd8170SKalle Valo } 739bdcd8170SKalle Valo 740bdcd8170SKalle Valo /* 741bdcd8170SKalle Valo * Callback to allocate a receive buffer for a pending packet. We use a 742bdcd8170SKalle Valo * pre-allocated list of buffers of maximum AMSDU size (4K). 743bdcd8170SKalle Valo */ 744bdcd8170SKalle Valo struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target, 745bdcd8170SKalle Valo enum htc_endpoint_id endpoint, 746bdcd8170SKalle Valo int len) 747bdcd8170SKalle Valo { 748bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 749bdcd8170SKalle Valo struct htc_packet *packet = NULL; 750bdcd8170SKalle Valo struct list_head *pkt_pos; 751bdcd8170SKalle Valo int refill_cnt = 0, depth = 0; 752bdcd8170SKalle Valo 753bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, "%s: eid=%d, len:%d\n", 754bdcd8170SKalle Valo __func__, endpoint, len); 755bdcd8170SKalle Valo 756bdcd8170SKalle Valo if ((len <= ATH6KL_BUFFER_SIZE) || 757bdcd8170SKalle Valo (len > ATH6KL_AMSDU_BUFFER_SIZE)) 758bdcd8170SKalle Valo return NULL; 759bdcd8170SKalle Valo 760bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 761bdcd8170SKalle Valo 762bdcd8170SKalle Valo if (list_empty(&ar->amsdu_rx_buffer_queue)) { 763bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 764bdcd8170SKalle Valo refill_cnt = ATH6KL_MAX_AMSDU_RX_BUFFERS; 765bdcd8170SKalle Valo goto refill_buf; 766bdcd8170SKalle Valo } 767bdcd8170SKalle Valo 768bdcd8170SKalle Valo packet = list_first_entry(&ar->amsdu_rx_buffer_queue, 769bdcd8170SKalle Valo struct htc_packet, list); 770bdcd8170SKalle Valo list_del(&packet->list); 771bdcd8170SKalle Valo list_for_each(pkt_pos, &ar->amsdu_rx_buffer_queue) 772bdcd8170SKalle Valo depth++; 773bdcd8170SKalle Valo 774bdcd8170SKalle Valo refill_cnt = ATH6KL_MAX_AMSDU_RX_BUFFERS - depth; 775bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 776bdcd8170SKalle Valo 777bdcd8170SKalle Valo /* set actual endpoint ID */ 778bdcd8170SKalle Valo packet->endpoint = endpoint; 779bdcd8170SKalle Valo 780bdcd8170SKalle Valo refill_buf: 781bdcd8170SKalle Valo if (refill_cnt >= ATH6KL_AMSDU_REFILL_THRESHOLD) 782bdcd8170SKalle Valo ath6kl_refill_amsdu_rxbufs(ar, refill_cnt); 783bdcd8170SKalle Valo 784bdcd8170SKalle Valo return packet; 785bdcd8170SKalle Valo } 786bdcd8170SKalle Valo 787bdcd8170SKalle Valo static void aggr_slice_amsdu(struct aggr_info *p_aggr, 788bdcd8170SKalle Valo struct rxtid *rxtid, struct sk_buff *skb) 789bdcd8170SKalle Valo { 790bdcd8170SKalle Valo struct sk_buff *new_skb; 791bdcd8170SKalle Valo struct ethhdr *hdr; 792bdcd8170SKalle Valo u16 frame_8023_len, payload_8023_len, mac_hdr_len, amsdu_len; 793bdcd8170SKalle Valo u8 *framep; 794bdcd8170SKalle Valo 795bdcd8170SKalle Valo mac_hdr_len = sizeof(struct ethhdr); 796bdcd8170SKalle Valo framep = skb->data + mac_hdr_len; 797bdcd8170SKalle Valo amsdu_len = skb->len - mac_hdr_len; 798bdcd8170SKalle Valo 799bdcd8170SKalle Valo while (amsdu_len > mac_hdr_len) { 800bdcd8170SKalle Valo hdr = (struct ethhdr *) framep; 801bdcd8170SKalle Valo payload_8023_len = ntohs(hdr->h_proto); 802bdcd8170SKalle Valo 803bdcd8170SKalle Valo if (payload_8023_len < MIN_MSDU_SUBFRAME_PAYLOAD_LEN || 804bdcd8170SKalle Valo payload_8023_len > MAX_MSDU_SUBFRAME_PAYLOAD_LEN) { 805bdcd8170SKalle Valo ath6kl_err("802.3 AMSDU frame bound check failed. len %d\n", 806bdcd8170SKalle Valo payload_8023_len); 807bdcd8170SKalle Valo break; 808bdcd8170SKalle Valo } 809bdcd8170SKalle Valo 810bdcd8170SKalle Valo frame_8023_len = payload_8023_len + mac_hdr_len; 811bdcd8170SKalle Valo new_skb = aggr_get_free_skb(p_aggr); 812bdcd8170SKalle Valo if (!new_skb) { 813bdcd8170SKalle Valo ath6kl_err("no buffer available\n"); 814bdcd8170SKalle Valo break; 815bdcd8170SKalle Valo } 816bdcd8170SKalle Valo 817bdcd8170SKalle Valo memcpy(new_skb->data, framep, frame_8023_len); 818bdcd8170SKalle Valo skb_put(new_skb, frame_8023_len); 819bdcd8170SKalle Valo if (ath6kl_wmi_dot3_2_dix(new_skb)) { 820bdcd8170SKalle Valo ath6kl_err("dot3_2_dix error\n"); 821bdcd8170SKalle Valo dev_kfree_skb(new_skb); 822bdcd8170SKalle Valo break; 823bdcd8170SKalle Valo } 824bdcd8170SKalle Valo 825bdcd8170SKalle Valo skb_queue_tail(&rxtid->q, new_skb); 826bdcd8170SKalle Valo 827bdcd8170SKalle Valo /* Is this the last subframe within this aggregate ? */ 828bdcd8170SKalle Valo if ((amsdu_len - frame_8023_len) == 0) 829bdcd8170SKalle Valo break; 830bdcd8170SKalle Valo 831bdcd8170SKalle Valo /* Add the length of A-MSDU subframe padding bytes - 832bdcd8170SKalle Valo * Round to nearest word. 833bdcd8170SKalle Valo */ 83413e34ea1SVasanthakumar Thiagarajan frame_8023_len = ALIGN(frame_8023_len, 4); 835bdcd8170SKalle Valo 836bdcd8170SKalle Valo framep += frame_8023_len; 837bdcd8170SKalle Valo amsdu_len -= frame_8023_len; 838bdcd8170SKalle Valo } 839bdcd8170SKalle Valo 840bdcd8170SKalle Valo dev_kfree_skb(skb); 841bdcd8170SKalle Valo } 842bdcd8170SKalle Valo 843bdcd8170SKalle Valo static void aggr_deque_frms(struct aggr_info *p_aggr, u8 tid, 844bdcd8170SKalle Valo u16 seq_no, u8 order) 845bdcd8170SKalle Valo { 846bdcd8170SKalle Valo struct sk_buff *skb; 847bdcd8170SKalle Valo struct rxtid *rxtid; 848bdcd8170SKalle Valo struct skb_hold_q *node; 849bdcd8170SKalle Valo u16 idx, idx_end, seq_end; 850bdcd8170SKalle Valo struct rxtid_stats *stats; 851bdcd8170SKalle Valo 852bdcd8170SKalle Valo if (!p_aggr) 853bdcd8170SKalle Valo return; 854bdcd8170SKalle Valo 855bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 856bdcd8170SKalle Valo stats = &p_aggr->stat[tid]; 857bdcd8170SKalle Valo 858bdcd8170SKalle Valo idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz); 859bdcd8170SKalle Valo 860bdcd8170SKalle Valo /* 861bdcd8170SKalle Valo * idx_end is typically the last possible frame in the window, 862bdcd8170SKalle Valo * but changes to 'the' seq_no, when BAR comes. If seq_no 863bdcd8170SKalle Valo * is non-zero, we will go up to that and stop. 864bdcd8170SKalle Valo * Note: last seq no in current window will occupy the same 865bdcd8170SKalle Valo * index position as index that is just previous to start. 866bdcd8170SKalle Valo * An imp point : if win_sz is 7, for seq_no space of 4095, 867bdcd8170SKalle Valo * then, there would be holes when sequence wrap around occurs. 868bdcd8170SKalle Valo * Target should judiciously choose the win_sz, based on 869bdcd8170SKalle Valo * this condition. For 4095, (TID_WINDOW_SZ = 2 x win_sz 870bdcd8170SKalle Valo * 2, 4, 8, 16 win_sz works fine). 871bdcd8170SKalle Valo * We must deque from "idx" to "idx_end", including both. 872bdcd8170SKalle Valo */ 873bdcd8170SKalle Valo seq_end = seq_no ? seq_no : rxtid->seq_next; 874bdcd8170SKalle Valo idx_end = AGGR_WIN_IDX(seq_end, rxtid->hold_q_sz); 875bdcd8170SKalle Valo 876bdcd8170SKalle Valo spin_lock_bh(&rxtid->lock); 877bdcd8170SKalle Valo 878bdcd8170SKalle Valo do { 879bdcd8170SKalle Valo node = &rxtid->hold_q[idx]; 880bdcd8170SKalle Valo if ((order == 1) && (!node->skb)) 881bdcd8170SKalle Valo break; 882bdcd8170SKalle Valo 883bdcd8170SKalle Valo if (node->skb) { 884bdcd8170SKalle Valo if (node->is_amsdu) 885bdcd8170SKalle Valo aggr_slice_amsdu(p_aggr, rxtid, node->skb); 886bdcd8170SKalle Valo else 887bdcd8170SKalle Valo skb_queue_tail(&rxtid->q, node->skb); 888bdcd8170SKalle Valo node->skb = NULL; 889bdcd8170SKalle Valo } else 890bdcd8170SKalle Valo stats->num_hole++; 891bdcd8170SKalle Valo 892bdcd8170SKalle Valo rxtid->seq_next = ATH6KL_NEXT_SEQ_NO(rxtid->seq_next); 893bdcd8170SKalle Valo idx = AGGR_WIN_IDX(rxtid->seq_next, rxtid->hold_q_sz); 894bdcd8170SKalle Valo } while (idx != idx_end); 895bdcd8170SKalle Valo 896bdcd8170SKalle Valo spin_unlock_bh(&rxtid->lock); 897bdcd8170SKalle Valo 898bdcd8170SKalle Valo stats->num_delivered += skb_queue_len(&rxtid->q); 899bdcd8170SKalle Valo 900bdcd8170SKalle Valo while ((skb = skb_dequeue(&rxtid->q))) 901bdcd8170SKalle Valo ath6kl_deliver_frames_to_nw_stack(p_aggr->dev, skb); 902bdcd8170SKalle Valo } 903bdcd8170SKalle Valo 904bdcd8170SKalle Valo static bool aggr_process_recv_frm(struct aggr_info *agg_info, u8 tid, 905bdcd8170SKalle Valo u16 seq_no, 906bdcd8170SKalle Valo bool is_amsdu, struct sk_buff *frame) 907bdcd8170SKalle Valo { 908bdcd8170SKalle Valo struct rxtid *rxtid; 909bdcd8170SKalle Valo struct rxtid_stats *stats; 910bdcd8170SKalle Valo struct sk_buff *skb; 911bdcd8170SKalle Valo struct skb_hold_q *node; 912bdcd8170SKalle Valo u16 idx, st, cur, end; 913bdcd8170SKalle Valo bool is_queued = false; 914bdcd8170SKalle Valo u16 extended_end; 915bdcd8170SKalle Valo 916bdcd8170SKalle Valo rxtid = &agg_info->rx_tid[tid]; 917bdcd8170SKalle Valo stats = &agg_info->stat[tid]; 918bdcd8170SKalle Valo 919bdcd8170SKalle Valo stats->num_into_aggr++; 920bdcd8170SKalle Valo 921bdcd8170SKalle Valo if (!rxtid->aggr) { 922bdcd8170SKalle Valo if (is_amsdu) { 923bdcd8170SKalle Valo aggr_slice_amsdu(agg_info, rxtid, frame); 924bdcd8170SKalle Valo is_queued = true; 925bdcd8170SKalle Valo stats->num_amsdu++; 926bdcd8170SKalle Valo while ((skb = skb_dequeue(&rxtid->q))) 927bdcd8170SKalle Valo ath6kl_deliver_frames_to_nw_stack(agg_info->dev, 928bdcd8170SKalle Valo skb); 929bdcd8170SKalle Valo } 930bdcd8170SKalle Valo return is_queued; 931bdcd8170SKalle Valo } 932bdcd8170SKalle Valo 933bdcd8170SKalle Valo /* Check the incoming sequence no, if it's in the window */ 934bdcd8170SKalle Valo st = rxtid->seq_next; 935bdcd8170SKalle Valo cur = seq_no; 936bdcd8170SKalle Valo end = (st + rxtid->hold_q_sz-1) & ATH6KL_MAX_SEQ_NO; 937bdcd8170SKalle Valo 938bdcd8170SKalle Valo if (((st < end) && (cur < st || cur > end)) || 939bdcd8170SKalle Valo ((st > end) && (cur > end) && (cur < st))) { 940bdcd8170SKalle Valo extended_end = (end + rxtid->hold_q_sz - 1) & 941bdcd8170SKalle Valo ATH6KL_MAX_SEQ_NO; 942bdcd8170SKalle Valo 943bdcd8170SKalle Valo if (((end < extended_end) && 944bdcd8170SKalle Valo (cur < end || cur > extended_end)) || 945bdcd8170SKalle Valo ((end > extended_end) && (cur > extended_end) && 946bdcd8170SKalle Valo (cur < end))) { 947bdcd8170SKalle Valo aggr_deque_frms(agg_info, tid, 0, 0); 948bdcd8170SKalle Valo if (cur >= rxtid->hold_q_sz - 1) 949bdcd8170SKalle Valo rxtid->seq_next = cur - (rxtid->hold_q_sz - 1); 950bdcd8170SKalle Valo else 951bdcd8170SKalle Valo rxtid->seq_next = ATH6KL_MAX_SEQ_NO - 952bdcd8170SKalle Valo (rxtid->hold_q_sz - 2 - cur); 953bdcd8170SKalle Valo } else { 954bdcd8170SKalle Valo /* 955bdcd8170SKalle Valo * Dequeue only those frames that are outside the 956bdcd8170SKalle Valo * new shifted window. 957bdcd8170SKalle Valo */ 958bdcd8170SKalle Valo if (cur >= rxtid->hold_q_sz - 1) 959bdcd8170SKalle Valo st = cur - (rxtid->hold_q_sz - 1); 960bdcd8170SKalle Valo else 961bdcd8170SKalle Valo st = ATH6KL_MAX_SEQ_NO - 962bdcd8170SKalle Valo (rxtid->hold_q_sz - 2 - cur); 963bdcd8170SKalle Valo 964bdcd8170SKalle Valo aggr_deque_frms(agg_info, tid, st, 0); 965bdcd8170SKalle Valo } 966bdcd8170SKalle Valo 967bdcd8170SKalle Valo stats->num_oow++; 968bdcd8170SKalle Valo } 969bdcd8170SKalle Valo 970bdcd8170SKalle Valo idx = AGGR_WIN_IDX(seq_no, rxtid->hold_q_sz); 971bdcd8170SKalle Valo 972bdcd8170SKalle Valo node = &rxtid->hold_q[idx]; 973bdcd8170SKalle Valo 974bdcd8170SKalle Valo spin_lock_bh(&rxtid->lock); 975bdcd8170SKalle Valo 976bdcd8170SKalle Valo /* 977bdcd8170SKalle Valo * Is the cur frame duplicate or something beyond our window(hold_q 978bdcd8170SKalle Valo * -> which is 2x, already)? 979bdcd8170SKalle Valo * 980bdcd8170SKalle Valo * 1. Duplicate is easy - drop incoming frame. 981bdcd8170SKalle Valo * 2. Not falling in current sliding window. 982bdcd8170SKalle Valo * 2a. is the frame_seq_no preceding current tid_seq_no? 983bdcd8170SKalle Valo * -> drop the frame. perhaps sender did not get our ACK. 984bdcd8170SKalle Valo * this is taken care of above. 985bdcd8170SKalle Valo * 2b. is the frame_seq_no beyond window(st, TID_WINDOW_SZ); 986bdcd8170SKalle Valo * -> Taken care of it above, by moving window forward. 987bdcd8170SKalle Valo */ 988bdcd8170SKalle Valo dev_kfree_skb(node->skb); 989bdcd8170SKalle Valo stats->num_dups++; 990bdcd8170SKalle Valo 991bdcd8170SKalle Valo node->skb = frame; 992bdcd8170SKalle Valo is_queued = true; 993bdcd8170SKalle Valo node->is_amsdu = is_amsdu; 994bdcd8170SKalle Valo node->seq_no = seq_no; 995bdcd8170SKalle Valo 996bdcd8170SKalle Valo if (node->is_amsdu) 997bdcd8170SKalle Valo stats->num_amsdu++; 998bdcd8170SKalle Valo else 999bdcd8170SKalle Valo stats->num_mpdu++; 1000bdcd8170SKalle Valo 1001bdcd8170SKalle Valo spin_unlock_bh(&rxtid->lock); 1002bdcd8170SKalle Valo 1003bdcd8170SKalle Valo aggr_deque_frms(agg_info, tid, 0, 1); 1004bdcd8170SKalle Valo 1005bdcd8170SKalle Valo if (agg_info->timer_scheduled) 1006bdcd8170SKalle Valo rxtid->progress = true; 1007bdcd8170SKalle Valo else 1008bdcd8170SKalle Valo for (idx = 0 ; idx < rxtid->hold_q_sz; idx++) { 1009bdcd8170SKalle Valo if (rxtid->hold_q[idx].skb) { 1010bdcd8170SKalle Valo /* 1011bdcd8170SKalle Valo * There is a frame in the queue and no 1012bdcd8170SKalle Valo * timer so start a timer to ensure that 1013bdcd8170SKalle Valo * the frame doesn't remain stuck 1014bdcd8170SKalle Valo * forever. 1015bdcd8170SKalle Valo */ 1016bdcd8170SKalle Valo agg_info->timer_scheduled = true; 1017bdcd8170SKalle Valo mod_timer(&agg_info->timer, 1018bdcd8170SKalle Valo (jiffies + 1019bdcd8170SKalle Valo HZ * (AGGR_RX_TIMEOUT) / 1000)); 1020bdcd8170SKalle Valo rxtid->progress = false; 1021bdcd8170SKalle Valo rxtid->timer_mon = true; 1022bdcd8170SKalle Valo break; 1023bdcd8170SKalle Valo } 1024bdcd8170SKalle Valo } 1025bdcd8170SKalle Valo 1026bdcd8170SKalle Valo return is_queued; 1027bdcd8170SKalle Valo } 1028bdcd8170SKalle Valo 1029bdcd8170SKalle Valo void ath6kl_rx(struct htc_target *target, struct htc_packet *packet) 1030bdcd8170SKalle Valo { 1031bdcd8170SKalle Valo struct ath6kl *ar = target->dev->ar; 1032bdcd8170SKalle Valo struct sk_buff *skb = packet->pkt_cntxt; 1033bdcd8170SKalle Valo struct wmi_rx_meta_v2 *meta; 1034bdcd8170SKalle Valo struct wmi_data_hdr *dhdr; 1035bdcd8170SKalle Valo int min_hdr_len; 1036bdcd8170SKalle Valo u8 meta_type, dot11_hdr = 0; 1037bdcd8170SKalle Valo int status = packet->status; 1038bdcd8170SKalle Valo enum htc_endpoint_id ept = packet->endpoint; 1039bdcd8170SKalle Valo bool is_amsdu, prev_ps, ps_state = false; 1040bdcd8170SKalle Valo struct ath6kl_sta *conn = NULL; 1041bdcd8170SKalle Valo struct sk_buff *skb1 = NULL; 1042bdcd8170SKalle Valo struct ethhdr *datap = NULL; 1043bdcd8170SKalle Valo u16 seq_no, offset; 1044bdcd8170SKalle Valo u8 tid; 1045bdcd8170SKalle Valo 1046bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, 1047bdcd8170SKalle Valo "%s: ar=0x%p eid=%d, skb=0x%p, data=0x%p, len=0x%x status:%d", 1048bdcd8170SKalle Valo __func__, ar, ept, skb, packet->buf, 1049bdcd8170SKalle Valo packet->act_len, status); 1050bdcd8170SKalle Valo 1051bdcd8170SKalle Valo if (status || !(skb->data + HTC_HDR_LENGTH)) { 1052bdcd8170SKalle Valo ar->net_stats.rx_errors++; 1053bdcd8170SKalle Valo dev_kfree_skb(skb); 1054bdcd8170SKalle Valo return; 1055bdcd8170SKalle Valo } 1056bdcd8170SKalle Valo 1057bdcd8170SKalle Valo /* 1058bdcd8170SKalle Valo * Take lock to protect buffer counts and adaptive power throughput 1059bdcd8170SKalle Valo * state. 1060bdcd8170SKalle Valo */ 1061bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 1062bdcd8170SKalle Valo 1063bdcd8170SKalle Valo ar->net_stats.rx_packets++; 1064bdcd8170SKalle Valo ar->net_stats.rx_bytes += packet->act_len; 1065bdcd8170SKalle Valo 106683dc5f2fSVasanthakumar Thiagarajan spin_unlock_bh(&ar->lock); 106783dc5f2fSVasanthakumar Thiagarajan 1068bdcd8170SKalle Valo skb_put(skb, packet->act_len + HTC_HDR_LENGTH); 1069bdcd8170SKalle Valo skb_pull(skb, HTC_HDR_LENGTH); 1070bdcd8170SKalle Valo 1071bdcd8170SKalle Valo ath6kl_dbg_dump(ATH6KL_DBG_RAW_BYTES, __func__, skb->data, skb->len); 1072bdcd8170SKalle Valo 1073bdcd8170SKalle Valo skb->dev = ar->net_dev; 1074bdcd8170SKalle Valo 1075bdcd8170SKalle Valo if (!test_bit(WMI_ENABLED, &ar->flag)) { 1076bdcd8170SKalle Valo if (EPPING_ALIGNMENT_PAD > 0) 1077bdcd8170SKalle Valo skb_pull(skb, EPPING_ALIGNMENT_PAD); 1078bdcd8170SKalle Valo ath6kl_deliver_frames_to_nw_stack(ar->net_dev, skb); 1079bdcd8170SKalle Valo return; 1080bdcd8170SKalle Valo } 1081bdcd8170SKalle Valo 1082bdcd8170SKalle Valo if (ept == ar->ctrl_ep) { 1083bdcd8170SKalle Valo ath6kl_wmi_control_rx(ar->wmi, skb); 1084bdcd8170SKalle Valo return; 1085bdcd8170SKalle Valo } 1086bdcd8170SKalle Valo 108767f9178fSVasanthakumar Thiagarajan min_hdr_len = sizeof(struct ethhdr) + sizeof(struct wmi_data_hdr) + 1088bdcd8170SKalle Valo sizeof(struct ath6kl_llc_snap_hdr); 1089bdcd8170SKalle Valo 1090bdcd8170SKalle Valo dhdr = (struct wmi_data_hdr *) skb->data; 1091bdcd8170SKalle Valo 1092bdcd8170SKalle Valo /* 1093bdcd8170SKalle Valo * In the case of AP mode we may receive NULL data frames 1094bdcd8170SKalle Valo * that do not have LLC hdr. They are 16 bytes in size. 1095bdcd8170SKalle Valo * Allow these frames in the AP mode. 1096bdcd8170SKalle Valo */ 1097bdcd8170SKalle Valo if (ar->nw_type != AP_NETWORK && 1098bdcd8170SKalle Valo ((packet->act_len < min_hdr_len) || 1099bdcd8170SKalle Valo (packet->act_len > WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH))) { 1100bdcd8170SKalle Valo ath6kl_info("frame len is too short or too long\n"); 1101bdcd8170SKalle Valo ar->net_stats.rx_errors++; 1102bdcd8170SKalle Valo ar->net_stats.rx_length_errors++; 1103bdcd8170SKalle Valo dev_kfree_skb(skb); 1104bdcd8170SKalle Valo return; 1105bdcd8170SKalle Valo } 1106bdcd8170SKalle Valo 1107bdcd8170SKalle Valo /* Get the Power save state of the STA */ 1108bdcd8170SKalle Valo if (ar->nw_type == AP_NETWORK) { 1109bdcd8170SKalle Valo meta_type = wmi_data_hdr_get_meta(dhdr); 1110bdcd8170SKalle Valo 1111bdcd8170SKalle Valo ps_state = !!((dhdr->info >> WMI_DATA_HDR_PS_SHIFT) & 1112bdcd8170SKalle Valo WMI_DATA_HDR_PS_MASK); 1113bdcd8170SKalle Valo 1114bdcd8170SKalle Valo offset = sizeof(struct wmi_data_hdr); 1115bdcd8170SKalle Valo 1116bdcd8170SKalle Valo switch (meta_type) { 1117bdcd8170SKalle Valo case 0: 1118bdcd8170SKalle Valo break; 1119bdcd8170SKalle Valo case WMI_META_VERSION_1: 1120bdcd8170SKalle Valo offset += sizeof(struct wmi_rx_meta_v1); 1121bdcd8170SKalle Valo break; 1122bdcd8170SKalle Valo case WMI_META_VERSION_2: 1123bdcd8170SKalle Valo offset += sizeof(struct wmi_rx_meta_v2); 1124bdcd8170SKalle Valo break; 1125bdcd8170SKalle Valo default: 1126bdcd8170SKalle Valo break; 1127bdcd8170SKalle Valo } 1128bdcd8170SKalle Valo 1129bdcd8170SKalle Valo datap = (struct ethhdr *) (skb->data + offset); 1130bdcd8170SKalle Valo conn = ath6kl_find_sta(ar, datap->h_source); 1131bdcd8170SKalle Valo 1132bdcd8170SKalle Valo if (!conn) { 1133bdcd8170SKalle Valo dev_kfree_skb(skb); 1134bdcd8170SKalle Valo return; 1135bdcd8170SKalle Valo } 1136bdcd8170SKalle Valo 1137bdcd8170SKalle Valo /* 1138bdcd8170SKalle Valo * If there is a change in PS state of the STA, 1139bdcd8170SKalle Valo * take appropriate steps: 1140bdcd8170SKalle Valo * 1141bdcd8170SKalle Valo * 1. If Sleep-->Awake, flush the psq for the STA 1142bdcd8170SKalle Valo * Clear the PVB for the STA. 1143bdcd8170SKalle Valo * 2. If Awake-->Sleep, Starting queueing frames 1144bdcd8170SKalle Valo * the STA. 1145bdcd8170SKalle Valo */ 1146bdcd8170SKalle Valo prev_ps = !!(conn->sta_flags & STA_PS_SLEEP); 1147bdcd8170SKalle Valo 1148bdcd8170SKalle Valo if (ps_state) 1149bdcd8170SKalle Valo conn->sta_flags |= STA_PS_SLEEP; 1150bdcd8170SKalle Valo else 1151bdcd8170SKalle Valo conn->sta_flags &= ~STA_PS_SLEEP; 1152bdcd8170SKalle Valo 1153bdcd8170SKalle Valo if (prev_ps ^ !!(conn->sta_flags & STA_PS_SLEEP)) { 1154bdcd8170SKalle Valo if (!(conn->sta_flags & STA_PS_SLEEP)) { 1155bdcd8170SKalle Valo struct sk_buff *skbuff = NULL; 1156bdcd8170SKalle Valo 1157bdcd8170SKalle Valo spin_lock_bh(&conn->psq_lock); 1158bdcd8170SKalle Valo while ((skbuff = skb_dequeue(&conn->psq)) 1159bdcd8170SKalle Valo != NULL) { 1160bdcd8170SKalle Valo spin_unlock_bh(&conn->psq_lock); 1161bdcd8170SKalle Valo ath6kl_data_tx(skbuff, ar->net_dev); 1162bdcd8170SKalle Valo spin_lock_bh(&conn->psq_lock); 1163bdcd8170SKalle Valo } 1164bdcd8170SKalle Valo spin_unlock_bh(&conn->psq_lock); 1165bdcd8170SKalle Valo /* Clear the PVB for this STA */ 1166bdcd8170SKalle Valo ath6kl_wmi_set_pvb_cmd(ar->wmi, conn->aid, 0); 1167bdcd8170SKalle Valo } 1168bdcd8170SKalle Valo } 1169bdcd8170SKalle Valo 1170bdcd8170SKalle Valo /* drop NULL data frames here */ 1171bdcd8170SKalle Valo if ((packet->act_len < min_hdr_len) || 1172bdcd8170SKalle Valo (packet->act_len > 1173bdcd8170SKalle Valo WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH)) { 1174bdcd8170SKalle Valo dev_kfree_skb(skb); 1175bdcd8170SKalle Valo return; 1176bdcd8170SKalle Valo } 1177bdcd8170SKalle Valo } 1178bdcd8170SKalle Valo 1179bdcd8170SKalle Valo is_amsdu = wmi_data_hdr_is_amsdu(dhdr) ? true : false; 1180bdcd8170SKalle Valo tid = wmi_data_hdr_get_up(dhdr); 1181bdcd8170SKalle Valo seq_no = wmi_data_hdr_get_seqno(dhdr); 1182bdcd8170SKalle Valo meta_type = wmi_data_hdr_get_meta(dhdr); 1183bdcd8170SKalle Valo dot11_hdr = wmi_data_hdr_get_dot11(dhdr); 1184594a0bc8SVasanthakumar Thiagarajan skb_pull(skb, sizeof(struct wmi_data_hdr)); 1185bdcd8170SKalle Valo 1186bdcd8170SKalle Valo switch (meta_type) { 1187bdcd8170SKalle Valo case WMI_META_VERSION_1: 1188bdcd8170SKalle Valo skb_pull(skb, sizeof(struct wmi_rx_meta_v1)); 1189bdcd8170SKalle Valo break; 1190bdcd8170SKalle Valo case WMI_META_VERSION_2: 1191bdcd8170SKalle Valo meta = (struct wmi_rx_meta_v2 *) skb->data; 1192bdcd8170SKalle Valo if (meta->csum_flags & 0x1) { 1193bdcd8170SKalle Valo skb->ip_summed = CHECKSUM_COMPLETE; 1194bdcd8170SKalle Valo skb->csum = (__force __wsum) meta->csum; 1195bdcd8170SKalle Valo } 1196bdcd8170SKalle Valo skb_pull(skb, sizeof(struct wmi_rx_meta_v2)); 1197bdcd8170SKalle Valo break; 1198bdcd8170SKalle Valo default: 1199bdcd8170SKalle Valo break; 1200bdcd8170SKalle Valo } 1201bdcd8170SKalle Valo 1202bdcd8170SKalle Valo if (dot11_hdr) 1203bdcd8170SKalle Valo status = ath6kl_wmi_dot11_hdr_remove(ar->wmi, skb); 1204bdcd8170SKalle Valo else if (!is_amsdu) 1205bdcd8170SKalle Valo status = ath6kl_wmi_dot3_2_dix(skb); 1206bdcd8170SKalle Valo 1207bdcd8170SKalle Valo if (status) { 1208bdcd8170SKalle Valo /* 1209bdcd8170SKalle Valo * Drop frames that could not be processed (lack of 1210bdcd8170SKalle Valo * memory, etc.) 1211bdcd8170SKalle Valo */ 1212bdcd8170SKalle Valo dev_kfree_skb(skb); 1213bdcd8170SKalle Valo return; 1214bdcd8170SKalle Valo } 1215bdcd8170SKalle Valo 1216bdcd8170SKalle Valo if (!(ar->net_dev->flags & IFF_UP)) { 1217bdcd8170SKalle Valo dev_kfree_skb(skb); 1218bdcd8170SKalle Valo return; 1219bdcd8170SKalle Valo } 1220bdcd8170SKalle Valo 1221bdcd8170SKalle Valo if (ar->nw_type == AP_NETWORK) { 1222bdcd8170SKalle Valo datap = (struct ethhdr *) skb->data; 1223bdcd8170SKalle Valo if (is_multicast_ether_addr(datap->h_dest)) 1224bdcd8170SKalle Valo /* 1225bdcd8170SKalle Valo * Bcast/Mcast frames should be sent to the 1226bdcd8170SKalle Valo * OS stack as well as on the air. 1227bdcd8170SKalle Valo */ 1228bdcd8170SKalle Valo skb1 = skb_copy(skb, GFP_ATOMIC); 1229bdcd8170SKalle Valo else { 1230bdcd8170SKalle Valo /* 1231bdcd8170SKalle Valo * Search for a connected STA with dstMac 1232bdcd8170SKalle Valo * as the Mac address. If found send the 1233bdcd8170SKalle Valo * frame to it on the air else send the 1234bdcd8170SKalle Valo * frame up the stack. 1235bdcd8170SKalle Valo */ 1236bdcd8170SKalle Valo struct ath6kl_sta *conn = NULL; 1237bdcd8170SKalle Valo conn = ath6kl_find_sta(ar, datap->h_dest); 1238bdcd8170SKalle Valo 1239bdcd8170SKalle Valo if (conn && ar->intra_bss) { 1240bdcd8170SKalle Valo skb1 = skb; 1241bdcd8170SKalle Valo skb = NULL; 1242bdcd8170SKalle Valo } else if (conn && !ar->intra_bss) { 1243bdcd8170SKalle Valo dev_kfree_skb(skb); 1244bdcd8170SKalle Valo skb = NULL; 1245bdcd8170SKalle Valo } 1246bdcd8170SKalle Valo } 1247bdcd8170SKalle Valo if (skb1) 1248bdcd8170SKalle Valo ath6kl_data_tx(skb1, ar->net_dev); 1249bdcd8170SKalle Valo } 1250bdcd8170SKalle Valo 12515694f962SKalle Valo datap = (struct ethhdr *) skb->data; 12525694f962SKalle Valo 12535694f962SKalle Valo if (is_unicast_ether_addr(datap->h_dest) && 12545694f962SKalle Valo aggr_process_recv_frm(ar->aggr_cntxt, tid, seq_no, 1255bdcd8170SKalle Valo is_amsdu, skb)) 12565694f962SKalle Valo /* aggregation code will handle the skb */ 12575694f962SKalle Valo return; 12585694f962SKalle Valo 1259bdcd8170SKalle Valo ath6kl_deliver_frames_to_nw_stack(ar->net_dev, skb); 1260bdcd8170SKalle Valo } 1261bdcd8170SKalle Valo 1262bdcd8170SKalle Valo static void aggr_timeout(unsigned long arg) 1263bdcd8170SKalle Valo { 1264bdcd8170SKalle Valo u8 i, j; 1265bdcd8170SKalle Valo struct aggr_info *p_aggr = (struct aggr_info *) arg; 1266bdcd8170SKalle Valo struct rxtid *rxtid; 1267bdcd8170SKalle Valo struct rxtid_stats *stats; 1268bdcd8170SKalle Valo 1269bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1270bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[i]; 1271bdcd8170SKalle Valo stats = &p_aggr->stat[i]; 1272bdcd8170SKalle Valo 1273bdcd8170SKalle Valo if (!rxtid->aggr || !rxtid->timer_mon || rxtid->progress) 1274bdcd8170SKalle Valo continue; 1275bdcd8170SKalle Valo 1276bdcd8170SKalle Valo stats->num_timeouts++; 127737ca6335SKalle Valo ath6kl_dbg(ATH6KL_DBG_AGGR, 127837ca6335SKalle Valo "aggr timeout (st %d end %d)\n", 1279bdcd8170SKalle Valo rxtid->seq_next, 1280bdcd8170SKalle Valo ((rxtid->seq_next + rxtid->hold_q_sz-1) & 1281bdcd8170SKalle Valo ATH6KL_MAX_SEQ_NO)); 1282bdcd8170SKalle Valo aggr_deque_frms(p_aggr, i, 0, 0); 1283bdcd8170SKalle Valo } 1284bdcd8170SKalle Valo 1285bdcd8170SKalle Valo p_aggr->timer_scheduled = false; 1286bdcd8170SKalle Valo 1287bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1288bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[i]; 1289bdcd8170SKalle Valo 1290bdcd8170SKalle Valo if (rxtid->aggr && rxtid->hold_q) { 1291bdcd8170SKalle Valo for (j = 0; j < rxtid->hold_q_sz; j++) { 1292bdcd8170SKalle Valo if (rxtid->hold_q[j].skb) { 1293bdcd8170SKalle Valo p_aggr->timer_scheduled = true; 1294bdcd8170SKalle Valo rxtid->timer_mon = true; 1295bdcd8170SKalle Valo rxtid->progress = false; 1296bdcd8170SKalle Valo break; 1297bdcd8170SKalle Valo } 1298bdcd8170SKalle Valo } 1299bdcd8170SKalle Valo 1300bdcd8170SKalle Valo if (j >= rxtid->hold_q_sz) 1301bdcd8170SKalle Valo rxtid->timer_mon = false; 1302bdcd8170SKalle Valo } 1303bdcd8170SKalle Valo } 1304bdcd8170SKalle Valo 1305bdcd8170SKalle Valo if (p_aggr->timer_scheduled) 1306bdcd8170SKalle Valo mod_timer(&p_aggr->timer, 1307bdcd8170SKalle Valo jiffies + msecs_to_jiffies(AGGR_RX_TIMEOUT)); 1308bdcd8170SKalle Valo } 1309bdcd8170SKalle Valo 1310bdcd8170SKalle Valo static void aggr_delete_tid_state(struct aggr_info *p_aggr, u8 tid) 1311bdcd8170SKalle Valo { 1312bdcd8170SKalle Valo struct rxtid *rxtid; 1313bdcd8170SKalle Valo struct rxtid_stats *stats; 1314bdcd8170SKalle Valo 1315bdcd8170SKalle Valo if (!p_aggr || tid >= NUM_OF_TIDS) 1316bdcd8170SKalle Valo return; 1317bdcd8170SKalle Valo 1318bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1319bdcd8170SKalle Valo stats = &p_aggr->stat[tid]; 1320bdcd8170SKalle Valo 1321bdcd8170SKalle Valo if (rxtid->aggr) 1322bdcd8170SKalle Valo aggr_deque_frms(p_aggr, tid, 0, 0); 1323bdcd8170SKalle Valo 1324bdcd8170SKalle Valo rxtid->aggr = false; 1325bdcd8170SKalle Valo rxtid->progress = false; 1326bdcd8170SKalle Valo rxtid->timer_mon = false; 1327bdcd8170SKalle Valo rxtid->win_sz = 0; 1328bdcd8170SKalle Valo rxtid->seq_next = 0; 1329bdcd8170SKalle Valo rxtid->hold_q_sz = 0; 1330bdcd8170SKalle Valo 1331bdcd8170SKalle Valo kfree(rxtid->hold_q); 1332bdcd8170SKalle Valo rxtid->hold_q = NULL; 1333bdcd8170SKalle Valo 1334bdcd8170SKalle Valo memset(stats, 0, sizeof(struct rxtid_stats)); 1335bdcd8170SKalle Valo } 1336bdcd8170SKalle Valo 1337bdcd8170SKalle Valo void aggr_recv_addba_req_evt(struct ath6kl *ar, u8 tid, u16 seq_no, u8 win_sz) 1338bdcd8170SKalle Valo { 1339bdcd8170SKalle Valo struct aggr_info *p_aggr = ar->aggr_cntxt; 1340bdcd8170SKalle Valo struct rxtid *rxtid; 1341bdcd8170SKalle Valo struct rxtid_stats *stats; 1342bdcd8170SKalle Valo u16 hold_q_size; 1343bdcd8170SKalle Valo 1344bdcd8170SKalle Valo if (!p_aggr) 1345bdcd8170SKalle Valo return; 1346bdcd8170SKalle Valo 1347bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1348bdcd8170SKalle Valo stats = &p_aggr->stat[tid]; 1349bdcd8170SKalle Valo 1350bdcd8170SKalle Valo if (win_sz < AGGR_WIN_SZ_MIN || win_sz > AGGR_WIN_SZ_MAX) 1351bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_WLAN_RX, "%s: win_sz %d, tid %d\n", 1352bdcd8170SKalle Valo __func__, win_sz, tid); 1353bdcd8170SKalle Valo 1354bdcd8170SKalle Valo if (rxtid->aggr) 1355bdcd8170SKalle Valo aggr_delete_tid_state(p_aggr, tid); 1356bdcd8170SKalle Valo 1357bdcd8170SKalle Valo rxtid->seq_next = seq_no; 1358bdcd8170SKalle Valo hold_q_size = TID_WINDOW_SZ(win_sz) * sizeof(struct skb_hold_q); 1359bdcd8170SKalle Valo rxtid->hold_q = kzalloc(hold_q_size, GFP_KERNEL); 1360bdcd8170SKalle Valo if (!rxtid->hold_q) 1361bdcd8170SKalle Valo return; 1362bdcd8170SKalle Valo 1363bdcd8170SKalle Valo rxtid->win_sz = win_sz; 1364bdcd8170SKalle Valo rxtid->hold_q_sz = TID_WINDOW_SZ(win_sz); 1365bdcd8170SKalle Valo if (!skb_queue_empty(&rxtid->q)) 1366bdcd8170SKalle Valo return; 1367bdcd8170SKalle Valo 1368bdcd8170SKalle Valo rxtid->aggr = true; 1369bdcd8170SKalle Valo } 1370bdcd8170SKalle Valo 1371bdcd8170SKalle Valo struct aggr_info *aggr_init(struct net_device *dev) 1372bdcd8170SKalle Valo { 1373bdcd8170SKalle Valo struct aggr_info *p_aggr = NULL; 1374bdcd8170SKalle Valo struct rxtid *rxtid; 1375bdcd8170SKalle Valo u8 i; 1376bdcd8170SKalle Valo 1377bdcd8170SKalle Valo p_aggr = kzalloc(sizeof(struct aggr_info), GFP_KERNEL); 1378bdcd8170SKalle Valo if (!p_aggr) { 1379bdcd8170SKalle Valo ath6kl_err("failed to alloc memory for aggr_node\n"); 1380bdcd8170SKalle Valo return NULL; 1381bdcd8170SKalle Valo } 1382bdcd8170SKalle Valo 1383bdcd8170SKalle Valo p_aggr->aggr_sz = AGGR_SZ_DEFAULT; 1384bdcd8170SKalle Valo p_aggr->dev = dev; 1385bdcd8170SKalle Valo init_timer(&p_aggr->timer); 1386bdcd8170SKalle Valo p_aggr->timer.function = aggr_timeout; 1387bdcd8170SKalle Valo p_aggr->timer.data = (unsigned long) p_aggr; 1388bdcd8170SKalle Valo 1389bdcd8170SKalle Valo p_aggr->timer_scheduled = false; 1390bdcd8170SKalle Valo skb_queue_head_init(&p_aggr->free_q); 1391bdcd8170SKalle Valo 1392bdcd8170SKalle Valo ath6kl_alloc_netbufs(&p_aggr->free_q, AGGR_NUM_OF_FREE_NETBUFS); 1393bdcd8170SKalle Valo 1394bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1395bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[i]; 1396bdcd8170SKalle Valo rxtid->aggr = false; 1397bdcd8170SKalle Valo rxtid->progress = false; 1398bdcd8170SKalle Valo rxtid->timer_mon = false; 1399bdcd8170SKalle Valo skb_queue_head_init(&rxtid->q); 1400bdcd8170SKalle Valo spin_lock_init(&rxtid->lock); 1401bdcd8170SKalle Valo } 1402bdcd8170SKalle Valo 1403bdcd8170SKalle Valo return p_aggr; 1404bdcd8170SKalle Valo } 1405bdcd8170SKalle Valo 1406bdcd8170SKalle Valo void aggr_recv_delba_req_evt(struct ath6kl *ar, u8 tid) 1407bdcd8170SKalle Valo { 1408bdcd8170SKalle Valo struct aggr_info *p_aggr = ar->aggr_cntxt; 1409bdcd8170SKalle Valo struct rxtid *rxtid; 1410bdcd8170SKalle Valo 1411bdcd8170SKalle Valo if (!p_aggr) 1412bdcd8170SKalle Valo return; 1413bdcd8170SKalle Valo 1414bdcd8170SKalle Valo rxtid = &p_aggr->rx_tid[tid]; 1415bdcd8170SKalle Valo 1416bdcd8170SKalle Valo if (rxtid->aggr) 1417bdcd8170SKalle Valo aggr_delete_tid_state(p_aggr, tid); 1418bdcd8170SKalle Valo } 1419bdcd8170SKalle Valo 1420bdcd8170SKalle Valo void aggr_reset_state(struct aggr_info *aggr_info) 1421bdcd8170SKalle Valo { 1422bdcd8170SKalle Valo u8 tid; 1423bdcd8170SKalle Valo 1424bdcd8170SKalle Valo for (tid = 0; tid < NUM_OF_TIDS; tid++) 1425bdcd8170SKalle Valo aggr_delete_tid_state(aggr_info, tid); 1426bdcd8170SKalle Valo } 1427bdcd8170SKalle Valo 1428bdcd8170SKalle Valo /* clean up our amsdu buffer list */ 1429bdcd8170SKalle Valo void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar) 1430bdcd8170SKalle Valo { 1431bdcd8170SKalle Valo struct htc_packet *packet, *tmp_pkt; 1432bdcd8170SKalle Valo 1433bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 1434bdcd8170SKalle Valo if (list_empty(&ar->amsdu_rx_buffer_queue)) { 1435bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 1436bdcd8170SKalle Valo return; 1437bdcd8170SKalle Valo } 1438bdcd8170SKalle Valo 1439bdcd8170SKalle Valo list_for_each_entry_safe(packet, tmp_pkt, &ar->amsdu_rx_buffer_queue, 1440bdcd8170SKalle Valo list) { 1441bdcd8170SKalle Valo list_del(&packet->list); 1442bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 1443bdcd8170SKalle Valo dev_kfree_skb(packet->pkt_cntxt); 1444bdcd8170SKalle Valo spin_lock_bh(&ar->lock); 1445bdcd8170SKalle Valo } 1446bdcd8170SKalle Valo 1447bdcd8170SKalle Valo spin_unlock_bh(&ar->lock); 1448bdcd8170SKalle Valo } 1449bdcd8170SKalle Valo 1450bdcd8170SKalle Valo void aggr_module_destroy(struct aggr_info *aggr_info) 1451bdcd8170SKalle Valo { 1452bdcd8170SKalle Valo struct rxtid *rxtid; 1453bdcd8170SKalle Valo u8 i, k; 1454bdcd8170SKalle Valo 1455bdcd8170SKalle Valo if (!aggr_info) 1456bdcd8170SKalle Valo return; 1457bdcd8170SKalle Valo 1458bdcd8170SKalle Valo if (aggr_info->timer_scheduled) { 1459bdcd8170SKalle Valo del_timer(&aggr_info->timer); 1460bdcd8170SKalle Valo aggr_info->timer_scheduled = false; 1461bdcd8170SKalle Valo } 1462bdcd8170SKalle Valo 1463bdcd8170SKalle Valo for (i = 0; i < NUM_OF_TIDS; i++) { 1464bdcd8170SKalle Valo rxtid = &aggr_info->rx_tid[i]; 1465bdcd8170SKalle Valo if (rxtid->hold_q) { 1466bdcd8170SKalle Valo for (k = 0; k < rxtid->hold_q_sz; k++) 1467bdcd8170SKalle Valo dev_kfree_skb(rxtid->hold_q[k].skb); 1468bdcd8170SKalle Valo kfree(rxtid->hold_q); 1469bdcd8170SKalle Valo } 1470bdcd8170SKalle Valo 1471bdcd8170SKalle Valo skb_queue_purge(&rxtid->q); 1472bdcd8170SKalle Valo } 1473bdcd8170SKalle Valo 1474bdcd8170SKalle Valo skb_queue_purge(&aggr_info->free_q); 1475bdcd8170SKalle Valo kfree(aggr_info); 1476bdcd8170SKalle Valo } 1477