1*bdcd8170SKalle Valo /* 2*bdcd8170SKalle Valo * Copyright (c) 2004-2011 Atheros Communications Inc. 3*bdcd8170SKalle Valo * 4*bdcd8170SKalle Valo * Permission to use, copy, modify, and/or distribute this software for any 5*bdcd8170SKalle Valo * purpose with or without fee is hereby granted, provided that the above 6*bdcd8170SKalle Valo * copyright notice and this permission notice appear in all copies. 7*bdcd8170SKalle Valo * 8*bdcd8170SKalle Valo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*bdcd8170SKalle Valo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*bdcd8170SKalle Valo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*bdcd8170SKalle Valo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*bdcd8170SKalle Valo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*bdcd8170SKalle Valo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*bdcd8170SKalle Valo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*bdcd8170SKalle Valo */ 16*bdcd8170SKalle Valo 17*bdcd8170SKalle Valo #include "core.h" 18*bdcd8170SKalle Valo #include "debug.h" 19*bdcd8170SKalle Valo 20*bdcd8170SKalle Valo int ath6kl_printk(const char *level, const char *fmt, ...) 21*bdcd8170SKalle Valo { 22*bdcd8170SKalle Valo struct va_format vaf; 23*bdcd8170SKalle Valo va_list args; 24*bdcd8170SKalle Valo int rtn; 25*bdcd8170SKalle Valo 26*bdcd8170SKalle Valo va_start(args, fmt); 27*bdcd8170SKalle Valo 28*bdcd8170SKalle Valo vaf.fmt = fmt; 29*bdcd8170SKalle Valo vaf.va = &args; 30*bdcd8170SKalle Valo 31*bdcd8170SKalle Valo rtn = printk("%sath6kl: %pV", level, &vaf); 32*bdcd8170SKalle Valo 33*bdcd8170SKalle Valo va_end(args); 34*bdcd8170SKalle Valo 35*bdcd8170SKalle Valo return rtn; 36*bdcd8170SKalle Valo } 37*bdcd8170SKalle Valo 38*bdcd8170SKalle Valo #ifdef CONFIG_ATH6KL_DEBUG 39*bdcd8170SKalle Valo void ath6kl_dump_registers(struct ath6kl_device *dev, 40*bdcd8170SKalle Valo struct ath6kl_irq_proc_registers *irq_proc_reg, 41*bdcd8170SKalle Valo struct ath6kl_irq_enable_reg *irq_enable_reg) 42*bdcd8170SKalle Valo { 43*bdcd8170SKalle Valo 44*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, ("<------- Register Table -------->\n")); 45*bdcd8170SKalle Valo 46*bdcd8170SKalle Valo if (irq_proc_reg != NULL) { 47*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 48*bdcd8170SKalle Valo "Host Int status: 0x%x\n", 49*bdcd8170SKalle Valo irq_proc_reg->host_int_status); 50*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 51*bdcd8170SKalle Valo "CPU Int status: 0x%x\n", 52*bdcd8170SKalle Valo irq_proc_reg->cpu_int_status); 53*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 54*bdcd8170SKalle Valo "Error Int status: 0x%x\n", 55*bdcd8170SKalle Valo irq_proc_reg->error_int_status); 56*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 57*bdcd8170SKalle Valo "Counter Int status: 0x%x\n", 58*bdcd8170SKalle Valo irq_proc_reg->counter_int_status); 59*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 60*bdcd8170SKalle Valo "Mbox Frame: 0x%x\n", 61*bdcd8170SKalle Valo irq_proc_reg->mbox_frame); 62*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 63*bdcd8170SKalle Valo "Rx Lookahead Valid: 0x%x\n", 64*bdcd8170SKalle Valo irq_proc_reg->rx_lkahd_valid); 65*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 66*bdcd8170SKalle Valo "Rx Lookahead 0: 0x%x\n", 67*bdcd8170SKalle Valo irq_proc_reg->rx_lkahd[0]); 68*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 69*bdcd8170SKalle Valo "Rx Lookahead 1: 0x%x\n", 70*bdcd8170SKalle Valo irq_proc_reg->rx_lkahd[1]); 71*bdcd8170SKalle Valo 72*bdcd8170SKalle Valo if (dev->ar->mbox_info.gmbox_addr != 0) { 73*bdcd8170SKalle Valo /* 74*bdcd8170SKalle Valo * If the target supports GMBOX hardware, dump some 75*bdcd8170SKalle Valo * additional state. 76*bdcd8170SKalle Valo */ 77*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 78*bdcd8170SKalle Valo "GMBOX Host Int status 2: 0x%x\n", 79*bdcd8170SKalle Valo irq_proc_reg->host_int_status2); 80*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 81*bdcd8170SKalle Valo "GMBOX RX Avail: 0x%x\n", 82*bdcd8170SKalle Valo irq_proc_reg->gmbox_rx_avail); 83*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 84*bdcd8170SKalle Valo "GMBOX lookahead alias 0: 0x%x\n", 85*bdcd8170SKalle Valo irq_proc_reg->rx_gmbox_lkahd_alias[0]); 86*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 87*bdcd8170SKalle Valo "GMBOX lookahead alias 1: 0x%x\n", 88*bdcd8170SKalle Valo irq_proc_reg->rx_gmbox_lkahd_alias[1]); 89*bdcd8170SKalle Valo } 90*bdcd8170SKalle Valo 91*bdcd8170SKalle Valo } 92*bdcd8170SKalle Valo 93*bdcd8170SKalle Valo if (irq_enable_reg != NULL) { 94*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 95*bdcd8170SKalle Valo "Int status Enable: 0x%x\n", 96*bdcd8170SKalle Valo irq_enable_reg->int_status_en); 97*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, "Counter Int status Enable: 0x%x\n", 98*bdcd8170SKalle Valo irq_enable_reg->cntr_int_status_en); 99*bdcd8170SKalle Valo } 100*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, "<------------------------------->\n"); 101*bdcd8170SKalle Valo } 102*bdcd8170SKalle Valo 103*bdcd8170SKalle Valo static void dump_cred_dist(struct htc_endpoint_credit_dist *ep_dist) 104*bdcd8170SKalle Valo { 105*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 106*bdcd8170SKalle Valo "--- endpoint: %d svc_id: 0x%X ---\n", 107*bdcd8170SKalle Valo ep_dist->endpoint, ep_dist->svc_id); 108*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, " dist_flags : 0x%X\n", 109*bdcd8170SKalle Valo ep_dist->dist_flags); 110*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, " cred_norm : %d\n", 111*bdcd8170SKalle Valo ep_dist->cred_norm); 112*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, " cred_min : %d\n", 113*bdcd8170SKalle Valo ep_dist->cred_min); 114*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, " credits : %d\n", 115*bdcd8170SKalle Valo ep_dist->credits); 116*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, " cred_assngd : %d\n", 117*bdcd8170SKalle Valo ep_dist->cred_assngd); 118*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, " seek_cred : %d\n", 119*bdcd8170SKalle Valo ep_dist->seek_cred); 120*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, " cred_sz : %d\n", 121*bdcd8170SKalle Valo ep_dist->cred_sz); 122*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, " cred_per_msg : %d\n", 123*bdcd8170SKalle Valo ep_dist->cred_per_msg); 124*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, " cred_to_dist : %d\n", 125*bdcd8170SKalle Valo ep_dist->cred_to_dist); 126*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, " txq_depth : %d\n", 127*bdcd8170SKalle Valo get_queue_depth(&((struct htc_endpoint *) 128*bdcd8170SKalle Valo ep_dist->htc_rsvd)->txq)); 129*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_ANY, 130*bdcd8170SKalle Valo "----------------------------------\n"); 131*bdcd8170SKalle Valo } 132*bdcd8170SKalle Valo 133*bdcd8170SKalle Valo void dump_cred_dist_stats(struct htc_target *target) 134*bdcd8170SKalle Valo { 135*bdcd8170SKalle Valo struct htc_endpoint_credit_dist *ep_list; 136*bdcd8170SKalle Valo 137*bdcd8170SKalle Valo if (!AR_DBG_LVL_CHECK(ATH6KL_DBG_TRC)) 138*bdcd8170SKalle Valo return; 139*bdcd8170SKalle Valo 140*bdcd8170SKalle Valo list_for_each_entry(ep_list, &target->cred_dist_list, list) 141*bdcd8170SKalle Valo dump_cred_dist(ep_list); 142*bdcd8170SKalle Valo 143*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_HTC_SEND, "ctxt:%p dist:%p\n", 144*bdcd8170SKalle Valo target->cred_dist_cntxt, NULL); 145*bdcd8170SKalle Valo ath6kl_dbg(ATH6KL_DBG_TRC, "credit distribution, total : %d, free : %d\n", 146*bdcd8170SKalle Valo target->cred_dist_cntxt->total_avail_credits, 147*bdcd8170SKalle Valo target->cred_dist_cntxt->cur_free_credits); 148*bdcd8170SKalle Valo } 149*bdcd8170SKalle Valo 150*bdcd8170SKalle Valo #endif 151