1 /* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 */ 20 21 /***********************\ 22 * PHY related functions * 23 \***********************/ 24 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <asm/unaligned.h> 28 29 #include "ath5k.h" 30 #include "reg.h" 31 #include "rfbuffer.h" 32 #include "rfgain.h" 33 #include "../regd.h" 34 35 36 /** 37 * DOC: PHY related functions 38 * 39 * Here we handle the low-level functions related to baseband 40 * and analog frontend (RF) parts. This is by far the most complex 41 * part of the hw code so make sure you know what you are doing. 42 * 43 * Here is a list of what this is all about: 44 * 45 * - Channel setting/switching 46 * 47 * - Automatic Gain Control (AGC) calibration 48 * 49 * - Noise Floor calibration 50 * 51 * - I/Q imbalance calibration (QAM correction) 52 * 53 * - Calibration due to thermal changes (gain_F) 54 * 55 * - Spur noise mitigation 56 * 57 * - RF/PHY initialization for the various operating modes and bwmodes 58 * 59 * - Antenna control 60 * 61 * - TX power control per channel/rate/packet type 62 * 63 * Also have in mind we never got documentation for most of these 64 * functions, what we have comes mostly from Atheros's code, reverse 65 * engineering and patent docs/presentations etc. 66 */ 67 68 69 /******************\ 70 * Helper functions * 71 \******************/ 72 73 /** 74 * ath5k_hw_radio_revision() - Get the PHY Chip revision 75 * @ah: The &struct ath5k_hw 76 * @band: One of enum ieee80211_band 77 * 78 * Returns the revision number of a 2GHz, 5GHz or single chip 79 * radio. 80 */ 81 u16 82 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band) 83 { 84 unsigned int i; 85 u32 srev; 86 u16 ret; 87 88 /* 89 * Set the radio chip access register 90 */ 91 switch (band) { 92 case IEEE80211_BAND_2GHZ: 93 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 94 break; 95 case IEEE80211_BAND_5GHZ: 96 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 97 break; 98 default: 99 return 0; 100 } 101 102 usleep_range(2000, 2500); 103 104 /* ...wait until PHY is ready and read the selected radio revision */ 105 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 106 107 for (i = 0; i < 8; i++) 108 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 109 110 if (ah->ah_version == AR5K_AR5210) { 111 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 112 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 113 } else { 114 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 115 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 116 ((srev & 0x0f) << 4), 8); 117 } 118 119 /* Reset to the 5GHz mode */ 120 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 121 122 return ret; 123 } 124 125 /** 126 * ath5k_channel_ok() - Check if a channel is supported by the hw 127 * @ah: The &struct ath5k_hw 128 * @channel: The &struct ieee80211_channel 129 * 130 * Note: We don't do any regulatory domain checks here, it's just 131 * a sanity check. 132 */ 133 bool 134 ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) 135 { 136 u16 freq = channel->center_freq; 137 138 /* Check if the channel is in our supported range */ 139 if (channel->band == IEEE80211_BAND_2GHZ) { 140 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 141 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 142 return true; 143 } else if (channel->band == IEEE80211_BAND_5GHZ) 144 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 145 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 146 return true; 147 148 return false; 149 } 150 151 /** 152 * ath5k_hw_chan_has_spur_noise() - Check if channel is sensitive to spur noise 153 * @ah: The &struct ath5k_hw 154 * @channel: The &struct ieee80211_channel 155 */ 156 bool 157 ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 158 struct ieee80211_channel *channel) 159 { 160 u8 refclk_freq; 161 162 if ((ah->ah_radio == AR5K_RF5112) || 163 (ah->ah_radio == AR5K_RF5413) || 164 (ah->ah_radio == AR5K_RF2413) || 165 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 166 refclk_freq = 40; 167 else 168 refclk_freq = 32; 169 170 if ((channel->center_freq % refclk_freq != 0) && 171 ((channel->center_freq % refclk_freq < 10) || 172 (channel->center_freq % refclk_freq > 22))) 173 return true; 174 else 175 return false; 176 } 177 178 /** 179 * ath5k_hw_rfb_op() - Perform an operation on the given RF Buffer 180 * @ah: The &struct ath5k_hw 181 * @rf_regs: The struct ath5k_rf_reg 182 * @val: New value 183 * @reg_id: RF register ID 184 * @set: Indicate we need to swap data 185 * 186 * This is an internal function used to modify RF Banks before 187 * writing them to AR5K_RF_BUFFER. Check out rfbuffer.h for more 188 * infos. 189 */ 190 static unsigned int 191 ath5k_hw_rfb_op(struct ath5k_hw *ah, const struct ath5k_rf_reg *rf_regs, 192 u32 val, u8 reg_id, bool set) 193 { 194 const struct ath5k_rf_reg *rfreg = NULL; 195 u8 offset, bank, num_bits, col, position; 196 u16 entry; 197 u32 mask, data, last_bit, bits_shifted, first_bit; 198 u32 *rfb; 199 s32 bits_left; 200 int i; 201 202 data = 0; 203 rfb = ah->ah_rf_banks; 204 205 for (i = 0; i < ah->ah_rf_regs_count; i++) { 206 if (rf_regs[i].index == reg_id) { 207 rfreg = &rf_regs[i]; 208 break; 209 } 210 } 211 212 if (rfb == NULL || rfreg == NULL) { 213 ATH5K_PRINTF("Rf register not found!\n"); 214 /* should not happen */ 215 return 0; 216 } 217 218 bank = rfreg->bank; 219 num_bits = rfreg->field.len; 220 first_bit = rfreg->field.pos; 221 col = rfreg->field.col; 222 223 /* first_bit is an offset from bank's 224 * start. Since we have all banks on 225 * the same array, we use this offset 226 * to mark each bank's start */ 227 offset = ah->ah_offset[bank]; 228 229 /* Boundary check */ 230 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 231 ATH5K_PRINTF("invalid values at offset %u\n", offset); 232 return 0; 233 } 234 235 entry = ((first_bit - 1) / 8) + offset; 236 position = (first_bit - 1) % 8; 237 238 if (set) 239 data = ath5k_hw_bitswap(val, num_bits); 240 241 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 242 position = 0, entry++) { 243 244 last_bit = (position + bits_left > 8) ? 8 : 245 position + bits_left; 246 247 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 248 (col * 8); 249 250 if (set) { 251 rfb[entry] &= ~mask; 252 rfb[entry] |= ((data << position) << (col * 8)) & mask; 253 data >>= (8 - position); 254 } else { 255 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 256 << bits_shifted; 257 bits_shifted += last_bit - position; 258 } 259 260 bits_left -= 8 - position; 261 } 262 263 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 264 265 return data; 266 } 267 268 /** 269 * ath5k_hw_write_ofdm_timings() - set OFDM timings on AR5212 270 * @ah: the &struct ath5k_hw 271 * @channel: the currently set channel upon reset 272 * 273 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 274 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init. 275 * 276 * Since delta slope is floating point we split it on its exponent and 277 * mantissa and provide these values on hw. 278 * 279 * For more infos i think this patent is related 280 * "http://www.freepatentsonline.com/7184495.html" 281 */ 282 static inline int 283 ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 284 struct ieee80211_channel *channel) 285 { 286 /* Get exponent and mantissa and set it */ 287 u32 coef_scaled, coef_exp, coef_man, 288 ds_coef_exp, ds_coef_man, clock; 289 290 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 291 (channel->hw_value == AR5K_MODE_11B)); 292 293 /* Get coefficient 294 * ALGO: coef = (5 * clock / carrier_freq) / 2 295 * we scale coef by shifting clock value by 24 for 296 * better precision since we use integers */ 297 switch (ah->ah_bwmode) { 298 case AR5K_BWMODE_40MHZ: 299 clock = 40 * 2; 300 break; 301 case AR5K_BWMODE_10MHZ: 302 clock = 40 / 2; 303 break; 304 case AR5K_BWMODE_5MHZ: 305 clock = 40 / 4; 306 break; 307 default: 308 clock = 40; 309 break; 310 } 311 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 312 313 /* Get exponent 314 * ALGO: coef_exp = 14 - highest set bit position */ 315 coef_exp = ilog2(coef_scaled); 316 317 /* Doesn't make sense if it's zero*/ 318 if (!coef_scaled || !coef_exp) 319 return -EINVAL; 320 321 /* Note: we've shifted coef_scaled by 24 */ 322 coef_exp = 14 - (coef_exp - 24); 323 324 325 /* Get mantissa (significant digits) 326 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 327 coef_man = coef_scaled + 328 (1 << (24 - coef_exp - 1)); 329 330 /* Calculate delta slope coefficient exponent 331 * and mantissa (remove scaling) and set them on hw */ 332 ds_coef_man = coef_man >> (24 - coef_exp); 333 ds_coef_exp = coef_exp - 16; 334 335 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 336 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 337 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 338 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 339 340 return 0; 341 } 342 343 /** 344 * ath5k_hw_phy_disable() - Disable PHY 345 * @ah: The &struct ath5k_hw 346 */ 347 int ath5k_hw_phy_disable(struct ath5k_hw *ah) 348 { 349 /*Just a try M.F.*/ 350 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 351 352 return 0; 353 } 354 355 /** 356 * ath5k_hw_wait_for_synth() - Wait for synth to settle 357 * @ah: The &struct ath5k_hw 358 * @channel: The &struct ieee80211_channel 359 */ 360 static void 361 ath5k_hw_wait_for_synth(struct ath5k_hw *ah, 362 struct ieee80211_channel *channel) 363 { 364 /* 365 * On 5211+ read activation -> rx delay 366 * and use it (100ns steps). 367 */ 368 if (ah->ah_version != AR5K_AR5210) { 369 u32 delay; 370 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 371 AR5K_PHY_RX_DELAY_M; 372 delay = (channel->hw_value == AR5K_MODE_11B) ? 373 ((delay << 2) / 22) : (delay / 10); 374 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) 375 delay = delay << 1; 376 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) 377 delay = delay << 2; 378 /* XXX: /2 on turbo ? Let's be safe 379 * for now */ 380 usleep_range(100 + delay, 100 + (2 * delay)); 381 } else { 382 usleep_range(1000, 1500); 383 } 384 } 385 386 387 /**********************\ 388 * RF Gain optimization * 389 \**********************/ 390 391 /** 392 * DOC: RF Gain optimization 393 * 394 * This code is used to optimize RF gain on different environments 395 * (temperature mostly) based on feedback from a power detector. 396 * 397 * It's only used on RF5111 and RF5112, later RF chips seem to have 398 * auto adjustment on hw -notice they have a much smaller BANK 7 and 399 * no gain optimization ladder-. 400 * 401 * For more infos check out this patent doc 402 * "http://www.freepatentsonline.com/7400691.html" 403 * 404 * This paper describes power drops as seen on the receiver due to 405 * probe packets 406 * "http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 407 * %20of%20Power%20Control.pdf" 408 * 409 * And this is the MadWiFi bug entry related to the above 410 * "http://madwifi-project.org/ticket/1659" 411 * with various measurements and diagrams 412 */ 413 414 /** 415 * ath5k_hw_rfgain_opt_init() - Initialize ah_gain during attach 416 * @ah: The &struct ath5k_hw 417 */ 418 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 419 { 420 /* Initialize the gain optimization values */ 421 switch (ah->ah_radio) { 422 case AR5K_RF5111: 423 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 424 ah->ah_gain.g_low = 20; 425 ah->ah_gain.g_high = 35; 426 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 427 break; 428 case AR5K_RF5112: 429 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 430 ah->ah_gain.g_low = 20; 431 ah->ah_gain.g_high = 85; 432 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 433 break; 434 default: 435 return -EINVAL; 436 } 437 438 return 0; 439 } 440 441 /** 442 * ath5k_hw_request_rfgain_probe() - Request a PAPD probe packet 443 * @ah: The &struct ath5k_hw 444 * 445 * Schedules a gain probe check on the next transmitted packet. 446 * That means our next packet is going to be sent with lower 447 * tx power and a Peak to Average Power Detector (PAPD) will try 448 * to measure the gain. 449 * 450 * TODO: Force a tx packet (bypassing PCU arbitrator etc) 451 * just after we enable the probe so that we don't mess with 452 * standard traffic. 453 */ 454 static void 455 ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 456 { 457 458 /* Skip if gain calibration is inactive or 459 * we already handle a probe request */ 460 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 461 return; 462 463 /* Send the packet with 2dB below max power as 464 * patent doc suggest */ 465 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 466 AR5K_PHY_PAPD_PROBE_TXPOWER) | 467 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 468 469 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 470 471 } 472 473 /** 474 * ath5k_hw_rf_gainf_corr() - Calculate Gain_F measurement correction 475 * @ah: The &struct ath5k_hw 476 * 477 * Calculate Gain_F measurement correction 478 * based on the current step for RF5112 rev. 2 479 */ 480 static u32 481 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 482 { 483 u32 mix, step; 484 u32 *rf; 485 const struct ath5k_gain_opt *go; 486 const struct ath5k_gain_opt_step *g_step; 487 const struct ath5k_rf_reg *rf_regs; 488 489 /* Only RF5112 Rev. 2 supports it */ 490 if ((ah->ah_radio != AR5K_RF5112) || 491 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 492 return 0; 493 494 go = &rfgain_opt_5112; 495 rf_regs = rf_regs_5112a; 496 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 497 498 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 499 500 if (ah->ah_rf_banks == NULL) 501 return 0; 502 503 rf = ah->ah_rf_banks; 504 ah->ah_gain.g_f_corr = 0; 505 506 /* No VGA (Variable Gain Amplifier) override, skip */ 507 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 508 return 0; 509 510 /* Mix gain stepping */ 511 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 512 513 /* Mix gain override */ 514 mix = g_step->gos_param[0]; 515 516 switch (mix) { 517 case 3: 518 ah->ah_gain.g_f_corr = step * 2; 519 break; 520 case 2: 521 ah->ah_gain.g_f_corr = (step - 5) * 2; 522 break; 523 case 1: 524 ah->ah_gain.g_f_corr = step; 525 break; 526 default: 527 ah->ah_gain.g_f_corr = 0; 528 break; 529 } 530 531 return ah->ah_gain.g_f_corr; 532 } 533 534 /** 535 * ath5k_hw_rf_check_gainf_readback() - Validate Gain_F feedback from detector 536 * @ah: The &struct ath5k_hw 537 * 538 * Check if current gain_F measurement is in the range of our 539 * power detector windows. If we get a measurement outside range 540 * we know it's not accurate (detectors can't measure anything outside 541 * their detection window) so we must ignore it. 542 * 543 * Returns true if readback was O.K. or false on failure 544 */ 545 static bool 546 ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 547 { 548 const struct ath5k_rf_reg *rf_regs; 549 u32 step, mix_ovr, level[4]; 550 u32 *rf; 551 552 if (ah->ah_rf_banks == NULL) 553 return false; 554 555 rf = ah->ah_rf_banks; 556 557 if (ah->ah_radio == AR5K_RF5111) { 558 559 rf_regs = rf_regs_5111; 560 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 561 562 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 563 false); 564 565 level[0] = 0; 566 level[1] = (step == 63) ? 50 : step + 4; 567 level[2] = (step != 63) ? 64 : level[0]; 568 level[3] = level[2] + 50; 569 570 ah->ah_gain.g_high = level[3] - 571 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 572 ah->ah_gain.g_low = level[0] + 573 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 574 } else { 575 576 rf_regs = rf_regs_5112; 577 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 578 579 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 580 false); 581 582 level[0] = level[2] = 0; 583 584 if (mix_ovr == 1) { 585 level[1] = level[3] = 83; 586 } else { 587 level[1] = level[3] = 107; 588 ah->ah_gain.g_high = 55; 589 } 590 } 591 592 return (ah->ah_gain.g_current >= level[0] && 593 ah->ah_gain.g_current <= level[1]) || 594 (ah->ah_gain.g_current >= level[2] && 595 ah->ah_gain.g_current <= level[3]); 596 } 597 598 /** 599 * ath5k_hw_rf_gainf_adjust() - Perform Gain_F adjustment 600 * @ah: The &struct ath5k_hw 601 * 602 * Choose the right target gain based on current gain 603 * and RF gain optimization ladder 604 */ 605 static s8 606 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 607 { 608 const struct ath5k_gain_opt *go; 609 const struct ath5k_gain_opt_step *g_step; 610 int ret = 0; 611 612 switch (ah->ah_radio) { 613 case AR5K_RF5111: 614 go = &rfgain_opt_5111; 615 break; 616 case AR5K_RF5112: 617 go = &rfgain_opt_5112; 618 break; 619 default: 620 return 0; 621 } 622 623 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 624 625 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 626 627 /* Reached maximum */ 628 if (ah->ah_gain.g_step_idx == 0) 629 return -1; 630 631 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 632 ah->ah_gain.g_target >= ah->ah_gain.g_high && 633 ah->ah_gain.g_step_idx > 0; 634 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 635 ah->ah_gain.g_target -= 2 * 636 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 637 g_step->gos_gain); 638 639 ret = 1; 640 goto done; 641 } 642 643 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 644 645 /* Reached minimum */ 646 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 647 return -2; 648 649 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 650 ah->ah_gain.g_target <= ah->ah_gain.g_low && 651 ah->ah_gain.g_step_idx < go->go_steps_count - 1; 652 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 653 ah->ah_gain.g_target -= 2 * 654 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 655 g_step->gos_gain); 656 657 ret = 2; 658 goto done; 659 } 660 661 done: 662 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 663 "ret %d, gain step %u, current gain %u, target gain %u\n", 664 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 665 ah->ah_gain.g_target); 666 667 return ret; 668 } 669 670 /** 671 * ath5k_hw_gainf_calibrate() - Do a gain_F calibration 672 * @ah: The &struct ath5k_hw 673 * 674 * Main callback for thermal RF gain calibration engine 675 * Check for a new gain reading and schedule an adjustment 676 * if needed. 677 * 678 * Returns one of enum ath5k_rfgain codes 679 */ 680 enum ath5k_rfgain 681 ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 682 { 683 u32 data, type; 684 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 685 686 if (ah->ah_rf_banks == NULL || 687 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 688 return AR5K_RFGAIN_INACTIVE; 689 690 /* No check requested, either engine is inactive 691 * or an adjustment is already requested */ 692 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 693 goto done; 694 695 /* Read the PAPD (Peak to Average Power Detector) 696 * register */ 697 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 698 699 /* No probe is scheduled, read gain_F measurement */ 700 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 701 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 702 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 703 704 /* If tx packet is CCK correct the gain_F measurement 705 * by cck ofdm gain delta */ 706 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 707 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 708 ah->ah_gain.g_current += 709 ee->ee_cck_ofdm_gain_delta; 710 else 711 ah->ah_gain.g_current += 712 AR5K_GAIN_CCK_PROBE_CORR; 713 } 714 715 /* Further correct gain_F measurement for 716 * RF5112A radios */ 717 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 718 ath5k_hw_rf_gainf_corr(ah); 719 ah->ah_gain.g_current = 720 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 721 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) : 722 0; 723 } 724 725 /* Check if measurement is ok and if we need 726 * to adjust gain, schedule a gain adjustment, 727 * else switch back to the active state */ 728 if (ath5k_hw_rf_check_gainf_readback(ah) && 729 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 730 ath5k_hw_rf_gainf_adjust(ah)) { 731 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 732 } else { 733 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 734 } 735 } 736 737 done: 738 return ah->ah_gain.g_state; 739 } 740 741 /** 742 * ath5k_hw_rfgain_init() - Write initial RF gain settings to hw 743 * @ah: The &struct ath5k_hw 744 * @band: One of enum ieee80211_band 745 * 746 * Write initial RF gain table to set the RF sensitivity. 747 * 748 * NOTE: This one works on all RF chips and has nothing to do 749 * with Gain_F calibration 750 */ 751 static int 752 ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band) 753 { 754 const struct ath5k_ini_rfgain *ath5k_rfg; 755 unsigned int i, size, index; 756 757 switch (ah->ah_radio) { 758 case AR5K_RF5111: 759 ath5k_rfg = rfgain_5111; 760 size = ARRAY_SIZE(rfgain_5111); 761 break; 762 case AR5K_RF5112: 763 ath5k_rfg = rfgain_5112; 764 size = ARRAY_SIZE(rfgain_5112); 765 break; 766 case AR5K_RF2413: 767 ath5k_rfg = rfgain_2413; 768 size = ARRAY_SIZE(rfgain_2413); 769 break; 770 case AR5K_RF2316: 771 ath5k_rfg = rfgain_2316; 772 size = ARRAY_SIZE(rfgain_2316); 773 break; 774 case AR5K_RF5413: 775 ath5k_rfg = rfgain_5413; 776 size = ARRAY_SIZE(rfgain_5413); 777 break; 778 case AR5K_RF2317: 779 case AR5K_RF2425: 780 ath5k_rfg = rfgain_2425; 781 size = ARRAY_SIZE(rfgain_2425); 782 break; 783 default: 784 return -EINVAL; 785 } 786 787 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0; 788 789 for (i = 0; i < size; i++) { 790 AR5K_REG_WAIT(i); 791 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index], 792 (u32)ath5k_rfg[i].rfg_register); 793 } 794 795 return 0; 796 } 797 798 799 /********************\ 800 * RF Registers setup * 801 \********************/ 802 803 /** 804 * ath5k_hw_rfregs_init() - Initialize RF register settings 805 * @ah: The &struct ath5k_hw 806 * @channel: The &struct ieee80211_channel 807 * @mode: One of enum ath5k_driver_mode 808 * 809 * Setup RF registers by writing RF buffer on hw. For 810 * more infos on this, check out rfbuffer.h 811 */ 812 static int 813 ath5k_hw_rfregs_init(struct ath5k_hw *ah, 814 struct ieee80211_channel *channel, 815 unsigned int mode) 816 { 817 const struct ath5k_rf_reg *rf_regs; 818 const struct ath5k_ini_rfbuffer *ini_rfb; 819 const struct ath5k_gain_opt *go = NULL; 820 const struct ath5k_gain_opt_step *g_step; 821 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 822 u8 ee_mode = 0; 823 u32 *rfb; 824 int i, obdb = -1, bank = -1; 825 826 switch (ah->ah_radio) { 827 case AR5K_RF5111: 828 rf_regs = rf_regs_5111; 829 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 830 ini_rfb = rfb_5111; 831 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 832 go = &rfgain_opt_5111; 833 break; 834 case AR5K_RF5112: 835 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 836 rf_regs = rf_regs_5112a; 837 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 838 ini_rfb = rfb_5112a; 839 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 840 } else { 841 rf_regs = rf_regs_5112; 842 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 843 ini_rfb = rfb_5112; 844 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 845 } 846 go = &rfgain_opt_5112; 847 break; 848 case AR5K_RF2413: 849 rf_regs = rf_regs_2413; 850 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 851 ini_rfb = rfb_2413; 852 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 853 break; 854 case AR5K_RF2316: 855 rf_regs = rf_regs_2316; 856 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 857 ini_rfb = rfb_2316; 858 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 859 break; 860 case AR5K_RF5413: 861 rf_regs = rf_regs_5413; 862 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 863 ini_rfb = rfb_5413; 864 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 865 break; 866 case AR5K_RF2317: 867 rf_regs = rf_regs_2425; 868 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 869 ini_rfb = rfb_2317; 870 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 871 break; 872 case AR5K_RF2425: 873 rf_regs = rf_regs_2425; 874 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 875 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 876 ini_rfb = rfb_2425; 877 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 878 } else { 879 ini_rfb = rfb_2417; 880 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 881 } 882 break; 883 default: 884 return -EINVAL; 885 } 886 887 /* If it's the first time we set RF buffer, allocate 888 * ah->ah_rf_banks based on ah->ah_rf_banks_size 889 * we set above */ 890 if (ah->ah_rf_banks == NULL) { 891 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 892 GFP_KERNEL); 893 if (ah->ah_rf_banks == NULL) { 894 ATH5K_ERR(ah, "out of memory\n"); 895 return -ENOMEM; 896 } 897 } 898 899 /* Copy values to modify them */ 900 rfb = ah->ah_rf_banks; 901 902 for (i = 0; i < ah->ah_rf_banks_size; i++) { 903 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 904 ATH5K_ERR(ah, "invalid bank\n"); 905 return -EINVAL; 906 } 907 908 /* Bank changed, write down the offset */ 909 if (bank != ini_rfb[i].rfb_bank) { 910 bank = ini_rfb[i].rfb_bank; 911 ah->ah_offset[bank] = i; 912 } 913 914 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 915 } 916 917 /* Set Output and Driver bias current (OB/DB) */ 918 if (channel->band == IEEE80211_BAND_2GHZ) { 919 920 if (channel->hw_value == AR5K_MODE_11B) 921 ee_mode = AR5K_EEPROM_MODE_11B; 922 else 923 ee_mode = AR5K_EEPROM_MODE_11G; 924 925 /* For RF511X/RF211X combination we 926 * use b_OB and b_DB parameters stored 927 * in eeprom on ee->ee_ob[ee_mode][0] 928 * 929 * For all other chips we use OB/DB for 2GHz 930 * stored in the b/g modal section just like 931 * 802.11a on ee->ee_ob[ee_mode][1] */ 932 if ((ah->ah_radio == AR5K_RF5111) || 933 (ah->ah_radio == AR5K_RF5112)) 934 obdb = 0; 935 else 936 obdb = 1; 937 938 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 939 AR5K_RF_OB_2GHZ, true); 940 941 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 942 AR5K_RF_DB_2GHZ, true); 943 944 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 945 } else if ((channel->band == IEEE80211_BAND_5GHZ) || 946 (ah->ah_radio == AR5K_RF5111)) { 947 948 /* For 11a, Turbo and XR we need to choose 949 * OB/DB based on frequency range */ 950 ee_mode = AR5K_EEPROM_MODE_11A; 951 obdb = channel->center_freq >= 5725 ? 3 : 952 (channel->center_freq >= 5500 ? 2 : 953 (channel->center_freq >= 5260 ? 1 : 954 (channel->center_freq > 4000 ? 0 : -1))); 955 956 if (obdb < 0) 957 return -EINVAL; 958 959 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 960 AR5K_RF_OB_5GHZ, true); 961 962 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 963 AR5K_RF_DB_5GHZ, true); 964 } 965 966 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 967 968 /* Set turbo mode (N/A on RF5413) */ 969 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) && 970 (ah->ah_radio != AR5K_RF5413)) 971 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false); 972 973 /* Bank Modifications (chip-specific) */ 974 if (ah->ah_radio == AR5K_RF5111) { 975 976 /* Set gain_F settings according to current step */ 977 if (channel->hw_value != AR5K_MODE_11B) { 978 979 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 980 AR5K_PHY_FRAME_CTL_TX_CLIP, 981 g_step->gos_param[0]); 982 983 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 984 AR5K_RF_PWD_90, true); 985 986 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 987 AR5K_RF_PWD_84, true); 988 989 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 990 AR5K_RF_RFGAIN_SEL, true); 991 992 /* We programmed gain_F parameters, switch back 993 * to active state */ 994 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 995 996 } 997 998 /* Bank 6/7 setup */ 999 1000 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 1001 AR5K_RF_PWD_XPD, true); 1002 1003 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 1004 AR5K_RF_XPD_GAIN, true); 1005 1006 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 1007 AR5K_RF_GAIN_I, true); 1008 1009 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 1010 AR5K_RF_PLO_SEL, true); 1011 1012 /* Tweak power detectors for half/quarter rate support */ 1013 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 1014 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 1015 u8 wait_i; 1016 1017 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, 1018 AR5K_RF_WAIT_S, true); 1019 1020 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 1021 0x1f : 0x10; 1022 1023 ath5k_hw_rfb_op(ah, rf_regs, wait_i, 1024 AR5K_RF_WAIT_I, true); 1025 ath5k_hw_rfb_op(ah, rf_regs, 3, 1026 AR5K_RF_MAX_TIME, true); 1027 1028 } 1029 } 1030 1031 if (ah->ah_radio == AR5K_RF5112) { 1032 1033 /* Set gain_F settings according to current step */ 1034 if (channel->hw_value != AR5K_MODE_11B) { 1035 1036 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 1037 AR5K_RF_MIXGAIN_OVR, true); 1038 1039 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 1040 AR5K_RF_PWD_138, true); 1041 1042 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 1043 AR5K_RF_PWD_137, true); 1044 1045 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 1046 AR5K_RF_PWD_136, true); 1047 1048 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 1049 AR5K_RF_PWD_132, true); 1050 1051 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 1052 AR5K_RF_PWD_131, true); 1053 1054 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 1055 AR5K_RF_PWD_130, true); 1056 1057 /* We programmed gain_F parameters, switch back 1058 * to active state */ 1059 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 1060 } 1061 1062 /* Bank 6/7 setup */ 1063 1064 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 1065 AR5K_RF_XPD_SEL, true); 1066 1067 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 1068 /* Rev. 1 supports only one xpd */ 1069 ath5k_hw_rfb_op(ah, rf_regs, 1070 ee->ee_x_gain[ee_mode], 1071 AR5K_RF_XPD_GAIN, true); 1072 1073 } else { 1074 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 1075 if (ee->ee_pd_gains[ee_mode] > 1) { 1076 ath5k_hw_rfb_op(ah, rf_regs, 1077 pdg_curve_to_idx[0], 1078 AR5K_RF_PD_GAIN_LO, true); 1079 ath5k_hw_rfb_op(ah, rf_regs, 1080 pdg_curve_to_idx[1], 1081 AR5K_RF_PD_GAIN_HI, true); 1082 } else { 1083 ath5k_hw_rfb_op(ah, rf_regs, 1084 pdg_curve_to_idx[0], 1085 AR5K_RF_PD_GAIN_LO, true); 1086 ath5k_hw_rfb_op(ah, rf_regs, 1087 pdg_curve_to_idx[0], 1088 AR5K_RF_PD_GAIN_HI, true); 1089 } 1090 1091 /* Lower synth voltage on Rev 2 */ 1092 if (ah->ah_radio == AR5K_RF5112 && 1093 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) { 1094 ath5k_hw_rfb_op(ah, rf_regs, 2, 1095 AR5K_RF_HIGH_VC_CP, true); 1096 1097 ath5k_hw_rfb_op(ah, rf_regs, 2, 1098 AR5K_RF_MID_VC_CP, true); 1099 1100 ath5k_hw_rfb_op(ah, rf_regs, 2, 1101 AR5K_RF_LOW_VC_CP, true); 1102 1103 ath5k_hw_rfb_op(ah, rf_regs, 2, 1104 AR5K_RF_PUSH_UP, true); 1105 } 1106 1107 /* Decrease power consumption on 5213+ BaseBand */ 1108 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 1109 ath5k_hw_rfb_op(ah, rf_regs, 1, 1110 AR5K_RF_PAD2GND, true); 1111 1112 ath5k_hw_rfb_op(ah, rf_regs, 1, 1113 AR5K_RF_XB2_LVL, true); 1114 1115 ath5k_hw_rfb_op(ah, rf_regs, 1, 1116 AR5K_RF_XB5_LVL, true); 1117 1118 ath5k_hw_rfb_op(ah, rf_regs, 1, 1119 AR5K_RF_PWD_167, true); 1120 1121 ath5k_hw_rfb_op(ah, rf_regs, 1, 1122 AR5K_RF_PWD_166, true); 1123 } 1124 } 1125 1126 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 1127 AR5K_RF_GAIN_I, true); 1128 1129 /* Tweak power detector for half/quarter rates */ 1130 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 1131 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 1132 u8 pd_delay; 1133 1134 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 1135 0xf : 0x8; 1136 1137 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, 1138 AR5K_RF_PD_PERIOD_A, true); 1139 ath5k_hw_rfb_op(ah, rf_regs, 0xf, 1140 AR5K_RF_PD_DELAY_A, true); 1141 1142 } 1143 } 1144 1145 if (ah->ah_radio == AR5K_RF5413 && 1146 channel->band == IEEE80211_BAND_2GHZ) { 1147 1148 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 1149 true); 1150 1151 /* Set optimum value for early revisions (on pci-e chips) */ 1152 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 1153 ah->ah_mac_srev < AR5K_SREV_AR5413) 1154 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 1155 AR5K_RF_PWD_ICLOBUF_2G, true); 1156 1157 } 1158 1159 /* Write RF banks on hw */ 1160 for (i = 0; i < ah->ah_rf_banks_size; i++) { 1161 AR5K_REG_WAIT(i); 1162 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 1163 } 1164 1165 return 0; 1166 } 1167 1168 1169 /**************************\ 1170 PHY/RF channel functions 1171 \**************************/ 1172 1173 /** 1174 * ath5k_hw_rf5110_chan2athchan() - Convert channel freq on RF5110 1175 * @channel: The &struct ieee80211_channel 1176 * 1177 * Map channel frequency to IEEE channel number and convert it 1178 * to an internal channel value used by the RF5110 chipset. 1179 */ 1180 static u32 1181 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 1182 { 1183 u32 athchan; 1184 1185 athchan = (ath5k_hw_bitswap( 1186 (ieee80211_frequency_to_channel( 1187 channel->center_freq) - 24) / 2, 5) 1188 << 1) | (1 << 6) | 0x1; 1189 return athchan; 1190 } 1191 1192 /** 1193 * ath5k_hw_rf5110_channel() - Set channel frequency on RF5110 1194 * @ah: The &struct ath5k_hw 1195 * @channel: The &struct ieee80211_channel 1196 */ 1197 static int 1198 ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 1199 struct ieee80211_channel *channel) 1200 { 1201 u32 data; 1202 1203 /* 1204 * Set the channel and wait 1205 */ 1206 data = ath5k_hw_rf5110_chan2athchan(channel); 1207 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 1208 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 1209 usleep_range(1000, 1500); 1210 1211 return 0; 1212 } 1213 1214 /** 1215 * ath5k_hw_rf5111_chan2athchan() - Handle 2GHz channels on RF5111/2111 1216 * @ieee: IEEE channel number 1217 * @athchan: The &struct ath5k_athchan_2ghz 1218 * 1219 * In order to enable the RF2111 frequency converter on RF5111/2111 setups 1220 * we need to add some offsets and extra flags to the data values we pass 1221 * on to the PHY. So for every 2GHz channel this function gets called 1222 * to do the conversion. 1223 */ 1224 static int 1225 ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 1226 struct ath5k_athchan_2ghz *athchan) 1227 { 1228 int channel; 1229 1230 /* Cast this value to catch negative channel numbers (>= -19) */ 1231 channel = (int)ieee; 1232 1233 /* 1234 * Map 2GHz IEEE channel to 5GHz Atheros channel 1235 */ 1236 if (channel <= 13) { 1237 athchan->a2_athchan = 115 + channel; 1238 athchan->a2_flags = 0x46; 1239 } else if (channel == 14) { 1240 athchan->a2_athchan = 124; 1241 athchan->a2_flags = 0x44; 1242 } else if (channel >= 15 && channel <= 26) { 1243 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1244 athchan->a2_flags = 0x46; 1245 } else 1246 return -EINVAL; 1247 1248 return 0; 1249 } 1250 1251 /** 1252 * ath5k_hw_rf5111_channel() - Set channel frequency on RF5111/2111 1253 * @ah: The &struct ath5k_hw 1254 * @channel: The &struct ieee80211_channel 1255 */ 1256 static int 1257 ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 1258 struct ieee80211_channel *channel) 1259 { 1260 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 1261 unsigned int ath5k_channel = 1262 ieee80211_frequency_to_channel(channel->center_freq); 1263 u32 data0, data1, clock; 1264 int ret; 1265 1266 /* 1267 * Set the channel on the RF5111 radio 1268 */ 1269 data0 = data1 = 0; 1270 1271 if (channel->band == IEEE80211_BAND_2GHZ) { 1272 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1273 ret = ath5k_hw_rf5111_chan2athchan( 1274 ieee80211_frequency_to_channel(channel->center_freq), 1275 &ath5k_channel_2ghz); 1276 if (ret) 1277 return ret; 1278 1279 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 1280 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 1281 << 5) | (1 << 4); 1282 } 1283 1284 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 1285 clock = 1; 1286 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 1287 (clock << 1) | (1 << 10) | 1; 1288 } else { 1289 clock = 0; 1290 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 1291 << 2) | (clock << 1) | (1 << 10) | 1; 1292 } 1293 1294 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 1295 AR5K_RF_BUFFER); 1296 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 1297 AR5K_RF_BUFFER_CONTROL_3); 1298 1299 return 0; 1300 } 1301 1302 /** 1303 * ath5k_hw_rf5112_channel() - Set channel frequency on 5112 and newer 1304 * @ah: The &struct ath5k_hw 1305 * @channel: The &struct ieee80211_channel 1306 * 1307 * On RF5112/2112 and newer we don't need to do any conversion. 1308 * We pass the frequency value after a few modifications to the 1309 * chip directly. 1310 * 1311 * NOTE: Make sure channel frequency given is within our range or else 1312 * we might damage the chip ! Use ath5k_channel_ok before calling this one. 1313 */ 1314 static int 1315 ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 1316 struct ieee80211_channel *channel) 1317 { 1318 u32 data, data0, data1, data2; 1319 u16 c; 1320 1321 data = data0 = data1 = data2 = 0; 1322 c = channel->center_freq; 1323 1324 /* My guess based on code: 1325 * 2GHz RF has 2 synth modes, one with a Local Oscillator 1326 * at 2224Hz and one with a LO at 2192Hz. IF is 1520Hz 1327 * (3040/2). data0 is used to set the PLL divider and data1 1328 * selects synth mode. */ 1329 if (c < 4800) { 1330 /* Channel 14 and all frequencies with 2Hz spacing 1331 * below/above (non-standard channels) */ 1332 if (!((c - 2224) % 5)) { 1333 /* Same as (c - 2224) / 5 */ 1334 data0 = ((2 * (c - 704)) - 3040) / 10; 1335 data1 = 1; 1336 /* Channel 1 and all frequencies with 5Hz spacing 1337 * below/above (standard channels without channel 14) */ 1338 } else if (!((c - 2192) % 5)) { 1339 /* Same as (c - 2192) / 5 */ 1340 data0 = ((2 * (c - 672)) - 3040) / 10; 1341 data1 = 0; 1342 } else 1343 return -EINVAL; 1344 1345 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 1346 /* This is more complex, we have a single synthesizer with 1347 * 4 reference clock settings (?) based on frequency spacing 1348 * and set using data2. LO is at 4800Hz and data0 is again used 1349 * to set some divider. 1350 * 1351 * NOTE: There is an old atheros presentation at Stanford 1352 * that mentions a method called dual direct conversion 1353 * with 1GHz sliding IF for RF5110. Maybe that's what we 1354 * have here, or an updated version. */ 1355 } else if ((c % 5) != 2 || c > 5435) { 1356 if (!(c % 20) && c >= 5120) { 1357 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1358 data2 = ath5k_hw_bitswap(3, 2); 1359 } else if (!(c % 10)) { 1360 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1361 data2 = ath5k_hw_bitswap(2, 2); 1362 } else if (!(c % 5)) { 1363 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1364 data2 = ath5k_hw_bitswap(1, 2); 1365 } else 1366 return -EINVAL; 1367 } else { 1368 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1369 data2 = ath5k_hw_bitswap(0, 2); 1370 } 1371 1372 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1373 1374 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1375 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1376 1377 return 0; 1378 } 1379 1380 /** 1381 * ath5k_hw_rf2425_channel() - Set channel frequency on RF2425 1382 * @ah: The &struct ath5k_hw 1383 * @channel: The &struct ieee80211_channel 1384 * 1385 * AR2425/2417 have a different 2GHz RF so code changes 1386 * a little bit from RF5112. 1387 */ 1388 static int 1389 ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1390 struct ieee80211_channel *channel) 1391 { 1392 u32 data, data0, data2; 1393 u16 c; 1394 1395 data = data0 = data2 = 0; 1396 c = channel->center_freq; 1397 1398 if (c < 4800) { 1399 data0 = ath5k_hw_bitswap((c - 2272), 8); 1400 data2 = 0; 1401 /* ? 5GHz ? */ 1402 } else if ((c % 5) != 2 || c > 5435) { 1403 if (!(c % 20) && c < 5120) 1404 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1405 else if (!(c % 10)) 1406 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1407 else if (!(c % 5)) 1408 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1409 else 1410 return -EINVAL; 1411 data2 = ath5k_hw_bitswap(1, 2); 1412 } else { 1413 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1414 data2 = ath5k_hw_bitswap(0, 2); 1415 } 1416 1417 data = (data0 << 4) | data2 << 2 | 0x1001; 1418 1419 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1420 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1421 1422 return 0; 1423 } 1424 1425 /** 1426 * ath5k_hw_channel() - Set a channel on the radio chip 1427 * @ah: The &struct ath5k_hw 1428 * @channel: The &struct ieee80211_channel 1429 * 1430 * This is the main function called to set a channel on the 1431 * radio chip based on the radio chip version. 1432 */ 1433 static int 1434 ath5k_hw_channel(struct ath5k_hw *ah, 1435 struct ieee80211_channel *channel) 1436 { 1437 int ret; 1438 /* 1439 * Check bounds supported by the PHY (we don't care about regulatory 1440 * restrictions at this point). 1441 */ 1442 if (!ath5k_channel_ok(ah, channel)) { 1443 ATH5K_ERR(ah, 1444 "channel frequency (%u MHz) out of supported " 1445 "band range\n", 1446 channel->center_freq); 1447 return -EINVAL; 1448 } 1449 1450 /* 1451 * Set the channel and wait 1452 */ 1453 switch (ah->ah_radio) { 1454 case AR5K_RF5110: 1455 ret = ath5k_hw_rf5110_channel(ah, channel); 1456 break; 1457 case AR5K_RF5111: 1458 ret = ath5k_hw_rf5111_channel(ah, channel); 1459 break; 1460 case AR5K_RF2317: 1461 case AR5K_RF2425: 1462 ret = ath5k_hw_rf2425_channel(ah, channel); 1463 break; 1464 default: 1465 ret = ath5k_hw_rf5112_channel(ah, channel); 1466 break; 1467 } 1468 1469 if (ret) 1470 return ret; 1471 1472 /* Set JAPAN setting for channel 14 */ 1473 if (channel->center_freq == 2484) { 1474 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1475 AR5K_PHY_CCKTXCTL_JAPAN); 1476 } else { 1477 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1478 AR5K_PHY_CCKTXCTL_WORLD); 1479 } 1480 1481 ah->ah_current_channel = channel; 1482 1483 return 0; 1484 } 1485 1486 1487 /*****************\ 1488 PHY calibration 1489 \*****************/ 1490 1491 /** 1492 * DOC: PHY Calibration routines 1493 * 1494 * Noise floor calibration: When we tell the hardware to 1495 * perform a noise floor calibration by setting the 1496 * AR5K_PHY_AGCCTL_NF bit on AR5K_PHY_AGCCTL, it will periodically 1497 * sample-and-hold the minimum noise level seen at the antennas. 1498 * This value is then stored in a ring buffer of recently measured 1499 * noise floor values so we have a moving window of the last few 1500 * samples. The median of the values in the history is then loaded 1501 * into the hardware for its own use for RSSI and CCA measurements. 1502 * This type of calibration doesn't interfere with traffic. 1503 * 1504 * AGC calibration: When we tell the hardware to perform 1505 * an AGC (Automatic Gain Control) calibration by setting the 1506 * AR5K_PHY_AGCCTL_CAL, hw disconnects the antennas and does 1507 * a calibration on the DC offsets of ADCs. During this period 1508 * rx/tx gets disabled so we have to deal with it on the driver 1509 * part. 1510 * 1511 * I/Q calibration: When we tell the hardware to perform 1512 * an I/Q calibration, it tries to correct I/Q imbalance and 1513 * fix QAM constellation by sampling data from rxed frames. 1514 * It doesn't interfere with traffic. 1515 * 1516 * For more infos on AGC and I/Q calibration check out patent doc 1517 * #03/094463. 1518 */ 1519 1520 /** 1521 * ath5k_hw_read_measured_noise_floor() - Read measured NF from hw 1522 * @ah: The &struct ath5k_hw 1523 */ 1524 static s32 1525 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1526 { 1527 s32 val; 1528 1529 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1530 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); 1531 } 1532 1533 /** 1534 * ath5k_hw_init_nfcal_hist() - Initialize NF calibration history buffer 1535 * @ah: The &struct ath5k_hw 1536 */ 1537 void 1538 ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1539 { 1540 int i; 1541 1542 ah->ah_nfcal_hist.index = 0; 1543 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1544 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1545 } 1546 1547 /** 1548 * ath5k_hw_update_nfcal_hist() - Update NF calibration history buffer 1549 * @ah: The &struct ath5k_hw 1550 * @noise_floor: The NF we got from hw 1551 */ 1552 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1553 { 1554 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1555 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1); 1556 hist->nfval[hist->index] = noise_floor; 1557 } 1558 1559 /** 1560 * ath5k_hw_get_median_noise_floor() - Get median NF from history buffer 1561 * @ah: The &struct ath5k_hw 1562 */ 1563 static s16 1564 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1565 { 1566 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1567 s16 tmp; 1568 int i, j; 1569 1570 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1571 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1572 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1573 if (sort[j] > sort[j - 1]) { 1574 tmp = sort[j]; 1575 sort[j] = sort[j - 1]; 1576 sort[j - 1] = tmp; 1577 } 1578 } 1579 } 1580 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1581 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1582 "cal %d:%d\n", i, sort[i]); 1583 } 1584 return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2]; 1585 } 1586 1587 /** 1588 * ath5k_hw_update_noise_floor() - Update NF on hardware 1589 * @ah: The &struct ath5k_hw 1590 * 1591 * This is the main function we call to perform a NF calibration, 1592 * it reads NF from hardware, calculates the median and updates 1593 * NF on hw. 1594 */ 1595 void 1596 ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1597 { 1598 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1599 u32 val; 1600 s16 nf, threshold; 1601 u8 ee_mode; 1602 1603 /* keep last value if calibration hasn't completed */ 1604 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1605 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1606 "NF did not complete in calibration window\n"); 1607 1608 return; 1609 } 1610 1611 ah->ah_cal_mask |= AR5K_CALIBRATION_NF; 1612 1613 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel); 1614 1615 /* completed NF calibration, test threshold */ 1616 nf = ath5k_hw_read_measured_noise_floor(ah); 1617 threshold = ee->ee_noise_floor_thr[ee_mode]; 1618 1619 if (nf > threshold) { 1620 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1621 "noise floor failure detected; " 1622 "read %d, threshold %d\n", 1623 nf, threshold); 1624 1625 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1626 } 1627 1628 ath5k_hw_update_nfcal_hist(ah, nf); 1629 nf = ath5k_hw_get_median_noise_floor(ah); 1630 1631 /* load noise floor (in .5 dBm) so the hardware will use it */ 1632 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1633 val |= (nf * 2) & AR5K_PHY_NF_M; 1634 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1635 1636 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1637 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1638 1639 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1640 0, false); 1641 1642 /* 1643 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1644 * so that we're not capped by the median we just loaded. 1645 * This will be used as the initial value for the next noise 1646 * floor calibration. 1647 */ 1648 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1649 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1650 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1651 AR5K_PHY_AGCCTL_NF_EN | 1652 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1653 AR5K_PHY_AGCCTL_NF); 1654 1655 ah->ah_noise_floor = nf; 1656 1657 ah->ah_cal_mask &= ~AR5K_CALIBRATION_NF; 1658 1659 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1660 "noise floor calibrated: %d\n", nf); 1661 } 1662 1663 /** 1664 * ath5k_hw_rf5110_calibrate() - Perform a PHY calibration on RF5110 1665 * @ah: The &struct ath5k_hw 1666 * @channel: The &struct ieee80211_channel 1667 * 1668 * Do a complete PHY calibration (AGC + NF + I/Q) on RF5110 1669 */ 1670 static int 1671 ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1672 struct ieee80211_channel *channel) 1673 { 1674 u32 phy_sig, phy_agc, phy_sat, beacon; 1675 int ret; 1676 1677 /* 1678 * Disable beacons and RX/TX queues, wait 1679 */ 1680 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1681 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1682 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1683 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1684 1685 usleep_range(2000, 2500); 1686 1687 /* 1688 * Set the channel (with AGC turned off) 1689 */ 1690 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1691 udelay(10); 1692 ret = ath5k_hw_channel(ah, channel); 1693 1694 /* 1695 * Activate PHY and wait 1696 */ 1697 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1698 usleep_range(1000, 1500); 1699 1700 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1701 1702 if (ret) 1703 return ret; 1704 1705 /* 1706 * Calibrate the radio chip 1707 */ 1708 1709 /* Remember normal state */ 1710 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1711 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1712 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1713 1714 /* Update radio registers */ 1715 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1716 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1717 1718 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1719 AR5K_PHY_AGCCOARSE_LO)) | 1720 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1721 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1722 1723 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1724 AR5K_PHY_ADCSAT_THR)) | 1725 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1726 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1727 1728 udelay(20); 1729 1730 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1731 udelay(10); 1732 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1733 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1734 1735 usleep_range(1000, 1500); 1736 1737 /* 1738 * Enable calibration and wait until completion 1739 */ 1740 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1741 1742 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1743 AR5K_PHY_AGCCTL_CAL, 0, false); 1744 1745 /* Reset to normal state */ 1746 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1747 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1748 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1749 1750 if (ret) { 1751 ATH5K_ERR(ah, "calibration timeout (%uMHz)\n", 1752 channel->center_freq); 1753 return ret; 1754 } 1755 1756 /* 1757 * Re-enable RX/TX and beacons 1758 */ 1759 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1760 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1761 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1762 1763 return 0; 1764 } 1765 1766 /** 1767 * ath5k_hw_rf511x_iq_calibrate() - Perform I/Q calibration on RF5111 and newer 1768 * @ah: The &struct ath5k_hw 1769 */ 1770 static int 1771 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) 1772 { 1773 u32 i_pwr, q_pwr; 1774 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1775 int i; 1776 1777 /* Skip if I/Q calibration is not needed or if it's still running */ 1778 if (!ah->ah_iq_cal_needed) 1779 return -EINVAL; 1780 else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) { 1781 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, 1782 "I/Q calibration still running"); 1783 return -EBUSY; 1784 } 1785 1786 /* Calibration has finished, get the results and re-run */ 1787 1788 /* Work around for empty results which can apparently happen on 5212: 1789 * Read registers up to 10 times until we get both i_pr and q_pwr */ 1790 for (i = 0; i <= 10; i++) { 1791 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1792 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1793 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1794 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, 1795 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1796 if (i_pwr && q_pwr) 1797 break; 1798 } 1799 1800 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1801 1802 if (ah->ah_version == AR5K_AR5211) 1803 q_coffd = q_pwr >> 6; 1804 else 1805 q_coffd = q_pwr >> 7; 1806 1807 /* In case i_coffd became zero, cancel calibration 1808 * not only it's too small, it'll also result a divide 1809 * by zero later on. */ 1810 if (i_coffd == 0 || q_coffd < 2) 1811 return -ECANCELED; 1812 1813 /* Protect against loss of sign bits */ 1814 1815 i_coff = (-iq_corr) / i_coffd; 1816 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1817 1818 if (ah->ah_version == AR5K_AR5211) 1819 q_coff = (i_pwr / q_coffd) - 64; 1820 else 1821 q_coff = (i_pwr / q_coffd) - 128; 1822 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1823 1824 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, 1825 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1826 i_coff, q_coff, i_coffd, q_coffd); 1827 1828 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1829 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1830 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1831 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1832 1833 /* Re-enable calibration -if we don't we'll commit 1834 * the same values again and again */ 1835 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1836 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1837 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1838 1839 return 0; 1840 } 1841 1842 /** 1843 * ath5k_hw_phy_calibrate() - Perform a PHY calibration 1844 * @ah: The &struct ath5k_hw 1845 * @channel: The &struct ieee80211_channel 1846 * 1847 * The main function we call from above to perform 1848 * a short or full PHY calibration based on RF chip 1849 * and current channel 1850 */ 1851 int 1852 ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1853 struct ieee80211_channel *channel) 1854 { 1855 int ret; 1856 1857 if (ah->ah_radio == AR5K_RF5110) 1858 return ath5k_hw_rf5110_calibrate(ah, channel); 1859 1860 ret = ath5k_hw_rf511x_iq_calibrate(ah); 1861 if (ret) { 1862 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, 1863 "No I/Q correction performed (%uMHz)\n", 1864 channel->center_freq); 1865 1866 /* Happens all the time if there is not much 1867 * traffic, consider it normal behaviour. */ 1868 ret = 0; 1869 } 1870 1871 /* On full calibration do an AGC calibration and 1872 * request a PAPD probe for gainf calibration if 1873 * needed */ 1874 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) { 1875 1876 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1877 AR5K_PHY_AGCCTL_CAL); 1878 1879 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1880 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF, 1881 0, false); 1882 if (ret) { 1883 ATH5K_ERR(ah, 1884 "gain calibration timeout (%uMHz)\n", 1885 channel->center_freq); 1886 } 1887 1888 if ((ah->ah_radio == AR5K_RF5111 || 1889 ah->ah_radio == AR5K_RF5112) 1890 && (channel->hw_value != AR5K_MODE_11B)) 1891 ath5k_hw_request_rfgain_probe(ah); 1892 } 1893 1894 /* Update noise floor 1895 * XXX: Only do this after AGC calibration */ 1896 if (!(ah->ah_cal_mask & AR5K_CALIBRATION_NF)) 1897 ath5k_hw_update_noise_floor(ah); 1898 1899 return ret; 1900 } 1901 1902 1903 /***************************\ 1904 * Spur mitigation functions * 1905 \***************************/ 1906 1907 /** 1908 * ath5k_hw_set_spur_mitigation_filter() - Configure SPUR filter 1909 * @ah: The &struct ath5k_hw 1910 * @channel: The &struct ieee80211_channel 1911 * 1912 * This function gets called during PHY initialization to 1913 * configure the spur filter for the given channel. Spur is noise 1914 * generated due to "reflection" effects, for more information on this 1915 * method check out patent US7643810 1916 */ 1917 static void 1918 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1919 struct ieee80211_channel *channel) 1920 { 1921 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1922 u32 mag_mask[4] = {0, 0, 0, 0}; 1923 u32 pilot_mask[2] = {0, 0}; 1924 /* Note: fbin values are scaled up by 2 */ 1925 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1926 s32 spur_delta_phase, spur_freq_sigma_delta; 1927 s32 spur_offset, num_symbols_x16; 1928 u8 num_symbol_offsets, i, freq_band; 1929 1930 /* Convert current frequency to fbin value (the same way channels 1931 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1932 * up by 2 so we can compare it later */ 1933 if (channel->band == IEEE80211_BAND_2GHZ) { 1934 chan_fbin = (channel->center_freq - 2300) * 10; 1935 freq_band = AR5K_EEPROM_BAND_2GHZ; 1936 } else { 1937 chan_fbin = (channel->center_freq - 4900) * 10; 1938 freq_band = AR5K_EEPROM_BAND_5GHZ; 1939 } 1940 1941 /* Check if any spur_chan_fbin from EEPROM is 1942 * within our current channel's spur detection range */ 1943 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1944 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1945 /* XXX: Half/Quarter channels ?*/ 1946 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 1947 spur_detection_window *= 2; 1948 1949 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1950 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1951 1952 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1953 * so it's zero if we got nothing from EEPROM */ 1954 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1955 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1956 break; 1957 } 1958 1959 if ((chan_fbin - spur_detection_window <= 1960 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1961 (chan_fbin + spur_detection_window >= 1962 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1963 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1964 break; 1965 } 1966 } 1967 1968 /* We need to enable spur filter for this channel */ 1969 if (spur_chan_fbin) { 1970 spur_offset = spur_chan_fbin - chan_fbin; 1971 /* 1972 * Calculate deltas: 1973 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1974 * spur_delta_phase -> spur_offset / chip_freq << 11 1975 * Note: Both values have 100Hz resolution 1976 */ 1977 switch (ah->ah_bwmode) { 1978 case AR5K_BWMODE_40MHZ: 1979 /* Both sample_freq and chip_freq are 80MHz */ 1980 spur_delta_phase = (spur_offset << 16) / 25; 1981 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1982 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2; 1983 break; 1984 case AR5K_BWMODE_10MHZ: 1985 /* Both sample_freq and chip_freq are 20MHz (?) */ 1986 spur_delta_phase = (spur_offset << 18) / 25; 1987 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1988 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2; 1989 case AR5K_BWMODE_5MHZ: 1990 /* Both sample_freq and chip_freq are 10MHz (?) */ 1991 spur_delta_phase = (spur_offset << 19) / 25; 1992 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1993 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4; 1994 default: 1995 if (channel->band == IEEE80211_BAND_5GHZ) { 1996 /* Both sample_freq and chip_freq are 40MHz */ 1997 spur_delta_phase = (spur_offset << 17) / 25; 1998 spur_freq_sigma_delta = 1999 (spur_delta_phase >> 10); 2000 symbol_width = 2001 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 2002 } else { 2003 /* sample_freq -> 40MHz chip_freq -> 44MHz 2004 * (for b compatibility) */ 2005 spur_delta_phase = (spur_offset << 17) / 25; 2006 spur_freq_sigma_delta = 2007 (spur_offset << 8) / 55; 2008 symbol_width = 2009 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 2010 } 2011 break; 2012 } 2013 2014 /* Calculate pilot and magnitude masks */ 2015 2016 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 2017 * and divide by symbol_width to find how many symbols we have 2018 * Note: number of symbols is scaled up by 16 */ 2019 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 2020 2021 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 2022 if (!(num_symbols_x16 & 0xF)) 2023 /* _X_ */ 2024 num_symbol_offsets = 3; 2025 else 2026 /* _xx_ */ 2027 num_symbol_offsets = 4; 2028 2029 for (i = 0; i < num_symbol_offsets; i++) { 2030 2031 /* Calculate pilot mask */ 2032 s32 curr_sym_off = 2033 (num_symbols_x16 / 16) + i + 25; 2034 2035 /* Pilot magnitude mask seems to be a way to 2036 * declare the boundaries for our detection 2037 * window or something, it's 2 for the middle 2038 * value(s) where the symbol is expected to be 2039 * and 1 on the boundary values */ 2040 u8 plt_mag_map = 2041 (i == 0 || i == (num_symbol_offsets - 1)) 2042 ? 1 : 2; 2043 2044 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 2045 if (curr_sym_off <= 25) 2046 pilot_mask[0] |= 1 << curr_sym_off; 2047 else if (curr_sym_off >= 27) 2048 pilot_mask[0] |= 1 << (curr_sym_off - 1); 2049 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 2050 pilot_mask[1] |= 1 << (curr_sym_off - 33); 2051 2052 /* Calculate magnitude mask (for viterbi decoder) */ 2053 if (curr_sym_off >= -1 && curr_sym_off <= 14) 2054 mag_mask[0] |= 2055 plt_mag_map << (curr_sym_off + 1) * 2; 2056 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 2057 mag_mask[1] |= 2058 plt_mag_map << (curr_sym_off - 15) * 2; 2059 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 2060 mag_mask[2] |= 2061 plt_mag_map << (curr_sym_off - 31) * 2; 2062 else if (curr_sym_off >= 47 && curr_sym_off <= 53) 2063 mag_mask[3] |= 2064 plt_mag_map << (curr_sym_off - 47) * 2; 2065 2066 } 2067 2068 /* Write settings on hw to enable spur filter */ 2069 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 2070 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 2071 /* XXX: Self correlator also ? */ 2072 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 2073 AR5K_PHY_IQ_PILOT_MASK_EN | 2074 AR5K_PHY_IQ_CHAN_MASK_EN | 2075 AR5K_PHY_IQ_SPUR_FILT_EN); 2076 2077 /* Set delta phase and freq sigma delta */ 2078 ath5k_hw_reg_write(ah, 2079 AR5K_REG_SM(spur_delta_phase, 2080 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 2081 AR5K_REG_SM(spur_freq_sigma_delta, 2082 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 2083 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 2084 AR5K_PHY_TIMING_11); 2085 2086 /* Write pilot masks */ 2087 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 2088 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 2089 AR5K_PHY_TIMING_8_PILOT_MASK_2, 2090 pilot_mask[1]); 2091 2092 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 2093 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 2094 AR5K_PHY_TIMING_10_PILOT_MASK_2, 2095 pilot_mask[1]); 2096 2097 /* Write magnitude masks */ 2098 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 2099 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 2100 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 2101 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 2102 AR5K_PHY_BIN_MASK_CTL_MASK_4, 2103 mag_mask[3]); 2104 2105 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 2106 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 2107 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 2108 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 2109 AR5K_PHY_BIN_MASK2_4_MASK_4, 2110 mag_mask[3]); 2111 2112 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 2113 AR5K_PHY_IQ_SPUR_FILT_EN) { 2114 /* Clean up spur mitigation settings and disable filter */ 2115 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 2116 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 2117 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 2118 AR5K_PHY_IQ_PILOT_MASK_EN | 2119 AR5K_PHY_IQ_CHAN_MASK_EN | 2120 AR5K_PHY_IQ_SPUR_FILT_EN); 2121 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 2122 2123 /* Clear pilot masks */ 2124 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 2125 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 2126 AR5K_PHY_TIMING_8_PILOT_MASK_2, 2127 0); 2128 2129 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 2130 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 2131 AR5K_PHY_TIMING_10_PILOT_MASK_2, 2132 0); 2133 2134 /* Clear magnitude masks */ 2135 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 2136 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 2137 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 2138 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 2139 AR5K_PHY_BIN_MASK_CTL_MASK_4, 2140 0); 2141 2142 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 2143 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 2144 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 2145 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 2146 AR5K_PHY_BIN_MASK2_4_MASK_4, 2147 0); 2148 } 2149 } 2150 2151 2152 /*****************\ 2153 * Antenna control * 2154 \*****************/ 2155 2156 /** 2157 * DOC: Antenna control 2158 * 2159 * Hw supports up to 14 antennas ! I haven't found any card that implements 2160 * that. The maximum number of antennas I've seen is up to 4 (2 for 2GHz and 2 2161 * for 5GHz). Antenna 1 (MAIN) should be omnidirectional, 2 (AUX) 2162 * omnidirectional or sectorial and antennas 3-14 sectorial (or directional). 2163 * 2164 * We can have a single antenna for RX and multiple antennas for TX. 2165 * RX antenna is our "default" antenna (usually antenna 1) set on 2166 * DEFAULT_ANTENNA register and TX antenna is set on each TX control descriptor 2167 * (0 for automatic selection, 1 - 14 antenna number). 2168 * 2169 * We can let hw do all the work doing fast antenna diversity for both 2170 * tx and rx or we can do things manually. Here are the options we have 2171 * (all are bits of STA_ID1 register): 2172 * 2173 * AR5K_STA_ID1_DEFAULT_ANTENNA -> When 0 is set as the TX antenna on TX 2174 * control descriptor, use the default antenna to transmit or else use the last 2175 * antenna on which we received an ACK. 2176 * 2177 * AR5K_STA_ID1_DESC_ANTENNA -> Update default antenna after each TX frame to 2178 * the antenna on which we got the ACK for that frame. 2179 * 2180 * AR5K_STA_ID1_RTS_DEF_ANTENNA -> Use default antenna for RTS or else use the 2181 * one on the TX descriptor. 2182 * 2183 * AR5K_STA_ID1_SELFGEN_DEF_ANT -> Use default antenna for self generated frames 2184 * (ACKs etc), or else use current antenna (the one we just used for TX). 2185 * 2186 * Using the above we support the following scenarios: 2187 * 2188 * AR5K_ANTMODE_DEFAULT -> Hw handles antenna diversity etc automatically 2189 * 2190 * AR5K_ANTMODE_FIXED_A -> Only antenna A (MAIN) is present 2191 * 2192 * AR5K_ANTMODE_FIXED_B -> Only antenna B (AUX) is present 2193 * 2194 * AR5K_ANTMODE_SINGLE_AP -> Sta locked on a single ap 2195 * 2196 * AR5K_ANTMODE_SECTOR_AP -> AP with tx antenna set on tx desc 2197 * 2198 * AR5K_ANTMODE_SECTOR_STA -> STA with tx antenna set on tx desc 2199 * 2200 * AR5K_ANTMODE_DEBUG Debug mode -A -> Rx, B-> Tx- 2201 * 2202 * Also note that when setting antenna to F on tx descriptor card inverts 2203 * current tx antenna. 2204 */ 2205 2206 /** 2207 * ath5k_hw_set_def_antenna() - Set default rx antenna on AR5211/5212 and newer 2208 * @ah: The &struct ath5k_hw 2209 * @ant: Antenna number 2210 */ 2211 static void 2212 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 2213 { 2214 if (ah->ah_version != AR5K_AR5210) 2215 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 2216 } 2217 2218 /** 2219 * ath5k_hw_set_fast_div() - Enable/disable fast rx antenna diversity 2220 * @ah: The &struct ath5k_hw 2221 * @ee_mode: One of enum ath5k_driver_mode 2222 * @enable: True to enable, false to disable 2223 */ 2224 static void 2225 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 2226 { 2227 switch (ee_mode) { 2228 case AR5K_EEPROM_MODE_11G: 2229 /* XXX: This is set to 2230 * disabled on initvals !!! */ 2231 case AR5K_EEPROM_MODE_11A: 2232 if (enable) 2233 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 2234 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 2235 else 2236 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 2237 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 2238 break; 2239 case AR5K_EEPROM_MODE_11B: 2240 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 2241 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 2242 break; 2243 default: 2244 return; 2245 } 2246 2247 if (enable) { 2248 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 2249 AR5K_PHY_RESTART_DIV_GC, 4); 2250 2251 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 2252 AR5K_PHY_FAST_ANT_DIV_EN); 2253 } else { 2254 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 2255 AR5K_PHY_RESTART_DIV_GC, 0); 2256 2257 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 2258 AR5K_PHY_FAST_ANT_DIV_EN); 2259 } 2260 } 2261 2262 /** 2263 * ath5k_hw_set_antenna_switch() - Set up antenna switch table 2264 * @ah: The &struct ath5k_hw 2265 * @ee_mode: One of enum ath5k_driver_mode 2266 * 2267 * Switch table comes from EEPROM and includes information on controlling 2268 * the 2 antenna RX attenuators 2269 */ 2270 void 2271 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) 2272 { 2273 u8 ant0, ant1; 2274 2275 /* 2276 * In case a fixed antenna was set as default 2277 * use the same switch table twice. 2278 */ 2279 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 2280 ant0 = ant1 = AR5K_ANT_SWTABLE_A; 2281 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 2282 ant0 = ant1 = AR5K_ANT_SWTABLE_B; 2283 else { 2284 ant0 = AR5K_ANT_SWTABLE_A; 2285 ant1 = AR5K_ANT_SWTABLE_B; 2286 } 2287 2288 /* Set antenna idle switch table */ 2289 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 2290 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 2291 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | 2292 AR5K_PHY_ANT_CTL_TXRX_EN)); 2293 2294 /* Set antenna switch tables */ 2295 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], 2296 AR5K_PHY_ANT_SWITCH_TABLE_0); 2297 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], 2298 AR5K_PHY_ANT_SWITCH_TABLE_1); 2299 } 2300 2301 /** 2302 * ath5k_hw_set_antenna_mode() - Set antenna operating mode 2303 * @ah: The &struct ath5k_hw 2304 * @ant_mode: One of enum ath5k_ant_mode 2305 */ 2306 void 2307 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 2308 { 2309 struct ieee80211_channel *channel = ah->ah_current_channel; 2310 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 2311 bool use_def_for_sg; 2312 int ee_mode; 2313 u8 def_ant, tx_ant; 2314 u32 sta_id1 = 0; 2315 2316 /* if channel is not initialized yet we can't set the antennas 2317 * so just store the mode. it will be set on the next reset */ 2318 if (channel == NULL) { 2319 ah->ah_ant_mode = ant_mode; 2320 return; 2321 } 2322 2323 def_ant = ah->ah_def_ant; 2324 2325 ee_mode = ath5k_eeprom_mode_from_channel(channel); 2326 if (ee_mode < 0) { 2327 ATH5K_ERR(ah, 2328 "invalid channel: %d\n", channel->center_freq); 2329 return; 2330 } 2331 2332 switch (ant_mode) { 2333 case AR5K_ANTMODE_DEFAULT: 2334 tx_ant = 0; 2335 use_def_for_tx = false; 2336 update_def_on_tx = false; 2337 use_def_for_rts = false; 2338 use_def_for_sg = false; 2339 fast_div = true; 2340 break; 2341 case AR5K_ANTMODE_FIXED_A: 2342 def_ant = 1; 2343 tx_ant = 1; 2344 use_def_for_tx = true; 2345 update_def_on_tx = false; 2346 use_def_for_rts = true; 2347 use_def_for_sg = true; 2348 fast_div = false; 2349 break; 2350 case AR5K_ANTMODE_FIXED_B: 2351 def_ant = 2; 2352 tx_ant = 2; 2353 use_def_for_tx = true; 2354 update_def_on_tx = false; 2355 use_def_for_rts = true; 2356 use_def_for_sg = true; 2357 fast_div = false; 2358 break; 2359 case AR5K_ANTMODE_SINGLE_AP: 2360 def_ant = 1; /* updated on tx */ 2361 tx_ant = 0; 2362 use_def_for_tx = true; 2363 update_def_on_tx = true; 2364 use_def_for_rts = true; 2365 use_def_for_sg = true; 2366 fast_div = true; 2367 break; 2368 case AR5K_ANTMODE_SECTOR_AP: 2369 tx_ant = 1; /* variable */ 2370 use_def_for_tx = false; 2371 update_def_on_tx = false; 2372 use_def_for_rts = true; 2373 use_def_for_sg = false; 2374 fast_div = false; 2375 break; 2376 case AR5K_ANTMODE_SECTOR_STA: 2377 tx_ant = 1; /* variable */ 2378 use_def_for_tx = true; 2379 update_def_on_tx = false; 2380 use_def_for_rts = true; 2381 use_def_for_sg = false; 2382 fast_div = true; 2383 break; 2384 case AR5K_ANTMODE_DEBUG: 2385 def_ant = 1; 2386 tx_ant = 2; 2387 use_def_for_tx = false; 2388 update_def_on_tx = false; 2389 use_def_for_rts = false; 2390 use_def_for_sg = false; 2391 fast_div = false; 2392 break; 2393 default: 2394 return; 2395 } 2396 2397 ah->ah_tx_ant = tx_ant; 2398 ah->ah_ant_mode = ant_mode; 2399 ah->ah_def_ant = def_ant; 2400 2401 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 2402 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 2403 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 2404 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 2405 2406 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 2407 2408 if (sta_id1) 2409 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 2410 2411 ath5k_hw_set_antenna_switch(ah, ee_mode); 2412 /* Note: set diversity before default antenna 2413 * because it won't work correctly */ 2414 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 2415 ath5k_hw_set_def_antenna(ah, def_ant); 2416 } 2417 2418 2419 /****************\ 2420 * TX power setup * 2421 \****************/ 2422 2423 /* 2424 * Helper functions 2425 */ 2426 2427 /** 2428 * ath5k_get_interpolated_value() - Get interpolated Y val between two points 2429 * @target: X value of the middle point 2430 * @x_left: X value of the left point 2431 * @x_right: X value of the right point 2432 * @y_left: Y value of the left point 2433 * @y_right: Y value of the right point 2434 */ 2435 static s16 2436 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 2437 s16 y_left, s16 y_right) 2438 { 2439 s16 ratio, result; 2440 2441 /* Avoid divide by zero and skip interpolation 2442 * if we have the same point */ 2443 if ((x_left == x_right) || (y_left == y_right)) 2444 return y_left; 2445 2446 /* 2447 * Since we use ints and not fps, we need to scale up in 2448 * order to get a sane ratio value (or else we 'll eg. get 2449 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 2450 * to have some accuracy both for 0.5 and 0.25 steps. 2451 */ 2452 ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left)); 2453 2454 /* Now scale down to be in range */ 2455 result = y_left + (ratio * (target - x_left) / 100); 2456 2457 return result; 2458 } 2459 2460 /** 2461 * ath5k_get_linear_pcdac_min() - Find vertical boundary (min pwr) for the 2462 * linear PCDAC curve 2463 * @stepL: Left array with y values (pcdac steps) 2464 * @stepR: Right array with y values (pcdac steps) 2465 * @pwrL: Left array with x values (power steps) 2466 * @pwrR: Right array with x values (power steps) 2467 * 2468 * Since we have the top of the curve and we draw the line below 2469 * until we reach 1 (1 pcdac step) we need to know which point 2470 * (x value) that is so that we don't go below x axis and have negative 2471 * pcdac values when creating the curve, or fill the table with zeros. 2472 */ 2473 static s16 2474 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 2475 const s16 *pwrL, const s16 *pwrR) 2476 { 2477 s8 tmp; 2478 s16 min_pwrL, min_pwrR; 2479 s16 pwr_i; 2480 2481 /* Some vendors write the same pcdac value twice !!! */ 2482 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 2483 return max(pwrL[0], pwrR[0]); 2484 2485 if (pwrL[0] == pwrL[1]) 2486 min_pwrL = pwrL[0]; 2487 else { 2488 pwr_i = pwrL[0]; 2489 do { 2490 pwr_i--; 2491 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2492 pwrL[0], pwrL[1], 2493 stepL[0], stepL[1]); 2494 } while (tmp > 1); 2495 2496 min_pwrL = pwr_i; 2497 } 2498 2499 if (pwrR[0] == pwrR[1]) 2500 min_pwrR = pwrR[0]; 2501 else { 2502 pwr_i = pwrR[0]; 2503 do { 2504 pwr_i--; 2505 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2506 pwrR[0], pwrR[1], 2507 stepR[0], stepR[1]); 2508 } while (tmp > 1); 2509 2510 min_pwrR = pwr_i; 2511 } 2512 2513 /* Keep the right boundary so that it works for both curves */ 2514 return max(min_pwrL, min_pwrR); 2515 } 2516 2517 /** 2518 * ath5k_create_power_curve() - Create a Power to PDADC or PCDAC curve 2519 * @pmin: Minimum power value (xmin) 2520 * @pmax: Maximum power value (xmax) 2521 * @pwr: Array of power steps (x values) 2522 * @vpd: Array of matching PCDAC/PDADC steps (y values) 2523 * @num_points: Number of provided points 2524 * @vpd_table: Array to fill with the full PCDAC/PDADC values (y values) 2525 * @type: One of enum ath5k_powertable_type (eeprom.h) 2526 * 2527 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2528 * Power to PCDAC curve. 2529 * 2530 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2531 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2532 * PCDAC/PDADC step for each curve is 64 but we can write more than 2533 * one curves on hw so we can go up to 128 (which is the max step we 2534 * can write on the final table). 2535 * 2536 * We write y values (PCDAC/PDADC steps) on hw. 2537 */ 2538 static void 2539 ath5k_create_power_curve(s16 pmin, s16 pmax, 2540 const s16 *pwr, const u8 *vpd, 2541 u8 num_points, 2542 u8 *vpd_table, u8 type) 2543 { 2544 u8 idx[2] = { 0, 1 }; 2545 s16 pwr_i = 2 * pmin; 2546 int i; 2547 2548 if (num_points < 2) 2549 return; 2550 2551 /* We want the whole line, so adjust boundaries 2552 * to cover the entire power range. Note that 2553 * power values are already 0.25dB so no need 2554 * to multiply pwr_i by 2 */ 2555 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2556 pwr_i = pmin; 2557 pmin = 0; 2558 pmax = 63; 2559 } 2560 2561 /* Find surrounding turning points (TPs) 2562 * and interpolate between them */ 2563 for (i = 0; (i <= (u16) (pmax - pmin)) && 2564 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2565 2566 /* We passed the right TP, move to the next set of TPs 2567 * if we pass the last TP, extrapolate above using the last 2568 * two TPs for ratio */ 2569 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2570 idx[0]++; 2571 idx[1]++; 2572 } 2573 2574 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2575 pwr[idx[0]], pwr[idx[1]], 2576 vpd[idx[0]], vpd[idx[1]]); 2577 2578 /* Increase by 0.5dB 2579 * (0.25 dB units) */ 2580 pwr_i += 2; 2581 } 2582 } 2583 2584 /** 2585 * ath5k_get_chan_pcal_surrounding_piers() - Get surrounding calibration piers 2586 * for a given channel. 2587 * @ah: The &struct ath5k_hw 2588 * @channel: The &struct ieee80211_channel 2589 * @pcinfo_l: The &struct ath5k_chan_pcal_info to put the left cal. pier 2590 * @pcinfo_r: The &struct ath5k_chan_pcal_info to put the right cal. pier 2591 * 2592 * Get the surrounding per-channel power calibration piers 2593 * for a given frequency so that we can interpolate between 2594 * them and come up with an appropriate dataset for our current 2595 * channel. 2596 */ 2597 static void 2598 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2599 struct ieee80211_channel *channel, 2600 struct ath5k_chan_pcal_info **pcinfo_l, 2601 struct ath5k_chan_pcal_info **pcinfo_r) 2602 { 2603 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2604 struct ath5k_chan_pcal_info *pcinfo; 2605 u8 idx_l, idx_r; 2606 u8 mode, max, i; 2607 u32 target = channel->center_freq; 2608 2609 idx_l = 0; 2610 idx_r = 0; 2611 2612 switch (channel->hw_value) { 2613 case AR5K_EEPROM_MODE_11A: 2614 pcinfo = ee->ee_pwr_cal_a; 2615 mode = AR5K_EEPROM_MODE_11A; 2616 break; 2617 case AR5K_EEPROM_MODE_11B: 2618 pcinfo = ee->ee_pwr_cal_b; 2619 mode = AR5K_EEPROM_MODE_11B; 2620 break; 2621 case AR5K_EEPROM_MODE_11G: 2622 default: 2623 pcinfo = ee->ee_pwr_cal_g; 2624 mode = AR5K_EEPROM_MODE_11G; 2625 break; 2626 } 2627 max = ee->ee_n_piers[mode] - 1; 2628 2629 /* Frequency is below our calibrated 2630 * range. Use the lowest power curve 2631 * we have */ 2632 if (target < pcinfo[0].freq) { 2633 idx_l = idx_r = 0; 2634 goto done; 2635 } 2636 2637 /* Frequency is above our calibrated 2638 * range. Use the highest power curve 2639 * we have */ 2640 if (target > pcinfo[max].freq) { 2641 idx_l = idx_r = max; 2642 goto done; 2643 } 2644 2645 /* Frequency is inside our calibrated 2646 * channel range. Pick the surrounding 2647 * calibration piers so that we can 2648 * interpolate */ 2649 for (i = 0; i <= max; i++) { 2650 2651 /* Frequency matches one of our calibration 2652 * piers, no need to interpolate, just use 2653 * that calibration pier */ 2654 if (pcinfo[i].freq == target) { 2655 idx_l = idx_r = i; 2656 goto done; 2657 } 2658 2659 /* We found a calibration pier that's above 2660 * frequency, use this pier and the previous 2661 * one to interpolate */ 2662 if (target < pcinfo[i].freq) { 2663 idx_r = i; 2664 idx_l = idx_r - 1; 2665 goto done; 2666 } 2667 } 2668 2669 done: 2670 *pcinfo_l = &pcinfo[idx_l]; 2671 *pcinfo_r = &pcinfo[idx_r]; 2672 } 2673 2674 /** 2675 * ath5k_get_rate_pcal_data() - Get the interpolated per-rate power 2676 * calibration data 2677 * @ah: The &struct ath5k_hw *ah, 2678 * @channel: The &struct ieee80211_channel 2679 * @rates: The &struct ath5k_rate_pcal_info to fill 2680 * 2681 * Get the surrounding per-rate power calibration data 2682 * for a given frequency and interpolate between power 2683 * values to set max target power supported by hw for 2684 * each rate on this frequency. 2685 */ 2686 static void 2687 ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2688 struct ieee80211_channel *channel, 2689 struct ath5k_rate_pcal_info *rates) 2690 { 2691 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2692 struct ath5k_rate_pcal_info *rpinfo; 2693 u8 idx_l, idx_r; 2694 u8 mode, max, i; 2695 u32 target = channel->center_freq; 2696 2697 idx_l = 0; 2698 idx_r = 0; 2699 2700 switch (channel->hw_value) { 2701 case AR5K_MODE_11A: 2702 rpinfo = ee->ee_rate_tpwr_a; 2703 mode = AR5K_EEPROM_MODE_11A; 2704 break; 2705 case AR5K_MODE_11B: 2706 rpinfo = ee->ee_rate_tpwr_b; 2707 mode = AR5K_EEPROM_MODE_11B; 2708 break; 2709 case AR5K_MODE_11G: 2710 default: 2711 rpinfo = ee->ee_rate_tpwr_g; 2712 mode = AR5K_EEPROM_MODE_11G; 2713 break; 2714 } 2715 max = ee->ee_rate_target_pwr_num[mode] - 1; 2716 2717 /* Get the surrounding calibration 2718 * piers - same as above */ 2719 if (target < rpinfo[0].freq) { 2720 idx_l = idx_r = 0; 2721 goto done; 2722 } 2723 2724 if (target > rpinfo[max].freq) { 2725 idx_l = idx_r = max; 2726 goto done; 2727 } 2728 2729 for (i = 0; i <= max; i++) { 2730 2731 if (rpinfo[i].freq == target) { 2732 idx_l = idx_r = i; 2733 goto done; 2734 } 2735 2736 if (target < rpinfo[i].freq) { 2737 idx_r = i; 2738 idx_l = idx_r - 1; 2739 goto done; 2740 } 2741 } 2742 2743 done: 2744 /* Now interpolate power value, based on the frequency */ 2745 rates->freq = target; 2746 2747 rates->target_power_6to24 = 2748 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2749 rpinfo[idx_r].freq, 2750 rpinfo[idx_l].target_power_6to24, 2751 rpinfo[idx_r].target_power_6to24); 2752 2753 rates->target_power_36 = 2754 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2755 rpinfo[idx_r].freq, 2756 rpinfo[idx_l].target_power_36, 2757 rpinfo[idx_r].target_power_36); 2758 2759 rates->target_power_48 = 2760 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2761 rpinfo[idx_r].freq, 2762 rpinfo[idx_l].target_power_48, 2763 rpinfo[idx_r].target_power_48); 2764 2765 rates->target_power_54 = 2766 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2767 rpinfo[idx_r].freq, 2768 rpinfo[idx_l].target_power_54, 2769 rpinfo[idx_r].target_power_54); 2770 } 2771 2772 /** 2773 * ath5k_get_max_ctl_power() - Get max edge power for a given frequency 2774 * @ah: the &struct ath5k_hw 2775 * @channel: The &struct ieee80211_channel 2776 * 2777 * Get the max edge power for this channel if 2778 * we have such data from EEPROM's Conformance Test 2779 * Limits (CTL), and limit max power if needed. 2780 */ 2781 static void 2782 ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2783 struct ieee80211_channel *channel) 2784 { 2785 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2786 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2787 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2788 u8 *ctl_val = ee->ee_ctl; 2789 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2790 s16 edge_pwr = 0; 2791 u8 rep_idx; 2792 u8 i, ctl_mode; 2793 u8 ctl_idx = 0xFF; 2794 u32 target = channel->center_freq; 2795 2796 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2797 2798 switch (channel->hw_value) { 2799 case AR5K_MODE_11A: 2800 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2801 ctl_mode |= AR5K_CTL_TURBO; 2802 else 2803 ctl_mode |= AR5K_CTL_11A; 2804 break; 2805 case AR5K_MODE_11G: 2806 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2807 ctl_mode |= AR5K_CTL_TURBOG; 2808 else 2809 ctl_mode |= AR5K_CTL_11G; 2810 break; 2811 case AR5K_MODE_11B: 2812 ctl_mode |= AR5K_CTL_11B; 2813 break; 2814 default: 2815 return; 2816 } 2817 2818 for (i = 0; i < ee->ee_ctls; i++) { 2819 if (ctl_val[i] == ctl_mode) { 2820 ctl_idx = i; 2821 break; 2822 } 2823 } 2824 2825 /* If we have a CTL dataset available grab it and find the 2826 * edge power for our frequency */ 2827 if (ctl_idx == 0xFF) 2828 return; 2829 2830 /* Edge powers are sorted by frequency from lower 2831 * to higher. Each CTL corresponds to 8 edge power 2832 * measurements. */ 2833 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2834 2835 /* Don't do boundaries check because we 2836 * might have more that one bands defined 2837 * for this mode */ 2838 2839 /* Get the edge power that's closer to our 2840 * frequency */ 2841 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2842 rep_idx += i; 2843 if (target <= rep[rep_idx].freq) 2844 edge_pwr = (s16) rep[rep_idx].edge; 2845 } 2846 2847 if (edge_pwr) 2848 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr); 2849 } 2850 2851 2852 /* 2853 * Power to PCDAC table functions 2854 */ 2855 2856 /** 2857 * DOC: Power to PCDAC table functions 2858 * 2859 * For RF5111 we have an XPD -eXternal Power Detector- curve 2860 * for each calibrated channel. Each curve has 0,5dB Power steps 2861 * on x axis and PCDAC steps (offsets) on y axis and looks like an 2862 * exponential function. To recreate the curve we read 11 points 2863 * from eeprom (eeprom.c) and interpolate here. 2864 * 2865 * For RF5112 we have 4 XPD -eXternal Power Detector- curves 2866 * for each calibrated channel on 0, -6, -12 and -18dBm but we only 2867 * use the higher (3) and the lower (0) curves. Each curve again has 0.5dB 2868 * power steps on x axis and PCDAC steps on y axis and looks like a 2869 * linear function. To recreate the curve and pass the power values 2870 * on hw, we get 4 points for xpd 0 (lower gain -> max power) 2871 * and 3 points for xpd 3 (higher gain -> lower power) from eeprom (eeprom.c) 2872 * and interpolate here. 2873 * 2874 * For a given channel we get the calibrated points (piers) for it or 2875 * -if we don't have calibration data for this specific channel- from the 2876 * available surrounding channels we have calibration data for, after we do a 2877 * linear interpolation between them. Then since we have our calibrated points 2878 * for this channel, we do again a linear interpolation between them to get the 2879 * whole curve. 2880 * 2881 * We finally write the Y values of the curve(s) (the PCDAC values) on hw 2882 */ 2883 2884 /** 2885 * ath5k_fill_pwr_to_pcdac_table() - Fill Power to PCDAC table on RF5111 2886 * @ah: The &struct ath5k_hw 2887 * @table_min: Minimum power (x min) 2888 * @table_max: Maximum power (x max) 2889 * 2890 * No further processing is needed for RF5111, the only thing we have to 2891 * do is fill the values below and above calibration range since eeprom data 2892 * may not cover the entire PCDAC table. 2893 */ 2894 static void 2895 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2896 s16 *table_max) 2897 { 2898 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2899 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2900 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2901 s16 min_pwr, max_pwr; 2902 2903 /* Get table boundaries */ 2904 min_pwr = table_min[0]; 2905 pcdac_0 = pcdac_tmp[0]; 2906 2907 max_pwr = table_max[0]; 2908 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2909 2910 /* Extrapolate below minimum using pcdac_0 */ 2911 pcdac_i = 0; 2912 for (i = 0; i < min_pwr; i++) 2913 pcdac_out[pcdac_i++] = pcdac_0; 2914 2915 /* Copy values from pcdac_tmp */ 2916 pwr_idx = min_pwr; 2917 for (i = 0; pwr_idx <= max_pwr && 2918 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2919 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2920 pwr_idx++; 2921 } 2922 2923 /* Extrapolate above maximum */ 2924 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2925 pcdac_out[pcdac_i++] = pcdac_n; 2926 2927 } 2928 2929 /** 2930 * ath5k_combine_linear_pcdac_curves() - Combine available PCDAC Curves 2931 * @ah: The &struct ath5k_hw 2932 * @table_min: Minimum power (x min) 2933 * @table_max: Maximum power (x max) 2934 * @pdcurves: Number of pd curves 2935 * 2936 * Combine available XPD Curves and fill Linear Power to PCDAC table on RF5112 2937 * RFX112 can have up to 2 curves (one for low txpower range and one for 2938 * higher txpower range). We need to put them both on pcdac_out and place 2939 * them in the correct location. In case we only have one curve available 2940 * just fit it on pcdac_out (it's supposed to cover the entire range of 2941 * available pwr levels since it's always the higher power curve). Extrapolate 2942 * below and above final table if needed. 2943 */ 2944 static void 2945 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2946 s16 *table_max, u8 pdcurves) 2947 { 2948 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2949 u8 *pcdac_low_pwr; 2950 u8 *pcdac_high_pwr; 2951 u8 *pcdac_tmp; 2952 u8 pwr; 2953 s16 max_pwr_idx; 2954 s16 min_pwr_idx; 2955 s16 mid_pwr_idx = 0; 2956 /* Edge flag turns on the 7nth bit on the PCDAC 2957 * to declare the higher power curve (force values 2958 * to be greater than 64). If we only have one curve 2959 * we don't need to set this, if we have 2 curves and 2960 * fill the table backwards this can also be used to 2961 * switch from higher power curve to lower power curve */ 2962 u8 edge_flag; 2963 int i; 2964 2965 /* When we have only one curve available 2966 * that's the higher power curve. If we have 2967 * two curves the first is the high power curve 2968 * and the next is the low power curve. */ 2969 if (pdcurves > 1) { 2970 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2971 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2972 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2973 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2974 2975 /* If table size goes beyond 31.5dB, keep the 2976 * upper 31.5dB range when setting tx power. 2977 * Note: 126 = 31.5 dB in quarter dB steps */ 2978 if (table_max[0] - table_min[1] > 126) 2979 min_pwr_idx = table_max[0] - 126; 2980 else 2981 min_pwr_idx = table_min[1]; 2982 2983 /* Since we fill table backwards 2984 * start from high power curve */ 2985 pcdac_tmp = pcdac_high_pwr; 2986 2987 edge_flag = 0x40; 2988 } else { 2989 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2990 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2991 min_pwr_idx = table_min[0]; 2992 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2993 pcdac_tmp = pcdac_high_pwr; 2994 edge_flag = 0; 2995 } 2996 2997 /* This is used when setting tx power*/ 2998 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2; 2999 3000 /* Fill Power to PCDAC table backwards */ 3001 pwr = max_pwr_idx; 3002 for (i = 63; i >= 0; i--) { 3003 /* Entering lower power range, reset 3004 * edge flag and set pcdac_tmp to lower 3005 * power curve.*/ 3006 if (edge_flag == 0x40 && 3007 (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 3008 edge_flag = 0x00; 3009 pcdac_tmp = pcdac_low_pwr; 3010 pwr = mid_pwr_idx / 2; 3011 } 3012 3013 /* Don't go below 1, extrapolate below if we have 3014 * already switched to the lower power curve -or 3015 * we only have one curve and edge_flag is zero 3016 * anyway */ 3017 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 3018 while (i >= 0) { 3019 pcdac_out[i] = pcdac_out[i + 1]; 3020 i--; 3021 } 3022 break; 3023 } 3024 3025 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 3026 3027 /* Extrapolate above if pcdac is greater than 3028 * 126 -this can happen because we OR pcdac_out 3029 * value with edge_flag on high power curve */ 3030 if (pcdac_out[i] > 126) 3031 pcdac_out[i] = 126; 3032 3033 /* Decrease by a 0.5dB step */ 3034 pwr--; 3035 } 3036 } 3037 3038 /** 3039 * ath5k_write_pcdac_table() - Write the PCDAC values on hw 3040 * @ah: The &struct ath5k_hw 3041 */ 3042 static void 3043 ath5k_write_pcdac_table(struct ath5k_hw *ah) 3044 { 3045 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 3046 int i; 3047 3048 /* 3049 * Write TX power values 3050 */ 3051 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 3052 ath5k_hw_reg_write(ah, 3053 (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) | 3054 (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16), 3055 AR5K_PHY_PCDAC_TXPOWER(i)); 3056 } 3057 } 3058 3059 3060 /* 3061 * Power to PDADC table functions 3062 */ 3063 3064 /** 3065 * DOC: Power to PDADC table functions 3066 * 3067 * For RF2413 and later we have a Power to PDADC table (Power Detector) 3068 * instead of a PCDAC (Power Control) and 4 pd gain curves for each 3069 * calibrated channel. Each curve has power on x axis in 0.5 db steps and 3070 * PDADC steps on y axis and looks like an exponential function like the 3071 * RF5111 curve. 3072 * 3073 * To recreate the curves we read the points from eeprom (eeprom.c) 3074 * and interpolate here. Note that in most cases only 2 (higher and lower) 3075 * curves are used (like RF5112) but vendors have the opportunity to include 3076 * all 4 curves on eeprom. The final curve (higher power) has an extra 3077 * point for better accuracy like RF5112. 3078 * 3079 * The process is similar to what we do above for RF5111/5112 3080 */ 3081 3082 /** 3083 * ath5k_combine_pwr_to_pdadc_curves() - Combine the various PDADC curves 3084 * @ah: The &struct ath5k_hw 3085 * @pwr_min: Minimum power (x min) 3086 * @pwr_max: Maximum power (x max) 3087 * @pdcurves: Number of available curves 3088 * 3089 * Combine the various pd curves and create the final Power to PDADC table 3090 * We can have up to 4 pd curves, we need to do a similar process 3091 * as we do for RF5112. This time we don't have an edge_flag but we 3092 * set the gain boundaries on a separate register. 3093 */ 3094 static void 3095 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 3096 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 3097 { 3098 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 3099 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 3100 u8 *pdadc_tmp; 3101 s16 pdadc_0; 3102 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 3103 u8 pd_gain_overlap; 3104 3105 /* Note: Register value is initialized on initvals 3106 * there is no feedback from hw. 3107 * XXX: What about pd_gain_overlap from EEPROM ? */ 3108 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 3109 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 3110 3111 /* Create final PDADC table */ 3112 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 3113 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 3114 3115 if (pdg == pdcurves - 1) 3116 /* 2 dB boundary stretch for last 3117 * (higher power) curve */ 3118 gain_boundaries[pdg] = pwr_max[pdg] + 4; 3119 else 3120 /* Set gain boundary in the middle 3121 * between this curve and the next one */ 3122 gain_boundaries[pdg] = 3123 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 3124 3125 /* Sanity check in case our 2 db stretch got out of 3126 * range. */ 3127 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 3128 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 3129 3130 /* For the first curve (lower power) 3131 * start from 0 dB */ 3132 if (pdg == 0) 3133 pdadc_0 = 0; 3134 else 3135 /* For the other curves use the gain overlap */ 3136 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 3137 pd_gain_overlap; 3138 3139 /* Force each power step to be at least 0.5 dB */ 3140 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 3141 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 3142 else 3143 pwr_step = 1; 3144 3145 /* If pdadc_0 is negative, we need to extrapolate 3146 * below this pdgain by a number of pwr_steps */ 3147 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 3148 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 3149 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 3150 pdadc_0++; 3151 } 3152 3153 /* Set last pwr level, using gain boundaries */ 3154 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 3155 /* Limit it to be inside pwr range */ 3156 table_size = pwr_max[pdg] - pwr_min[pdg]; 3157 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 3158 3159 /* Fill pdadc_out table */ 3160 while (pdadc_0 < max_idx && pdadc_i < 128) 3161 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 3162 3163 /* Need to extrapolate above this pdgain? */ 3164 if (pdadc_n <= max_idx) 3165 continue; 3166 3167 /* Force each power step to be at least 0.5 dB */ 3168 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 3169 pwr_step = pdadc_tmp[table_size - 1] - 3170 pdadc_tmp[table_size - 2]; 3171 else 3172 pwr_step = 1; 3173 3174 /* Extrapolate above */ 3175 while ((pdadc_0 < (s16) pdadc_n) && 3176 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 3177 s16 tmp = pdadc_tmp[table_size - 1] + 3178 (pdadc_0 - max_idx) * pwr_step; 3179 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 3180 pdadc_0++; 3181 } 3182 } 3183 3184 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 3185 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 3186 pdg++; 3187 } 3188 3189 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 3190 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 3191 pdadc_i++; 3192 } 3193 3194 /* Set gain boundaries */ 3195 ath5k_hw_reg_write(ah, 3196 AR5K_REG_SM(pd_gain_overlap, 3197 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 3198 AR5K_REG_SM(gain_boundaries[0], 3199 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 3200 AR5K_REG_SM(gain_boundaries[1], 3201 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 3202 AR5K_REG_SM(gain_boundaries[2], 3203 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 3204 AR5K_REG_SM(gain_boundaries[3], 3205 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 3206 AR5K_PHY_TPC_RG5); 3207 3208 /* Used for setting rate power table */ 3209 ah->ah_txpower.txp_min_idx = pwr_min[0]; 3210 3211 } 3212 3213 /** 3214 * ath5k_write_pwr_to_pdadc_table() - Write the PDADC values on hw 3215 * @ah: The &struct ath5k_hw 3216 * @ee_mode: One of enum ath5k_driver_mode 3217 */ 3218 static void 3219 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) 3220 { 3221 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 3222 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 3223 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode]; 3224 u8 pdcurves = ee->ee_pd_gains[ee_mode]; 3225 u32 reg; 3226 u8 i; 3227 3228 /* Select the right pdgain curves */ 3229 3230 /* Clear current settings */ 3231 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 3232 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 3233 AR5K_PHY_TPC_RG1_PDGAIN_2 | 3234 AR5K_PHY_TPC_RG1_PDGAIN_3 | 3235 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 3236 3237 /* 3238 * Use pd_gains curve from eeprom 3239 * 3240 * This overrides the default setting from initvals 3241 * in case some vendors (e.g. Zcomax) don't use the default 3242 * curves. If we don't honor their settings we 'll get a 3243 * 5dB (1 * gain overlap ?) drop. 3244 */ 3245 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 3246 3247 switch (pdcurves) { 3248 case 3: 3249 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 3250 /* Fall through */ 3251 case 2: 3252 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 3253 /* Fall through */ 3254 case 1: 3255 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 3256 break; 3257 } 3258 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 3259 3260 /* 3261 * Write TX power values 3262 */ 3263 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 3264 u32 val = get_unaligned_le32(&pdadc_out[4 * i]); 3265 ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i)); 3266 } 3267 } 3268 3269 3270 /* 3271 * Common code for PCDAC/PDADC tables 3272 */ 3273 3274 /** 3275 * ath5k_setup_channel_powertable() - Set up power table for this channel 3276 * @ah: The &struct ath5k_hw 3277 * @channel: The &struct ieee80211_channel 3278 * @ee_mode: One of enum ath5k_driver_mode 3279 * @type: One of enum ath5k_powertable_type (eeprom.h) 3280 * 3281 * This is the main function that uses all of the above 3282 * to set PCDAC/PDADC table on hw for the current channel. 3283 * This table is used for tx power calibration on the baseband, 3284 * without it we get weird tx power levels and in some cases 3285 * distorted spectral mask 3286 */ 3287 static int 3288 ath5k_setup_channel_powertable(struct ath5k_hw *ah, 3289 struct ieee80211_channel *channel, 3290 u8 ee_mode, u8 type) 3291 { 3292 struct ath5k_pdgain_info *pdg_L, *pdg_R; 3293 struct ath5k_chan_pcal_info *pcinfo_L; 3294 struct ath5k_chan_pcal_info *pcinfo_R; 3295 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 3296 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 3297 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 3298 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 3299 u8 *tmpL; 3300 u8 *tmpR; 3301 u32 target = channel->center_freq; 3302 int pdg, i; 3303 3304 /* Get surrounding freq piers for this channel */ 3305 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 3306 &pcinfo_L, 3307 &pcinfo_R); 3308 3309 /* Loop over pd gain curves on 3310 * surrounding freq piers by index */ 3311 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 3312 3313 /* Fill curves in reverse order 3314 * from lower power (max gain) 3315 * to higher power. Use curve -> idx 3316 * backmapping we did on eeprom init */ 3317 u8 idx = pdg_curve_to_idx[pdg]; 3318 3319 /* Grab the needed curves by index */ 3320 pdg_L = &pcinfo_L->pd_curves[idx]; 3321 pdg_R = &pcinfo_R->pd_curves[idx]; 3322 3323 /* Initialize the temp tables */ 3324 tmpL = ah->ah_txpower.tmpL[pdg]; 3325 tmpR = ah->ah_txpower.tmpR[pdg]; 3326 3327 /* Set curve's x boundaries and create 3328 * curves so that they cover the same 3329 * range (if we don't do that one table 3330 * will have values on some range and the 3331 * other one won't have any so interpolation 3332 * will fail) */ 3333 table_min[pdg] = min(pdg_L->pd_pwr[0], 3334 pdg_R->pd_pwr[0]) / 2; 3335 3336 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 3337 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 3338 3339 /* Now create the curves on surrounding channels 3340 * and interpolate if needed to get the final 3341 * curve for this gain on this channel */ 3342 switch (type) { 3343 case AR5K_PWRTABLE_LINEAR_PCDAC: 3344 /* Override min/max so that we don't loose 3345 * accuracy (don't divide by 2) */ 3346 table_min[pdg] = min(pdg_L->pd_pwr[0], 3347 pdg_R->pd_pwr[0]); 3348 3349 table_max[pdg] = 3350 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 3351 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 3352 3353 /* Override minimum so that we don't get 3354 * out of bounds while extrapolating 3355 * below. Don't do this when we have 2 3356 * curves and we are on the high power curve 3357 * because table_min is ok in this case */ 3358 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 3359 3360 table_min[pdg] = 3361 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 3362 pdg_R->pd_step, 3363 pdg_L->pd_pwr, 3364 pdg_R->pd_pwr); 3365 3366 /* Don't go too low because we will 3367 * miss the upper part of the curve. 3368 * Note: 126 = 31.5dB (max power supported) 3369 * in 0.25dB units */ 3370 if (table_max[pdg] - table_min[pdg] > 126) 3371 table_min[pdg] = table_max[pdg] - 126; 3372 } 3373 3374 /* Fall through */ 3375 case AR5K_PWRTABLE_PWR_TO_PCDAC: 3376 case AR5K_PWRTABLE_PWR_TO_PDADC: 3377 3378 ath5k_create_power_curve(table_min[pdg], 3379 table_max[pdg], 3380 pdg_L->pd_pwr, 3381 pdg_L->pd_step, 3382 pdg_L->pd_points, tmpL, type); 3383 3384 /* We are in a calibration 3385 * pier, no need to interpolate 3386 * between freq piers */ 3387 if (pcinfo_L == pcinfo_R) 3388 continue; 3389 3390 ath5k_create_power_curve(table_min[pdg], 3391 table_max[pdg], 3392 pdg_R->pd_pwr, 3393 pdg_R->pd_step, 3394 pdg_R->pd_points, tmpR, type); 3395 break; 3396 default: 3397 return -EINVAL; 3398 } 3399 3400 /* Interpolate between curves 3401 * of surrounding freq piers to 3402 * get the final curve for this 3403 * pd gain. Re-use tmpL for interpolation 3404 * output */ 3405 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 3406 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 3407 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 3408 (s16) pcinfo_L->freq, 3409 (s16) pcinfo_R->freq, 3410 (s16) tmpL[i], 3411 (s16) tmpR[i]); 3412 } 3413 } 3414 3415 /* Now we have a set of curves for this 3416 * channel on tmpL (x range is table_max - table_min 3417 * and y values are tmpL[pdg][]) sorted in the same 3418 * order as EEPROM (because we've used the backmapping). 3419 * So for RF5112 it's from higher power to lower power 3420 * and for RF2413 it's from lower power to higher power. 3421 * For RF5111 we only have one curve. */ 3422 3423 /* Fill min and max power levels for this 3424 * channel by interpolating the values on 3425 * surrounding channels to complete the dataset */ 3426 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 3427 (s16) pcinfo_L->freq, 3428 (s16) pcinfo_R->freq, 3429 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 3430 3431 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 3432 (s16) pcinfo_L->freq, 3433 (s16) pcinfo_R->freq, 3434 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 3435 3436 /* Fill PCDAC/PDADC table */ 3437 switch (type) { 3438 case AR5K_PWRTABLE_LINEAR_PCDAC: 3439 /* For RF5112 we can have one or two curves 3440 * and each curve covers a certain power lvl 3441 * range so we need to do some more processing */ 3442 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 3443 ee->ee_pd_gains[ee_mode]); 3444 3445 /* Set txp.offset so that we can 3446 * match max power value with max 3447 * table index */ 3448 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 3449 break; 3450 case AR5K_PWRTABLE_PWR_TO_PCDAC: 3451 /* We are done for RF5111 since it has only 3452 * one curve, just fit the curve on the table */ 3453 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 3454 3455 /* No rate powertable adjustment for RF5111 */ 3456 ah->ah_txpower.txp_min_idx = 0; 3457 ah->ah_txpower.txp_offset = 0; 3458 break; 3459 case AR5K_PWRTABLE_PWR_TO_PDADC: 3460 /* Set PDADC boundaries and fill 3461 * final PDADC table */ 3462 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 3463 ee->ee_pd_gains[ee_mode]); 3464 3465 /* Set txp.offset, note that table_min 3466 * can be negative */ 3467 ah->ah_txpower.txp_offset = table_min[0]; 3468 break; 3469 default: 3470 return -EINVAL; 3471 } 3472 3473 ah->ah_txpower.txp_setup = true; 3474 3475 return 0; 3476 } 3477 3478 /** 3479 * ath5k_write_channel_powertable() - Set power table for current channel on hw 3480 * @ah: The &struct ath5k_hw 3481 * @ee_mode: One of enum ath5k_driver_mode 3482 * @type: One of enum ath5k_powertable_type (eeprom.h) 3483 */ 3484 static void 3485 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) 3486 { 3487 if (type == AR5K_PWRTABLE_PWR_TO_PDADC) 3488 ath5k_write_pwr_to_pdadc_table(ah, ee_mode); 3489 else 3490 ath5k_write_pcdac_table(ah); 3491 } 3492 3493 3494 /** 3495 * DOC: Per-rate tx power setting 3496 * 3497 * This is the code that sets the desired tx power limit (below 3498 * maximum) on hw for each rate (we also have TPC that sets 3499 * power per packet type). We do that by providing an index on the 3500 * PCDAC/PDADC table we set up above, for each rate. 3501 * 3502 * For now we only limit txpower based on maximum tx power 3503 * supported by hw (what's inside rate_info) + conformance test 3504 * limits. We need to limit this even more, based on regulatory domain 3505 * etc to be safe. Normally this is done from above so we don't care 3506 * here, all we care is that the tx power we set will be O.K. 3507 * for the hw (e.g. won't create noise on PA etc). 3508 * 3509 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps - 3510 * x values) and is indexed as follows: 3511 * rates[0] - rates[7] -> OFDM rates 3512 * rates[8] - rates[14] -> CCK rates 3513 * rates[15] -> XR rates (they all have the same power) 3514 */ 3515 3516 /** 3517 * ath5k_setup_rate_powertable() - Set up rate power table for a given tx power 3518 * @ah: The &struct ath5k_hw 3519 * @max_pwr: The maximum tx power requested in 0.5dB steps 3520 * @rate_info: The &struct ath5k_rate_pcal_info to fill 3521 * @ee_mode: One of enum ath5k_driver_mode 3522 */ 3523 static void 3524 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 3525 struct ath5k_rate_pcal_info *rate_info, 3526 u8 ee_mode) 3527 { 3528 unsigned int i; 3529 u16 *rates; 3530 3531 /* max_pwr is power level we got from driver/user in 0.5dB 3532 * units, switch to 0.25dB units so we can compare */ 3533 max_pwr *= 2; 3534 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 3535 3536 /* apply rate limits */ 3537 rates = ah->ah_txpower.txp_rates_power_table; 3538 3539 /* OFDM rates 6 to 24Mb/s */ 3540 for (i = 0; i < 5; i++) 3541 rates[i] = min(max_pwr, rate_info->target_power_6to24); 3542 3543 /* Rest OFDM rates */ 3544 rates[5] = min(rates[0], rate_info->target_power_36); 3545 rates[6] = min(rates[0], rate_info->target_power_48); 3546 rates[7] = min(rates[0], rate_info->target_power_54); 3547 3548 /* CCK rates */ 3549 /* 1L */ 3550 rates[8] = min(rates[0], rate_info->target_power_6to24); 3551 /* 2L */ 3552 rates[9] = min(rates[0], rate_info->target_power_36); 3553 /* 2S */ 3554 rates[10] = min(rates[0], rate_info->target_power_36); 3555 /* 5L */ 3556 rates[11] = min(rates[0], rate_info->target_power_48); 3557 /* 5S */ 3558 rates[12] = min(rates[0], rate_info->target_power_48); 3559 /* 11L */ 3560 rates[13] = min(rates[0], rate_info->target_power_54); 3561 /* 11S */ 3562 rates[14] = min(rates[0], rate_info->target_power_54); 3563 3564 /* XR rates */ 3565 rates[15] = min(rates[0], rate_info->target_power_6to24); 3566 3567 /* CCK rates have different peak to average ratio 3568 * so we have to tweak their power so that gainf 3569 * correction works ok. For this we use OFDM to 3570 * CCK delta from eeprom */ 3571 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 3572 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 3573 for (i = 8; i <= 15; i++) 3574 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 3575 3576 /* Now that we have all rates setup use table offset to 3577 * match the power range set by user with the power indices 3578 * on PCDAC/PDADC table */ 3579 for (i = 0; i < 16; i++) { 3580 rates[i] += ah->ah_txpower.txp_offset; 3581 /* Don't get out of bounds */ 3582 if (rates[i] > 63) 3583 rates[i] = 63; 3584 } 3585 3586 /* Min/max in 0.25dB units */ 3587 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 3588 ah->ah_txpower.txp_cur_pwr = 2 * rates[0]; 3589 ah->ah_txpower.txp_ofdm = rates[7]; 3590 } 3591 3592 3593 /** 3594 * ath5k_hw_txpower() - Set transmission power limit for a given channel 3595 * @ah: The &struct ath5k_hw 3596 * @channel: The &struct ieee80211_channel 3597 * @txpower: Requested tx power in 0.5dB steps 3598 * 3599 * Combines all of the above to set the requested tx power limit 3600 * on hw. 3601 */ 3602 static int 3603 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3604 u8 txpower) 3605 { 3606 struct ath5k_rate_pcal_info rate_info; 3607 struct ieee80211_channel *curr_channel = ah->ah_current_channel; 3608 int ee_mode; 3609 u8 type; 3610 int ret; 3611 3612 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 3613 ATH5K_ERR(ah, "invalid tx power: %u\n", txpower); 3614 return -EINVAL; 3615 } 3616 3617 ee_mode = ath5k_eeprom_mode_from_channel(channel); 3618 if (ee_mode < 0) { 3619 ATH5K_ERR(ah, 3620 "invalid channel: %d\n", channel->center_freq); 3621 return -EINVAL; 3622 } 3623 3624 /* Initialize TX power table */ 3625 switch (ah->ah_radio) { 3626 case AR5K_RF5110: 3627 /* TODO */ 3628 return 0; 3629 case AR5K_RF5111: 3630 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3631 break; 3632 case AR5K_RF5112: 3633 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3634 break; 3635 case AR5K_RF2413: 3636 case AR5K_RF5413: 3637 case AR5K_RF2316: 3638 case AR5K_RF2317: 3639 case AR5K_RF2425: 3640 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3641 break; 3642 default: 3643 return -EINVAL; 3644 } 3645 3646 /* 3647 * If we don't change channel/mode skip tx powertable calculation 3648 * and use the cached one. 3649 */ 3650 if (!ah->ah_txpower.txp_setup || 3651 (channel->hw_value != curr_channel->hw_value) || 3652 (channel->center_freq != curr_channel->center_freq)) { 3653 /* Reset TX power values */ 3654 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 3655 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 3656 3657 /* Calculate the powertable */ 3658 ret = ath5k_setup_channel_powertable(ah, channel, 3659 ee_mode, type); 3660 if (ret) 3661 return ret; 3662 } 3663 3664 /* Write table on hw */ 3665 ath5k_write_channel_powertable(ah, ee_mode, type); 3666 3667 /* Limit max power if we have a CTL available */ 3668 ath5k_get_max_ctl_power(ah, channel); 3669 3670 /* FIXME: Antenna reduction stuff */ 3671 3672 /* FIXME: Limit power on turbo modes */ 3673 3674 /* FIXME: TPC scale reduction */ 3675 3676 /* Get surrounding channels for per-rate power table 3677 * calibration */ 3678 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3679 3680 /* Setup rate power table */ 3681 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3682 3683 /* Write rate power table on hw */ 3684 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3685 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3686 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3687 3688 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3689 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3690 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3691 3692 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3693 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3694 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3695 3696 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3697 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3698 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3699 3700 /* FIXME: TPC support */ 3701 if (ah->ah_txpower.txp_tpc) { 3702 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3703 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3704 3705 ath5k_hw_reg_write(ah, 3706 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3707 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3708 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3709 AR5K_TPC); 3710 } else { 3711 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3712 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3713 } 3714 3715 return 0; 3716 } 3717 3718 /** 3719 * ath5k_hw_set_txpower_limit() - Set txpower limit for the current channel 3720 * @ah: The &struct ath5k_hw 3721 * @txpower: The requested tx power limit in 0.5dB steps 3722 * 3723 * This function provides access to ath5k_hw_txpower to the driver in 3724 * case user or an application changes it while PHY is running. 3725 */ 3726 int 3727 ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3728 { 3729 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER, 3730 "changing txpower to %d\n", txpower); 3731 3732 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); 3733 } 3734 3735 3736 /*************\ 3737 Init function 3738 \*************/ 3739 3740 /** 3741 * ath5k_hw_phy_init() - Initialize PHY 3742 * @ah: The &struct ath5k_hw 3743 * @channel: The @struct ieee80211_channel 3744 * @mode: One of enum ath5k_driver_mode 3745 * @fast: Try a fast channel switch instead 3746 * 3747 * This is the main function used during reset to initialize PHY 3748 * or do a fast channel change if possible. 3749 * 3750 * NOTE: Do not call this one from the driver, it assumes PHY is in a 3751 * warm reset state ! 3752 */ 3753 int 3754 ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3755 u8 mode, bool fast) 3756 { 3757 struct ieee80211_channel *curr_channel; 3758 int ret, i; 3759 u32 phy_tst1; 3760 ret = 0; 3761 3762 /* 3763 * Sanity check for fast flag 3764 * Don't try fast channel change when changing modulation 3765 * mode/band. We check for chip compatibility on 3766 * ath5k_hw_reset. 3767 */ 3768 curr_channel = ah->ah_current_channel; 3769 if (fast && (channel->hw_value != curr_channel->hw_value)) 3770 return -EINVAL; 3771 3772 /* 3773 * On fast channel change we only set the synth parameters 3774 * while PHY is running, enable calibration and skip the rest. 3775 */ 3776 if (fast) { 3777 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3778 AR5K_PHY_RFBUS_REQ_REQUEST); 3779 for (i = 0; i < 100; i++) { 3780 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) 3781 break; 3782 udelay(5); 3783 } 3784 /* Failed */ 3785 if (i >= 100) 3786 return -EIO; 3787 3788 /* Set channel and wait for synth */ 3789 ret = ath5k_hw_channel(ah, channel); 3790 if (ret) 3791 return ret; 3792 3793 ath5k_hw_wait_for_synth(ah, channel); 3794 } 3795 3796 /* 3797 * Set TX power 3798 * 3799 * Note: We need to do that before we set 3800 * RF buffer settings on 5211/5212+ so that we 3801 * properly set curve indices. 3802 */ 3803 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ? 3804 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER); 3805 if (ret) 3806 return ret; 3807 3808 /* Write OFDM timings on 5212*/ 3809 if (ah->ah_version == AR5K_AR5212 && 3810 channel->hw_value != AR5K_MODE_11B) { 3811 3812 ret = ath5k_hw_write_ofdm_timings(ah, channel); 3813 if (ret) 3814 return ret; 3815 3816 /* Spur info is available only from EEPROM versions 3817 * greater than 5.3, but the EEPROM routines will use 3818 * static values for older versions */ 3819 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) 3820 ath5k_hw_set_spur_mitigation_filter(ah, 3821 channel); 3822 } 3823 3824 /* If we used fast channel switching 3825 * we are done, release RF bus and 3826 * fire up NF calibration. 3827 * 3828 * Note: Only NF calibration due to 3829 * channel change, not AGC calibration 3830 * since AGC is still running ! 3831 */ 3832 if (fast) { 3833 /* 3834 * Release RF Bus grant 3835 */ 3836 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3837 AR5K_PHY_RFBUS_REQ_REQUEST); 3838 3839 /* 3840 * Start NF calibration 3841 */ 3842 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3843 AR5K_PHY_AGCCTL_NF); 3844 3845 return ret; 3846 } 3847 3848 /* 3849 * For 5210 we do all initialization using 3850 * initvals, so we don't have to modify 3851 * any settings (5210 also only supports 3852 * a/aturbo modes) 3853 */ 3854 if (ah->ah_version != AR5K_AR5210) { 3855 3856 /* 3857 * Write initial RF gain settings 3858 * This should work for both 5111/5112 3859 */ 3860 ret = ath5k_hw_rfgain_init(ah, channel->band); 3861 if (ret) 3862 return ret; 3863 3864 usleep_range(1000, 1500); 3865 3866 /* 3867 * Write RF buffer 3868 */ 3869 ret = ath5k_hw_rfregs_init(ah, channel, mode); 3870 if (ret) 3871 return ret; 3872 3873 /*Enable/disable 802.11b mode on 5111 3874 (enable 2111 frequency converter + CCK)*/ 3875 if (ah->ah_radio == AR5K_RF5111) { 3876 if (mode == AR5K_MODE_11B) 3877 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 3878 AR5K_TXCFG_B_MODE); 3879 else 3880 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 3881 AR5K_TXCFG_B_MODE); 3882 } 3883 3884 } else if (ah->ah_version == AR5K_AR5210) { 3885 usleep_range(1000, 1500); 3886 /* Disable phy and wait */ 3887 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 3888 usleep_range(1000, 1500); 3889 } 3890 3891 /* Set channel on PHY */ 3892 ret = ath5k_hw_channel(ah, channel); 3893 if (ret) 3894 return ret; 3895 3896 /* 3897 * Enable the PHY and wait until completion 3898 * This includes BaseBand and Synthesizer 3899 * activation. 3900 */ 3901 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 3902 3903 ath5k_hw_wait_for_synth(ah, channel); 3904 3905 /* 3906 * Perform ADC test to see if baseband is ready 3907 * Set tx hold and check adc test register 3908 */ 3909 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 3910 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 3911 for (i = 0; i <= 20; i++) { 3912 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 3913 break; 3914 usleep_range(200, 250); 3915 } 3916 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 3917 3918 /* 3919 * Start automatic gain control calibration 3920 * 3921 * During AGC calibration RX path is re-routed to 3922 * a power detector so we don't receive anything. 3923 * 3924 * This method is used to calibrate some static offsets 3925 * used together with on-the fly I/Q calibration (the 3926 * one performed via ath5k_hw_phy_calibrate), which doesn't 3927 * interrupt rx path. 3928 * 3929 * While rx path is re-routed to the power detector we also 3930 * start a noise floor calibration to measure the 3931 * card's noise floor (the noise we measure when we are not 3932 * transmitting or receiving anything). 3933 * 3934 * If we are in a noisy environment, AGC calibration may time 3935 * out and/or noise floor calibration might timeout. 3936 */ 3937 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3938 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 3939 3940 /* At the same time start I/Q calibration for QAM constellation 3941 * -no need for CCK- */ 3942 ah->ah_iq_cal_needed = false; 3943 if (!(mode == AR5K_MODE_11B)) { 3944 ah->ah_iq_cal_needed = true; 3945 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 3946 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 3947 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 3948 AR5K_PHY_IQ_RUN); 3949 } 3950 3951 /* Wait for gain calibration to finish (we check for I/Q calibration 3952 * during ath5k_phy_calibrate) */ 3953 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 3954 AR5K_PHY_AGCCTL_CAL, 0, false)) { 3955 ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n", 3956 channel->center_freq); 3957 } 3958 3959 /* Restore antenna mode */ 3960 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 3961 3962 return ret; 3963 } 3964