1 /* 2 * PHY functions 3 * 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/slab.h> 25 #include <asm/unaligned.h> 26 27 #include "ath5k.h" 28 #include "reg.h" 29 #include "rfbuffer.h" 30 #include "rfgain.h" 31 #include "../regd.h" 32 33 34 /******************\ 35 * Helper functions * 36 \******************/ 37 38 /* 39 * Get the PHY Chip revision 40 */ 41 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band) 42 { 43 unsigned int i; 44 u32 srev; 45 u16 ret; 46 47 /* 48 * Set the radio chip access register 49 */ 50 switch (band) { 51 case IEEE80211_BAND_2GHZ: 52 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 53 break; 54 case IEEE80211_BAND_5GHZ: 55 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 56 break; 57 default: 58 return 0; 59 } 60 61 usleep_range(2000, 2500); 62 63 /* ...wait until PHY is ready and read the selected radio revision */ 64 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 65 66 for (i = 0; i < 8; i++) 67 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 68 69 if (ah->ah_version == AR5K_AR5210) { 70 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 71 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 72 } else { 73 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 74 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 75 ((srev & 0x0f) << 4), 8); 76 } 77 78 /* Reset to the 5GHz mode */ 79 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 80 81 return ret; 82 } 83 84 /* 85 * Check if a channel is supported 86 */ 87 bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) 88 { 89 u16 freq = channel->center_freq; 90 91 /* Check if the channel is in our supported range */ 92 if (channel->band == IEEE80211_BAND_2GHZ) { 93 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 94 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 95 return true; 96 } else if (channel->band == IEEE80211_BAND_5GHZ) 97 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 98 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 99 return true; 100 101 return false; 102 } 103 104 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 105 struct ieee80211_channel *channel) 106 { 107 u8 refclk_freq; 108 109 if ((ah->ah_radio == AR5K_RF5112) || 110 (ah->ah_radio == AR5K_RF5413) || 111 (ah->ah_radio == AR5K_RF2413) || 112 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 113 refclk_freq = 40; 114 else 115 refclk_freq = 32; 116 117 if ((channel->center_freq % refclk_freq != 0) && 118 ((channel->center_freq % refclk_freq < 10) || 119 (channel->center_freq % refclk_freq > 22))) 120 return true; 121 else 122 return false; 123 } 124 125 /* 126 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER 127 */ 128 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah, 129 const struct ath5k_rf_reg *rf_regs, 130 u32 val, u8 reg_id, bool set) 131 { 132 const struct ath5k_rf_reg *rfreg = NULL; 133 u8 offset, bank, num_bits, col, position; 134 u16 entry; 135 u32 mask, data, last_bit, bits_shifted, first_bit; 136 u32 *rfb; 137 s32 bits_left; 138 int i; 139 140 data = 0; 141 rfb = ah->ah_rf_banks; 142 143 for (i = 0; i < ah->ah_rf_regs_count; i++) { 144 if (rf_regs[i].index == reg_id) { 145 rfreg = &rf_regs[i]; 146 break; 147 } 148 } 149 150 if (rfb == NULL || rfreg == NULL) { 151 ATH5K_PRINTF("Rf register not found!\n"); 152 /* should not happen */ 153 return 0; 154 } 155 156 bank = rfreg->bank; 157 num_bits = rfreg->field.len; 158 first_bit = rfreg->field.pos; 159 col = rfreg->field.col; 160 161 /* first_bit is an offset from bank's 162 * start. Since we have all banks on 163 * the same array, we use this offset 164 * to mark each bank's start */ 165 offset = ah->ah_offset[bank]; 166 167 /* Boundary check */ 168 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) { 169 ATH5K_PRINTF("invalid values at offset %u\n", offset); 170 return 0; 171 } 172 173 entry = ((first_bit - 1) / 8) + offset; 174 position = (first_bit - 1) % 8; 175 176 if (set) 177 data = ath5k_hw_bitswap(val, num_bits); 178 179 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 180 position = 0, entry++) { 181 182 last_bit = (position + bits_left > 8) ? 8 : 183 position + bits_left; 184 185 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) << 186 (col * 8); 187 188 if (set) { 189 rfb[entry] &= ~mask; 190 rfb[entry] |= ((data << position) << (col * 8)) & mask; 191 data >>= (8 - position); 192 } else { 193 data |= (((rfb[entry] & mask) >> (col * 8)) >> position) 194 << bits_shifted; 195 bits_shifted += last_bit - position; 196 } 197 198 bits_left -= 8 - position; 199 } 200 201 data = set ? 1 : ath5k_hw_bitswap(data, num_bits); 202 203 return data; 204 } 205 206 /** 207 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212 208 * 209 * @ah: the &struct ath5k_hw 210 * @channel: the currently set channel upon reset 211 * 212 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM 213 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init. 214 * 215 * Since delta slope is floating point we split it on its exponent and 216 * mantissa and provide these values on hw. 217 * 218 * For more infos i think this patent is related 219 * http://www.freepatentsonline.com/7184495.html 220 */ 221 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, 222 struct ieee80211_channel *channel) 223 { 224 /* Get exponent and mantissa and set it */ 225 u32 coef_scaled, coef_exp, coef_man, 226 ds_coef_exp, ds_coef_man, clock; 227 228 BUG_ON(!(ah->ah_version == AR5K_AR5212) || 229 (channel->hw_value == AR5K_MODE_11B)); 230 231 /* Get coefficient 232 * ALGO: coef = (5 * clock / carrier_freq) / 2 233 * we scale coef by shifting clock value by 24 for 234 * better precision since we use integers */ 235 switch (ah->ah_bwmode) { 236 case AR5K_BWMODE_40MHZ: 237 clock = 40 * 2; 238 break; 239 case AR5K_BWMODE_10MHZ: 240 clock = 40 / 2; 241 break; 242 case AR5K_BWMODE_5MHZ: 243 clock = 40 / 4; 244 break; 245 default: 246 clock = 40; 247 break; 248 } 249 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq; 250 251 /* Get exponent 252 * ALGO: coef_exp = 14 - highest set bit position */ 253 coef_exp = ilog2(coef_scaled); 254 255 /* Doesn't make sense if it's zero*/ 256 if (!coef_scaled || !coef_exp) 257 return -EINVAL; 258 259 /* Note: we've shifted coef_scaled by 24 */ 260 coef_exp = 14 - (coef_exp - 24); 261 262 263 /* Get mantissa (significant digits) 264 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */ 265 coef_man = coef_scaled + 266 (1 << (24 - coef_exp - 1)); 267 268 /* Calculate delta slope coefficient exponent 269 * and mantissa (remove scaling) and set them on hw */ 270 ds_coef_man = coef_man >> (24 - coef_exp); 271 ds_coef_exp = coef_exp - 16; 272 273 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 274 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man); 275 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, 276 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp); 277 278 return 0; 279 } 280 281 int ath5k_hw_phy_disable(struct ath5k_hw *ah) 282 { 283 /*Just a try M.F.*/ 284 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 285 286 return 0; 287 } 288 289 /* 290 * Wait for synth to settle 291 */ 292 static void ath5k_hw_wait_for_synth(struct ath5k_hw *ah, 293 struct ieee80211_channel *channel) 294 { 295 /* 296 * On 5211+ read activation -> rx delay 297 * and use it (100ns steps). 298 */ 299 if (ah->ah_version != AR5K_AR5210) { 300 u32 delay; 301 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 302 AR5K_PHY_RX_DELAY_M; 303 delay = (channel->hw_value == AR5K_MODE_11B) ? 304 ((delay << 2) / 22) : (delay / 10); 305 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) 306 delay = delay << 1; 307 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) 308 delay = delay << 2; 309 /* XXX: /2 on turbo ? Let's be safe 310 * for now */ 311 usleep_range(100 + delay, 100 + (2 * delay)); 312 } else { 313 usleep_range(1000, 1500); 314 } 315 } 316 317 318 /**********************\ 319 * RF Gain optimization * 320 \**********************/ 321 322 /* 323 * This code is used to optimize RF gain on different environments 324 * (temperature mostly) based on feedback from a power detector. 325 * 326 * It's only used on RF5111 and RF5112, later RF chips seem to have 327 * auto adjustment on hw -notice they have a much smaller BANK 7 and 328 * no gain optimization ladder-. 329 * 330 * For more infos check out this patent doc 331 * http://www.freepatentsonline.com/7400691.html 332 * 333 * This paper describes power drops as seen on the receiver due to 334 * probe packets 335 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues 336 * %20of%20Power%20Control.pdf 337 * 338 * And this is the MadWiFi bug entry related to the above 339 * http://madwifi-project.org/ticket/1659 340 * with various measurements and diagrams 341 */ 342 343 /* Initialize ah_gain during attach */ 344 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) 345 { 346 /* Initialize the gain optimization values */ 347 switch (ah->ah_radio) { 348 case AR5K_RF5111: 349 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 350 ah->ah_gain.g_low = 20; 351 ah->ah_gain.g_high = 35; 352 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 353 break; 354 case AR5K_RF5112: 355 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 356 ah->ah_gain.g_low = 20; 357 ah->ah_gain.g_high = 85; 358 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 359 break; 360 default: 361 return -EINVAL; 362 } 363 364 return 0; 365 } 366 367 /* Schedule a gain probe check on the next transmitted packet. 368 * That means our next packet is going to be sent with lower 369 * tx power and a Peak to Average Power Detector (PAPD) will try 370 * to measure the gain. 371 * 372 * TODO: Force a tx packet (bypassing PCU arbitrator etc) 373 * just after we enable the probe so that we don't mess with 374 * standard traffic. 375 */ 376 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) 377 { 378 379 /* Skip if gain calibration is inactive or 380 * we already handle a probe request */ 381 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) 382 return; 383 384 /* Send the packet with 2dB below max power as 385 * patent doc suggest */ 386 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, 387 AR5K_PHY_PAPD_PROBE_TXPOWER) | 388 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE); 389 390 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; 391 392 } 393 394 /* Calculate gain_F measurement correction 395 * based on the current step for RF5112 rev. 2 */ 396 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) 397 { 398 u32 mix, step; 399 u32 *rf; 400 const struct ath5k_gain_opt *go; 401 const struct ath5k_gain_opt_step *g_step; 402 const struct ath5k_rf_reg *rf_regs; 403 404 /* Only RF5112 Rev. 2 supports it */ 405 if ((ah->ah_radio != AR5K_RF5112) || 406 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) 407 return 0; 408 409 go = &rfgain_opt_5112; 410 rf_regs = rf_regs_5112a; 411 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 412 413 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 414 415 if (ah->ah_rf_banks == NULL) 416 return 0; 417 418 rf = ah->ah_rf_banks; 419 ah->ah_gain.g_f_corr = 0; 420 421 /* No VGA (Variable Gain Amplifier) override, skip */ 422 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) 423 return 0; 424 425 /* Mix gain stepping */ 426 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); 427 428 /* Mix gain override */ 429 mix = g_step->gos_param[0]; 430 431 switch (mix) { 432 case 3: 433 ah->ah_gain.g_f_corr = step * 2; 434 break; 435 case 2: 436 ah->ah_gain.g_f_corr = (step - 5) * 2; 437 break; 438 case 1: 439 ah->ah_gain.g_f_corr = step; 440 break; 441 default: 442 ah->ah_gain.g_f_corr = 0; 443 break; 444 } 445 446 return ah->ah_gain.g_f_corr; 447 } 448 449 /* Check if current gain_F measurement is in the range of our 450 * power detector windows. If we get a measurement outside range 451 * we know it's not accurate (detectors can't measure anything outside 452 * their detection window) so we must ignore it */ 453 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) 454 { 455 const struct ath5k_rf_reg *rf_regs; 456 u32 step, mix_ovr, level[4]; 457 u32 *rf; 458 459 if (ah->ah_rf_banks == NULL) 460 return false; 461 462 rf = ah->ah_rf_banks; 463 464 if (ah->ah_radio == AR5K_RF5111) { 465 466 rf_regs = rf_regs_5111; 467 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 468 469 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, 470 false); 471 472 level[0] = 0; 473 level[1] = (step == 63) ? 50 : step + 4; 474 level[2] = (step != 63) ? 64 : level[0]; 475 level[3] = level[2] + 50; 476 477 ah->ah_gain.g_high = level[3] - 478 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 479 ah->ah_gain.g_low = level[0] + 480 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0); 481 } else { 482 483 rf_regs = rf_regs_5112; 484 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 485 486 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, 487 false); 488 489 level[0] = level[2] = 0; 490 491 if (mix_ovr == 1) { 492 level[1] = level[3] = 83; 493 } else { 494 level[1] = level[3] = 107; 495 ah->ah_gain.g_high = 55; 496 } 497 } 498 499 return (ah->ah_gain.g_current >= level[0] && 500 ah->ah_gain.g_current <= level[1]) || 501 (ah->ah_gain.g_current >= level[2] && 502 ah->ah_gain.g_current <= level[3]); 503 } 504 505 /* Perform gain_F adjustment by choosing the right set 506 * of parameters from RF gain optimization ladder */ 507 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) 508 { 509 const struct ath5k_gain_opt *go; 510 const struct ath5k_gain_opt_step *g_step; 511 int ret = 0; 512 513 switch (ah->ah_radio) { 514 case AR5K_RF5111: 515 go = &rfgain_opt_5111; 516 break; 517 case AR5K_RF5112: 518 go = &rfgain_opt_5112; 519 break; 520 default: 521 return 0; 522 } 523 524 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 525 526 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { 527 528 /* Reached maximum */ 529 if (ah->ah_gain.g_step_idx == 0) 530 return -1; 531 532 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 533 ah->ah_gain.g_target >= ah->ah_gain.g_high && 534 ah->ah_gain.g_step_idx > 0; 535 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 536 ah->ah_gain.g_target -= 2 * 537 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - 538 g_step->gos_gain); 539 540 ret = 1; 541 goto done; 542 } 543 544 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { 545 546 /* Reached minimum */ 547 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) 548 return -2; 549 550 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 551 ah->ah_gain.g_target <= ah->ah_gain.g_low && 552 ah->ah_gain.g_step_idx < go->go_steps_count - 1; 553 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 554 ah->ah_gain.g_target -= 2 * 555 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 556 g_step->gos_gain); 557 558 ret = 2; 559 goto done; 560 } 561 562 done: 563 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 564 "ret %d, gain step %u, current gain %u, target gain %u\n", 565 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 566 ah->ah_gain.g_target); 567 568 return ret; 569 } 570 571 /* Main callback for thermal RF gain calibration engine 572 * Check for a new gain reading and schedule an adjustment 573 * if needed. 574 */ 575 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) 576 { 577 u32 data, type; 578 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 579 580 if (ah->ah_rf_banks == NULL || 581 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 582 return AR5K_RFGAIN_INACTIVE; 583 584 /* No check requested, either engine is inactive 585 * or an adjustment is already requested */ 586 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 587 goto done; 588 589 /* Read the PAPD (Peak to Average Power Detector) 590 * register */ 591 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 592 593 /* No probe is scheduled, read gain_F measurement */ 594 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 595 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 596 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 597 598 /* If tx packet is CCK correct the gain_F measurement 599 * by cck ofdm gain delta */ 600 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 601 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 602 ah->ah_gain.g_current += 603 ee->ee_cck_ofdm_gain_delta; 604 else 605 ah->ah_gain.g_current += 606 AR5K_GAIN_CCK_PROBE_CORR; 607 } 608 609 /* Further correct gain_F measurement for 610 * RF5112A radios */ 611 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 612 ath5k_hw_rf_gainf_corr(ah); 613 ah->ah_gain.g_current = 614 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 615 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) : 616 0; 617 } 618 619 /* Check if measurement is ok and if we need 620 * to adjust gain, schedule a gain adjustment, 621 * else switch back to the active state */ 622 if (ath5k_hw_rf_check_gainf_readback(ah) && 623 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 624 ath5k_hw_rf_gainf_adjust(ah)) { 625 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 626 } else { 627 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 628 } 629 } 630 631 done: 632 return ah->ah_gain.g_state; 633 } 634 635 /* Write initial RF gain table to set the RF sensitivity 636 * this one works on all RF chips and has nothing to do 637 * with gain_F calibration */ 638 static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band) 639 { 640 const struct ath5k_ini_rfgain *ath5k_rfg; 641 unsigned int i, size, index; 642 643 switch (ah->ah_radio) { 644 case AR5K_RF5111: 645 ath5k_rfg = rfgain_5111; 646 size = ARRAY_SIZE(rfgain_5111); 647 break; 648 case AR5K_RF5112: 649 ath5k_rfg = rfgain_5112; 650 size = ARRAY_SIZE(rfgain_5112); 651 break; 652 case AR5K_RF2413: 653 ath5k_rfg = rfgain_2413; 654 size = ARRAY_SIZE(rfgain_2413); 655 break; 656 case AR5K_RF2316: 657 ath5k_rfg = rfgain_2316; 658 size = ARRAY_SIZE(rfgain_2316); 659 break; 660 case AR5K_RF5413: 661 ath5k_rfg = rfgain_5413; 662 size = ARRAY_SIZE(rfgain_5413); 663 break; 664 case AR5K_RF2317: 665 case AR5K_RF2425: 666 ath5k_rfg = rfgain_2425; 667 size = ARRAY_SIZE(rfgain_2425); 668 break; 669 default: 670 return -EINVAL; 671 } 672 673 index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0; 674 675 for (i = 0; i < size; i++) { 676 AR5K_REG_WAIT(i); 677 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index], 678 (u32)ath5k_rfg[i].rfg_register); 679 } 680 681 return 0; 682 } 683 684 685 686 /********************\ 687 * RF Registers setup * 688 \********************/ 689 690 /* 691 * Setup RF registers by writing RF buffer on hw 692 */ 693 static int ath5k_hw_rfregs_init(struct ath5k_hw *ah, 694 struct ieee80211_channel *channel, unsigned int mode) 695 { 696 const struct ath5k_rf_reg *rf_regs; 697 const struct ath5k_ini_rfbuffer *ini_rfb; 698 const struct ath5k_gain_opt *go = NULL; 699 const struct ath5k_gain_opt_step *g_step; 700 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 701 u8 ee_mode = 0; 702 u32 *rfb; 703 int i, obdb = -1, bank = -1; 704 705 switch (ah->ah_radio) { 706 case AR5K_RF5111: 707 rf_regs = rf_regs_5111; 708 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 709 ini_rfb = rfb_5111; 710 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 711 go = &rfgain_opt_5111; 712 break; 713 case AR5K_RF5112: 714 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 715 rf_regs = rf_regs_5112a; 716 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 717 ini_rfb = rfb_5112a; 718 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 719 } else { 720 rf_regs = rf_regs_5112; 721 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 722 ini_rfb = rfb_5112; 723 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 724 } 725 go = &rfgain_opt_5112; 726 break; 727 case AR5K_RF2413: 728 rf_regs = rf_regs_2413; 729 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 730 ini_rfb = rfb_2413; 731 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 732 break; 733 case AR5K_RF2316: 734 rf_regs = rf_regs_2316; 735 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 736 ini_rfb = rfb_2316; 737 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 738 break; 739 case AR5K_RF5413: 740 rf_regs = rf_regs_5413; 741 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 742 ini_rfb = rfb_5413; 743 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 744 break; 745 case AR5K_RF2317: 746 rf_regs = rf_regs_2425; 747 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 748 ini_rfb = rfb_2317; 749 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 750 break; 751 case AR5K_RF2425: 752 rf_regs = rf_regs_2425; 753 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 754 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 755 ini_rfb = rfb_2425; 756 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 757 } else { 758 ini_rfb = rfb_2417; 759 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 760 } 761 break; 762 default: 763 return -EINVAL; 764 } 765 766 /* If it's the first time we set RF buffer, allocate 767 * ah->ah_rf_banks based on ah->ah_rf_banks_size 768 * we set above */ 769 if (ah->ah_rf_banks == NULL) { 770 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 771 GFP_KERNEL); 772 if (ah->ah_rf_banks == NULL) { 773 ATH5K_ERR(ah, "out of memory\n"); 774 return -ENOMEM; 775 } 776 } 777 778 /* Copy values to modify them */ 779 rfb = ah->ah_rf_banks; 780 781 for (i = 0; i < ah->ah_rf_banks_size; i++) { 782 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 783 ATH5K_ERR(ah, "invalid bank\n"); 784 return -EINVAL; 785 } 786 787 /* Bank changed, write down the offset */ 788 if (bank != ini_rfb[i].rfb_bank) { 789 bank = ini_rfb[i].rfb_bank; 790 ah->ah_offset[bank] = i; 791 } 792 793 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 794 } 795 796 /* Set Output and Driver bias current (OB/DB) */ 797 if (channel->band == IEEE80211_BAND_2GHZ) { 798 799 if (channel->hw_value == AR5K_MODE_11B) 800 ee_mode = AR5K_EEPROM_MODE_11B; 801 else 802 ee_mode = AR5K_EEPROM_MODE_11G; 803 804 /* For RF511X/RF211X combination we 805 * use b_OB and b_DB parameters stored 806 * in eeprom on ee->ee_ob[ee_mode][0] 807 * 808 * For all other chips we use OB/DB for 2GHz 809 * stored in the b/g modal section just like 810 * 802.11a on ee->ee_ob[ee_mode][1] */ 811 if ((ah->ah_radio == AR5K_RF5111) || 812 (ah->ah_radio == AR5K_RF5112)) 813 obdb = 0; 814 else 815 obdb = 1; 816 817 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 818 AR5K_RF_OB_2GHZ, true); 819 820 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 821 AR5K_RF_DB_2GHZ, true); 822 823 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 824 } else if ((channel->band == IEEE80211_BAND_5GHZ) || 825 (ah->ah_radio == AR5K_RF5111)) { 826 827 /* For 11a, Turbo and XR we need to choose 828 * OB/DB based on frequency range */ 829 ee_mode = AR5K_EEPROM_MODE_11A; 830 obdb = channel->center_freq >= 5725 ? 3 : 831 (channel->center_freq >= 5500 ? 2 : 832 (channel->center_freq >= 5260 ? 1 : 833 (channel->center_freq > 4000 ? 0 : -1))); 834 835 if (obdb < 0) 836 return -EINVAL; 837 838 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 839 AR5K_RF_OB_5GHZ, true); 840 841 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 842 AR5K_RF_DB_5GHZ, true); 843 } 844 845 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 846 847 /* Set turbo mode (N/A on RF5413) */ 848 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) && 849 (ah->ah_radio != AR5K_RF5413)) 850 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false); 851 852 /* Bank Modifications (chip-specific) */ 853 if (ah->ah_radio == AR5K_RF5111) { 854 855 /* Set gain_F settings according to current step */ 856 if (channel->hw_value != AR5K_MODE_11B) { 857 858 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 859 AR5K_PHY_FRAME_CTL_TX_CLIP, 860 g_step->gos_param[0]); 861 862 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 863 AR5K_RF_PWD_90, true); 864 865 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 866 AR5K_RF_PWD_84, true); 867 868 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 869 AR5K_RF_RFGAIN_SEL, true); 870 871 /* We programmed gain_F parameters, switch back 872 * to active state */ 873 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 874 875 } 876 877 /* Bank 6/7 setup */ 878 879 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 880 AR5K_RF_PWD_XPD, true); 881 882 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 883 AR5K_RF_XPD_GAIN, true); 884 885 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 886 AR5K_RF_GAIN_I, true); 887 888 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 889 AR5K_RF_PLO_SEL, true); 890 891 /* Tweak power detectors for half/quarter rate support */ 892 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 893 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 894 u8 wait_i; 895 896 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, 897 AR5K_RF_WAIT_S, true); 898 899 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 900 0x1f : 0x10; 901 902 ath5k_hw_rfb_op(ah, rf_regs, wait_i, 903 AR5K_RF_WAIT_I, true); 904 ath5k_hw_rfb_op(ah, rf_regs, 3, 905 AR5K_RF_MAX_TIME, true); 906 907 } 908 } 909 910 if (ah->ah_radio == AR5K_RF5112) { 911 912 /* Set gain_F settings according to current step */ 913 if (channel->hw_value != AR5K_MODE_11B) { 914 915 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 916 AR5K_RF_MIXGAIN_OVR, true); 917 918 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 919 AR5K_RF_PWD_138, true); 920 921 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 922 AR5K_RF_PWD_137, true); 923 924 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 925 AR5K_RF_PWD_136, true); 926 927 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 928 AR5K_RF_PWD_132, true); 929 930 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 931 AR5K_RF_PWD_131, true); 932 933 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 934 AR5K_RF_PWD_130, true); 935 936 /* We programmed gain_F parameters, switch back 937 * to active state */ 938 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 939 } 940 941 /* Bank 6/7 setup */ 942 943 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 944 AR5K_RF_XPD_SEL, true); 945 946 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 947 /* Rev. 1 supports only one xpd */ 948 ath5k_hw_rfb_op(ah, rf_regs, 949 ee->ee_x_gain[ee_mode], 950 AR5K_RF_XPD_GAIN, true); 951 952 } else { 953 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 954 if (ee->ee_pd_gains[ee_mode] > 1) { 955 ath5k_hw_rfb_op(ah, rf_regs, 956 pdg_curve_to_idx[0], 957 AR5K_RF_PD_GAIN_LO, true); 958 ath5k_hw_rfb_op(ah, rf_regs, 959 pdg_curve_to_idx[1], 960 AR5K_RF_PD_GAIN_HI, true); 961 } else { 962 ath5k_hw_rfb_op(ah, rf_regs, 963 pdg_curve_to_idx[0], 964 AR5K_RF_PD_GAIN_LO, true); 965 ath5k_hw_rfb_op(ah, rf_regs, 966 pdg_curve_to_idx[0], 967 AR5K_RF_PD_GAIN_HI, true); 968 } 969 970 /* Lower synth voltage on Rev 2 */ 971 if (ah->ah_radio == AR5K_RF5112 && 972 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) { 973 ath5k_hw_rfb_op(ah, rf_regs, 2, 974 AR5K_RF_HIGH_VC_CP, true); 975 976 ath5k_hw_rfb_op(ah, rf_regs, 2, 977 AR5K_RF_MID_VC_CP, true); 978 979 ath5k_hw_rfb_op(ah, rf_regs, 2, 980 AR5K_RF_LOW_VC_CP, true); 981 982 ath5k_hw_rfb_op(ah, rf_regs, 2, 983 AR5K_RF_PUSH_UP, true); 984 } 985 986 /* Decrease power consumption on 5213+ BaseBand */ 987 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 988 ath5k_hw_rfb_op(ah, rf_regs, 1, 989 AR5K_RF_PAD2GND, true); 990 991 ath5k_hw_rfb_op(ah, rf_regs, 1, 992 AR5K_RF_XB2_LVL, true); 993 994 ath5k_hw_rfb_op(ah, rf_regs, 1, 995 AR5K_RF_XB5_LVL, true); 996 997 ath5k_hw_rfb_op(ah, rf_regs, 1, 998 AR5K_RF_PWD_167, true); 999 1000 ath5k_hw_rfb_op(ah, rf_regs, 1, 1001 AR5K_RF_PWD_166, true); 1002 } 1003 } 1004 1005 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 1006 AR5K_RF_GAIN_I, true); 1007 1008 /* Tweak power detector for half/quarter rates */ 1009 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || 1010 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { 1011 u8 pd_delay; 1012 1013 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? 1014 0xf : 0x8; 1015 1016 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, 1017 AR5K_RF_PD_PERIOD_A, true); 1018 ath5k_hw_rfb_op(ah, rf_regs, 0xf, 1019 AR5K_RF_PD_DELAY_A, true); 1020 1021 } 1022 } 1023 1024 if (ah->ah_radio == AR5K_RF5413 && 1025 channel->band == IEEE80211_BAND_2GHZ) { 1026 1027 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 1028 true); 1029 1030 /* Set optimum value for early revisions (on pci-e chips) */ 1031 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 1032 ah->ah_mac_srev < AR5K_SREV_AR5413) 1033 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 1034 AR5K_RF_PWD_ICLOBUF_2G, true); 1035 1036 } 1037 1038 /* Write RF banks on hw */ 1039 for (i = 0; i < ah->ah_rf_banks_size; i++) { 1040 AR5K_REG_WAIT(i); 1041 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 1042 } 1043 1044 return 0; 1045 } 1046 1047 1048 /**************************\ 1049 PHY/RF channel functions 1050 \**************************/ 1051 1052 /* 1053 * Conversion needed for RF5110 1054 */ 1055 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel) 1056 { 1057 u32 athchan; 1058 1059 /* 1060 * Convert IEEE channel/MHz to an internal channel value used 1061 * by the AR5210 chipset. This has not been verified with 1062 * newer chipsets like the AR5212A who have a completely 1063 * different RF/PHY part. 1064 */ 1065 athchan = (ath5k_hw_bitswap( 1066 (ieee80211_frequency_to_channel( 1067 channel->center_freq) - 24) / 2, 5) 1068 << 1) | (1 << 6) | 0x1; 1069 return athchan; 1070 } 1071 1072 /* 1073 * Set channel on RF5110 1074 */ 1075 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah, 1076 struct ieee80211_channel *channel) 1077 { 1078 u32 data; 1079 1080 /* 1081 * Set the channel and wait 1082 */ 1083 data = ath5k_hw_rf5110_chan2athchan(channel); 1084 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); 1085 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); 1086 usleep_range(1000, 1500); 1087 1088 return 0; 1089 } 1090 1091 /* 1092 * Conversion needed for 5111 1093 */ 1094 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee, 1095 struct ath5k_athchan_2ghz *athchan) 1096 { 1097 int channel; 1098 1099 /* Cast this value to catch negative channel numbers (>= -19) */ 1100 channel = (int)ieee; 1101 1102 /* 1103 * Map 2GHz IEEE channel to 5GHz Atheros channel 1104 */ 1105 if (channel <= 13) { 1106 athchan->a2_athchan = 115 + channel; 1107 athchan->a2_flags = 0x46; 1108 } else if (channel == 14) { 1109 athchan->a2_athchan = 124; 1110 athchan->a2_flags = 0x44; 1111 } else if (channel >= 15 && channel <= 26) { 1112 athchan->a2_athchan = ((channel - 14) * 4) + 132; 1113 athchan->a2_flags = 0x46; 1114 } else 1115 return -EINVAL; 1116 1117 return 0; 1118 } 1119 1120 /* 1121 * Set channel on 5111 1122 */ 1123 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah, 1124 struct ieee80211_channel *channel) 1125 { 1126 struct ath5k_athchan_2ghz ath5k_channel_2ghz; 1127 unsigned int ath5k_channel = 1128 ieee80211_frequency_to_channel(channel->center_freq); 1129 u32 data0, data1, clock; 1130 int ret; 1131 1132 /* 1133 * Set the channel on the RF5111 radio 1134 */ 1135 data0 = data1 = 0; 1136 1137 if (channel->band == IEEE80211_BAND_2GHZ) { 1138 /* Map 2GHz channel to 5GHz Atheros channel ID */ 1139 ret = ath5k_hw_rf5111_chan2athchan( 1140 ieee80211_frequency_to_channel(channel->center_freq), 1141 &ath5k_channel_2ghz); 1142 if (ret) 1143 return ret; 1144 1145 ath5k_channel = ath5k_channel_2ghz.a2_athchan; 1146 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff) 1147 << 5) | (1 << 4); 1148 } 1149 1150 if (ath5k_channel < 145 || !(ath5k_channel & 1)) { 1151 clock = 1; 1152 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) | 1153 (clock << 1) | (1 << 10) | 1; 1154 } else { 1155 clock = 0; 1156 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff) 1157 << 2) | (clock << 1) | (1 << 10) | 1; 1158 } 1159 1160 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), 1161 AR5K_RF_BUFFER); 1162 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), 1163 AR5K_RF_BUFFER_CONTROL_3); 1164 1165 return 0; 1166 } 1167 1168 /* 1169 * Set channel on 5112 and newer 1170 */ 1171 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, 1172 struct ieee80211_channel *channel) 1173 { 1174 u32 data, data0, data1, data2; 1175 u16 c; 1176 1177 data = data0 = data1 = data2 = 0; 1178 c = channel->center_freq; 1179 1180 if (c < 4800) { 1181 if (!((c - 2224) % 5)) { 1182 data0 = ((2 * (c - 704)) - 3040) / 10; 1183 data1 = 1; 1184 } else if (!((c - 2192) % 5)) { 1185 data0 = ((2 * (c - 672)) - 3040) / 10; 1186 data1 = 0; 1187 } else 1188 return -EINVAL; 1189 1190 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); 1191 } else if ((c % 5) != 2 || c > 5435) { 1192 if (!(c % 20) && c >= 5120) { 1193 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1194 data2 = ath5k_hw_bitswap(3, 2); 1195 } else if (!(c % 10)) { 1196 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1197 data2 = ath5k_hw_bitswap(2, 2); 1198 } else if (!(c % 5)) { 1199 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1200 data2 = ath5k_hw_bitswap(1, 2); 1201 } else 1202 return -EINVAL; 1203 } else { 1204 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1205 data2 = ath5k_hw_bitswap(0, 2); 1206 } 1207 1208 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; 1209 1210 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1211 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1212 1213 return 0; 1214 } 1215 1216 /* 1217 * Set the channel on the RF2425 1218 */ 1219 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, 1220 struct ieee80211_channel *channel) 1221 { 1222 u32 data, data0, data2; 1223 u16 c; 1224 1225 data = data0 = data2 = 0; 1226 c = channel->center_freq; 1227 1228 if (c < 4800) { 1229 data0 = ath5k_hw_bitswap((c - 2272), 8); 1230 data2 = 0; 1231 /* ? 5GHz ? */ 1232 } else if ((c % 5) != 2 || c > 5435) { 1233 if (!(c % 20) && c < 5120) 1234 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); 1235 else if (!(c % 10)) 1236 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); 1237 else if (!(c % 5)) 1238 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); 1239 else 1240 return -EINVAL; 1241 data2 = ath5k_hw_bitswap(1, 2); 1242 } else { 1243 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8); 1244 data2 = ath5k_hw_bitswap(0, 2); 1245 } 1246 1247 data = (data0 << 4) | data2 << 2 | 0x1001; 1248 1249 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); 1250 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); 1251 1252 return 0; 1253 } 1254 1255 /* 1256 * Set a channel on the radio chip 1257 */ 1258 static int ath5k_hw_channel(struct ath5k_hw *ah, 1259 struct ieee80211_channel *channel) 1260 { 1261 int ret; 1262 /* 1263 * Check bounds supported by the PHY (we don't care about regulatory 1264 * restrictions at this point). 1265 */ 1266 if (!ath5k_channel_ok(ah, channel)) { 1267 ATH5K_ERR(ah, 1268 "channel frequency (%u MHz) out of supported " 1269 "band range\n", 1270 channel->center_freq); 1271 return -EINVAL; 1272 } 1273 1274 /* 1275 * Set the channel and wait 1276 */ 1277 switch (ah->ah_radio) { 1278 case AR5K_RF5110: 1279 ret = ath5k_hw_rf5110_channel(ah, channel); 1280 break; 1281 case AR5K_RF5111: 1282 ret = ath5k_hw_rf5111_channel(ah, channel); 1283 break; 1284 case AR5K_RF2317: 1285 case AR5K_RF2425: 1286 ret = ath5k_hw_rf2425_channel(ah, channel); 1287 break; 1288 default: 1289 ret = ath5k_hw_rf5112_channel(ah, channel); 1290 break; 1291 } 1292 1293 if (ret) 1294 return ret; 1295 1296 /* Set JAPAN setting for channel 14 */ 1297 if (channel->center_freq == 2484) { 1298 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1299 AR5K_PHY_CCKTXCTL_JAPAN); 1300 } else { 1301 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 1302 AR5K_PHY_CCKTXCTL_WORLD); 1303 } 1304 1305 ah->ah_current_channel = channel; 1306 1307 return 0; 1308 } 1309 1310 /*****************\ 1311 PHY calibration 1312 \*****************/ 1313 1314 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) 1315 { 1316 s32 val; 1317 1318 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 1319 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8); 1320 } 1321 1322 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) 1323 { 1324 int i; 1325 1326 ah->ah_nfcal_hist.index = 0; 1327 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) 1328 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1329 } 1330 1331 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1332 { 1333 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1334 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1); 1335 hist->nfval[hist->index] = noise_floor; 1336 } 1337 1338 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) 1339 { 1340 s16 sort[ATH5K_NF_CAL_HIST_MAX]; 1341 s16 tmp; 1342 int i, j; 1343 1344 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1345 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1346 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1347 if (sort[j] > sort[j - 1]) { 1348 tmp = sort[j]; 1349 sort[j] = sort[j - 1]; 1350 sort[j - 1] = tmp; 1351 } 1352 } 1353 } 1354 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1355 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1356 "cal %d:%d\n", i, sort[i]); 1357 } 1358 return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2]; 1359 } 1360 1361 /* 1362 * When we tell the hardware to perform a noise floor calibration 1363 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically 1364 * sample-and-hold the minimum noise level seen at the antennas. 1365 * This value is then stored in a ring buffer of recently measured 1366 * noise floor values so we have a moving window of the last few 1367 * samples. 1368 * 1369 * The median of the values in the history is then loaded into the 1370 * hardware for its own use for RSSI and CCA measurements. 1371 */ 1372 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah) 1373 { 1374 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1375 u32 val; 1376 s16 nf, threshold; 1377 u8 ee_mode; 1378 1379 /* keep last value if calibration hasn't completed */ 1380 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1381 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1382 "NF did not complete in calibration window\n"); 1383 1384 return; 1385 } 1386 1387 ah->ah_cal_mask |= AR5K_CALIBRATION_NF; 1388 1389 ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel); 1390 1391 /* completed NF calibration, test threshold */ 1392 nf = ath5k_hw_read_measured_noise_floor(ah); 1393 threshold = ee->ee_noise_floor_thr[ee_mode]; 1394 1395 if (nf > threshold) { 1396 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1397 "noise floor failure detected; " 1398 "read %d, threshold %d\n", 1399 nf, threshold); 1400 1401 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE; 1402 } 1403 1404 ath5k_hw_update_nfcal_hist(ah, nf); 1405 nf = ath5k_hw_get_median_noise_floor(ah); 1406 1407 /* load noise floor (in .5 dBm) so the hardware will use it */ 1408 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; 1409 val |= (nf * 2) & AR5K_PHY_NF_M; 1410 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1411 1412 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1413 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE)); 1414 1415 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, 1416 0, false); 1417 1418 /* 1419 * Load a high max CCA Power value (-50 dBm in .5 dBm units) 1420 * so that we're not capped by the median we just loaded. 1421 * This will be used as the initial value for the next noise 1422 * floor calibration. 1423 */ 1424 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M); 1425 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); 1426 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1427 AR5K_PHY_AGCCTL_NF_EN | 1428 AR5K_PHY_AGCCTL_NF_NOUPDATE | 1429 AR5K_PHY_AGCCTL_NF); 1430 1431 ah->ah_noise_floor = nf; 1432 1433 ah->ah_cal_mask &= ~AR5K_CALIBRATION_NF; 1434 1435 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 1436 "noise floor calibrated: %d\n", nf); 1437 } 1438 1439 /* 1440 * Perform a PHY calibration on RF5110 1441 * -Fix BPSK/QAM Constellation (I/Q correction) 1442 */ 1443 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, 1444 struct ieee80211_channel *channel) 1445 { 1446 u32 phy_sig, phy_agc, phy_sat, beacon; 1447 int ret; 1448 1449 /* 1450 * Disable beacons and RX/TX queues, wait 1451 */ 1452 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, 1453 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1454 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); 1455 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); 1456 1457 usleep_range(2000, 2500); 1458 1459 /* 1460 * Set the channel (with AGC turned off) 1461 */ 1462 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1463 udelay(10); 1464 ret = ath5k_hw_channel(ah, channel); 1465 1466 /* 1467 * Activate PHY and wait 1468 */ 1469 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 1470 usleep_range(1000, 1500); 1471 1472 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1473 1474 if (ret) 1475 return ret; 1476 1477 /* 1478 * Calibrate the radio chip 1479 */ 1480 1481 /* Remember normal state */ 1482 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); 1483 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); 1484 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); 1485 1486 /* Update radio registers */ 1487 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | 1488 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG); 1489 1490 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | 1491 AR5K_PHY_AGCCOARSE_LO)) | 1492 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) | 1493 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE); 1494 1495 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | 1496 AR5K_PHY_ADCSAT_THR)) | 1497 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) | 1498 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT); 1499 1500 udelay(20); 1501 1502 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1503 udelay(10); 1504 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); 1505 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); 1506 1507 usleep_range(1000, 1500); 1508 1509 /* 1510 * Enable calibration and wait until completion 1511 */ 1512 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); 1513 1514 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1515 AR5K_PHY_AGCCTL_CAL, 0, false); 1516 1517 /* Reset to normal state */ 1518 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); 1519 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); 1520 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1521 1522 if (ret) { 1523 ATH5K_ERR(ah, "calibration timeout (%uMHz)\n", 1524 channel->center_freq); 1525 return ret; 1526 } 1527 1528 /* 1529 * Re-enable RX/TX and beacons 1530 */ 1531 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, 1532 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210); 1533 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); 1534 1535 return 0; 1536 } 1537 1538 /* 1539 * Perform I/Q calibration on RF5111/5112 and newer chips 1540 */ 1541 static int 1542 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) 1543 { 1544 u32 i_pwr, q_pwr; 1545 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1546 int i; 1547 1548 /* Skip if I/Q calibration is not needed or if it's still running */ 1549 if (!ah->ah_iq_cal_needed) 1550 return -EINVAL; 1551 else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) { 1552 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, 1553 "I/Q calibration still running"); 1554 return -EBUSY; 1555 } 1556 1557 /* Calibration has finished, get the results and re-run */ 1558 1559 /* Work around for empty results which can apparently happen on 5212: 1560 * Read registers up to 10 times until we get both i_pr and q_pwr */ 1561 for (i = 0; i <= 10; i++) { 1562 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1563 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1564 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1565 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, 1566 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1567 if (i_pwr && q_pwr) 1568 break; 1569 } 1570 1571 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; 1572 1573 if (ah->ah_version == AR5K_AR5211) 1574 q_coffd = q_pwr >> 6; 1575 else 1576 q_coffd = q_pwr >> 7; 1577 1578 /* In case i_coffd became zero, cancel calibration 1579 * not only it's too small, it'll also result a divide 1580 * by zero later on. */ 1581 if (i_coffd == 0 || q_coffd < 2) 1582 return -ECANCELED; 1583 1584 /* Protect against loss of sign bits */ 1585 1586 i_coff = (-iq_corr) / i_coffd; 1587 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */ 1588 1589 if (ah->ah_version == AR5K_AR5211) 1590 q_coff = (i_pwr / q_coffd) - 64; 1591 else 1592 q_coff = (i_pwr / q_coffd) - 128; 1593 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1594 1595 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, 1596 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1597 i_coff, q_coff, i_coffd, q_coffd); 1598 1599 /* Commit new I/Q values (set enable bit last to match HAL sources) */ 1600 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); 1601 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); 1602 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); 1603 1604 /* Re-enable calibration -if we don't we'll commit 1605 * the same values again and again */ 1606 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 1607 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 1608 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); 1609 1610 return 0; 1611 } 1612 1613 /* 1614 * Perform a PHY calibration 1615 */ 1616 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1617 struct ieee80211_channel *channel) 1618 { 1619 int ret; 1620 1621 if (ah->ah_radio == AR5K_RF5110) 1622 return ath5k_hw_rf5110_calibrate(ah, channel); 1623 1624 ret = ath5k_hw_rf511x_iq_calibrate(ah); 1625 if (ret) { 1626 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, 1627 "No I/Q correction performed (%uMHz)\n", 1628 channel->center_freq); 1629 1630 /* Happens all the time if there is not much 1631 * traffic, consider it normal behaviour. */ 1632 ret = 0; 1633 } 1634 1635 /* On full calibration do an AGC calibration and 1636 * request a PAPD probe for gainf calibration if 1637 * needed */ 1638 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) { 1639 1640 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1641 AR5K_PHY_AGCCTL_CAL); 1642 1643 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 1644 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF, 1645 0, false); 1646 if (ret) { 1647 ATH5K_ERR(ah, 1648 "gain calibration timeout (%uMHz)\n", 1649 channel->center_freq); 1650 } 1651 1652 if ((ah->ah_radio == AR5K_RF5111 || 1653 ah->ah_radio == AR5K_RF5112) 1654 && (channel->hw_value != AR5K_MODE_11B)) 1655 ath5k_hw_request_rfgain_probe(ah); 1656 } 1657 1658 /* Update noise floor 1659 * XXX: Only do this after AGC calibration */ 1660 if (!(ah->ah_cal_mask & AR5K_CALIBRATION_NF)) 1661 ath5k_hw_update_noise_floor(ah); 1662 1663 return ret; 1664 } 1665 1666 1667 /***************************\ 1668 * Spur mitigation functions * 1669 \***************************/ 1670 1671 static void 1672 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, 1673 struct ieee80211_channel *channel) 1674 { 1675 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 1676 u32 mag_mask[4] = {0, 0, 0, 0}; 1677 u32 pilot_mask[2] = {0, 0}; 1678 /* Note: fbin values are scaled up by 2 */ 1679 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window; 1680 s32 spur_delta_phase, spur_freq_sigma_delta; 1681 s32 spur_offset, num_symbols_x16; 1682 u8 num_symbol_offsets, i, freq_band; 1683 1684 /* Convert current frequency to fbin value (the same way channels 1685 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale 1686 * up by 2 so we can compare it later */ 1687 if (channel->band == IEEE80211_BAND_2GHZ) { 1688 chan_fbin = (channel->center_freq - 2300) * 10; 1689 freq_band = AR5K_EEPROM_BAND_2GHZ; 1690 } else { 1691 chan_fbin = (channel->center_freq - 4900) * 10; 1692 freq_band = AR5K_EEPROM_BAND_5GHZ; 1693 } 1694 1695 /* Check if any spur_chan_fbin from EEPROM is 1696 * within our current channel's spur detection range */ 1697 spur_chan_fbin = AR5K_EEPROM_NO_SPUR; 1698 spur_detection_window = AR5K_SPUR_CHAN_WIDTH; 1699 /* XXX: Half/Quarter channels ?*/ 1700 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 1701 spur_detection_window *= 2; 1702 1703 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) { 1704 spur_chan_fbin = ee->ee_spur_chans[i][freq_band]; 1705 1706 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag 1707 * so it's zero if we got nothing from EEPROM */ 1708 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) { 1709 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1710 break; 1711 } 1712 1713 if ((chan_fbin - spur_detection_window <= 1714 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) && 1715 (chan_fbin + spur_detection_window >= 1716 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) { 1717 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK; 1718 break; 1719 } 1720 } 1721 1722 /* We need to enable spur filter for this channel */ 1723 if (spur_chan_fbin) { 1724 spur_offset = spur_chan_fbin - chan_fbin; 1725 /* 1726 * Calculate deltas: 1727 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21 1728 * spur_delta_phase -> spur_offset / chip_freq << 11 1729 * Note: Both values have 100Hz resolution 1730 */ 1731 switch (ah->ah_bwmode) { 1732 case AR5K_BWMODE_40MHZ: 1733 /* Both sample_freq and chip_freq are 80MHz */ 1734 spur_delta_phase = (spur_offset << 16) / 25; 1735 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1736 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2; 1737 break; 1738 case AR5K_BWMODE_10MHZ: 1739 /* Both sample_freq and chip_freq are 20MHz (?) */ 1740 spur_delta_phase = (spur_offset << 18) / 25; 1741 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1742 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2; 1743 case AR5K_BWMODE_5MHZ: 1744 /* Both sample_freq and chip_freq are 10MHz (?) */ 1745 spur_delta_phase = (spur_offset << 19) / 25; 1746 spur_freq_sigma_delta = (spur_delta_phase >> 10); 1747 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4; 1748 default: 1749 if (channel->band == IEEE80211_BAND_5GHZ) { 1750 /* Both sample_freq and chip_freq are 40MHz */ 1751 spur_delta_phase = (spur_offset << 17) / 25; 1752 spur_freq_sigma_delta = 1753 (spur_delta_phase >> 10); 1754 symbol_width = 1755 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1756 } else { 1757 /* sample_freq -> 40MHz chip_freq -> 44MHz 1758 * (for b compatibility) */ 1759 spur_delta_phase = (spur_offset << 17) / 25; 1760 spur_freq_sigma_delta = 1761 (spur_offset << 8) / 55; 1762 symbol_width = 1763 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz; 1764 } 1765 break; 1766 } 1767 1768 /* Calculate pilot and magnitude masks */ 1769 1770 /* Scale up spur_offset by 1000 to switch to 100HZ resolution 1771 * and divide by symbol_width to find how many symbols we have 1772 * Note: number of symbols is scaled up by 16 */ 1773 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width; 1774 1775 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */ 1776 if (!(num_symbols_x16 & 0xF)) 1777 /* _X_ */ 1778 num_symbol_offsets = 3; 1779 else 1780 /* _xx_ */ 1781 num_symbol_offsets = 4; 1782 1783 for (i = 0; i < num_symbol_offsets; i++) { 1784 1785 /* Calculate pilot mask */ 1786 s32 curr_sym_off = 1787 (num_symbols_x16 / 16) + i + 25; 1788 1789 /* Pilot magnitude mask seems to be a way to 1790 * declare the boundaries for our detection 1791 * window or something, it's 2 for the middle 1792 * value(s) where the symbol is expected to be 1793 * and 1 on the boundary values */ 1794 u8 plt_mag_map = 1795 (i == 0 || i == (num_symbol_offsets - 1)) 1796 ? 1 : 2; 1797 1798 if (curr_sym_off >= 0 && curr_sym_off <= 32) { 1799 if (curr_sym_off <= 25) 1800 pilot_mask[0] |= 1 << curr_sym_off; 1801 else if (curr_sym_off >= 27) 1802 pilot_mask[0] |= 1 << (curr_sym_off - 1); 1803 } else if (curr_sym_off >= 33 && curr_sym_off <= 52) 1804 pilot_mask[1] |= 1 << (curr_sym_off - 33); 1805 1806 /* Calculate magnitude mask (for viterbi decoder) */ 1807 if (curr_sym_off >= -1 && curr_sym_off <= 14) 1808 mag_mask[0] |= 1809 plt_mag_map << (curr_sym_off + 1) * 2; 1810 else if (curr_sym_off >= 15 && curr_sym_off <= 30) 1811 mag_mask[1] |= 1812 plt_mag_map << (curr_sym_off - 15) * 2; 1813 else if (curr_sym_off >= 31 && curr_sym_off <= 46) 1814 mag_mask[2] |= 1815 plt_mag_map << (curr_sym_off - 31) * 2; 1816 else if (curr_sym_off >= 47 && curr_sym_off <= 53) 1817 mag_mask[3] |= 1818 plt_mag_map << (curr_sym_off - 47) * 2; 1819 1820 } 1821 1822 /* Write settings on hw to enable spur filter */ 1823 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1824 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff); 1825 /* XXX: Self correlator also ? */ 1826 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 1827 AR5K_PHY_IQ_PILOT_MASK_EN | 1828 AR5K_PHY_IQ_CHAN_MASK_EN | 1829 AR5K_PHY_IQ_SPUR_FILT_EN); 1830 1831 /* Set delta phase and freq sigma delta */ 1832 ath5k_hw_reg_write(ah, 1833 AR5K_REG_SM(spur_delta_phase, 1834 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) | 1835 AR5K_REG_SM(spur_freq_sigma_delta, 1836 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) | 1837 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC, 1838 AR5K_PHY_TIMING_11); 1839 1840 /* Write pilot masks */ 1841 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); 1842 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1843 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1844 pilot_mask[1]); 1845 1846 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); 1847 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1848 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1849 pilot_mask[1]); 1850 1851 /* Write magnitude masks */ 1852 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); 1853 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); 1854 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); 1855 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1856 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1857 mag_mask[3]); 1858 1859 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); 1860 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); 1861 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); 1862 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1863 AR5K_PHY_BIN_MASK2_4_MASK_4, 1864 mag_mask[3]); 1865 1866 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1867 AR5K_PHY_IQ_SPUR_FILT_EN) { 1868 /* Clean up spur mitigation settings and disable filter */ 1869 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1870 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1871 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1872 AR5K_PHY_IQ_PILOT_MASK_EN | 1873 AR5K_PHY_IQ_CHAN_MASK_EN | 1874 AR5K_PHY_IQ_SPUR_FILT_EN); 1875 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); 1876 1877 /* Clear pilot masks */ 1878 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); 1879 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, 1880 AR5K_PHY_TIMING_8_PILOT_MASK_2, 1881 0); 1882 1883 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); 1884 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, 1885 AR5K_PHY_TIMING_10_PILOT_MASK_2, 1886 0); 1887 1888 /* Clear magnitude masks */ 1889 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); 1890 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); 1891 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); 1892 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1893 AR5K_PHY_BIN_MASK_CTL_MASK_4, 1894 0); 1895 1896 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); 1897 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); 1898 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); 1899 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, 1900 AR5K_PHY_BIN_MASK2_4_MASK_4, 1901 0); 1902 } 1903 } 1904 1905 1906 /*****************\ 1907 * Antenna control * 1908 \*****************/ 1909 1910 static void /*TODO:Boundary check*/ 1911 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) 1912 { 1913 if (ah->ah_version != AR5K_AR5210) 1914 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); 1915 } 1916 1917 /* 1918 * Enable/disable fast rx antenna diversity 1919 */ 1920 static void 1921 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) 1922 { 1923 switch (ee_mode) { 1924 case AR5K_EEPROM_MODE_11G: 1925 /* XXX: This is set to 1926 * disabled on initvals !!! */ 1927 case AR5K_EEPROM_MODE_11A: 1928 if (enable) 1929 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, 1930 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1931 else 1932 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1933 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1934 break; 1935 case AR5K_EEPROM_MODE_11B: 1936 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 1937 AR5K_PHY_AGCCTL_OFDM_DIV_DIS); 1938 break; 1939 default: 1940 return; 1941 } 1942 1943 if (enable) { 1944 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1945 AR5K_PHY_RESTART_DIV_GC, 4); 1946 1947 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1948 AR5K_PHY_FAST_ANT_DIV_EN); 1949 } else { 1950 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, 1951 AR5K_PHY_RESTART_DIV_GC, 0); 1952 1953 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, 1954 AR5K_PHY_FAST_ANT_DIV_EN); 1955 } 1956 } 1957 1958 void 1959 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) 1960 { 1961 u8 ant0, ant1; 1962 1963 /* 1964 * In case a fixed antenna was set as default 1965 * use the same switch table twice. 1966 */ 1967 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) 1968 ant0 = ant1 = AR5K_ANT_SWTABLE_A; 1969 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) 1970 ant0 = ant1 = AR5K_ANT_SWTABLE_B; 1971 else { 1972 ant0 = AR5K_ANT_SWTABLE_A; 1973 ant1 = AR5K_ANT_SWTABLE_B; 1974 } 1975 1976 /* Set antenna idle switch table */ 1977 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, 1978 AR5K_PHY_ANT_CTL_SWTABLE_IDLE, 1979 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | 1980 AR5K_PHY_ANT_CTL_TXRX_EN)); 1981 1982 /* Set antenna switch tables */ 1983 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], 1984 AR5K_PHY_ANT_SWITCH_TABLE_0); 1985 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], 1986 AR5K_PHY_ANT_SWITCH_TABLE_1); 1987 } 1988 1989 /* 1990 * Set antenna operating mode 1991 */ 1992 void 1993 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) 1994 { 1995 struct ieee80211_channel *channel = ah->ah_current_channel; 1996 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div; 1997 bool use_def_for_sg; 1998 int ee_mode; 1999 u8 def_ant, tx_ant; 2000 u32 sta_id1 = 0; 2001 2002 /* if channel is not initialized yet we can't set the antennas 2003 * so just store the mode. it will be set on the next reset */ 2004 if (channel == NULL) { 2005 ah->ah_ant_mode = ant_mode; 2006 return; 2007 } 2008 2009 def_ant = ah->ah_def_ant; 2010 2011 ee_mode = ath5k_eeprom_mode_from_channel(channel); 2012 if (ee_mode < 0) { 2013 ATH5K_ERR(ah, 2014 "invalid channel: %d\n", channel->center_freq); 2015 return; 2016 } 2017 2018 switch (ant_mode) { 2019 case AR5K_ANTMODE_DEFAULT: 2020 tx_ant = 0; 2021 use_def_for_tx = false; 2022 update_def_on_tx = false; 2023 use_def_for_rts = false; 2024 use_def_for_sg = false; 2025 fast_div = true; 2026 break; 2027 case AR5K_ANTMODE_FIXED_A: 2028 def_ant = 1; 2029 tx_ant = 1; 2030 use_def_for_tx = true; 2031 update_def_on_tx = false; 2032 use_def_for_rts = true; 2033 use_def_for_sg = true; 2034 fast_div = false; 2035 break; 2036 case AR5K_ANTMODE_FIXED_B: 2037 def_ant = 2; 2038 tx_ant = 2; 2039 use_def_for_tx = true; 2040 update_def_on_tx = false; 2041 use_def_for_rts = true; 2042 use_def_for_sg = true; 2043 fast_div = false; 2044 break; 2045 case AR5K_ANTMODE_SINGLE_AP: 2046 def_ant = 1; /* updated on tx */ 2047 tx_ant = 0; 2048 use_def_for_tx = true; 2049 update_def_on_tx = true; 2050 use_def_for_rts = true; 2051 use_def_for_sg = true; 2052 fast_div = true; 2053 break; 2054 case AR5K_ANTMODE_SECTOR_AP: 2055 tx_ant = 1; /* variable */ 2056 use_def_for_tx = false; 2057 update_def_on_tx = false; 2058 use_def_for_rts = true; 2059 use_def_for_sg = false; 2060 fast_div = false; 2061 break; 2062 case AR5K_ANTMODE_SECTOR_STA: 2063 tx_ant = 1; /* variable */ 2064 use_def_for_tx = true; 2065 update_def_on_tx = false; 2066 use_def_for_rts = true; 2067 use_def_for_sg = false; 2068 fast_div = true; 2069 break; 2070 case AR5K_ANTMODE_DEBUG: 2071 def_ant = 1; 2072 tx_ant = 2; 2073 use_def_for_tx = false; 2074 update_def_on_tx = false; 2075 use_def_for_rts = false; 2076 use_def_for_sg = false; 2077 fast_div = false; 2078 break; 2079 default: 2080 return; 2081 } 2082 2083 ah->ah_tx_ant = tx_ant; 2084 ah->ah_ant_mode = ant_mode; 2085 ah->ah_def_ant = def_ant; 2086 2087 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0; 2088 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0; 2089 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0; 2090 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0; 2091 2092 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); 2093 2094 if (sta_id1) 2095 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); 2096 2097 ath5k_hw_set_antenna_switch(ah, ee_mode); 2098 /* Note: set diversity before default antenna 2099 * because it won't work correctly */ 2100 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); 2101 ath5k_hw_set_def_antenna(ah, def_ant); 2102 } 2103 2104 2105 /****************\ 2106 * TX power setup * 2107 \****************/ 2108 2109 /* 2110 * Helper functions 2111 */ 2112 2113 /* 2114 * Do linear interpolation between two given (x, y) points 2115 */ 2116 static s16 2117 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right, 2118 s16 y_left, s16 y_right) 2119 { 2120 s16 ratio, result; 2121 2122 /* Avoid divide by zero and skip interpolation 2123 * if we have the same point */ 2124 if ((x_left == x_right) || (y_left == y_right)) 2125 return y_left; 2126 2127 /* 2128 * Since we use ints and not fps, we need to scale up in 2129 * order to get a sane ratio value (or else we 'll eg. get 2130 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 2131 * to have some accuracy both for 0.5 and 0.25 steps. 2132 */ 2133 ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left)); 2134 2135 /* Now scale down to be in range */ 2136 result = y_left + (ratio * (target - x_left) / 100); 2137 2138 return result; 2139 } 2140 2141 /* 2142 * Find vertical boundary (min pwr) for the linear PCDAC curve. 2143 * 2144 * Since we have the top of the curve and we draw the line below 2145 * until we reach 1 (1 pcdac step) we need to know which point 2146 * (x value) that is so that we don't go below y axis and have negative 2147 * pcdac values when creating the curve, or fill the table with zeroes. 2148 */ 2149 static s16 2150 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR, 2151 const s16 *pwrL, const s16 *pwrR) 2152 { 2153 s8 tmp; 2154 s16 min_pwrL, min_pwrR; 2155 s16 pwr_i; 2156 2157 /* Some vendors write the same pcdac value twice !!! */ 2158 if (stepL[0] == stepL[1] || stepR[0] == stepR[1]) 2159 return max(pwrL[0], pwrR[0]); 2160 2161 if (pwrL[0] == pwrL[1]) 2162 min_pwrL = pwrL[0]; 2163 else { 2164 pwr_i = pwrL[0]; 2165 do { 2166 pwr_i--; 2167 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2168 pwrL[0], pwrL[1], 2169 stepL[0], stepL[1]); 2170 } while (tmp > 1); 2171 2172 min_pwrL = pwr_i; 2173 } 2174 2175 if (pwrR[0] == pwrR[1]) 2176 min_pwrR = pwrR[0]; 2177 else { 2178 pwr_i = pwrR[0]; 2179 do { 2180 pwr_i--; 2181 tmp = (s8) ath5k_get_interpolated_value(pwr_i, 2182 pwrR[0], pwrR[1], 2183 stepR[0], stepR[1]); 2184 } while (tmp > 1); 2185 2186 min_pwrR = pwr_i; 2187 } 2188 2189 /* Keep the right boundary so that it works for both curves */ 2190 return max(min_pwrL, min_pwrR); 2191 } 2192 2193 /* 2194 * Interpolate (pwr,vpd) points to create a Power to PDADC or a 2195 * Power to PCDAC curve. 2196 * 2197 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC 2198 * steps (offsets) on y axis. Power can go up to 31.5dB and max 2199 * PCDAC/PDADC step for each curve is 64 but we can write more than 2200 * one curves on hw so we can go up to 128 (which is the max step we 2201 * can write on the final table). 2202 * 2203 * We write y values (PCDAC/PDADC steps) on hw. 2204 */ 2205 static void 2206 ath5k_create_power_curve(s16 pmin, s16 pmax, 2207 const s16 *pwr, const u8 *vpd, 2208 u8 num_points, 2209 u8 *vpd_table, u8 type) 2210 { 2211 u8 idx[2] = { 0, 1 }; 2212 s16 pwr_i = 2 * pmin; 2213 int i; 2214 2215 if (num_points < 2) 2216 return; 2217 2218 /* We want the whole line, so adjust boundaries 2219 * to cover the entire power range. Note that 2220 * power values are already 0.25dB so no need 2221 * to multiply pwr_i by 2 */ 2222 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) { 2223 pwr_i = pmin; 2224 pmin = 0; 2225 pmax = 63; 2226 } 2227 2228 /* Find surrounding turning points (TPs) 2229 * and interpolate between them */ 2230 for (i = 0; (i <= (u16) (pmax - pmin)) && 2231 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2232 2233 /* We passed the right TP, move to the next set of TPs 2234 * if we pass the last TP, extrapolate above using the last 2235 * two TPs for ratio */ 2236 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) { 2237 idx[0]++; 2238 idx[1]++; 2239 } 2240 2241 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i, 2242 pwr[idx[0]], pwr[idx[1]], 2243 vpd[idx[0]], vpd[idx[1]]); 2244 2245 /* Increase by 0.5dB 2246 * (0.25 dB units) */ 2247 pwr_i += 2; 2248 } 2249 } 2250 2251 /* 2252 * Get the surrounding per-channel power calibration piers 2253 * for a given frequency so that we can interpolate between 2254 * them and come up with an appropriate dataset for our current 2255 * channel. 2256 */ 2257 static void 2258 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, 2259 struct ieee80211_channel *channel, 2260 struct ath5k_chan_pcal_info **pcinfo_l, 2261 struct ath5k_chan_pcal_info **pcinfo_r) 2262 { 2263 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2264 struct ath5k_chan_pcal_info *pcinfo; 2265 u8 idx_l, idx_r; 2266 u8 mode, max, i; 2267 u32 target = channel->center_freq; 2268 2269 idx_l = 0; 2270 idx_r = 0; 2271 2272 switch (channel->hw_value) { 2273 case AR5K_EEPROM_MODE_11A: 2274 pcinfo = ee->ee_pwr_cal_a; 2275 mode = AR5K_EEPROM_MODE_11A; 2276 break; 2277 case AR5K_EEPROM_MODE_11B: 2278 pcinfo = ee->ee_pwr_cal_b; 2279 mode = AR5K_EEPROM_MODE_11B; 2280 break; 2281 case AR5K_EEPROM_MODE_11G: 2282 default: 2283 pcinfo = ee->ee_pwr_cal_g; 2284 mode = AR5K_EEPROM_MODE_11G; 2285 break; 2286 } 2287 max = ee->ee_n_piers[mode] - 1; 2288 2289 /* Frequency is below our calibrated 2290 * range. Use the lowest power curve 2291 * we have */ 2292 if (target < pcinfo[0].freq) { 2293 idx_l = idx_r = 0; 2294 goto done; 2295 } 2296 2297 /* Frequency is above our calibrated 2298 * range. Use the highest power curve 2299 * we have */ 2300 if (target > pcinfo[max].freq) { 2301 idx_l = idx_r = max; 2302 goto done; 2303 } 2304 2305 /* Frequency is inside our calibrated 2306 * channel range. Pick the surrounding 2307 * calibration piers so that we can 2308 * interpolate */ 2309 for (i = 0; i <= max; i++) { 2310 2311 /* Frequency matches one of our calibration 2312 * piers, no need to interpolate, just use 2313 * that calibration pier */ 2314 if (pcinfo[i].freq == target) { 2315 idx_l = idx_r = i; 2316 goto done; 2317 } 2318 2319 /* We found a calibration pier that's above 2320 * frequency, use this pier and the previous 2321 * one to interpolate */ 2322 if (target < pcinfo[i].freq) { 2323 idx_r = i; 2324 idx_l = idx_r - 1; 2325 goto done; 2326 } 2327 } 2328 2329 done: 2330 *pcinfo_l = &pcinfo[idx_l]; 2331 *pcinfo_r = &pcinfo[idx_r]; 2332 } 2333 2334 /* 2335 * Get the surrounding per-rate power calibration data 2336 * for a given frequency and interpolate between power 2337 * values to set max target power supported by hw for 2338 * each rate. 2339 */ 2340 static void 2341 ath5k_get_rate_pcal_data(struct ath5k_hw *ah, 2342 struct ieee80211_channel *channel, 2343 struct ath5k_rate_pcal_info *rates) 2344 { 2345 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2346 struct ath5k_rate_pcal_info *rpinfo; 2347 u8 idx_l, idx_r; 2348 u8 mode, max, i; 2349 u32 target = channel->center_freq; 2350 2351 idx_l = 0; 2352 idx_r = 0; 2353 2354 switch (channel->hw_value) { 2355 case AR5K_MODE_11A: 2356 rpinfo = ee->ee_rate_tpwr_a; 2357 mode = AR5K_EEPROM_MODE_11A; 2358 break; 2359 case AR5K_MODE_11B: 2360 rpinfo = ee->ee_rate_tpwr_b; 2361 mode = AR5K_EEPROM_MODE_11B; 2362 break; 2363 case AR5K_MODE_11G: 2364 default: 2365 rpinfo = ee->ee_rate_tpwr_g; 2366 mode = AR5K_EEPROM_MODE_11G; 2367 break; 2368 } 2369 max = ee->ee_rate_target_pwr_num[mode] - 1; 2370 2371 /* Get the surrounding calibration 2372 * piers - same as above */ 2373 if (target < rpinfo[0].freq) { 2374 idx_l = idx_r = 0; 2375 goto done; 2376 } 2377 2378 if (target > rpinfo[max].freq) { 2379 idx_l = idx_r = max; 2380 goto done; 2381 } 2382 2383 for (i = 0; i <= max; i++) { 2384 2385 if (rpinfo[i].freq == target) { 2386 idx_l = idx_r = i; 2387 goto done; 2388 } 2389 2390 if (target < rpinfo[i].freq) { 2391 idx_r = i; 2392 idx_l = idx_r - 1; 2393 goto done; 2394 } 2395 } 2396 2397 done: 2398 /* Now interpolate power value, based on the frequency */ 2399 rates->freq = target; 2400 2401 rates->target_power_6to24 = 2402 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2403 rpinfo[idx_r].freq, 2404 rpinfo[idx_l].target_power_6to24, 2405 rpinfo[idx_r].target_power_6to24); 2406 2407 rates->target_power_36 = 2408 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2409 rpinfo[idx_r].freq, 2410 rpinfo[idx_l].target_power_36, 2411 rpinfo[idx_r].target_power_36); 2412 2413 rates->target_power_48 = 2414 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2415 rpinfo[idx_r].freq, 2416 rpinfo[idx_l].target_power_48, 2417 rpinfo[idx_r].target_power_48); 2418 2419 rates->target_power_54 = 2420 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq, 2421 rpinfo[idx_r].freq, 2422 rpinfo[idx_l].target_power_54, 2423 rpinfo[idx_r].target_power_54); 2424 } 2425 2426 /* 2427 * Get the max edge power for this channel if 2428 * we have such data from EEPROM's Conformance Test 2429 * Limits (CTL), and limit max power if needed. 2430 */ 2431 static void 2432 ath5k_get_max_ctl_power(struct ath5k_hw *ah, 2433 struct ieee80211_channel *channel) 2434 { 2435 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2436 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2437 struct ath5k_edge_power *rep = ee->ee_ctl_pwr; 2438 u8 *ctl_val = ee->ee_ctl; 2439 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; 2440 s16 edge_pwr = 0; 2441 u8 rep_idx; 2442 u8 i, ctl_mode; 2443 u8 ctl_idx = 0xFF; 2444 u32 target = channel->center_freq; 2445 2446 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band); 2447 2448 switch (channel->hw_value) { 2449 case AR5K_MODE_11A: 2450 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2451 ctl_mode |= AR5K_CTL_TURBO; 2452 else 2453 ctl_mode |= AR5K_CTL_11A; 2454 break; 2455 case AR5K_MODE_11G: 2456 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) 2457 ctl_mode |= AR5K_CTL_TURBOG; 2458 else 2459 ctl_mode |= AR5K_CTL_11G; 2460 break; 2461 case AR5K_MODE_11B: 2462 ctl_mode |= AR5K_CTL_11B; 2463 break; 2464 default: 2465 return; 2466 } 2467 2468 for (i = 0; i < ee->ee_ctls; i++) { 2469 if (ctl_val[i] == ctl_mode) { 2470 ctl_idx = i; 2471 break; 2472 } 2473 } 2474 2475 /* If we have a CTL dataset available grab it and find the 2476 * edge power for our frequency */ 2477 if (ctl_idx == 0xFF) 2478 return; 2479 2480 /* Edge powers are sorted by frequency from lower 2481 * to higher. Each CTL corresponds to 8 edge power 2482 * measurements. */ 2483 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES; 2484 2485 /* Don't do boundaries check because we 2486 * might have more that one bands defined 2487 * for this mode */ 2488 2489 /* Get the edge power that's closer to our 2490 * frequency */ 2491 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) { 2492 rep_idx += i; 2493 if (target <= rep[rep_idx].freq) 2494 edge_pwr = (s16) rep[rep_idx].edge; 2495 } 2496 2497 if (edge_pwr) 2498 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr); 2499 } 2500 2501 2502 /* 2503 * Power to PCDAC table functions 2504 */ 2505 2506 /* 2507 * Fill Power to PCDAC table on RF5111 2508 * 2509 * No further processing is needed for RF5111, the only thing we have to 2510 * do is fill the values below and above calibration range since eeprom data 2511 * may not cover the entire PCDAC table. 2512 */ 2513 static void 2514 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2515 s16 *table_max) 2516 { 2517 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2518 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2519 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2520 s16 min_pwr, max_pwr; 2521 2522 /* Get table boundaries */ 2523 min_pwr = table_min[0]; 2524 pcdac_0 = pcdac_tmp[0]; 2525 2526 max_pwr = table_max[0]; 2527 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]]; 2528 2529 /* Extrapolate below minimum using pcdac_0 */ 2530 pcdac_i = 0; 2531 for (i = 0; i < min_pwr; i++) 2532 pcdac_out[pcdac_i++] = pcdac_0; 2533 2534 /* Copy values from pcdac_tmp */ 2535 pwr_idx = min_pwr; 2536 for (i = 0; pwr_idx <= max_pwr && 2537 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2538 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2539 pwr_idx++; 2540 } 2541 2542 /* Extrapolate above maximum */ 2543 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE) 2544 pcdac_out[pcdac_i++] = pcdac_n; 2545 2546 } 2547 2548 /* 2549 * Combine available XPD Curves and fill Linear Power to PCDAC table 2550 * on RF5112 2551 * 2552 * RFX112 can have up to 2 curves (one for low txpower range and one for 2553 * higher txpower range). We need to put them both on pcdac_out and place 2554 * them in the correct location. In case we only have one curve available 2555 * just fit it on pcdac_out (it's supposed to cover the entire range of 2556 * available pwr levels since it's always the higher power curve). Extrapolate 2557 * below and above final table if needed. 2558 */ 2559 static void 2560 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2561 s16 *table_max, u8 pdcurves) 2562 { 2563 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2564 u8 *pcdac_low_pwr; 2565 u8 *pcdac_high_pwr; 2566 u8 *pcdac_tmp; 2567 u8 pwr; 2568 s16 max_pwr_idx; 2569 s16 min_pwr_idx; 2570 s16 mid_pwr_idx = 0; 2571 /* Edge flag turns on the 7nth bit on the PCDAC 2572 * to declare the higher power curve (force values 2573 * to be greater than 64). If we only have one curve 2574 * we don't need to set this, if we have 2 curves and 2575 * fill the table backwards this can also be used to 2576 * switch from higher power curve to lower power curve */ 2577 u8 edge_flag; 2578 int i; 2579 2580 /* When we have only one curve available 2581 * that's the higher power curve. If we have 2582 * two curves the first is the high power curve 2583 * and the next is the low power curve. */ 2584 if (pdcurves > 1) { 2585 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; 2586 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2587 mid_pwr_idx = table_max[1] - table_min[1] - 1; 2588 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2589 2590 /* If table size goes beyond 31.5dB, keep the 2591 * upper 31.5dB range when setting tx power. 2592 * Note: 126 = 31.5 dB in quarter dB steps */ 2593 if (table_max[0] - table_min[1] > 126) 2594 min_pwr_idx = table_max[0] - 126; 2595 else 2596 min_pwr_idx = table_min[1]; 2597 2598 /* Since we fill table backwards 2599 * start from high power curve */ 2600 pcdac_tmp = pcdac_high_pwr; 2601 2602 edge_flag = 0x40; 2603 } else { 2604 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ 2605 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; 2606 min_pwr_idx = table_min[0]; 2607 max_pwr_idx = (table_max[0] - table_min[0]) / 2; 2608 pcdac_tmp = pcdac_high_pwr; 2609 edge_flag = 0; 2610 } 2611 2612 /* This is used when setting tx power*/ 2613 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2; 2614 2615 /* Fill Power to PCDAC table backwards */ 2616 pwr = max_pwr_idx; 2617 for (i = 63; i >= 0; i--) { 2618 /* Entering lower power range, reset 2619 * edge flag and set pcdac_tmp to lower 2620 * power curve.*/ 2621 if (edge_flag == 0x40 && 2622 (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2623 edge_flag = 0x00; 2624 pcdac_tmp = pcdac_low_pwr; 2625 pwr = mid_pwr_idx / 2; 2626 } 2627 2628 /* Don't go below 1, extrapolate below if we have 2629 * already switched to the lower power curve -or 2630 * we only have one curve and edge_flag is zero 2631 * anyway */ 2632 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2633 while (i >= 0) { 2634 pcdac_out[i] = pcdac_out[i + 1]; 2635 i--; 2636 } 2637 break; 2638 } 2639 2640 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag; 2641 2642 /* Extrapolate above if pcdac is greater than 2643 * 126 -this can happen because we OR pcdac_out 2644 * value with edge_flag on high power curve */ 2645 if (pcdac_out[i] > 126) 2646 pcdac_out[i] = 126; 2647 2648 /* Decrease by a 0.5dB step */ 2649 pwr--; 2650 } 2651 } 2652 2653 /* Write PCDAC values on hw */ 2654 static void 2655 ath5k_write_pcdac_table(struct ath5k_hw *ah) 2656 { 2657 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2658 int i; 2659 2660 /* 2661 * Write TX power values 2662 */ 2663 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2664 ath5k_hw_reg_write(ah, 2665 (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) | 2666 (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16), 2667 AR5K_PHY_PCDAC_TXPOWER(i)); 2668 } 2669 } 2670 2671 2672 /* 2673 * Power to PDADC table functions 2674 */ 2675 2676 /* 2677 * Set the gain boundaries and create final Power to PDADC table 2678 * 2679 * We can have up to 4 pd curves, we need to do a similar process 2680 * as we do for RF5112. This time we don't have an edge_flag but we 2681 * set the gain boundaries on a separate register. 2682 */ 2683 static void 2684 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, 2685 s16 *pwr_min, s16 *pwr_max, u8 pdcurves) 2686 { 2687 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS]; 2688 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2689 u8 *pdadc_tmp; 2690 s16 pdadc_0; 2691 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size; 2692 u8 pd_gain_overlap; 2693 2694 /* Note: Register value is initialized on initvals 2695 * there is no feedback from hw. 2696 * XXX: What about pd_gain_overlap from EEPROM ? */ 2697 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & 2698 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP; 2699 2700 /* Create final PDADC table */ 2701 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) { 2702 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; 2703 2704 if (pdg == pdcurves - 1) 2705 /* 2 dB boundary stretch for last 2706 * (higher power) curve */ 2707 gain_boundaries[pdg] = pwr_max[pdg] + 4; 2708 else 2709 /* Set gain boundary in the middle 2710 * between this curve and the next one */ 2711 gain_boundaries[pdg] = 2712 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2; 2713 2714 /* Sanity check in case our 2 db stretch got out of 2715 * range. */ 2716 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER) 2717 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER; 2718 2719 /* For the first curve (lower power) 2720 * start from 0 dB */ 2721 if (pdg == 0) 2722 pdadc_0 = 0; 2723 else 2724 /* For the other curves use the gain overlap */ 2725 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) - 2726 pd_gain_overlap; 2727 2728 /* Force each power step to be at least 0.5 dB */ 2729 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1) 2730 pwr_step = pdadc_tmp[1] - pdadc_tmp[0]; 2731 else 2732 pwr_step = 1; 2733 2734 /* If pdadc_0 is negative, we need to extrapolate 2735 * below this pdgain by a number of pwr_steps */ 2736 while ((pdadc_0 < 0) && (pdadc_i < 128)) { 2737 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step; 2738 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp; 2739 pdadc_0++; 2740 } 2741 2742 /* Set last pwr level, using gain boundaries */ 2743 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg]; 2744 /* Limit it to be inside pwr range */ 2745 table_size = pwr_max[pdg] - pwr_min[pdg]; 2746 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size; 2747 2748 /* Fill pdadc_out table */ 2749 while (pdadc_0 < max_idx && pdadc_i < 128) 2750 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++]; 2751 2752 /* Need to extrapolate above this pdgain? */ 2753 if (pdadc_n <= max_idx) 2754 continue; 2755 2756 /* Force each power step to be at least 0.5 dB */ 2757 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1) 2758 pwr_step = pdadc_tmp[table_size - 1] - 2759 pdadc_tmp[table_size - 2]; 2760 else 2761 pwr_step = 1; 2762 2763 /* Extrapolate above */ 2764 while ((pdadc_0 < (s16) pdadc_n) && 2765 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) { 2766 s16 tmp = pdadc_tmp[table_size - 1] + 2767 (pdadc_0 - max_idx) * pwr_step; 2768 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp; 2769 pdadc_0++; 2770 } 2771 } 2772 2773 while (pdg < AR5K_EEPROM_N_PD_GAINS) { 2774 gain_boundaries[pdg] = gain_boundaries[pdg - 1]; 2775 pdg++; 2776 } 2777 2778 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) { 2779 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1]; 2780 pdadc_i++; 2781 } 2782 2783 /* Set gain boundaries */ 2784 ath5k_hw_reg_write(ah, 2785 AR5K_REG_SM(pd_gain_overlap, 2786 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) | 2787 AR5K_REG_SM(gain_boundaries[0], 2788 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) | 2789 AR5K_REG_SM(gain_boundaries[1], 2790 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) | 2791 AR5K_REG_SM(gain_boundaries[2], 2792 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) | 2793 AR5K_REG_SM(gain_boundaries[3], 2794 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4), 2795 AR5K_PHY_TPC_RG5); 2796 2797 /* Used for setting rate power table */ 2798 ah->ah_txpower.txp_min_idx = pwr_min[0]; 2799 2800 } 2801 2802 /* Write PDADC values on hw */ 2803 static void 2804 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) 2805 { 2806 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2807 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; 2808 u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2809 u8 pdcurves = ee->ee_pd_gains[ee_mode]; 2810 u32 reg; 2811 u8 i; 2812 2813 /* Select the right pdgain curves */ 2814 2815 /* Clear current settings */ 2816 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); 2817 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 | 2818 AR5K_PHY_TPC_RG1_PDGAIN_2 | 2819 AR5K_PHY_TPC_RG1_PDGAIN_3 | 2820 AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2821 2822 /* 2823 * Use pd_gains curve from eeprom 2824 * 2825 * This overrides the default setting from initvals 2826 * in case some vendors (e.g. Zcomax) don't use the default 2827 * curves. If we don't honor their settings we 'll get a 2828 * 5dB (1 * gain overlap ?) drop. 2829 */ 2830 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN); 2831 2832 switch (pdcurves) { 2833 case 3: 2834 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3); 2835 /* Fall through */ 2836 case 2: 2837 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2); 2838 /* Fall through */ 2839 case 1: 2840 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1); 2841 break; 2842 } 2843 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); 2844 2845 /* 2846 * Write TX power values 2847 */ 2848 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2849 u32 val = get_unaligned_le32(&pdadc_out[4 * i]); 2850 ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i)); 2851 } 2852 } 2853 2854 2855 /* 2856 * Common code for PCDAC/PDADC tables 2857 */ 2858 2859 /* 2860 * This is the main function that uses all of the above 2861 * to set PCDAC/PDADC table on hw for the current channel. 2862 * This table is used for tx power calibration on the baseband, 2863 * without it we get weird tx power levels and in some cases 2864 * distorted spectral mask 2865 */ 2866 static int 2867 ath5k_setup_channel_powertable(struct ath5k_hw *ah, 2868 struct ieee80211_channel *channel, 2869 u8 ee_mode, u8 type) 2870 { 2871 struct ath5k_pdgain_info *pdg_L, *pdg_R; 2872 struct ath5k_chan_pcal_info *pcinfo_L; 2873 struct ath5k_chan_pcal_info *pcinfo_R; 2874 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 2875 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode]; 2876 s16 table_min[AR5K_EEPROM_N_PD_GAINS]; 2877 s16 table_max[AR5K_EEPROM_N_PD_GAINS]; 2878 u8 *tmpL; 2879 u8 *tmpR; 2880 u32 target = channel->center_freq; 2881 int pdg, i; 2882 2883 /* Get surrounding freq piers for this channel */ 2884 ath5k_get_chan_pcal_surrounding_piers(ah, channel, 2885 &pcinfo_L, 2886 &pcinfo_R); 2887 2888 /* Loop over pd gain curves on 2889 * surrounding freq piers by index */ 2890 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) { 2891 2892 /* Fill curves in reverse order 2893 * from lower power (max gain) 2894 * to higher power. Use curve -> idx 2895 * backmapping we did on eeprom init */ 2896 u8 idx = pdg_curve_to_idx[pdg]; 2897 2898 /* Grab the needed curves by index */ 2899 pdg_L = &pcinfo_L->pd_curves[idx]; 2900 pdg_R = &pcinfo_R->pd_curves[idx]; 2901 2902 /* Initialize the temp tables */ 2903 tmpL = ah->ah_txpower.tmpL[pdg]; 2904 tmpR = ah->ah_txpower.tmpR[pdg]; 2905 2906 /* Set curve's x boundaries and create 2907 * curves so that they cover the same 2908 * range (if we don't do that one table 2909 * will have values on some range and the 2910 * other one won't have any so interpolation 2911 * will fail) */ 2912 table_min[pdg] = min(pdg_L->pd_pwr[0], 2913 pdg_R->pd_pwr[0]) / 2; 2914 2915 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2916 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2; 2917 2918 /* Now create the curves on surrounding channels 2919 * and interpolate if needed to get the final 2920 * curve for this gain on this channel */ 2921 switch (type) { 2922 case AR5K_PWRTABLE_LINEAR_PCDAC: 2923 /* Override min/max so that we don't loose 2924 * accuracy (don't divide by 2) */ 2925 table_min[pdg] = min(pdg_L->pd_pwr[0], 2926 pdg_R->pd_pwr[0]); 2927 2928 table_max[pdg] = 2929 max(pdg_L->pd_pwr[pdg_L->pd_points - 1], 2930 pdg_R->pd_pwr[pdg_R->pd_points - 1]); 2931 2932 /* Override minimum so that we don't get 2933 * out of bounds while extrapolating 2934 * below. Don't do this when we have 2 2935 * curves and we are on the high power curve 2936 * because table_min is ok in this case */ 2937 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) { 2938 2939 table_min[pdg] = 2940 ath5k_get_linear_pcdac_min(pdg_L->pd_step, 2941 pdg_R->pd_step, 2942 pdg_L->pd_pwr, 2943 pdg_R->pd_pwr); 2944 2945 /* Don't go too low because we will 2946 * miss the upper part of the curve. 2947 * Note: 126 = 31.5dB (max power supported) 2948 * in 0.25dB units */ 2949 if (table_max[pdg] - table_min[pdg] > 126) 2950 table_min[pdg] = table_max[pdg] - 126; 2951 } 2952 2953 /* Fall through */ 2954 case AR5K_PWRTABLE_PWR_TO_PCDAC: 2955 case AR5K_PWRTABLE_PWR_TO_PDADC: 2956 2957 ath5k_create_power_curve(table_min[pdg], 2958 table_max[pdg], 2959 pdg_L->pd_pwr, 2960 pdg_L->pd_step, 2961 pdg_L->pd_points, tmpL, type); 2962 2963 /* We are in a calibration 2964 * pier, no need to interpolate 2965 * between freq piers */ 2966 if (pcinfo_L == pcinfo_R) 2967 continue; 2968 2969 ath5k_create_power_curve(table_min[pdg], 2970 table_max[pdg], 2971 pdg_R->pd_pwr, 2972 pdg_R->pd_step, 2973 pdg_R->pd_points, tmpR, type); 2974 break; 2975 default: 2976 return -EINVAL; 2977 } 2978 2979 /* Interpolate between curves 2980 * of surrounding freq piers to 2981 * get the final curve for this 2982 * pd gain. Re-use tmpL for interpolation 2983 * output */ 2984 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) && 2985 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) { 2986 tmpL[i] = (u8) ath5k_get_interpolated_value(target, 2987 (s16) pcinfo_L->freq, 2988 (s16) pcinfo_R->freq, 2989 (s16) tmpL[i], 2990 (s16) tmpR[i]); 2991 } 2992 } 2993 2994 /* Now we have a set of curves for this 2995 * channel on tmpL (x range is table_max - table_min 2996 * and y values are tmpL[pdg][]) sorted in the same 2997 * order as EEPROM (because we've used the backmapping). 2998 * So for RF5112 it's from higher power to lower power 2999 * and for RF2413 it's from lower power to higher power. 3000 * For RF5111 we only have one curve. */ 3001 3002 /* Fill min and max power levels for this 3003 * channel by interpolating the values on 3004 * surrounding channels to complete the dataset */ 3005 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, 3006 (s16) pcinfo_L->freq, 3007 (s16) pcinfo_R->freq, 3008 pcinfo_L->min_pwr, pcinfo_R->min_pwr); 3009 3010 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, 3011 (s16) pcinfo_L->freq, 3012 (s16) pcinfo_R->freq, 3013 pcinfo_L->max_pwr, pcinfo_R->max_pwr); 3014 3015 /* Fill PCDAC/PDADC table */ 3016 switch (type) { 3017 case AR5K_PWRTABLE_LINEAR_PCDAC: 3018 /* For RF5112 we can have one or two curves 3019 * and each curve covers a certain power lvl 3020 * range so we need to do some more processing */ 3021 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, 3022 ee->ee_pd_gains[ee_mode]); 3023 3024 /* Set txp.offset so that we can 3025 * match max power value with max 3026 * table index */ 3027 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); 3028 break; 3029 case AR5K_PWRTABLE_PWR_TO_PCDAC: 3030 /* We are done for RF5111 since it has only 3031 * one curve, just fit the curve on the table */ 3032 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); 3033 3034 /* No rate powertable adjustment for RF5111 */ 3035 ah->ah_txpower.txp_min_idx = 0; 3036 ah->ah_txpower.txp_offset = 0; 3037 break; 3038 case AR5K_PWRTABLE_PWR_TO_PDADC: 3039 /* Set PDADC boundaries and fill 3040 * final PDADC table */ 3041 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, 3042 ee->ee_pd_gains[ee_mode]); 3043 3044 /* Set txp.offset, note that table_min 3045 * can be negative */ 3046 ah->ah_txpower.txp_offset = table_min[0]; 3047 break; 3048 default: 3049 return -EINVAL; 3050 } 3051 3052 ah->ah_txpower.txp_setup = true; 3053 3054 return 0; 3055 } 3056 3057 /* Write power table for current channel to hw */ 3058 static void 3059 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) 3060 { 3061 if (type == AR5K_PWRTABLE_PWR_TO_PDADC) 3062 ath5k_write_pwr_to_pdadc_table(ah, ee_mode); 3063 else 3064 ath5k_write_pcdac_table(ah); 3065 } 3066 3067 /* 3068 * Per-rate tx power setting 3069 * 3070 * This is the code that sets the desired tx power (below 3071 * maximum) on hw for each rate (we also have TPC that sets 3072 * power per packet). We do that by providing an index on the 3073 * PCDAC/PDADC table we set up. 3074 */ 3075 3076 /* 3077 * Set rate power table 3078 * 3079 * For now we only limit txpower based on maximum tx power 3080 * supported by hw (what's inside rate_info). We need to limit 3081 * this even more, based on regulatory domain etc. 3082 * 3083 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps) 3084 * and is indexed as follows: 3085 * rates[0] - rates[7] -> OFDM rates 3086 * rates[8] - rates[14] -> CCK rates 3087 * rates[15] -> XR rates (they all have the same power) 3088 */ 3089 static void 3090 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, 3091 struct ath5k_rate_pcal_info *rate_info, 3092 u8 ee_mode) 3093 { 3094 unsigned int i; 3095 u16 *rates; 3096 3097 /* max_pwr is power level we got from driver/user in 0.5dB 3098 * units, switch to 0.25dB units so we can compare */ 3099 max_pwr *= 2; 3100 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; 3101 3102 /* apply rate limits */ 3103 rates = ah->ah_txpower.txp_rates_power_table; 3104 3105 /* OFDM rates 6 to 24Mb/s */ 3106 for (i = 0; i < 5; i++) 3107 rates[i] = min(max_pwr, rate_info->target_power_6to24); 3108 3109 /* Rest OFDM rates */ 3110 rates[5] = min(rates[0], rate_info->target_power_36); 3111 rates[6] = min(rates[0], rate_info->target_power_48); 3112 rates[7] = min(rates[0], rate_info->target_power_54); 3113 3114 /* CCK rates */ 3115 /* 1L */ 3116 rates[8] = min(rates[0], rate_info->target_power_6to24); 3117 /* 2L */ 3118 rates[9] = min(rates[0], rate_info->target_power_36); 3119 /* 2S */ 3120 rates[10] = min(rates[0], rate_info->target_power_36); 3121 /* 5L */ 3122 rates[11] = min(rates[0], rate_info->target_power_48); 3123 /* 5S */ 3124 rates[12] = min(rates[0], rate_info->target_power_48); 3125 /* 11L */ 3126 rates[13] = min(rates[0], rate_info->target_power_54); 3127 /* 11S */ 3128 rates[14] = min(rates[0], rate_info->target_power_54); 3129 3130 /* XR rates */ 3131 rates[15] = min(rates[0], rate_info->target_power_6to24); 3132 3133 /* CCK rates have different peak to average ratio 3134 * so we have to tweak their power so that gainf 3135 * correction works ok. For this we use OFDM to 3136 * CCK delta from eeprom */ 3137 if ((ee_mode == AR5K_EEPROM_MODE_11G) && 3138 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) 3139 for (i = 8; i <= 15; i++) 3140 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; 3141 3142 /* Now that we have all rates setup use table offset to 3143 * match the power range set by user with the power indices 3144 * on PCDAC/PDADC table */ 3145 for (i = 0; i < 16; i++) { 3146 rates[i] += ah->ah_txpower.txp_offset; 3147 /* Don't get out of bounds */ 3148 if (rates[i] > 63) 3149 rates[i] = 63; 3150 } 3151 3152 /* Min/max in 0.25dB units */ 3153 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; 3154 ah->ah_txpower.txp_cur_pwr = 2 * rates[0]; 3155 ah->ah_txpower.txp_ofdm = rates[7]; 3156 } 3157 3158 3159 /* 3160 * Set transmission power 3161 */ 3162 static int 3163 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3164 u8 txpower) 3165 { 3166 struct ath5k_rate_pcal_info rate_info; 3167 struct ieee80211_channel *curr_channel = ah->ah_current_channel; 3168 int ee_mode; 3169 u8 type; 3170 int ret; 3171 3172 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 3173 ATH5K_ERR(ah, "invalid tx power: %u\n", txpower); 3174 return -EINVAL; 3175 } 3176 3177 ee_mode = ath5k_eeprom_mode_from_channel(channel); 3178 if (ee_mode < 0) { 3179 ATH5K_ERR(ah, 3180 "invalid channel: %d\n", channel->center_freq); 3181 return -EINVAL; 3182 } 3183 3184 /* Initialize TX power table */ 3185 switch (ah->ah_radio) { 3186 case AR5K_RF5110: 3187 /* TODO */ 3188 return 0; 3189 case AR5K_RF5111: 3190 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 3191 break; 3192 case AR5K_RF5112: 3193 type = AR5K_PWRTABLE_LINEAR_PCDAC; 3194 break; 3195 case AR5K_RF2413: 3196 case AR5K_RF5413: 3197 case AR5K_RF2316: 3198 case AR5K_RF2317: 3199 case AR5K_RF2425: 3200 type = AR5K_PWRTABLE_PWR_TO_PDADC; 3201 break; 3202 default: 3203 return -EINVAL; 3204 } 3205 3206 /* 3207 * If we don't change channel/mode skip tx powertable calculation 3208 * and use the cached one. 3209 */ 3210 if (!ah->ah_txpower.txp_setup || 3211 (channel->hw_value != curr_channel->hw_value) || 3212 (channel->center_freq != curr_channel->center_freq)) { 3213 /* Reset TX power values */ 3214 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 3215 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 3216 3217 /* Calculate the powertable */ 3218 ret = ath5k_setup_channel_powertable(ah, channel, 3219 ee_mode, type); 3220 if (ret) 3221 return ret; 3222 } 3223 3224 /* Write table on hw */ 3225 ath5k_write_channel_powertable(ah, ee_mode, type); 3226 3227 /* Limit max power if we have a CTL available */ 3228 ath5k_get_max_ctl_power(ah, channel); 3229 3230 /* FIXME: Antenna reduction stuff */ 3231 3232 /* FIXME: Limit power on turbo modes */ 3233 3234 /* FIXME: TPC scale reduction */ 3235 3236 /* Get surrounding channels for per-rate power table 3237 * calibration */ 3238 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 3239 3240 /* Setup rate power table */ 3241 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 3242 3243 /* Write rate power table on hw */ 3244 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 3245 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 3246 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 3247 3248 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 3249 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 3250 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 3251 3252 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 3253 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 3254 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 3255 3256 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 3257 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 3258 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 3259 3260 /* FIXME: TPC support */ 3261 if (ah->ah_txpower.txp_tpc) { 3262 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 3263 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3264 3265 ath5k_hw_reg_write(ah, 3266 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 3267 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 3268 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 3269 AR5K_TPC); 3270 } else { 3271 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 3272 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 3273 } 3274 3275 return 0; 3276 } 3277 3278 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3279 { 3280 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER, 3281 "changing txpower to %d\n", txpower); 3282 3283 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); 3284 } 3285 3286 /*************\ 3287 Init function 3288 \*************/ 3289 3290 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 3291 u8 mode, bool fast) 3292 { 3293 struct ieee80211_channel *curr_channel; 3294 int ret, i; 3295 u32 phy_tst1; 3296 ret = 0; 3297 3298 /* 3299 * Sanity check for fast flag 3300 * Don't try fast channel change when changing modulation 3301 * mode/band. We check for chip compatibility on 3302 * ath5k_hw_reset. 3303 */ 3304 curr_channel = ah->ah_current_channel; 3305 if (fast && (channel->hw_value != curr_channel->hw_value)) 3306 return -EINVAL; 3307 3308 /* 3309 * On fast channel change we only set the synth parameters 3310 * while PHY is running, enable calibration and skip the rest. 3311 */ 3312 if (fast) { 3313 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3314 AR5K_PHY_RFBUS_REQ_REQUEST); 3315 for (i = 0; i < 100; i++) { 3316 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) 3317 break; 3318 udelay(5); 3319 } 3320 /* Failed */ 3321 if (i >= 100) 3322 return -EIO; 3323 3324 /* Set channel and wait for synth */ 3325 ret = ath5k_hw_channel(ah, channel); 3326 if (ret) 3327 return ret; 3328 3329 ath5k_hw_wait_for_synth(ah, channel); 3330 } 3331 3332 /* 3333 * Set TX power 3334 * 3335 * Note: We need to do that before we set 3336 * RF buffer settings on 5211/5212+ so that we 3337 * properly set curve indices. 3338 */ 3339 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ? 3340 ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER); 3341 if (ret) 3342 return ret; 3343 3344 /* Write OFDM timings on 5212*/ 3345 if (ah->ah_version == AR5K_AR5212 && 3346 channel->hw_value != AR5K_MODE_11B) { 3347 3348 ret = ath5k_hw_write_ofdm_timings(ah, channel); 3349 if (ret) 3350 return ret; 3351 3352 /* Spur info is available only from EEPROM versions 3353 * greater than 5.3, but the EEPROM routines will use 3354 * static values for older versions */ 3355 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) 3356 ath5k_hw_set_spur_mitigation_filter(ah, 3357 channel); 3358 } 3359 3360 /* If we used fast channel switching 3361 * we are done, release RF bus and 3362 * fire up NF calibration. 3363 * 3364 * Note: Only NF calibration due to 3365 * channel change, not AGC calibration 3366 * since AGC is still running ! 3367 */ 3368 if (fast) { 3369 /* 3370 * Release RF Bus grant 3371 */ 3372 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, 3373 AR5K_PHY_RFBUS_REQ_REQUEST); 3374 3375 /* 3376 * Start NF calibration 3377 */ 3378 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3379 AR5K_PHY_AGCCTL_NF); 3380 3381 return ret; 3382 } 3383 3384 /* 3385 * For 5210 we do all initialization using 3386 * initvals, so we don't have to modify 3387 * any settings (5210 also only supports 3388 * a/aturbo modes) 3389 */ 3390 if (ah->ah_version != AR5K_AR5210) { 3391 3392 /* 3393 * Write initial RF gain settings 3394 * This should work for both 5111/5112 3395 */ 3396 ret = ath5k_hw_rfgain_init(ah, channel->band); 3397 if (ret) 3398 return ret; 3399 3400 usleep_range(1000, 1500); 3401 3402 /* 3403 * Write RF buffer 3404 */ 3405 ret = ath5k_hw_rfregs_init(ah, channel, mode); 3406 if (ret) 3407 return ret; 3408 3409 /*Enable/disable 802.11b mode on 5111 3410 (enable 2111 frequency converter + CCK)*/ 3411 if (ah->ah_radio == AR5K_RF5111) { 3412 if (mode == AR5K_MODE_11B) 3413 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 3414 AR5K_TXCFG_B_MODE); 3415 else 3416 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 3417 AR5K_TXCFG_B_MODE); 3418 } 3419 3420 } else if (ah->ah_version == AR5K_AR5210) { 3421 usleep_range(1000, 1500); 3422 /* Disable phy and wait */ 3423 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 3424 usleep_range(1000, 1500); 3425 } 3426 3427 /* Set channel on PHY */ 3428 ret = ath5k_hw_channel(ah, channel); 3429 if (ret) 3430 return ret; 3431 3432 /* 3433 * Enable the PHY and wait until completion 3434 * This includes BaseBand and Synthesizer 3435 * activation. 3436 */ 3437 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 3438 3439 ath5k_hw_wait_for_synth(ah, channel); 3440 3441 /* 3442 * Perform ADC test to see if baseband is ready 3443 * Set tx hold and check adc test register 3444 */ 3445 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 3446 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 3447 for (i = 0; i <= 20; i++) { 3448 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 3449 break; 3450 usleep_range(200, 250); 3451 } 3452 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 3453 3454 /* 3455 * Start automatic gain control calibration 3456 * 3457 * During AGC calibration RX path is re-routed to 3458 * a power detector so we don't receive anything. 3459 * 3460 * This method is used to calibrate some static offsets 3461 * used together with on-the fly I/Q calibration (the 3462 * one performed via ath5k_hw_phy_calibrate), which doesn't 3463 * interrupt rx path. 3464 * 3465 * While rx path is re-routed to the power detector we also 3466 * start a noise floor calibration to measure the 3467 * card's noise floor (the noise we measure when we are not 3468 * transmitting or receiving anything). 3469 * 3470 * If we are in a noisy environment, AGC calibration may time 3471 * out and/or noise floor calibration might timeout. 3472 */ 3473 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 3474 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF); 3475 3476 /* At the same time start I/Q calibration for QAM constellation 3477 * -no need for CCK- */ 3478 ah->ah_iq_cal_needed = false; 3479 if (!(mode == AR5K_MODE_11B)) { 3480 ah->ah_iq_cal_needed = true; 3481 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 3482 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 3483 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 3484 AR5K_PHY_IQ_RUN); 3485 } 3486 3487 /* Wait for gain calibration to finish (we check for I/Q calibration 3488 * during ath5k_phy_calibrate) */ 3489 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 3490 AR5K_PHY_AGCCTL_CAL, 0, false)) { 3491 ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n", 3492 channel->center_freq); 3493 } 3494 3495 /* Restore antenna mode */ 3496 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 3497 3498 return ret; 3499 } 3500