1 /* 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 */ 18 19 /*************************************\ 20 * DMA and interrupt masking functions * 21 \*************************************/ 22 23 /* 24 * dma.c - DMA and interrupt masking functions 25 * 26 * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and 27 * handle queue setup for 5210 chipset (rest are handled on qcu.c). 28 * Also we setup interrupt mask register (IMR) and read the various iterrupt 29 * status registers (ISR). 30 * 31 * TODO: Handle SISR on 5211+ and introduce a function to return the queue 32 * number that resulted the interrupt. 33 */ 34 35 #include "ath5k.h" 36 #include "reg.h" 37 #include "debug.h" 38 #include "base.h" 39 40 /*********\ 41 * Receive * 42 \*********/ 43 44 /** 45 * ath5k_hw_start_rx_dma - Start DMA receive 46 * 47 * @ah: The &struct ath5k_hw 48 */ 49 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah) 50 { 51 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); 52 ath5k_hw_reg_read(ah, AR5K_CR); 53 } 54 55 /** 56 * ath5k_hw_stop_rx_dma - Stop DMA receive 57 * 58 * @ah: The &struct ath5k_hw 59 */ 60 int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) 61 { 62 unsigned int i; 63 64 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR); 65 66 /* 67 * It may take some time to disable the DMA receive unit 68 */ 69 for (i = 1000; i > 0 && 70 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0; 71 i--) 72 udelay(10); 73 74 return i ? 0 : -EBUSY; 75 } 76 77 /** 78 * ath5k_hw_get_rxdp - Get RX Descriptor's address 79 * 80 * @ah: The &struct ath5k_hw 81 */ 82 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah) 83 { 84 return ath5k_hw_reg_read(ah, AR5K_RXDP); 85 } 86 87 /** 88 * ath5k_hw_set_rxdp - Set RX Descriptor's address 89 * 90 * @ah: The &struct ath5k_hw 91 * @phys_addr: RX descriptor address 92 * 93 * XXX: Should we check if rx is enabled before setting rxdp ? 94 */ 95 void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) 96 { 97 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP); 98 } 99 100 101 /**********\ 102 * Transmit * 103 \**********/ 104 105 /** 106 * ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue 107 * 108 * @ah: The &struct ath5k_hw 109 * @queue: The hw queue number 110 * 111 * Start DMA transmit for a specific queue and since 5210 doesn't have 112 * QCU/DCU, set up queue parameters for 5210 here based on queue type (one 113 * queue for normal data and one queue for beacons). For queue setup 114 * on newer chips check out qcu.c. Returns -EINVAL if queue number is out 115 * of range or if queue is already disabled. 116 * 117 * NOTE: Must be called after setting up tx control descriptor for that 118 * queue (see below). 119 */ 120 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue) 121 { 122 u32 tx_queue; 123 124 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); 125 126 /* Return if queue is declared inactive */ 127 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) 128 return -EIO; 129 130 if (ah->ah_version == AR5K_AR5210) { 131 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); 132 133 /* 134 * Set the queue by type on 5210 135 */ 136 switch (ah->ah_txq[queue].tqi_type) { 137 case AR5K_TX_QUEUE_DATA: 138 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; 139 break; 140 case AR5K_TX_QUEUE_BEACON: 141 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; 142 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, 143 AR5K_BSR); 144 break; 145 case AR5K_TX_QUEUE_CAB: 146 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; 147 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V | 148 AR5K_BCR_BDMAE, AR5K_BSR); 149 break; 150 default: 151 return -EINVAL; 152 } 153 /* Start queue */ 154 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); 155 ath5k_hw_reg_read(ah, AR5K_CR); 156 } else { 157 /* Return if queue is disabled */ 158 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue)) 159 return -EIO; 160 161 /* Start queue */ 162 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue); 163 } 164 165 return 0; 166 } 167 168 /** 169 * ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue 170 * 171 * @ah: The &struct ath5k_hw 172 * @queue: The hw queue number 173 * 174 * Stop DMA transmit on a specific hw queue and drain queue so we don't 175 * have any pending frames. Returns -EBUSY if we still have pending frames, 176 * -EINVAL if queue number is out of range. 177 * 178 */ 179 int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue) 180 { 181 unsigned int i = 40; 182 u32 tx_queue, pending; 183 184 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); 185 186 /* Return if queue is declared inactive */ 187 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) 188 return -EIO; 189 190 if (ah->ah_version == AR5K_AR5210) { 191 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); 192 193 /* 194 * Set by queue type 195 */ 196 switch (ah->ah_txq[queue].tqi_type) { 197 case AR5K_TX_QUEUE_DATA: 198 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; 199 break; 200 case AR5K_TX_QUEUE_BEACON: 201 case AR5K_TX_QUEUE_CAB: 202 /* XXX Fix me... */ 203 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; 204 ath5k_hw_reg_write(ah, 0, AR5K_BSR); 205 break; 206 default: 207 return -EINVAL; 208 } 209 210 /* Stop queue */ 211 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); 212 ath5k_hw_reg_read(ah, AR5K_CR); 213 } else { 214 /* 215 * Schedule TX disable and wait until queue is empty 216 */ 217 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue); 218 219 /*Check for pending frames*/ 220 do { 221 pending = ath5k_hw_reg_read(ah, 222 AR5K_QUEUE_STATUS(queue)) & 223 AR5K_QCU_STS_FRMPENDCNT; 224 udelay(100); 225 } while (--i && pending); 226 227 /* For 2413+ order PCU to drop packets using 228 * QUIET mechanism */ 229 if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) && 230 pending){ 231 /* Set periodicity and duration */ 232 ath5k_hw_reg_write(ah, 233 AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)| 234 AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR), 235 AR5K_QUIET_CTL2); 236 237 /* Enable quiet period for current TSF */ 238 ath5k_hw_reg_write(ah, 239 AR5K_QUIET_CTL1_QT_EN | 240 AR5K_REG_SM(ath5k_hw_reg_read(ah, 241 AR5K_TSF_L32_5211) >> 10, 242 AR5K_QUIET_CTL1_NEXT_QT_TSF), 243 AR5K_QUIET_CTL1); 244 245 /* Force channel idle high */ 246 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, 247 AR5K_DIAG_SW_CHANEL_IDLE_HIGH); 248 249 /* Wait a while and disable mechanism */ 250 udelay(200); 251 AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1, 252 AR5K_QUIET_CTL1_QT_EN); 253 254 /* Re-check for pending frames */ 255 i = 40; 256 do { 257 pending = ath5k_hw_reg_read(ah, 258 AR5K_QUEUE_STATUS(queue)) & 259 AR5K_QCU_STS_FRMPENDCNT; 260 udelay(100); 261 } while (--i && pending); 262 263 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211, 264 AR5K_DIAG_SW_CHANEL_IDLE_HIGH); 265 } 266 267 /* Clear register */ 268 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD); 269 if (pending) 270 return -EBUSY; 271 } 272 273 /* TODO: Check for success on 5210 else return error */ 274 return 0; 275 } 276 277 /** 278 * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue 279 * 280 * @ah: The &struct ath5k_hw 281 * @queue: The hw queue number 282 * 283 * Get TX descriptor's address for a specific queue. For 5210 we ignore 284 * the queue number and use tx queue type since we only have 2 queues. 285 * We use TXDP0 for normal data queue and TXDP1 for beacon queue. 286 * For newer chips with QCU/DCU we just read the corresponding TXDP register. 287 * 288 * XXX: Is TXDP read and clear ? 289 */ 290 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue) 291 { 292 u16 tx_reg; 293 294 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); 295 296 /* 297 * Get the transmit queue descriptor pointer from the selected queue 298 */ 299 /*5210 doesn't have QCU*/ 300 if (ah->ah_version == AR5K_AR5210) { 301 switch (ah->ah_txq[queue].tqi_type) { 302 case AR5K_TX_QUEUE_DATA: 303 tx_reg = AR5K_NOQCU_TXDP0; 304 break; 305 case AR5K_TX_QUEUE_BEACON: 306 case AR5K_TX_QUEUE_CAB: 307 tx_reg = AR5K_NOQCU_TXDP1; 308 break; 309 default: 310 return 0xffffffff; 311 } 312 } else { 313 tx_reg = AR5K_QUEUE_TXDP(queue); 314 } 315 316 return ath5k_hw_reg_read(ah, tx_reg); 317 } 318 319 /** 320 * ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue 321 * 322 * @ah: The &struct ath5k_hw 323 * @queue: The hw queue number 324 * 325 * Set TX descriptor's address for a specific queue. For 5210 we ignore 326 * the queue number and we use tx queue type since we only have 2 queues 327 * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. 328 * For newer chips with QCU/DCU we just set the corresponding TXDP register. 329 * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still 330 * active. 331 */ 332 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) 333 { 334 u16 tx_reg; 335 336 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); 337 338 /* 339 * Set the transmit queue descriptor pointer register by type 340 * on 5210 341 */ 342 if (ah->ah_version == AR5K_AR5210) { 343 switch (ah->ah_txq[queue].tqi_type) { 344 case AR5K_TX_QUEUE_DATA: 345 tx_reg = AR5K_NOQCU_TXDP0; 346 break; 347 case AR5K_TX_QUEUE_BEACON: 348 case AR5K_TX_QUEUE_CAB: 349 tx_reg = AR5K_NOQCU_TXDP1; 350 break; 351 default: 352 return -EINVAL; 353 } 354 } else { 355 /* 356 * Set the transmit queue descriptor pointer for 357 * the selected queue on QCU for 5211+ 358 * (this won't work if the queue is still active) 359 */ 360 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) 361 return -EIO; 362 363 tx_reg = AR5K_QUEUE_TXDP(queue); 364 } 365 366 /* Set descriptor pointer */ 367 ath5k_hw_reg_write(ah, phys_addr, tx_reg); 368 369 return 0; 370 } 371 372 /** 373 * ath5k_hw_update_tx_triglevel - Update tx trigger level 374 * 375 * @ah: The &struct ath5k_hw 376 * @increase: Flag to force increase of trigger level 377 * 378 * This function increases/decreases the tx trigger level for the tx fifo 379 * buffer (aka FIFO threshold) that is used to indicate when PCU flushes 380 * the buffer and transmits it's data. Lowering this results sending small 381 * frames more quickly but can lead to tx underruns, raising it a lot can 382 * result other problems (i think bmiss is related). Right now we start with 383 * the lowest possible (64Bytes) and if we get tx underrun we increase it using 384 * the increase flag. Returns -EIO if we have have reached maximum/minimum. 385 * 386 * XXX: Link this with tx DMA size ? 387 * XXX: Use it to save interrupts ? 388 * TODO: Needs testing, i think it's related to bmiss... 389 */ 390 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase) 391 { 392 u32 trigger_level, imr; 393 int ret = -EIO; 394 395 /* 396 * Disable interrupts by setting the mask 397 */ 398 imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL); 399 400 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG), 401 AR5K_TXCFG_TXFULL); 402 403 if (!increase) { 404 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 405 goto done; 406 } else 407 trigger_level += 408 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); 409 410 /* 411 * Update trigger level on success 412 */ 413 if (ah->ah_version == AR5K_AR5210) 414 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL); 415 else 416 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, 417 AR5K_TXCFG_TXFULL, trigger_level); 418 419 ret = 0; 420 421 done: 422 /* 423 * Restore interrupt mask 424 */ 425 ath5k_hw_set_imr(ah, imr); 426 427 return ret; 428 } 429 430 /*******************\ 431 * Interrupt masking * 432 \*******************/ 433 434 /** 435 * ath5k_hw_is_intr_pending - Check if we have pending interrupts 436 * 437 * @ah: The &struct ath5k_hw 438 * 439 * Check if we have pending interrupts to process. Returns 1 if we 440 * have pending interrupts and 0 if we haven't. 441 */ 442 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah) 443 { 444 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0; 445 } 446 447 /** 448 * ath5k_hw_get_isr - Get interrupt status 449 * 450 * @ah: The @struct ath5k_hw 451 * @interrupt_mask: Driver's interrupt mask used to filter out 452 * interrupts in sw. 453 * 454 * This function is used inside our interrupt handler to determine the reason 455 * for the interrupt by reading Primary Interrupt Status Register. Returns an 456 * abstract interrupt status mask which is mostly ISR with some uncommon bits 457 * being mapped on some standard non hw-specific positions 458 * (check out &ath5k_int). 459 * 460 * NOTE: We use read-and-clear register, so after this function is called ISR 461 * is zeroed. 462 */ 463 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) 464 { 465 u32 data; 466 467 /* 468 * Read interrupt status from the Interrupt Status register 469 * on 5210 470 */ 471 if (ah->ah_version == AR5K_AR5210) { 472 data = ath5k_hw_reg_read(ah, AR5K_ISR); 473 if (unlikely(data == AR5K_INT_NOCARD)) { 474 *interrupt_mask = data; 475 return -ENODEV; 476 } 477 } else { 478 /* 479 * Read interrupt status from Interrupt 480 * Status Register shadow copy (Read And Clear) 481 * 482 * Note: PISR/SISR Not available on 5210 483 */ 484 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR); 485 if (unlikely(data == AR5K_INT_NOCARD)) { 486 *interrupt_mask = data; 487 return -ENODEV; 488 } 489 } 490 491 /* 492 * Get abstract interrupt mask (driver-compatible) 493 */ 494 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr; 495 496 if (ah->ah_version != AR5K_AR5210) { 497 u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2); 498 499 /*HIU = Host Interface Unit (PCI etc)*/ 500 if (unlikely(data & (AR5K_ISR_HIUERR))) 501 *interrupt_mask |= AR5K_INT_FATAL; 502 503 /*Beacon Not Ready*/ 504 if (unlikely(data & (AR5K_ISR_BNR))) 505 *interrupt_mask |= AR5K_INT_BNR; 506 507 if (unlikely(sisr2 & (AR5K_SISR2_SSERR | 508 AR5K_SISR2_DPERR | 509 AR5K_SISR2_MCABT))) 510 *interrupt_mask |= AR5K_INT_FATAL; 511 512 if (data & AR5K_ISR_TIM) 513 *interrupt_mask |= AR5K_INT_TIM; 514 515 if (data & AR5K_ISR_BCNMISC) { 516 if (sisr2 & AR5K_SISR2_TIM) 517 *interrupt_mask |= AR5K_INT_TIM; 518 if (sisr2 & AR5K_SISR2_DTIM) 519 *interrupt_mask |= AR5K_INT_DTIM; 520 if (sisr2 & AR5K_SISR2_DTIM_SYNC) 521 *interrupt_mask |= AR5K_INT_DTIM_SYNC; 522 if (sisr2 & AR5K_SISR2_BCN_TIMEOUT) 523 *interrupt_mask |= AR5K_INT_BCN_TIMEOUT; 524 if (sisr2 & AR5K_SISR2_CAB_TIMEOUT) 525 *interrupt_mask |= AR5K_INT_CAB_TIMEOUT; 526 } 527 528 if (data & AR5K_ISR_RXDOPPLER) 529 *interrupt_mask |= AR5K_INT_RX_DOPPLER; 530 if (data & AR5K_ISR_QCBRORN) { 531 *interrupt_mask |= AR5K_INT_QCBRORN; 532 ah->ah_txq_isr |= AR5K_REG_MS( 533 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), 534 AR5K_SISR3_QCBRORN); 535 } 536 if (data & AR5K_ISR_QCBRURN) { 537 *interrupt_mask |= AR5K_INT_QCBRURN; 538 ah->ah_txq_isr |= AR5K_REG_MS( 539 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), 540 AR5K_SISR3_QCBRURN); 541 } 542 if (data & AR5K_ISR_QTRIG) { 543 *interrupt_mask |= AR5K_INT_QTRIG; 544 ah->ah_txq_isr |= AR5K_REG_MS( 545 ath5k_hw_reg_read(ah, AR5K_RAC_SISR4), 546 AR5K_SISR4_QTRIG); 547 } 548 549 if (data & AR5K_ISR_TXOK) 550 ah->ah_txq_isr |= AR5K_REG_MS( 551 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0), 552 AR5K_SISR0_QCU_TXOK); 553 554 if (data & AR5K_ISR_TXDESC) 555 ah->ah_txq_isr |= AR5K_REG_MS( 556 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0), 557 AR5K_SISR0_QCU_TXDESC); 558 559 if (data & AR5K_ISR_TXERR) 560 ah->ah_txq_isr |= AR5K_REG_MS( 561 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1), 562 AR5K_SISR1_QCU_TXERR); 563 564 if (data & AR5K_ISR_TXEOL) 565 ah->ah_txq_isr |= AR5K_REG_MS( 566 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1), 567 AR5K_SISR1_QCU_TXEOL); 568 569 if (data & AR5K_ISR_TXURN) 570 ah->ah_txq_isr |= AR5K_REG_MS( 571 ath5k_hw_reg_read(ah, AR5K_RAC_SISR2), 572 AR5K_SISR2_QCU_TXURN); 573 } else { 574 if (unlikely(data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT 575 | AR5K_ISR_HIUERR | AR5K_ISR_DPERR))) 576 *interrupt_mask |= AR5K_INT_FATAL; 577 578 /* 579 * XXX: BMISS interrupts may occur after association. 580 * I found this on 5210 code but it needs testing. If this is 581 * true we should disable them before assoc and re-enable them 582 * after a successful assoc + some jiffies. 583 interrupt_mask &= ~AR5K_INT_BMISS; 584 */ 585 } 586 587 /* 588 * In case we didn't handle anything, 589 * print the register value. 590 */ 591 if (unlikely(*interrupt_mask == 0 && net_ratelimit())) 592 ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr); 593 594 return 0; 595 } 596 597 /** 598 * ath5k_hw_set_imr - Set interrupt mask 599 * 600 * @ah: The &struct ath5k_hw 601 * @new_mask: The new interrupt mask to be set 602 * 603 * Set the interrupt mask in hw to save interrupts. We do that by mapping 604 * ath5k_int bits to hw-specific bits to remove abstraction and writing 605 * Interrupt Mask Register. 606 */ 607 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask) 608 { 609 enum ath5k_int old_mask, int_mask; 610 611 old_mask = ah->ah_imr; 612 613 /* 614 * Disable card interrupts to prevent any race conditions 615 * (they will be re-enabled afterwards if AR5K_INT GLOBAL 616 * is set again on the new mask). 617 */ 618 if (old_mask & AR5K_INT_GLOBAL) { 619 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER); 620 ath5k_hw_reg_read(ah, AR5K_IER); 621 } 622 623 /* 624 * Add additional, chipset-dependent interrupt mask flags 625 * and write them to the IMR (interrupt mask register). 626 */ 627 int_mask = new_mask & AR5K_INT_COMMON; 628 629 if (ah->ah_version != AR5K_AR5210) { 630 /* Preserve per queue TXURN interrupt mask */ 631 u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2) 632 & AR5K_SIMR2_QCU_TXURN; 633 634 if (new_mask & AR5K_INT_FATAL) { 635 int_mask |= AR5K_IMR_HIUERR; 636 simr2 |= (AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR 637 | AR5K_SIMR2_DPERR); 638 } 639 640 /*Beacon Not Ready*/ 641 if (new_mask & AR5K_INT_BNR) 642 int_mask |= AR5K_INT_BNR; 643 644 if (new_mask & AR5K_INT_TIM) 645 int_mask |= AR5K_IMR_TIM; 646 647 if (new_mask & AR5K_INT_TIM) 648 simr2 |= AR5K_SISR2_TIM; 649 if (new_mask & AR5K_INT_DTIM) 650 simr2 |= AR5K_SISR2_DTIM; 651 if (new_mask & AR5K_INT_DTIM_SYNC) 652 simr2 |= AR5K_SISR2_DTIM_SYNC; 653 if (new_mask & AR5K_INT_BCN_TIMEOUT) 654 simr2 |= AR5K_SISR2_BCN_TIMEOUT; 655 if (new_mask & AR5K_INT_CAB_TIMEOUT) 656 simr2 |= AR5K_SISR2_CAB_TIMEOUT; 657 658 if (new_mask & AR5K_INT_RX_DOPPLER) 659 int_mask |= AR5K_IMR_RXDOPPLER; 660 661 /* Note: Per queue interrupt masks 662 * are set via reset_tx_queue (qcu.c) */ 663 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR); 664 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2); 665 666 } else { 667 if (new_mask & AR5K_INT_FATAL) 668 int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT 669 | AR5K_IMR_HIUERR | AR5K_IMR_DPERR); 670 671 ath5k_hw_reg_write(ah, int_mask, AR5K_IMR); 672 } 673 674 /* If RXNOFRM interrupt is masked disable it 675 * by setting AR5K_RXNOFRM to zero */ 676 if (!(new_mask & AR5K_INT_RXNOFRM)) 677 ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM); 678 679 /* Store new interrupt mask */ 680 ah->ah_imr = new_mask; 681 682 /* ..re-enable interrupts if AR5K_INT_GLOBAL is set */ 683 if (new_mask & AR5K_INT_GLOBAL) { 684 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER); 685 ath5k_hw_reg_read(ah, AR5K_IER); 686 } 687 688 return old_mask; 689 } 690 691