1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #include <linux/module.h> 44 #include <linux/delay.h> 45 #include <linux/hardirq.h> 46 #include <linux/if.h> 47 #include <linux/io.h> 48 #include <linux/netdevice.h> 49 #include <linux/cache.h> 50 #include <linux/pci.h> 51 #include <linux/ethtool.h> 52 #include <linux/uaccess.h> 53 54 #include <net/ieee80211_radiotap.h> 55 56 #include <asm/unaligned.h> 57 58 #include "base.h" 59 #include "reg.h" 60 #include "debug.h" 61 62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */ 63 static int modparam_nohwcrypt; 64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 66 67 static int modparam_all_channels; 68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); 69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); 70 71 72 /******************\ 73 * Internal defines * 74 \******************/ 75 76 /* Module info */ 77 MODULE_AUTHOR("Jiri Slaby"); 78 MODULE_AUTHOR("Nick Kossifidis"); 79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 81 MODULE_LICENSE("Dual BSD/GPL"); 82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)"); 83 84 85 /* Known PCI ids */ 86 static const struct pci_device_id ath5k_pci_id_table[] = { 87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ 88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ 89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ 90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ 91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ 92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ 93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ 94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ 95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */ 96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */ 97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */ 98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */ 99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */ 100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */ 101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ 102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ 103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ 104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ 105 { 0 } 106 }; 107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); 108 109 /* Known SREVs */ 110 static const struct ath5k_srev_name srev_names[] = { 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 147 }; 148 149 static const struct ieee80211_rate ath5k_rates[] = { 150 { .bitrate = 10, 151 .hw_value = ATH5K_RATE_CODE_1M, }, 152 { .bitrate = 20, 153 .hw_value = ATH5K_RATE_CODE_2M, 154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 155 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 156 { .bitrate = 55, 157 .hw_value = ATH5K_RATE_CODE_5_5M, 158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 159 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 160 { .bitrate = 110, 161 .hw_value = ATH5K_RATE_CODE_11M, 162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 163 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 164 { .bitrate = 60, 165 .hw_value = ATH5K_RATE_CODE_6M, 166 .flags = 0 }, 167 { .bitrate = 90, 168 .hw_value = ATH5K_RATE_CODE_9M, 169 .flags = 0 }, 170 { .bitrate = 120, 171 .hw_value = ATH5K_RATE_CODE_12M, 172 .flags = 0 }, 173 { .bitrate = 180, 174 .hw_value = ATH5K_RATE_CODE_18M, 175 .flags = 0 }, 176 { .bitrate = 240, 177 .hw_value = ATH5K_RATE_CODE_24M, 178 .flags = 0 }, 179 { .bitrate = 360, 180 .hw_value = ATH5K_RATE_CODE_36M, 181 .flags = 0 }, 182 { .bitrate = 480, 183 .hw_value = ATH5K_RATE_CODE_48M, 184 .flags = 0 }, 185 { .bitrate = 540, 186 .hw_value = ATH5K_RATE_CODE_54M, 187 .flags = 0 }, 188 /* XR missing */ 189 }; 190 191 /* 192 * Prototypes - PCI stack related functions 193 */ 194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev, 195 const struct pci_device_id *id); 196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev); 197 #ifdef CONFIG_PM 198 static int ath5k_pci_suspend(struct device *dev); 199 static int ath5k_pci_resume(struct device *dev); 200 201 SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume); 202 #define ATH5K_PM_OPS (&ath5k_pm_ops) 203 #else 204 #define ATH5K_PM_OPS NULL 205 #endif /* CONFIG_PM */ 206 207 static struct pci_driver ath5k_pci_driver = { 208 .name = KBUILD_MODNAME, 209 .id_table = ath5k_pci_id_table, 210 .probe = ath5k_pci_probe, 211 .remove = __devexit_p(ath5k_pci_remove), 212 .driver.pm = ATH5K_PM_OPS, 213 }; 214 215 216 217 /* 218 * Prototypes - MAC 802.11 stack related functions 219 */ 220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb); 221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 222 struct ath5k_txq *txq); 223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan); 224 static int ath5k_reset_wake(struct ath5k_softc *sc); 225 static int ath5k_start(struct ieee80211_hw *hw); 226 static void ath5k_stop(struct ieee80211_hw *hw); 227 static int ath5k_add_interface(struct ieee80211_hw *hw, 228 struct ieee80211_if_init_conf *conf); 229 static void ath5k_remove_interface(struct ieee80211_hw *hw, 230 struct ieee80211_if_init_conf *conf); 231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed); 232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, 233 int mc_count, struct dev_addr_list *mc_list); 234 static void ath5k_configure_filter(struct ieee80211_hw *hw, 235 unsigned int changed_flags, 236 unsigned int *new_flags, 237 u64 multicast); 238 static int ath5k_set_key(struct ieee80211_hw *hw, 239 enum set_key_cmd cmd, 240 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 241 struct ieee80211_key_conf *key); 242 static int ath5k_get_stats(struct ieee80211_hw *hw, 243 struct ieee80211_low_level_stats *stats); 244 static int ath5k_get_tx_stats(struct ieee80211_hw *hw, 245 struct ieee80211_tx_queue_stats *stats); 246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw); 247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf); 248 static void ath5k_reset_tsf(struct ieee80211_hw *hw); 249 static int ath5k_beacon_update(struct ieee80211_hw *hw, 250 struct ieee80211_vif *vif); 251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw, 252 struct ieee80211_vif *vif, 253 struct ieee80211_bss_conf *bss_conf, 254 u32 changes); 255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw); 256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw); 257 258 static const struct ieee80211_ops ath5k_hw_ops = { 259 .tx = ath5k_tx, 260 .start = ath5k_start, 261 .stop = ath5k_stop, 262 .add_interface = ath5k_add_interface, 263 .remove_interface = ath5k_remove_interface, 264 .config = ath5k_config, 265 .prepare_multicast = ath5k_prepare_multicast, 266 .configure_filter = ath5k_configure_filter, 267 .set_key = ath5k_set_key, 268 .get_stats = ath5k_get_stats, 269 .conf_tx = NULL, 270 .get_tx_stats = ath5k_get_tx_stats, 271 .get_tsf = ath5k_get_tsf, 272 .set_tsf = ath5k_set_tsf, 273 .reset_tsf = ath5k_reset_tsf, 274 .bss_info_changed = ath5k_bss_info_changed, 275 .sw_scan_start = ath5k_sw_scan_start, 276 .sw_scan_complete = ath5k_sw_scan_complete, 277 }; 278 279 /* 280 * Prototypes - Internal functions 281 */ 282 /* Attach detach */ 283 static int ath5k_attach(struct pci_dev *pdev, 284 struct ieee80211_hw *hw); 285 static void ath5k_detach(struct pci_dev *pdev, 286 struct ieee80211_hw *hw); 287 /* Channel/mode setup */ 288 static inline short ath5k_ieee2mhz(short chan); 289 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah, 290 struct ieee80211_channel *channels, 291 unsigned int mode, 292 unsigned int max); 293 static int ath5k_setup_bands(struct ieee80211_hw *hw); 294 static int ath5k_chan_set(struct ath5k_softc *sc, 295 struct ieee80211_channel *chan); 296 static void ath5k_setcurmode(struct ath5k_softc *sc, 297 unsigned int mode); 298 static void ath5k_mode_setup(struct ath5k_softc *sc); 299 300 /* Descriptor setup */ 301 static int ath5k_desc_alloc(struct ath5k_softc *sc, 302 struct pci_dev *pdev); 303 static void ath5k_desc_free(struct ath5k_softc *sc, 304 struct pci_dev *pdev); 305 /* Buffers setup */ 306 static int ath5k_rxbuf_setup(struct ath5k_softc *sc, 307 struct ath5k_buf *bf); 308 static int ath5k_txbuf_setup(struct ath5k_softc *sc, 309 struct ath5k_buf *bf, 310 struct ath5k_txq *txq); 311 static inline void ath5k_txbuf_free(struct ath5k_softc *sc, 312 struct ath5k_buf *bf) 313 { 314 BUG_ON(!bf); 315 if (!bf->skb) 316 return; 317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len, 318 PCI_DMA_TODEVICE); 319 dev_kfree_skb_any(bf->skb); 320 bf->skb = NULL; 321 } 322 323 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc, 324 struct ath5k_buf *bf) 325 { 326 struct ath5k_hw *ah = sc->ah; 327 struct ath_common *common = ath5k_hw_common(ah); 328 329 BUG_ON(!bf); 330 if (!bf->skb) 331 return; 332 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize, 333 PCI_DMA_FROMDEVICE); 334 dev_kfree_skb_any(bf->skb); 335 bf->skb = NULL; 336 } 337 338 339 /* Queues setup */ 340 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc, 341 int qtype, int subtype); 342 static int ath5k_beaconq_setup(struct ath5k_hw *ah); 343 static int ath5k_beaconq_config(struct ath5k_softc *sc); 344 static void ath5k_txq_drainq(struct ath5k_softc *sc, 345 struct ath5k_txq *txq); 346 static void ath5k_txq_cleanup(struct ath5k_softc *sc); 347 static void ath5k_txq_release(struct ath5k_softc *sc); 348 /* Rx handling */ 349 static int ath5k_rx_start(struct ath5k_softc *sc); 350 static void ath5k_rx_stop(struct ath5k_softc *sc); 351 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc, 352 struct ath5k_desc *ds, 353 struct sk_buff *skb, 354 struct ath5k_rx_status *rs); 355 static void ath5k_tasklet_rx(unsigned long data); 356 /* Tx handling */ 357 static void ath5k_tx_processq(struct ath5k_softc *sc, 358 struct ath5k_txq *txq); 359 static void ath5k_tasklet_tx(unsigned long data); 360 /* Beacon handling */ 361 static int ath5k_beacon_setup(struct ath5k_softc *sc, 362 struct ath5k_buf *bf); 363 static void ath5k_beacon_send(struct ath5k_softc *sc); 364 static void ath5k_beacon_config(struct ath5k_softc *sc); 365 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 366 static void ath5k_tasklet_beacon(unsigned long data); 367 368 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 369 { 370 u64 tsf = ath5k_hw_get_tsf64(ah); 371 372 if ((tsf & 0x7fff) < rstamp) 373 tsf -= 0x8000; 374 375 return (tsf & ~0x7fff) | rstamp; 376 } 377 378 /* Interrupt handling */ 379 static int ath5k_init(struct ath5k_softc *sc); 380 static int ath5k_stop_locked(struct ath5k_softc *sc); 381 static int ath5k_stop_hw(struct ath5k_softc *sc); 382 static irqreturn_t ath5k_intr(int irq, void *dev_id); 383 static void ath5k_tasklet_reset(unsigned long data); 384 385 static void ath5k_tasklet_calibrate(unsigned long data); 386 387 /* 388 * Module init/exit functions 389 */ 390 static int __init 391 init_ath5k_pci(void) 392 { 393 int ret; 394 395 ath5k_debug_init(); 396 397 ret = pci_register_driver(&ath5k_pci_driver); 398 if (ret) { 399 printk(KERN_ERR "ath5k_pci: can't register pci driver\n"); 400 return ret; 401 } 402 403 return 0; 404 } 405 406 static void __exit 407 exit_ath5k_pci(void) 408 { 409 pci_unregister_driver(&ath5k_pci_driver); 410 411 ath5k_debug_finish(); 412 } 413 414 module_init(init_ath5k_pci); 415 module_exit(exit_ath5k_pci); 416 417 418 /********************\ 419 * PCI Initialization * 420 \********************/ 421 422 static const char * 423 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 424 { 425 const char *name = "xxxxx"; 426 unsigned int i; 427 428 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 429 if (srev_names[i].sr_type != type) 430 continue; 431 432 if ((val & 0xf0) == srev_names[i].sr_val) 433 name = srev_names[i].sr_name; 434 435 if ((val & 0xff) == srev_names[i].sr_val) { 436 name = srev_names[i].sr_name; 437 break; 438 } 439 } 440 441 return name; 442 } 443 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 444 { 445 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 446 return ath5k_hw_reg_read(ah, reg_offset); 447 } 448 449 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 450 { 451 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 452 ath5k_hw_reg_write(ah, val, reg_offset); 453 } 454 455 static const struct ath_ops ath5k_common_ops = { 456 .read = ath5k_ioread32, 457 .write = ath5k_iowrite32, 458 }; 459 460 static int __devinit 461 ath5k_pci_probe(struct pci_dev *pdev, 462 const struct pci_device_id *id) 463 { 464 void __iomem *mem; 465 struct ath5k_softc *sc; 466 struct ath_common *common; 467 struct ieee80211_hw *hw; 468 int ret; 469 u8 csz; 470 471 ret = pci_enable_device(pdev); 472 if (ret) { 473 dev_err(&pdev->dev, "can't enable device\n"); 474 goto err; 475 } 476 477 /* XXX 32-bit addressing only */ 478 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 479 if (ret) { 480 dev_err(&pdev->dev, "32-bit DMA not available\n"); 481 goto err_dis; 482 } 483 484 /* 485 * Cache line size is used to size and align various 486 * structures used to communicate with the hardware. 487 */ 488 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 489 if (csz == 0) { 490 /* 491 * Linux 2.4.18 (at least) writes the cache line size 492 * register as a 16-bit wide register which is wrong. 493 * We must have this setup properly for rx buffer 494 * DMA to work so force a reasonable value here if it 495 * comes up zero. 496 */ 497 csz = L1_CACHE_BYTES >> 2; 498 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 499 } 500 /* 501 * The default setting of latency timer yields poor results, 502 * set it to the value used by other systems. It may be worth 503 * tweaking this setting more. 504 */ 505 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 506 507 /* Enable bus mastering */ 508 pci_set_master(pdev); 509 510 /* 511 * Disable the RETRY_TIMEOUT register (0x41) to keep 512 * PCI Tx retries from interfering with C3 CPU state. 513 */ 514 pci_write_config_byte(pdev, 0x41, 0); 515 516 ret = pci_request_region(pdev, 0, "ath5k"); 517 if (ret) { 518 dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); 519 goto err_dis; 520 } 521 522 mem = pci_iomap(pdev, 0, 0); 523 if (!mem) { 524 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; 525 ret = -EIO; 526 goto err_reg; 527 } 528 529 /* 530 * Allocate hw (mac80211 main struct) 531 * and hw->priv (driver private data) 532 */ 533 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops); 534 if (hw == NULL) { 535 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); 536 ret = -ENOMEM; 537 goto err_map; 538 } 539 540 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); 541 542 /* Initialize driver private data */ 543 SET_IEEE80211_DEV(hw, &pdev->dev); 544 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 545 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 546 IEEE80211_HW_SIGNAL_DBM | 547 IEEE80211_HW_NOISE_DBM; 548 549 hw->wiphy->interface_modes = 550 BIT(NL80211_IFTYPE_AP) | 551 BIT(NL80211_IFTYPE_STATION) | 552 BIT(NL80211_IFTYPE_ADHOC) | 553 BIT(NL80211_IFTYPE_MESH_POINT); 554 555 hw->extra_tx_headroom = 2; 556 hw->channel_change_time = 5000; 557 sc = hw->priv; 558 sc->hw = hw; 559 sc->pdev = pdev; 560 561 ath5k_debug_init_device(sc); 562 563 /* 564 * Mark the device as detached to avoid processing 565 * interrupts until setup is complete. 566 */ 567 __set_bit(ATH_STAT_INVALID, sc->status); 568 569 sc->iobase = mem; /* So we can unmap it on detach */ 570 sc->opmode = NL80211_IFTYPE_STATION; 571 sc->bintval = 1000; 572 mutex_init(&sc->lock); 573 spin_lock_init(&sc->rxbuflock); 574 spin_lock_init(&sc->txbuflock); 575 spin_lock_init(&sc->block); 576 577 /* Set private data */ 578 pci_set_drvdata(pdev, hw); 579 580 /* Setup interrupt handler */ 581 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 582 if (ret) { 583 ATH5K_ERR(sc, "request_irq failed\n"); 584 goto err_free; 585 } 586 587 /*If we passed the test malloc a ath5k_hw struct*/ 588 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL); 589 if (!sc->ah) { 590 ret = -ENOMEM; 591 ATH5K_ERR(sc, "out of memory\n"); 592 goto err_irq; 593 } 594 595 sc->ah->ah_sc = sc; 596 sc->ah->ah_iobase = sc->iobase; 597 common = ath5k_hw_common(sc->ah); 598 common->ops = &ath5k_common_ops; 599 common->ah = sc->ah; 600 common->hw = hw; 601 common->cachelsz = csz << 2; /* convert to bytes */ 602 603 /* Initialize device */ 604 ret = ath5k_hw_attach(sc); 605 if (ret) { 606 goto err_free_ah; 607 } 608 609 /* set up multi-rate retry capabilities */ 610 if (sc->ah->ah_version == AR5K_AR5212) { 611 hw->max_rates = 4; 612 hw->max_rate_tries = 11; 613 } 614 615 /* Finish private driver data initialization */ 616 ret = ath5k_attach(pdev, hw); 617 if (ret) 618 goto err_ah; 619 620 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 621 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), 622 sc->ah->ah_mac_srev, 623 sc->ah->ah_phy_revision); 624 625 if (!sc->ah->ah_single_chip) { 626 /* Single chip radio (!RF5111) */ 627 if (sc->ah->ah_radio_5ghz_revision && 628 !sc->ah->ah_radio_2ghz_revision) { 629 /* No 5GHz support -> report 2GHz radio */ 630 if (!test_bit(AR5K_MODE_11A, 631 sc->ah->ah_capabilities.cap_mode)) { 632 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 633 ath5k_chip_name(AR5K_VERSION_RAD, 634 sc->ah->ah_radio_5ghz_revision), 635 sc->ah->ah_radio_5ghz_revision); 636 /* No 2GHz support (5110 and some 637 * 5Ghz only cards) -> report 5Ghz radio */ 638 } else if (!test_bit(AR5K_MODE_11B, 639 sc->ah->ah_capabilities.cap_mode)) { 640 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 641 ath5k_chip_name(AR5K_VERSION_RAD, 642 sc->ah->ah_radio_5ghz_revision), 643 sc->ah->ah_radio_5ghz_revision); 644 /* Multiband radio */ 645 } else { 646 ATH5K_INFO(sc, "RF%s multiband radio found" 647 " (0x%x)\n", 648 ath5k_chip_name(AR5K_VERSION_RAD, 649 sc->ah->ah_radio_5ghz_revision), 650 sc->ah->ah_radio_5ghz_revision); 651 } 652 } 653 /* Multi chip radio (RF5111 - RF2111) -> 654 * report both 2GHz/5GHz radios */ 655 else if (sc->ah->ah_radio_5ghz_revision && 656 sc->ah->ah_radio_2ghz_revision){ 657 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 658 ath5k_chip_name(AR5K_VERSION_RAD, 659 sc->ah->ah_radio_5ghz_revision), 660 sc->ah->ah_radio_5ghz_revision); 661 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 662 ath5k_chip_name(AR5K_VERSION_RAD, 663 sc->ah->ah_radio_2ghz_revision), 664 sc->ah->ah_radio_2ghz_revision); 665 } 666 } 667 668 669 /* ready to process interrupts */ 670 __clear_bit(ATH_STAT_INVALID, sc->status); 671 672 return 0; 673 err_ah: 674 ath5k_hw_detach(sc->ah); 675 err_irq: 676 free_irq(pdev->irq, sc); 677 err_free_ah: 678 kfree(sc->ah); 679 err_free: 680 ieee80211_free_hw(hw); 681 err_map: 682 pci_iounmap(pdev, mem); 683 err_reg: 684 pci_release_region(pdev, 0); 685 err_dis: 686 pci_disable_device(pdev); 687 err: 688 return ret; 689 } 690 691 static void __devexit 692 ath5k_pci_remove(struct pci_dev *pdev) 693 { 694 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 695 struct ath5k_softc *sc = hw->priv; 696 697 ath5k_debug_finish_device(sc); 698 ath5k_detach(pdev, hw); 699 ath5k_hw_detach(sc->ah); 700 kfree(sc->ah); 701 free_irq(pdev->irq, sc); 702 pci_iounmap(pdev, sc->iobase); 703 pci_release_region(pdev, 0); 704 pci_disable_device(pdev); 705 ieee80211_free_hw(hw); 706 } 707 708 #ifdef CONFIG_PM 709 static int ath5k_pci_suspend(struct device *dev) 710 { 711 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev)); 712 struct ath5k_softc *sc = hw->priv; 713 714 ath5k_led_off(sc); 715 return 0; 716 } 717 718 static int ath5k_pci_resume(struct device *dev) 719 { 720 struct pci_dev *pdev = to_pci_dev(dev); 721 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 722 struct ath5k_softc *sc = hw->priv; 723 724 /* 725 * Suspend/Resume resets the PCI configuration space, so we have to 726 * re-disable the RETRY_TIMEOUT register (0x41) to keep 727 * PCI Tx retries from interfering with C3 CPU state 728 */ 729 pci_write_config_byte(pdev, 0x41, 0); 730 731 ath5k_led_enable(sc); 732 return 0; 733 } 734 #endif /* CONFIG_PM */ 735 736 737 /***********************\ 738 * Driver Initialization * 739 \***********************/ 740 741 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 742 { 743 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 744 struct ath5k_softc *sc = hw->priv; 745 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah); 746 747 return ath_reg_notifier_apply(wiphy, request, regulatory); 748 } 749 750 static int 751 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw) 752 { 753 struct ath5k_softc *sc = hw->priv; 754 struct ath5k_hw *ah = sc->ah; 755 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 756 u8 mac[ETH_ALEN] = {}; 757 int ret; 758 759 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device); 760 761 /* 762 * Check if the MAC has multi-rate retry support. 763 * We do this by trying to setup a fake extended 764 * descriptor. MAC's that don't have support will 765 * return false w/o doing anything. MAC's that do 766 * support it will return true w/o doing anything. 767 */ 768 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); 769 if (ret < 0) 770 goto err; 771 if (ret > 0) 772 __set_bit(ATH_STAT_MRRETRY, sc->status); 773 774 /* 775 * Collect the channel list. The 802.11 layer 776 * is resposible for filtering this list based 777 * on settings like the phy mode and regulatory 778 * domain restrictions. 779 */ 780 ret = ath5k_setup_bands(hw); 781 if (ret) { 782 ATH5K_ERR(sc, "can't get channels\n"); 783 goto err; 784 } 785 786 /* NB: setup here so ath5k_rate_update is happy */ 787 if (test_bit(AR5K_MODE_11A, ah->ah_modes)) 788 ath5k_setcurmode(sc, AR5K_MODE_11A); 789 else 790 ath5k_setcurmode(sc, AR5K_MODE_11B); 791 792 /* 793 * Allocate tx+rx descriptors and populate the lists. 794 */ 795 ret = ath5k_desc_alloc(sc, pdev); 796 if (ret) { 797 ATH5K_ERR(sc, "can't allocate descriptors\n"); 798 goto err; 799 } 800 801 /* 802 * Allocate hardware transmit queues: one queue for 803 * beacon frames and one data queue for each QoS 804 * priority. Note that hw functions handle reseting 805 * these queues at the needed time. 806 */ 807 ret = ath5k_beaconq_setup(ah); 808 if (ret < 0) { 809 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); 810 goto err_desc; 811 } 812 sc->bhalq = ret; 813 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); 814 if (IS_ERR(sc->cabq)) { 815 ATH5K_ERR(sc, "can't setup cab queue\n"); 816 ret = PTR_ERR(sc->cabq); 817 goto err_bhal; 818 } 819 820 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 821 if (IS_ERR(sc->txq)) { 822 ATH5K_ERR(sc, "can't setup xmit queue\n"); 823 ret = PTR_ERR(sc->txq); 824 goto err_queues; 825 } 826 827 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 828 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 829 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc); 830 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); 831 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); 832 833 ret = ath5k_eeprom_read_mac(ah, mac); 834 if (ret) { 835 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n", 836 sc->pdev->device); 837 goto err_queues; 838 } 839 840 SET_IEEE80211_PERM_ADDR(hw, mac); 841 /* All MAC address bits matter for ACKs */ 842 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); 843 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); 844 845 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 846 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 847 if (ret) { 848 ATH5K_ERR(sc, "can't initialize regulatory system\n"); 849 goto err_queues; 850 } 851 852 ret = ieee80211_register_hw(hw); 853 if (ret) { 854 ATH5K_ERR(sc, "can't register ieee80211 hw\n"); 855 goto err_queues; 856 } 857 858 if (!ath_is_world_regd(regulatory)) 859 regulatory_hint(hw->wiphy, regulatory->alpha2); 860 861 ath5k_init_leds(sc); 862 863 return 0; 864 err_queues: 865 ath5k_txq_release(sc); 866 err_bhal: 867 ath5k_hw_release_tx_queue(ah, sc->bhalq); 868 err_desc: 869 ath5k_desc_free(sc, pdev); 870 err: 871 return ret; 872 } 873 874 static void 875 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw) 876 { 877 struct ath5k_softc *sc = hw->priv; 878 879 /* 880 * NB: the order of these is important: 881 * o call the 802.11 layer before detaching ath5k_hw to 882 * insure callbacks into the driver to delete global 883 * key cache entries can be handled 884 * o reclaim the tx queue data structures after calling 885 * the 802.11 layer as we'll get called back to reclaim 886 * node state and potentially want to use them 887 * o to cleanup the tx queues the hal is called, so detach 888 * it last 889 * XXX: ??? detach ath5k_hw ??? 890 * Other than that, it's straightforward... 891 */ 892 ieee80211_unregister_hw(hw); 893 ath5k_desc_free(sc, pdev); 894 ath5k_txq_release(sc); 895 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 896 ath5k_unregister_leds(sc); 897 898 /* 899 * NB: can't reclaim these until after ieee80211_ifdetach 900 * returns because we'll get called back to reclaim node 901 * state and potentially want to use them. 902 */ 903 } 904 905 906 907 908 /********************\ 909 * Channel/mode setup * 910 \********************/ 911 912 /* 913 * Convert IEEE channel number to MHz frequency. 914 */ 915 static inline short 916 ath5k_ieee2mhz(short chan) 917 { 918 if (chan <= 14 || chan >= 27) 919 return ieee80211chan2mhz(chan); 920 else 921 return 2212 + chan * 20; 922 } 923 924 /* 925 * Returns true for the channel numbers used without all_channels modparam. 926 */ 927 static bool ath5k_is_standard_channel(short chan) 928 { 929 return ((chan <= 14) || 930 /* UNII 1,2 */ 931 ((chan & 3) == 0 && chan >= 36 && chan <= 64) || 932 /* midband */ 933 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 934 /* UNII-3 */ 935 ((chan & 3) == 1 && chan >= 149 && chan <= 165)); 936 } 937 938 static unsigned int 939 ath5k_copy_channels(struct ath5k_hw *ah, 940 struct ieee80211_channel *channels, 941 unsigned int mode, 942 unsigned int max) 943 { 944 unsigned int i, count, size, chfreq, freq, ch; 945 946 if (!test_bit(mode, ah->ah_modes)) 947 return 0; 948 949 switch (mode) { 950 case AR5K_MODE_11A: 951 case AR5K_MODE_11A_TURBO: 952 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 953 size = 220 ; 954 chfreq = CHANNEL_5GHZ; 955 break; 956 case AR5K_MODE_11B: 957 case AR5K_MODE_11G: 958 case AR5K_MODE_11G_TURBO: 959 size = 26; 960 chfreq = CHANNEL_2GHZ; 961 break; 962 default: 963 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); 964 return 0; 965 } 966 967 for (i = 0, count = 0; i < size && max > 0; i++) { 968 ch = i + 1 ; 969 freq = ath5k_ieee2mhz(ch); 970 971 /* Check if channel is supported by the chipset */ 972 if (!ath5k_channel_ok(ah, freq, chfreq)) 973 continue; 974 975 if (!modparam_all_channels && !ath5k_is_standard_channel(ch)) 976 continue; 977 978 /* Write channel info and increment counter */ 979 channels[count].center_freq = freq; 980 channels[count].band = (chfreq == CHANNEL_2GHZ) ? 981 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; 982 switch (mode) { 983 case AR5K_MODE_11A: 984 case AR5K_MODE_11G: 985 channels[count].hw_value = chfreq | CHANNEL_OFDM; 986 break; 987 case AR5K_MODE_11A_TURBO: 988 case AR5K_MODE_11G_TURBO: 989 channels[count].hw_value = chfreq | 990 CHANNEL_OFDM | CHANNEL_TURBO; 991 break; 992 case AR5K_MODE_11B: 993 channels[count].hw_value = CHANNEL_B; 994 } 995 996 count++; 997 max--; 998 } 999 1000 return count; 1001 } 1002 1003 static void 1004 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) 1005 { 1006 u8 i; 1007 1008 for (i = 0; i < AR5K_MAX_RATES; i++) 1009 sc->rate_idx[b->band][i] = -1; 1010 1011 for (i = 0; i < b->n_bitrates; i++) { 1012 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; 1013 if (b->bitrates[i].hw_value_short) 1014 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 1015 } 1016 } 1017 1018 static int 1019 ath5k_setup_bands(struct ieee80211_hw *hw) 1020 { 1021 struct ath5k_softc *sc = hw->priv; 1022 struct ath5k_hw *ah = sc->ah; 1023 struct ieee80211_supported_band *sband; 1024 int max_c, count_c = 0; 1025 int i; 1026 1027 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); 1028 max_c = ARRAY_SIZE(sc->channels); 1029 1030 /* 2GHz band */ 1031 sband = &sc->sbands[IEEE80211_BAND_2GHZ]; 1032 sband->band = IEEE80211_BAND_2GHZ; 1033 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; 1034 1035 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { 1036 /* G mode */ 1037 memcpy(sband->bitrates, &ath5k_rates[0], 1038 sizeof(struct ieee80211_rate) * 12); 1039 sband->n_bitrates = 12; 1040 1041 sband->channels = sc->channels; 1042 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1043 AR5K_MODE_11G, max_c); 1044 1045 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 1046 count_c = sband->n_channels; 1047 max_c -= count_c; 1048 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { 1049 /* B mode */ 1050 memcpy(sband->bitrates, &ath5k_rates[0], 1051 sizeof(struct ieee80211_rate) * 4); 1052 sband->n_bitrates = 4; 1053 1054 /* 5211 only supports B rates and uses 4bit rate codes 1055 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 1056 * fix them up here: 1057 */ 1058 if (ah->ah_version == AR5K_AR5211) { 1059 for (i = 0; i < 4; i++) { 1060 sband->bitrates[i].hw_value = 1061 sband->bitrates[i].hw_value & 0xF; 1062 sband->bitrates[i].hw_value_short = 1063 sband->bitrates[i].hw_value_short & 0xF; 1064 } 1065 } 1066 1067 sband->channels = sc->channels; 1068 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1069 AR5K_MODE_11B, max_c); 1070 1071 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 1072 count_c = sband->n_channels; 1073 max_c -= count_c; 1074 } 1075 ath5k_setup_rate_idx(sc, sband); 1076 1077 /* 5GHz band, A mode */ 1078 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { 1079 sband = &sc->sbands[IEEE80211_BAND_5GHZ]; 1080 sband->band = IEEE80211_BAND_5GHZ; 1081 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; 1082 1083 memcpy(sband->bitrates, &ath5k_rates[4], 1084 sizeof(struct ieee80211_rate) * 8); 1085 sband->n_bitrates = 8; 1086 1087 sband->channels = &sc->channels[count_c]; 1088 sband->n_channels = ath5k_copy_channels(ah, sband->channels, 1089 AR5K_MODE_11A, max_c); 1090 1091 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 1092 } 1093 ath5k_setup_rate_idx(sc, sband); 1094 1095 ath5k_debug_dump_bands(sc); 1096 1097 return 0; 1098 } 1099 1100 /* 1101 * Set/change channels. We always reset the chip. 1102 * To accomplish this we must first cleanup any pending DMA, 1103 * then restart stuff after a la ath5k_init. 1104 * 1105 * Called with sc->lock. 1106 */ 1107 static int 1108 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 1109 { 1110 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n", 1111 sc->curchan->center_freq, chan->center_freq); 1112 1113 /* 1114 * To switch channels clear any pending DMA operations; 1115 * wait long enough for the RX fifo to drain, reset the 1116 * hardware at the new frequency, and then re-enable 1117 * the relevant bits of the h/w. 1118 */ 1119 return ath5k_reset(sc, chan); 1120 } 1121 1122 static void 1123 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) 1124 { 1125 sc->curmode = mode; 1126 1127 if (mode == AR5K_MODE_11A) { 1128 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ]; 1129 } else { 1130 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ]; 1131 } 1132 } 1133 1134 static void 1135 ath5k_mode_setup(struct ath5k_softc *sc) 1136 { 1137 struct ath5k_hw *ah = sc->ah; 1138 u32 rfilt; 1139 1140 ah->ah_op_mode = sc->opmode; 1141 1142 /* configure rx filter */ 1143 rfilt = sc->filter_flags; 1144 ath5k_hw_set_rx_filter(ah, rfilt); 1145 1146 if (ath5k_hw_hasbssidmask(ah)) 1147 ath5k_hw_set_bssid_mask(ah, sc->bssidmask); 1148 1149 /* configure operational mode */ 1150 ath5k_hw_set_opmode(ah); 1151 1152 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 1153 } 1154 1155 static inline int 1156 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) 1157 { 1158 int rix; 1159 1160 /* return base rate on errors */ 1161 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 1162 "hw_rix out of bounds: %x\n", hw_rix)) 1163 return 0; 1164 1165 rix = sc->rate_idx[sc->curband->band][hw_rix]; 1166 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 1167 rix = 0; 1168 1169 return rix; 1170 } 1171 1172 /***************\ 1173 * Buffers setup * 1174 \***************/ 1175 1176 static 1177 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) 1178 { 1179 struct ath_common *common = ath5k_hw_common(sc->ah); 1180 struct sk_buff *skb; 1181 1182 /* 1183 * Allocate buffer with headroom_needed space for the 1184 * fake physical layer header at the start. 1185 */ 1186 skb = ath_rxbuf_alloc(common, 1187 common->rx_bufsize + common->cachelsz - 1, 1188 GFP_ATOMIC); 1189 1190 if (!skb) { 1191 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", 1192 common->rx_bufsize + common->cachelsz - 1); 1193 return NULL; 1194 } 1195 1196 *skb_addr = pci_map_single(sc->pdev, 1197 skb->data, common->rx_bufsize, 1198 PCI_DMA_FROMDEVICE); 1199 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) { 1200 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); 1201 dev_kfree_skb(skb); 1202 return NULL; 1203 } 1204 return skb; 1205 } 1206 1207 static int 1208 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 1209 { 1210 struct ath5k_hw *ah = sc->ah; 1211 struct sk_buff *skb = bf->skb; 1212 struct ath5k_desc *ds; 1213 1214 if (!skb) { 1215 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); 1216 if (!skb) 1217 return -ENOMEM; 1218 bf->skb = skb; 1219 } 1220 1221 /* 1222 * Setup descriptors. For receive we always terminate 1223 * the descriptor list with a self-linked entry so we'll 1224 * not get overrun under high load (as can happen with a 1225 * 5212 when ANI processing enables PHY error frames). 1226 * 1227 * To insure the last descriptor is self-linked we create 1228 * each descriptor as self-linked and add it to the end. As 1229 * each additional descriptor is added the previous self-linked 1230 * entry is ``fixed'' naturally. This should be safe even 1231 * if DMA is happening. When processing RX interrupts we 1232 * never remove/process the last, self-linked, entry on the 1233 * descriptor list. This insures the hardware always has 1234 * someplace to write a new frame. 1235 */ 1236 ds = bf->desc; 1237 ds->ds_link = bf->daddr; /* link to self */ 1238 ds->ds_data = bf->skbaddr; 1239 ah->ah_setup_rx_desc(ah, ds, 1240 skb_tailroom(skb), /* buffer size */ 1241 0); 1242 1243 if (sc->rxlink != NULL) 1244 *sc->rxlink = bf->daddr; 1245 sc->rxlink = &ds->ds_link; 1246 return 0; 1247 } 1248 1249 static int 1250 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 1251 struct ath5k_txq *txq) 1252 { 1253 struct ath5k_hw *ah = sc->ah; 1254 struct ath5k_desc *ds = bf->desc; 1255 struct sk_buff *skb = bf->skb; 1256 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1257 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 1258 struct ieee80211_rate *rate; 1259 unsigned int mrr_rate[3], mrr_tries[3]; 1260 int i, ret; 1261 u16 hw_rate; 1262 u16 cts_rate = 0; 1263 u16 duration = 0; 1264 u8 rc_flags; 1265 1266 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 1267 1268 /* XXX endianness */ 1269 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 1270 PCI_DMA_TODEVICE); 1271 1272 rate = ieee80211_get_tx_rate(sc->hw, info); 1273 1274 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1275 flags |= AR5K_TXDESC_NOACK; 1276 1277 rc_flags = info->control.rates[0].flags; 1278 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 1279 rate->hw_value_short : rate->hw_value; 1280 1281 pktlen = skb->len; 1282 1283 /* FIXME: If we are in g mode and rate is a CCK rate 1284 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1285 * from tx power (value is in dB units already) */ 1286 if (info->control.hw_key) { 1287 keyidx = info->control.hw_key->hw_key_idx; 1288 pktlen += info->control.hw_key->icv_len; 1289 } 1290 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1291 flags |= AR5K_TXDESC_RTSENA; 1292 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 1293 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, 1294 sc->vif, pktlen, info)); 1295 } 1296 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1297 flags |= AR5K_TXDESC_CTSENA; 1298 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 1299 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, 1300 sc->vif, pktlen, info)); 1301 } 1302 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 1303 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL, 1304 (sc->power_level * 2), 1305 hw_rate, 1306 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 1307 cts_rate, duration); 1308 if (ret) 1309 goto err_unmap; 1310 1311 memset(mrr_rate, 0, sizeof(mrr_rate)); 1312 memset(mrr_tries, 0, sizeof(mrr_tries)); 1313 for (i = 0; i < 3; i++) { 1314 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); 1315 if (!rate) 1316 break; 1317 1318 mrr_rate[i] = rate->hw_value; 1319 mrr_tries[i] = info->control.rates[i + 1].count; 1320 } 1321 1322 ah->ah_setup_mrr_tx_desc(ah, ds, 1323 mrr_rate[0], mrr_tries[0], 1324 mrr_rate[1], mrr_tries[1], 1325 mrr_rate[2], mrr_tries[2]); 1326 1327 ds->ds_link = 0; 1328 ds->ds_data = bf->skbaddr; 1329 1330 spin_lock_bh(&txq->lock); 1331 list_add_tail(&bf->list, &txq->q); 1332 sc->tx_stats[txq->qnum].len++; 1333 if (txq->link == NULL) /* is this first packet? */ 1334 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 1335 else /* no, so only link it */ 1336 *txq->link = bf->daddr; 1337 1338 txq->link = &ds->ds_link; 1339 ath5k_hw_start_tx_dma(ah, txq->qnum); 1340 mmiowb(); 1341 spin_unlock_bh(&txq->lock); 1342 1343 return 0; 1344 err_unmap: 1345 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); 1346 return ret; 1347 } 1348 1349 /*******************\ 1350 * Descriptors setup * 1351 \*******************/ 1352 1353 static int 1354 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev) 1355 { 1356 struct ath5k_desc *ds; 1357 struct ath5k_buf *bf; 1358 dma_addr_t da; 1359 unsigned int i; 1360 int ret; 1361 1362 /* allocate descriptors */ 1363 sc->desc_len = sizeof(struct ath5k_desc) * 1364 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 1365 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr); 1366 if (sc->desc == NULL) { 1367 ATH5K_ERR(sc, "can't allocate descriptors\n"); 1368 ret = -ENOMEM; 1369 goto err; 1370 } 1371 ds = sc->desc; 1372 da = sc->desc_daddr; 1373 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 1374 ds, sc->desc_len, (unsigned long long)sc->desc_daddr); 1375 1376 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 1377 sizeof(struct ath5k_buf), GFP_KERNEL); 1378 if (bf == NULL) { 1379 ATH5K_ERR(sc, "can't allocate bufptr\n"); 1380 ret = -ENOMEM; 1381 goto err_free; 1382 } 1383 sc->bufptr = bf; 1384 1385 INIT_LIST_HEAD(&sc->rxbuf); 1386 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 1387 bf->desc = ds; 1388 bf->daddr = da; 1389 list_add_tail(&bf->list, &sc->rxbuf); 1390 } 1391 1392 INIT_LIST_HEAD(&sc->txbuf); 1393 sc->txbuf_len = ATH_TXBUF; 1394 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, 1395 da += sizeof(*ds)) { 1396 bf->desc = ds; 1397 bf->daddr = da; 1398 list_add_tail(&bf->list, &sc->txbuf); 1399 } 1400 1401 /* beacon buffer */ 1402 bf->desc = ds; 1403 bf->daddr = da; 1404 sc->bbuf = bf; 1405 1406 return 0; 1407 err_free: 1408 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); 1409 err: 1410 sc->desc = NULL; 1411 return ret; 1412 } 1413 1414 static void 1415 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev) 1416 { 1417 struct ath5k_buf *bf; 1418 1419 ath5k_txbuf_free(sc, sc->bbuf); 1420 list_for_each_entry(bf, &sc->txbuf, list) 1421 ath5k_txbuf_free(sc, bf); 1422 list_for_each_entry(bf, &sc->rxbuf, list) 1423 ath5k_rxbuf_free(sc, bf); 1424 1425 /* Free memory associated with all descriptors */ 1426 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr); 1427 1428 kfree(sc->bufptr); 1429 sc->bufptr = NULL; 1430 } 1431 1432 1433 1434 1435 1436 /**************\ 1437 * Queues setup * 1438 \**************/ 1439 1440 static struct ath5k_txq * 1441 ath5k_txq_setup(struct ath5k_softc *sc, 1442 int qtype, int subtype) 1443 { 1444 struct ath5k_hw *ah = sc->ah; 1445 struct ath5k_txq *txq; 1446 struct ath5k_txq_info qi = { 1447 .tqi_subtype = subtype, 1448 .tqi_aifs = AR5K_TXQ_USEDEFAULT, 1449 .tqi_cw_min = AR5K_TXQ_USEDEFAULT, 1450 .tqi_cw_max = AR5K_TXQ_USEDEFAULT 1451 }; 1452 int qnum; 1453 1454 /* 1455 * Enable interrupts only for EOL and DESC conditions. 1456 * We mark tx descriptors to receive a DESC interrupt 1457 * when a tx queue gets deep; otherwise waiting for the 1458 * EOL to reap descriptors. Note that this is done to 1459 * reduce interrupt load and this only defers reaping 1460 * descriptors, never transmitting frames. Aside from 1461 * reducing interrupts this also permits more concurrency. 1462 * The only potential downside is if the tx queue backs 1463 * up in which case the top half of the kernel may backup 1464 * due to a lack of tx descriptors. 1465 */ 1466 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 1467 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 1468 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 1469 if (qnum < 0) { 1470 /* 1471 * NB: don't print a message, this happens 1472 * normally on parts with too few tx queues 1473 */ 1474 return ERR_PTR(qnum); 1475 } 1476 if (qnum >= ARRAY_SIZE(sc->txqs)) { 1477 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", 1478 qnum, ARRAY_SIZE(sc->txqs)); 1479 ath5k_hw_release_tx_queue(ah, qnum); 1480 return ERR_PTR(-EINVAL); 1481 } 1482 txq = &sc->txqs[qnum]; 1483 if (!txq->setup) { 1484 txq->qnum = qnum; 1485 txq->link = NULL; 1486 INIT_LIST_HEAD(&txq->q); 1487 spin_lock_init(&txq->lock); 1488 txq->setup = true; 1489 } 1490 return &sc->txqs[qnum]; 1491 } 1492 1493 static int 1494 ath5k_beaconq_setup(struct ath5k_hw *ah) 1495 { 1496 struct ath5k_txq_info qi = { 1497 .tqi_aifs = AR5K_TXQ_USEDEFAULT, 1498 .tqi_cw_min = AR5K_TXQ_USEDEFAULT, 1499 .tqi_cw_max = AR5K_TXQ_USEDEFAULT, 1500 /* NB: for dynamic turbo, don't enable any other interrupts */ 1501 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 1502 }; 1503 1504 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 1505 } 1506 1507 static int 1508 ath5k_beaconq_config(struct ath5k_softc *sc) 1509 { 1510 struct ath5k_hw *ah = sc->ah; 1511 struct ath5k_txq_info qi; 1512 int ret; 1513 1514 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); 1515 if (ret) 1516 return ret; 1517 if (sc->opmode == NL80211_IFTYPE_AP || 1518 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 1519 /* 1520 * Always burst out beacon and CAB traffic 1521 * (aifs = cwmin = cwmax = 0) 1522 */ 1523 qi.tqi_aifs = 0; 1524 qi.tqi_cw_min = 0; 1525 qi.tqi_cw_max = 0; 1526 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { 1527 /* 1528 * Adhoc mode; backoff between 0 and (2 * cw_min). 1529 */ 1530 qi.tqi_aifs = 0; 1531 qi.tqi_cw_min = 0; 1532 qi.tqi_cw_max = 2 * ah->ah_cw_min; 1533 } 1534 1535 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1536 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1537 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1538 1539 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); 1540 if (ret) { 1541 ATH5K_ERR(sc, "%s: unable to update parameters for beacon " 1542 "hardware queue!\n", __func__); 1543 return ret; 1544 } 1545 1546 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */; 1547 } 1548 1549 static void 1550 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1551 { 1552 struct ath5k_buf *bf, *bf0; 1553 1554 /* 1555 * NB: this assumes output has been stopped and 1556 * we do not need to block ath5k_tx_tasklet 1557 */ 1558 spin_lock_bh(&txq->lock); 1559 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1560 ath5k_debug_printtxbuf(sc, bf); 1561 1562 ath5k_txbuf_free(sc, bf); 1563 1564 spin_lock_bh(&sc->txbuflock); 1565 sc->tx_stats[txq->qnum].len--; 1566 list_move_tail(&bf->list, &sc->txbuf); 1567 sc->txbuf_len++; 1568 spin_unlock_bh(&sc->txbuflock); 1569 } 1570 txq->link = NULL; 1571 spin_unlock_bh(&txq->lock); 1572 } 1573 1574 /* 1575 * Drain the transmit queues and reclaim resources. 1576 */ 1577 static void 1578 ath5k_txq_cleanup(struct ath5k_softc *sc) 1579 { 1580 struct ath5k_hw *ah = sc->ah; 1581 unsigned int i; 1582 1583 /* XXX return value */ 1584 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) { 1585 /* don't touch the hardware if marked invalid */ 1586 ath5k_hw_stop_tx_dma(ah, sc->bhalq); 1587 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n", 1588 ath5k_hw_get_txdp(ah, sc->bhalq)); 1589 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1590 if (sc->txqs[i].setup) { 1591 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum); 1592 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, " 1593 "link %p\n", 1594 sc->txqs[i].qnum, 1595 ath5k_hw_get_txdp(ah, 1596 sc->txqs[i].qnum), 1597 sc->txqs[i].link); 1598 } 1599 } 1600 ieee80211_wake_queues(sc->hw); /* XXX move to callers */ 1601 1602 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) 1603 if (sc->txqs[i].setup) 1604 ath5k_txq_drainq(sc, &sc->txqs[i]); 1605 } 1606 1607 static void 1608 ath5k_txq_release(struct ath5k_softc *sc) 1609 { 1610 struct ath5k_txq *txq = sc->txqs; 1611 unsigned int i; 1612 1613 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) 1614 if (txq->setup) { 1615 ath5k_hw_release_tx_queue(sc->ah, txq->qnum); 1616 txq->setup = false; 1617 } 1618 } 1619 1620 1621 1622 1623 /*************\ 1624 * RX Handling * 1625 \*************/ 1626 1627 /* 1628 * Enable the receive h/w following a reset. 1629 */ 1630 static int 1631 ath5k_rx_start(struct ath5k_softc *sc) 1632 { 1633 struct ath5k_hw *ah = sc->ah; 1634 struct ath_common *common = ath5k_hw_common(ah); 1635 struct ath5k_buf *bf; 1636 int ret; 1637 1638 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz); 1639 1640 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1641 common->cachelsz, common->rx_bufsize); 1642 1643 spin_lock_bh(&sc->rxbuflock); 1644 sc->rxlink = NULL; 1645 list_for_each_entry(bf, &sc->rxbuf, list) { 1646 ret = ath5k_rxbuf_setup(sc, bf); 1647 if (ret != 0) { 1648 spin_unlock_bh(&sc->rxbuflock); 1649 goto err; 1650 } 1651 } 1652 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1653 ath5k_hw_set_rxdp(ah, bf->daddr); 1654 spin_unlock_bh(&sc->rxbuflock); 1655 1656 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1657 ath5k_mode_setup(sc); /* set filters, etc. */ 1658 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1659 1660 return 0; 1661 err: 1662 return ret; 1663 } 1664 1665 /* 1666 * Disable the receive h/w in preparation for a reset. 1667 */ 1668 static void 1669 ath5k_rx_stop(struct ath5k_softc *sc) 1670 { 1671 struct ath5k_hw *ah = sc->ah; 1672 1673 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1674 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1675 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */ 1676 1677 ath5k_debug_printrxbuffs(sc, ah); 1678 1679 sc->rxlink = NULL; /* just in case */ 1680 } 1681 1682 static unsigned int 1683 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds, 1684 struct sk_buff *skb, struct ath5k_rx_status *rs) 1685 { 1686 struct ieee80211_hdr *hdr = (void *)skb->data; 1687 unsigned int keyix, hlen; 1688 1689 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1690 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1691 return RX_FLAG_DECRYPTED; 1692 1693 /* Apparently when a default key is used to decrypt the packet 1694 the hw does not set the index used to decrypt. In such cases 1695 get the index from the packet. */ 1696 hlen = ieee80211_hdrlen(hdr->frame_control); 1697 if (ieee80211_has_protected(hdr->frame_control) && 1698 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1699 skb->len >= hlen + 4) { 1700 keyix = skb->data[hlen + 3] >> 6; 1701 1702 if (test_bit(keyix, sc->keymap)) 1703 return RX_FLAG_DECRYPTED; 1704 } 1705 1706 return 0; 1707 } 1708 1709 1710 static void 1711 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, 1712 struct ieee80211_rx_status *rxs) 1713 { 1714 struct ath_common *common = ath5k_hw_common(sc->ah); 1715 u64 tsf, bc_tstamp; 1716 u32 hw_tu; 1717 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1718 1719 if (ieee80211_is_beacon(mgmt->frame_control) && 1720 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1721 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) { 1722 /* 1723 * Received an IBSS beacon with the same BSSID. Hardware *must* 1724 * have updated the local TSF. We have to work around various 1725 * hardware bugs, though... 1726 */ 1727 tsf = ath5k_hw_get_tsf64(sc->ah); 1728 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1729 hw_tu = TSF_TO_TU(tsf); 1730 1731 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1732 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1733 (unsigned long long)bc_tstamp, 1734 (unsigned long long)rxs->mactime, 1735 (unsigned long long)(rxs->mactime - bc_tstamp), 1736 (unsigned long long)tsf); 1737 1738 /* 1739 * Sometimes the HW will give us a wrong tstamp in the rx 1740 * status, causing the timestamp extension to go wrong. 1741 * (This seems to happen especially with beacon frames bigger 1742 * than 78 byte (incl. FCS)) 1743 * But we know that the receive timestamp must be later than the 1744 * timestamp of the beacon since HW must have synced to that. 1745 * 1746 * NOTE: here we assume mactime to be after the frame was 1747 * received, not like mac80211 which defines it at the start. 1748 */ 1749 if (bc_tstamp > rxs->mactime) { 1750 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1751 "fixing mactime from %llx to %llx\n", 1752 (unsigned long long)rxs->mactime, 1753 (unsigned long long)tsf); 1754 rxs->mactime = tsf; 1755 } 1756 1757 /* 1758 * Local TSF might have moved higher than our beacon timers, 1759 * in that case we have to update them to continue sending 1760 * beacons. This also takes care of synchronizing beacon sending 1761 * times with other stations. 1762 */ 1763 if (hw_tu >= sc->nexttbtt) 1764 ath5k_beacon_update_timers(sc, bc_tstamp); 1765 } 1766 } 1767 1768 static void 1769 ath5k_tasklet_rx(unsigned long data) 1770 { 1771 struct ieee80211_rx_status *rxs; 1772 struct ath5k_rx_status rs = {}; 1773 struct sk_buff *skb, *next_skb; 1774 dma_addr_t next_skb_addr; 1775 struct ath5k_softc *sc = (void *)data; 1776 struct ath5k_hw *ah = sc->ah; 1777 struct ath_common *common = ath5k_hw_common(ah); 1778 struct ath5k_buf *bf; 1779 struct ath5k_desc *ds; 1780 int ret; 1781 int hdrlen; 1782 int padsize; 1783 int rx_flag; 1784 1785 spin_lock(&sc->rxbuflock); 1786 if (list_empty(&sc->rxbuf)) { 1787 ATH5K_WARN(sc, "empty rx buf pool\n"); 1788 goto unlock; 1789 } 1790 do { 1791 rx_flag = 0; 1792 1793 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1794 BUG_ON(bf->skb == NULL); 1795 skb = bf->skb; 1796 ds = bf->desc; 1797 1798 /* bail if HW is still using self-linked descriptor */ 1799 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) 1800 break; 1801 1802 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); 1803 if (unlikely(ret == -EINPROGRESS)) 1804 break; 1805 else if (unlikely(ret)) { 1806 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1807 spin_unlock(&sc->rxbuflock); 1808 return; 1809 } 1810 1811 if (unlikely(rs.rs_more)) { 1812 ATH5K_WARN(sc, "unsupported jumbo\n"); 1813 goto next; 1814 } 1815 1816 if (unlikely(rs.rs_status)) { 1817 if (rs.rs_status & AR5K_RXERR_PHY) 1818 goto next; 1819 if (rs.rs_status & AR5K_RXERR_DECRYPT) { 1820 /* 1821 * Decrypt error. If the error occurred 1822 * because there was no hardware key, then 1823 * let the frame through so the upper layers 1824 * can process it. This is necessary for 5210 1825 * parts which have no way to setup a ``clear'' 1826 * key cache entry. 1827 * 1828 * XXX do key cache faulting 1829 */ 1830 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID && 1831 !(rs.rs_status & AR5K_RXERR_CRC)) 1832 goto accept; 1833 } 1834 if (rs.rs_status & AR5K_RXERR_MIC) { 1835 rx_flag |= RX_FLAG_MMIC_ERROR; 1836 goto accept; 1837 } 1838 1839 /* let crypto-error packets fall through in MNTR */ 1840 if ((rs.rs_status & 1841 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) || 1842 sc->opmode != NL80211_IFTYPE_MONITOR) 1843 goto next; 1844 } 1845 accept: 1846 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); 1847 1848 /* 1849 * If we can't replace bf->skb with a new skb under memory 1850 * pressure, just skip this packet 1851 */ 1852 if (!next_skb) 1853 goto next; 1854 1855 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize, 1856 PCI_DMA_FROMDEVICE); 1857 skb_put(skb, rs.rs_datalen); 1858 1859 /* The MAC header is padded to have 32-bit boundary if the 1860 * packet payload is non-zero. The general calculation for 1861 * padsize would take into account odd header lengths: 1862 * padsize = (4 - hdrlen % 4) % 4; However, since only 1863 * even-length headers are used, padding can only be 0 or 2 1864 * bytes and we can optimize this a bit. In addition, we must 1865 * not try to remove padding from short control frames that do 1866 * not have payload. */ 1867 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1868 padsize = ath5k_pad_size(hdrlen); 1869 if (padsize) { 1870 memmove(skb->data + padsize, skb->data, hdrlen); 1871 skb_pull(skb, padsize); 1872 } 1873 rxs = IEEE80211_SKB_RXCB(skb); 1874 1875 /* 1876 * always extend the mac timestamp, since this information is 1877 * also needed for proper IBSS merging. 1878 * 1879 * XXX: it might be too late to do it here, since rs_tstamp is 1880 * 15bit only. that means TSF extension has to be done within 1881 * 32768usec (about 32ms). it might be necessary to move this to 1882 * the interrupt handler, like it is done in madwifi. 1883 * 1884 * Unfortunately we don't know when the hardware takes the rx 1885 * timestamp (beginning of phy frame, data frame, end of rx?). 1886 * The only thing we know is that it is hardware specific... 1887 * On AR5213 it seems the rx timestamp is at the end of the 1888 * frame, but i'm not sure. 1889 * 1890 * NOTE: mac80211 defines mactime at the beginning of the first 1891 * data symbol. Since we don't have any time references it's 1892 * impossible to comply to that. This affects IBSS merge only 1893 * right now, so it's not too bad... 1894 */ 1895 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp); 1896 rxs->flag = rx_flag | RX_FLAG_TSFT; 1897 1898 rxs->freq = sc->curchan->center_freq; 1899 rxs->band = sc->curband->band; 1900 1901 rxs->noise = sc->ah->ah_noise_floor; 1902 rxs->signal = rxs->noise + rs.rs_rssi; 1903 1904 /* An rssi of 35 indicates you should be able use 1905 * 54 Mbps reliably. A more elaborate scheme can be used 1906 * here but it requires a map of SNR/throughput for each 1907 * possible mode used */ 1908 rxs->qual = rs.rs_rssi * 100 / 35; 1909 1910 /* rssi can be more than 35 though, anything above that 1911 * should be considered at 100% */ 1912 if (rxs->qual > 100) 1913 rxs->qual = 100; 1914 1915 rxs->antenna = rs.rs_antenna; 1916 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate); 1917 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs); 1918 1919 if (rxs->rate_idx >= 0 && rs.rs_rate == 1920 sc->curband->bitrates[rxs->rate_idx].hw_value_short) 1921 rxs->flag |= RX_FLAG_SHORTPRE; 1922 1923 ath5k_debug_dump_skb(sc, skb, "RX ", 0); 1924 1925 /* check beacons in IBSS mode */ 1926 if (sc->opmode == NL80211_IFTYPE_ADHOC) 1927 ath5k_check_ibss_tsf(sc, skb, rxs); 1928 1929 ieee80211_rx(sc->hw, skb); 1930 1931 bf->skb = next_skb; 1932 bf->skbaddr = next_skb_addr; 1933 next: 1934 list_move_tail(&bf->list, &sc->rxbuf); 1935 } while (ath5k_rxbuf_setup(sc, bf) == 0); 1936 unlock: 1937 spin_unlock(&sc->rxbuflock); 1938 } 1939 1940 1941 1942 1943 /*************\ 1944 * TX Handling * 1945 \*************/ 1946 1947 static void 1948 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1949 { 1950 struct ath5k_tx_status ts = {}; 1951 struct ath5k_buf *bf, *bf0; 1952 struct ath5k_desc *ds; 1953 struct sk_buff *skb; 1954 struct ieee80211_tx_info *info; 1955 int i, ret; 1956 1957 spin_lock(&txq->lock); 1958 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1959 ds = bf->desc; 1960 1961 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); 1962 if (unlikely(ret == -EINPROGRESS)) 1963 break; 1964 else if (unlikely(ret)) { 1965 ATH5K_ERR(sc, "error %d while processing queue %u\n", 1966 ret, txq->qnum); 1967 break; 1968 } 1969 1970 skb = bf->skb; 1971 info = IEEE80211_SKB_CB(skb); 1972 bf->skb = NULL; 1973 1974 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, 1975 PCI_DMA_TODEVICE); 1976 1977 ieee80211_tx_info_clear_status(info); 1978 for (i = 0; i < 4; i++) { 1979 struct ieee80211_tx_rate *r = 1980 &info->status.rates[i]; 1981 1982 if (ts.ts_rate[i]) { 1983 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]); 1984 r->count = ts.ts_retry[i]; 1985 } else { 1986 r->idx = -1; 1987 r->count = 0; 1988 } 1989 } 1990 1991 /* count the successful attempt as well */ 1992 info->status.rates[ts.ts_final_idx].count++; 1993 1994 if (unlikely(ts.ts_status)) { 1995 sc->ll_stats.dot11ACKFailureCount++; 1996 if (ts.ts_status & AR5K_TXERR_FILT) 1997 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1998 } else { 1999 info->flags |= IEEE80211_TX_STAT_ACK; 2000 info->status.ack_signal = ts.ts_rssi; 2001 } 2002 2003 ieee80211_tx_status(sc->hw, skb); 2004 sc->tx_stats[txq->qnum].count++; 2005 2006 spin_lock(&sc->txbuflock); 2007 sc->tx_stats[txq->qnum].len--; 2008 list_move_tail(&bf->list, &sc->txbuf); 2009 sc->txbuf_len++; 2010 spin_unlock(&sc->txbuflock); 2011 } 2012 if (likely(list_empty(&txq->q))) 2013 txq->link = NULL; 2014 spin_unlock(&txq->lock); 2015 if (sc->txbuf_len > ATH_TXBUF / 5) 2016 ieee80211_wake_queues(sc->hw); 2017 } 2018 2019 static void 2020 ath5k_tasklet_tx(unsigned long data) 2021 { 2022 int i; 2023 struct ath5k_softc *sc = (void *)data; 2024 2025 for (i=0; i < AR5K_NUM_TX_QUEUES; i++) 2026 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) 2027 ath5k_tx_processq(sc, &sc->txqs[i]); 2028 } 2029 2030 2031 /*****************\ 2032 * Beacon handling * 2033 \*****************/ 2034 2035 /* 2036 * Setup the beacon frame for transmit. 2037 */ 2038 static int 2039 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 2040 { 2041 struct sk_buff *skb = bf->skb; 2042 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2043 struct ath5k_hw *ah = sc->ah; 2044 struct ath5k_desc *ds; 2045 int ret = 0; 2046 u8 antenna; 2047 u32 flags; 2048 2049 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len, 2050 PCI_DMA_TODEVICE); 2051 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 2052 "skbaddr %llx\n", skb, skb->data, skb->len, 2053 (unsigned long long)bf->skbaddr); 2054 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) { 2055 ATH5K_ERR(sc, "beacon DMA mapping failed\n"); 2056 return -EIO; 2057 } 2058 2059 ds = bf->desc; 2060 antenna = ah->ah_tx_ant; 2061 2062 flags = AR5K_TXDESC_NOACK; 2063 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 2064 ds->ds_link = bf->daddr; /* self-linked */ 2065 flags |= AR5K_TXDESC_VEOL; 2066 } else 2067 ds->ds_link = 0; 2068 2069 /* 2070 * If we use multiple antennas on AP and use 2071 * the Sectored AP scenario, switch antenna every 2072 * 4 beacons to make sure everybody hears our AP. 2073 * When a client tries to associate, hw will keep 2074 * track of the tx antenna to be used for this client 2075 * automaticaly, based on ACKed packets. 2076 * 2077 * Note: AP still listens and transmits RTS on the 2078 * default antenna which is supposed to be an omni. 2079 * 2080 * Note2: On sectored scenarios it's possible to have 2081 * multiple antennas (1omni -the default- and 14 sectors) 2082 * so if we choose to actually support this mode we need 2083 * to allow user to set how many antennas we have and tweak 2084 * the code below to send beacons on all of them. 2085 */ 2086 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 2087 antenna = sc->bsent & 4 ? 2 : 1; 2088 2089 2090 /* FIXME: If we are in g mode and rate is a CCK rate 2091 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 2092 * from tx power (value is in dB units already) */ 2093 ds->ds_data = bf->skbaddr; 2094 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 2095 ieee80211_get_hdrlen_from_skb(skb), 2096 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 2097 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 2098 1, AR5K_TXKEYIX_INVALID, 2099 antenna, flags, 0, 0); 2100 if (ret) 2101 goto err_unmap; 2102 2103 return 0; 2104 err_unmap: 2105 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE); 2106 return ret; 2107 } 2108 2109 /* 2110 * Transmit a beacon frame at SWBA. Dynamic updates to the 2111 * frame contents are done as needed and the slot time is 2112 * also adjusted based on current state. 2113 * 2114 * This is called from software irq context (beacontq or restq 2115 * tasklets) or user context from ath5k_beacon_config. 2116 */ 2117 static void 2118 ath5k_beacon_send(struct ath5k_softc *sc) 2119 { 2120 struct ath5k_buf *bf = sc->bbuf; 2121 struct ath5k_hw *ah = sc->ah; 2122 struct sk_buff *skb; 2123 2124 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 2125 2126 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || 2127 sc->opmode == NL80211_IFTYPE_MONITOR)) { 2128 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); 2129 return; 2130 } 2131 /* 2132 * Check if the previous beacon has gone out. If 2133 * not don't don't try to post another, skip this 2134 * period and wait for the next. Missed beacons 2135 * indicate a problem and should not occur. If we 2136 * miss too many consecutive beacons reset the device. 2137 */ 2138 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { 2139 sc->bmisscount++; 2140 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2141 "missed %u consecutive beacons\n", sc->bmisscount); 2142 if (sc->bmisscount > 10) { /* NB: 10 is a guess */ 2143 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2144 "stuck beacon time (%u missed)\n", 2145 sc->bmisscount); 2146 tasklet_schedule(&sc->restq); 2147 } 2148 return; 2149 } 2150 if (unlikely(sc->bmisscount != 0)) { 2151 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2152 "resume beacon xmit after %u misses\n", 2153 sc->bmisscount); 2154 sc->bmisscount = 0; 2155 } 2156 2157 /* 2158 * Stop any current dma and put the new frame on the queue. 2159 * This should never fail since we check above that no frames 2160 * are still pending on the queue. 2161 */ 2162 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) { 2163 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); 2164 /* NB: hw still stops DMA, so proceed */ 2165 } 2166 2167 /* refresh the beacon for AP mode */ 2168 if (sc->opmode == NL80211_IFTYPE_AP) 2169 ath5k_beacon_update(sc->hw, sc->vif); 2170 2171 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 2172 ath5k_hw_start_tx_dma(ah, sc->bhalq); 2173 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 2174 sc->bhalq, (unsigned long long)bf->daddr, bf->desc); 2175 2176 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); 2177 while (skb) { 2178 ath5k_tx_queue(sc->hw, skb, sc->cabq); 2179 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif); 2180 } 2181 2182 sc->bsent++; 2183 } 2184 2185 2186 /** 2187 * ath5k_beacon_update_timers - update beacon timers 2188 * 2189 * @sc: struct ath5k_softc pointer we are operating on 2190 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 2191 * beacon timer update based on the current HW TSF. 2192 * 2193 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 2194 * of a received beacon or the current local hardware TSF and write it to the 2195 * beacon timer registers. 2196 * 2197 * This is called in a variety of situations, e.g. when a beacon is received, 2198 * when a TSF update has been detected, but also when an new IBSS is created or 2199 * when we otherwise know we have to update the timers, but we keep it in this 2200 * function to have it all together in one place. 2201 */ 2202 static void 2203 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) 2204 { 2205 struct ath5k_hw *ah = sc->ah; 2206 u32 nexttbtt, intval, hw_tu, bc_tu; 2207 u64 hw_tsf; 2208 2209 intval = sc->bintval & AR5K_BEACON_PERIOD; 2210 if (WARN_ON(!intval)) 2211 return; 2212 2213 /* beacon TSF converted to TU */ 2214 bc_tu = TSF_TO_TU(bc_tsf); 2215 2216 /* current TSF converted to TU */ 2217 hw_tsf = ath5k_hw_get_tsf64(ah); 2218 hw_tu = TSF_TO_TU(hw_tsf); 2219 2220 #define FUDGE 3 2221 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */ 2222 if (bc_tsf == -1) { 2223 /* 2224 * no beacons received, called internally. 2225 * just need to refresh timers based on HW TSF. 2226 */ 2227 nexttbtt = roundup(hw_tu + FUDGE, intval); 2228 } else if (bc_tsf == 0) { 2229 /* 2230 * no beacon received, probably called by ath5k_reset_tsf(). 2231 * reset TSF to start with 0. 2232 */ 2233 nexttbtt = intval; 2234 intval |= AR5K_BEACON_RESET_TSF; 2235 } else if (bc_tsf > hw_tsf) { 2236 /* 2237 * beacon received, SW merge happend but HW TSF not yet updated. 2238 * not possible to reconfigure timers yet, but next time we 2239 * receive a beacon with the same BSSID, the hardware will 2240 * automatically update the TSF and then we need to reconfigure 2241 * the timers. 2242 */ 2243 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2244 "need to wait for HW TSF sync\n"); 2245 return; 2246 } else { 2247 /* 2248 * most important case for beacon synchronization between STA. 2249 * 2250 * beacon received and HW TSF has been already updated by HW. 2251 * update next TBTT based on the TSF of the beacon, but make 2252 * sure it is ahead of our local TSF timer. 2253 */ 2254 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2255 } 2256 #undef FUDGE 2257 2258 sc->nexttbtt = nexttbtt; 2259 2260 intval |= AR5K_BEACON_ENA; 2261 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2262 2263 /* 2264 * debugging output last in order to preserve the time critical aspect 2265 * of this function 2266 */ 2267 if (bc_tsf == -1) 2268 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2269 "reconfigured timers based on HW TSF\n"); 2270 else if (bc_tsf == 0) 2271 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2272 "reset HW TSF and timers\n"); 2273 else 2274 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2275 "updated timers based on beacon TSF\n"); 2276 2277 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2278 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2279 (unsigned long long) bc_tsf, 2280 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2281 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2282 intval & AR5K_BEACON_PERIOD, 2283 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2284 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2285 } 2286 2287 2288 /** 2289 * ath5k_beacon_config - Configure the beacon queues and interrupts 2290 * 2291 * @sc: struct ath5k_softc pointer we are operating on 2292 * 2293 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2294 * interrupts to detect TSF updates only. 2295 */ 2296 static void 2297 ath5k_beacon_config(struct ath5k_softc *sc) 2298 { 2299 struct ath5k_hw *ah = sc->ah; 2300 unsigned long flags; 2301 2302 spin_lock_irqsave(&sc->block, flags); 2303 sc->bmisscount = 0; 2304 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2305 2306 if (sc->enable_beacon) { 2307 /* 2308 * In IBSS mode we use a self-linked tx descriptor and let the 2309 * hardware send the beacons automatically. We have to load it 2310 * only once here. 2311 * We use the SWBA interrupt only to keep track of the beacon 2312 * timers in order to detect automatic TSF updates. 2313 */ 2314 ath5k_beaconq_config(sc); 2315 2316 sc->imask |= AR5K_INT_SWBA; 2317 2318 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2319 if (ath5k_hw_hasveol(ah)) 2320 ath5k_beacon_send(sc); 2321 } else 2322 ath5k_beacon_update_timers(sc, -1); 2323 } else { 2324 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq); 2325 } 2326 2327 ath5k_hw_set_imr(ah, sc->imask); 2328 mmiowb(); 2329 spin_unlock_irqrestore(&sc->block, flags); 2330 } 2331 2332 static void ath5k_tasklet_beacon(unsigned long data) 2333 { 2334 struct ath5k_softc *sc = (struct ath5k_softc *) data; 2335 2336 /* 2337 * Software beacon alert--time to send a beacon. 2338 * 2339 * In IBSS mode we use this interrupt just to 2340 * keep track of the next TBTT (target beacon 2341 * transmission time) in order to detect wether 2342 * automatic TSF updates happened. 2343 */ 2344 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2345 /* XXX: only if VEOL suppported */ 2346 u64 tsf = ath5k_hw_get_tsf64(sc->ah); 2347 sc->nexttbtt += sc->bintval; 2348 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2349 "SWBA nexttbtt: %x hw_tu: %x " 2350 "TSF: %llx\n", 2351 sc->nexttbtt, 2352 TSF_TO_TU(tsf), 2353 (unsigned long long) tsf); 2354 } else { 2355 spin_lock(&sc->block); 2356 ath5k_beacon_send(sc); 2357 spin_unlock(&sc->block); 2358 } 2359 } 2360 2361 2362 /********************\ 2363 * Interrupt handling * 2364 \********************/ 2365 2366 static int 2367 ath5k_init(struct ath5k_softc *sc) 2368 { 2369 struct ath5k_hw *ah = sc->ah; 2370 int ret, i; 2371 2372 mutex_lock(&sc->lock); 2373 2374 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); 2375 2376 /* 2377 * Stop anything previously setup. This is safe 2378 * no matter this is the first time through or not. 2379 */ 2380 ath5k_stop_locked(sc); 2381 2382 /* 2383 * The basic interface to setting the hardware in a good 2384 * state is ``reset''. On return the hardware is known to 2385 * be powered up and with interrupts disabled. This must 2386 * be followed by initialization of the appropriate bits 2387 * and then setup of the interrupt mask. 2388 */ 2389 sc->curchan = sc->hw->conf.channel; 2390 sc->curband = &sc->sbands[sc->curchan->band]; 2391 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2392 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2393 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI; 2394 ret = ath5k_reset(sc, NULL); 2395 if (ret) 2396 goto done; 2397 2398 ath5k_rfkill_hw_start(ah); 2399 2400 /* 2401 * Reset the key cache since some parts do not reset the 2402 * contents on initial power up or resume from suspend. 2403 */ 2404 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++) 2405 ath5k_hw_reset_key(ah, i); 2406 2407 /* Set ack to be sent at low bit-rates */ 2408 ath5k_hw_set_ack_bitrate_high(ah, false); 2409 2410 /* Set PHY calibration inteval */ 2411 ah->ah_cal_intval = ath5k_calinterval; 2412 2413 ret = 0; 2414 done: 2415 mmiowb(); 2416 mutex_unlock(&sc->lock); 2417 return ret; 2418 } 2419 2420 static int 2421 ath5k_stop_locked(struct ath5k_softc *sc) 2422 { 2423 struct ath5k_hw *ah = sc->ah; 2424 2425 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", 2426 test_bit(ATH_STAT_INVALID, sc->status)); 2427 2428 /* 2429 * Shutdown the hardware and driver: 2430 * stop output from above 2431 * disable interrupts 2432 * turn off timers 2433 * turn off the radio 2434 * clear transmit machinery 2435 * clear receive machinery 2436 * drain and release tx queues 2437 * reclaim beacon resources 2438 * power down hardware 2439 * 2440 * Note that some of this work is not possible if the 2441 * hardware is gone (invalid). 2442 */ 2443 ieee80211_stop_queues(sc->hw); 2444 2445 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2446 ath5k_led_off(sc); 2447 ath5k_hw_set_imr(ah, 0); 2448 synchronize_irq(sc->pdev->irq); 2449 } 2450 ath5k_txq_cleanup(sc); 2451 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2452 ath5k_rx_stop(sc); 2453 ath5k_hw_phy_disable(ah); 2454 } else 2455 sc->rxlink = NULL; 2456 2457 return 0; 2458 } 2459 2460 /* 2461 * Stop the device, grabbing the top-level lock to protect 2462 * against concurrent entry through ath5k_init (which can happen 2463 * if another thread does a system call and the thread doing the 2464 * stop is preempted). 2465 */ 2466 static int 2467 ath5k_stop_hw(struct ath5k_softc *sc) 2468 { 2469 int ret; 2470 2471 mutex_lock(&sc->lock); 2472 ret = ath5k_stop_locked(sc); 2473 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { 2474 /* 2475 * Don't set the card in full sleep mode! 2476 * 2477 * a) When the device is in this state it must be carefully 2478 * woken up or references to registers in the PCI clock 2479 * domain may freeze the bus (and system). This varies 2480 * by chip and is mostly an issue with newer parts 2481 * (madwifi sources mentioned srev >= 0x78) that go to 2482 * sleep more quickly. 2483 * 2484 * b) On older chips full sleep results a weird behaviour 2485 * during wakeup. I tested various cards with srev < 0x78 2486 * and they don't wake up after module reload, a second 2487 * module reload is needed to bring the card up again. 2488 * 2489 * Until we figure out what's going on don't enable 2490 * full chip reset on any chip (this is what Legacy HAL 2491 * and Sam's HAL do anyway). Instead Perform a full reset 2492 * on the device (same as initial state after attach) and 2493 * leave it idle (keep MAC/BB on warm reset) */ 2494 ret = ath5k_hw_on_hold(sc->ah); 2495 2496 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2497 "putting device to sleep\n"); 2498 } 2499 ath5k_txbuf_free(sc, sc->bbuf); 2500 2501 mmiowb(); 2502 mutex_unlock(&sc->lock); 2503 2504 tasklet_kill(&sc->rxtq); 2505 tasklet_kill(&sc->txtq); 2506 tasklet_kill(&sc->restq); 2507 tasklet_kill(&sc->calib); 2508 tasklet_kill(&sc->beacontq); 2509 2510 ath5k_rfkill_hw_stop(sc->ah); 2511 2512 return ret; 2513 } 2514 2515 static irqreturn_t 2516 ath5k_intr(int irq, void *dev_id) 2517 { 2518 struct ath5k_softc *sc = dev_id; 2519 struct ath5k_hw *ah = sc->ah; 2520 enum ath5k_int status; 2521 unsigned int counter = 1000; 2522 2523 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || 2524 !ath5k_hw_is_intr_pending(ah))) 2525 return IRQ_NONE; 2526 2527 do { 2528 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2529 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2530 status, sc->imask); 2531 if (unlikely(status & AR5K_INT_FATAL)) { 2532 /* 2533 * Fatal errors are unrecoverable. 2534 * Typically these are caused by DMA errors. 2535 */ 2536 tasklet_schedule(&sc->restq); 2537 } else if (unlikely(status & AR5K_INT_RXORN)) { 2538 tasklet_schedule(&sc->restq); 2539 } else { 2540 if (status & AR5K_INT_SWBA) { 2541 tasklet_hi_schedule(&sc->beacontq); 2542 } 2543 if (status & AR5K_INT_RXEOL) { 2544 /* 2545 * NB: the hardware should re-read the link when 2546 * RXE bit is written, but it doesn't work at 2547 * least on older hardware revs. 2548 */ 2549 sc->rxlink = NULL; 2550 } 2551 if (status & AR5K_INT_TXURN) { 2552 /* bump tx trigger level */ 2553 ath5k_hw_update_tx_triglevel(ah, true); 2554 } 2555 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2556 tasklet_schedule(&sc->rxtq); 2557 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2558 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2559 tasklet_schedule(&sc->txtq); 2560 if (status & AR5K_INT_BMISS) { 2561 /* TODO */ 2562 } 2563 if (status & AR5K_INT_SWI) { 2564 tasklet_schedule(&sc->calib); 2565 } 2566 if (status & AR5K_INT_MIB) { 2567 /* 2568 * These stats are also used for ANI i think 2569 * so how about updating them more often ? 2570 */ 2571 ath5k_hw_update_mib_counters(ah, &sc->ll_stats); 2572 } 2573 if (status & AR5K_INT_GPIO) 2574 tasklet_schedule(&sc->rf_kill.toggleq); 2575 2576 } 2577 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2578 2579 if (unlikely(!counter)) 2580 ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); 2581 2582 ath5k_hw_calibration_poll(ah); 2583 2584 return IRQ_HANDLED; 2585 } 2586 2587 static void 2588 ath5k_tasklet_reset(unsigned long data) 2589 { 2590 struct ath5k_softc *sc = (void *)data; 2591 2592 ath5k_reset_wake(sc); 2593 } 2594 2595 /* 2596 * Periodically recalibrate the PHY to account 2597 * for temperature/environment changes. 2598 */ 2599 static void 2600 ath5k_tasklet_calibrate(unsigned long data) 2601 { 2602 struct ath5k_softc *sc = (void *)data; 2603 struct ath5k_hw *ah = sc->ah; 2604 2605 /* Only full calibration for now */ 2606 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION) 2607 return; 2608 2609 /* Stop queues so that calibration 2610 * doesn't interfere with tx */ 2611 ieee80211_stop_queues(sc->hw); 2612 2613 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2614 ieee80211_frequency_to_channel(sc->curchan->center_freq), 2615 sc->curchan->hw_value); 2616 2617 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2618 /* 2619 * Rfgain is out of bounds, reset the chip 2620 * to load new gain values. 2621 */ 2622 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2623 ath5k_reset_wake(sc); 2624 } 2625 if (ath5k_hw_phy_calibrate(ah, sc->curchan)) 2626 ATH5K_ERR(sc, "calibration of channel %u failed\n", 2627 ieee80211_frequency_to_channel( 2628 sc->curchan->center_freq)); 2629 2630 ah->ah_swi_mask = 0; 2631 2632 /* Wake queues */ 2633 ieee80211_wake_queues(sc->hw); 2634 2635 } 2636 2637 2638 /********************\ 2639 * Mac80211 functions * 2640 \********************/ 2641 2642 static int 2643 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 2644 { 2645 struct ath5k_softc *sc = hw->priv; 2646 2647 return ath5k_tx_queue(hw, skb, sc->txq); 2648 } 2649 2650 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 2651 struct ath5k_txq *txq) 2652 { 2653 struct ath5k_softc *sc = hw->priv; 2654 struct ath5k_buf *bf; 2655 unsigned long flags; 2656 int hdrlen; 2657 int padsize; 2658 2659 ath5k_debug_dump_skb(sc, skb, "TX ", 1); 2660 2661 if (sc->opmode == NL80211_IFTYPE_MONITOR) 2662 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n"); 2663 2664 /* 2665 * the hardware expects the header padded to 4 byte boundaries 2666 * if this is not the case we add the padding after the header 2667 */ 2668 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 2669 padsize = ath5k_pad_size(hdrlen); 2670 if (padsize) { 2671 2672 if (skb_headroom(skb) < padsize) { 2673 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough" 2674 " headroom to pad %d\n", hdrlen, padsize); 2675 goto drop_packet; 2676 } 2677 skb_push(skb, padsize); 2678 memmove(skb->data, skb->data+padsize, hdrlen); 2679 } 2680 2681 spin_lock_irqsave(&sc->txbuflock, flags); 2682 if (list_empty(&sc->txbuf)) { 2683 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 2684 spin_unlock_irqrestore(&sc->txbuflock, flags); 2685 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); 2686 goto drop_packet; 2687 } 2688 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 2689 list_del(&bf->list); 2690 sc->txbuf_len--; 2691 if (list_empty(&sc->txbuf)) 2692 ieee80211_stop_queues(hw); 2693 spin_unlock_irqrestore(&sc->txbuflock, flags); 2694 2695 bf->skb = skb; 2696 2697 if (ath5k_txbuf_setup(sc, bf, txq)) { 2698 bf->skb = NULL; 2699 spin_lock_irqsave(&sc->txbuflock, flags); 2700 list_add_tail(&bf->list, &sc->txbuf); 2701 sc->txbuf_len++; 2702 spin_unlock_irqrestore(&sc->txbuflock, flags); 2703 goto drop_packet; 2704 } 2705 return NETDEV_TX_OK; 2706 2707 drop_packet: 2708 dev_kfree_skb_any(skb); 2709 return NETDEV_TX_OK; 2710 } 2711 2712 /* 2713 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2714 * and change to the given channel. 2715 */ 2716 static int 2717 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan) 2718 { 2719 struct ath5k_hw *ah = sc->ah; 2720 int ret; 2721 2722 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2723 2724 if (chan) { 2725 ath5k_hw_set_imr(ah, 0); 2726 ath5k_txq_cleanup(sc); 2727 ath5k_rx_stop(sc); 2728 2729 sc->curchan = chan; 2730 sc->curband = &sc->sbands[chan->band]; 2731 } 2732 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL); 2733 if (ret) { 2734 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); 2735 goto err; 2736 } 2737 2738 ret = ath5k_rx_start(sc); 2739 if (ret) { 2740 ATH5K_ERR(sc, "can't start recv logic\n"); 2741 goto err; 2742 } 2743 2744 /* 2745 * Change channels and update the h/w rate map if we're switching; 2746 * e.g. 11a to 11b/g. 2747 * 2748 * We may be doing a reset in response to an ioctl that changes the 2749 * channel so update any state that might change as a result. 2750 * 2751 * XXX needed? 2752 */ 2753 /* ath5k_chan_change(sc, c); */ 2754 2755 ath5k_beacon_config(sc); 2756 /* intrs are enabled by ath5k_beacon_config */ 2757 2758 return 0; 2759 err: 2760 return ret; 2761 } 2762 2763 static int 2764 ath5k_reset_wake(struct ath5k_softc *sc) 2765 { 2766 int ret; 2767 2768 ret = ath5k_reset(sc, sc->curchan); 2769 if (!ret) 2770 ieee80211_wake_queues(sc->hw); 2771 2772 return ret; 2773 } 2774 2775 static int ath5k_start(struct ieee80211_hw *hw) 2776 { 2777 return ath5k_init(hw->priv); 2778 } 2779 2780 static void ath5k_stop(struct ieee80211_hw *hw) 2781 { 2782 ath5k_stop_hw(hw->priv); 2783 } 2784 2785 static int ath5k_add_interface(struct ieee80211_hw *hw, 2786 struct ieee80211_if_init_conf *conf) 2787 { 2788 struct ath5k_softc *sc = hw->priv; 2789 int ret; 2790 2791 mutex_lock(&sc->lock); 2792 if (sc->vif) { 2793 ret = 0; 2794 goto end; 2795 } 2796 2797 sc->vif = conf->vif; 2798 2799 switch (conf->type) { 2800 case NL80211_IFTYPE_AP: 2801 case NL80211_IFTYPE_STATION: 2802 case NL80211_IFTYPE_ADHOC: 2803 case NL80211_IFTYPE_MESH_POINT: 2804 case NL80211_IFTYPE_MONITOR: 2805 sc->opmode = conf->type; 2806 break; 2807 default: 2808 ret = -EOPNOTSUPP; 2809 goto end; 2810 } 2811 2812 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr); 2813 ath5k_mode_setup(sc); 2814 2815 ret = 0; 2816 end: 2817 mutex_unlock(&sc->lock); 2818 return ret; 2819 } 2820 2821 static void 2822 ath5k_remove_interface(struct ieee80211_hw *hw, 2823 struct ieee80211_if_init_conf *conf) 2824 { 2825 struct ath5k_softc *sc = hw->priv; 2826 u8 mac[ETH_ALEN] = {}; 2827 2828 mutex_lock(&sc->lock); 2829 if (sc->vif != conf->vif) 2830 goto end; 2831 2832 ath5k_hw_set_lladdr(sc->ah, mac); 2833 sc->vif = NULL; 2834 end: 2835 mutex_unlock(&sc->lock); 2836 } 2837 2838 /* 2839 * TODO: Phy disable/diversity etc 2840 */ 2841 static int 2842 ath5k_config(struct ieee80211_hw *hw, u32 changed) 2843 { 2844 struct ath5k_softc *sc = hw->priv; 2845 struct ath5k_hw *ah = sc->ah; 2846 struct ieee80211_conf *conf = &hw->conf; 2847 int ret = 0; 2848 2849 mutex_lock(&sc->lock); 2850 2851 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 2852 ret = ath5k_chan_set(sc, conf->channel); 2853 if (ret < 0) 2854 goto unlock; 2855 } 2856 2857 if ((changed & IEEE80211_CONF_CHANGE_POWER) && 2858 (sc->power_level != conf->power_level)) { 2859 sc->power_level = conf->power_level; 2860 2861 /* Half dB steps */ 2862 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2)); 2863 } 2864 2865 /* TODO: 2866 * 1) Move this on config_interface and handle each case 2867 * separately eg. when we have only one STA vif, use 2868 * AR5K_ANTMODE_SINGLE_AP 2869 * 2870 * 2) Allow the user to change antenna mode eg. when only 2871 * one antenna is present 2872 * 2873 * 3) Allow the user to set default/tx antenna when possible 2874 * 2875 * 4) Default mode should handle 90% of the cases, together 2876 * with fixed a/b and single AP modes we should be able to 2877 * handle 99%. Sectored modes are extreme cases and i still 2878 * haven't found a usage for them. If we decide to support them, 2879 * then we must allow the user to set how many tx antennas we 2880 * have available 2881 */ 2882 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT); 2883 2884 unlock: 2885 mutex_unlock(&sc->lock); 2886 return ret; 2887 } 2888 2889 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, 2890 int mc_count, struct dev_addr_list *mclist) 2891 { 2892 u32 mfilt[2], val; 2893 int i; 2894 u8 pos; 2895 2896 mfilt[0] = 0; 2897 mfilt[1] = 1; 2898 2899 for (i = 0; i < mc_count; i++) { 2900 if (!mclist) 2901 break; 2902 /* calculate XOR of eight 6-bit values */ 2903 val = get_unaligned_le32(mclist->dmi_addr + 0); 2904 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2905 val = get_unaligned_le32(mclist->dmi_addr + 3); 2906 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2907 pos &= 0x3f; 2908 mfilt[pos / 32] |= (1 << (pos % 32)); 2909 /* XXX: we might be able to just do this instead, 2910 * but not sure, needs testing, if we do use this we'd 2911 * neet to inform below to not reset the mcast */ 2912 /* ath5k_hw_set_mcast_filterindex(ah, 2913 * mclist->dmi_addr[5]); */ 2914 mclist = mclist->next; 2915 } 2916 2917 return ((u64)(mfilt[1]) << 32) | mfilt[0]; 2918 } 2919 2920 #define SUPPORTED_FIF_FLAGS \ 2921 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \ 2922 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \ 2923 FIF_BCN_PRBRESP_PROMISC 2924 /* 2925 * o always accept unicast, broadcast, and multicast traffic 2926 * o multicast traffic for all BSSIDs will be enabled if mac80211 2927 * says it should be 2928 * o maintain current state of phy ofdm or phy cck error reception. 2929 * If the hardware detects any of these type of errors then 2930 * ath5k_hw_get_rx_filter() will pass to us the respective 2931 * hardware filters to be able to receive these type of frames. 2932 * o probe request frames are accepted only when operating in 2933 * hostap, adhoc, or monitor modes 2934 * o enable promiscuous mode according to the interface state 2935 * o accept beacons: 2936 * - when operating in adhoc mode so the 802.11 layer creates 2937 * node table entries for peers, 2938 * - when operating in station mode for collecting rssi data when 2939 * the station is otherwise quiet, or 2940 * - when scanning 2941 */ 2942 static void ath5k_configure_filter(struct ieee80211_hw *hw, 2943 unsigned int changed_flags, 2944 unsigned int *new_flags, 2945 u64 multicast) 2946 { 2947 struct ath5k_softc *sc = hw->priv; 2948 struct ath5k_hw *ah = sc->ah; 2949 u32 mfilt[2], rfilt; 2950 2951 mutex_lock(&sc->lock); 2952 2953 mfilt[0] = multicast; 2954 mfilt[1] = multicast >> 32; 2955 2956 /* Only deal with supported flags */ 2957 changed_flags &= SUPPORTED_FIF_FLAGS; 2958 *new_flags &= SUPPORTED_FIF_FLAGS; 2959 2960 /* If HW detects any phy or radar errors, leave those filters on. 2961 * Also, always enable Unicast, Broadcasts and Multicast 2962 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */ 2963 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) | 2964 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | 2965 AR5K_RX_FILTER_MCAST); 2966 2967 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) { 2968 if (*new_flags & FIF_PROMISC_IN_BSS) { 2969 rfilt |= AR5K_RX_FILTER_PROM; 2970 __set_bit(ATH_STAT_PROMISC, sc->status); 2971 } else { 2972 __clear_bit(ATH_STAT_PROMISC, sc->status); 2973 } 2974 } 2975 2976 /* Note, AR5K_RX_FILTER_MCAST is already enabled */ 2977 if (*new_flags & FIF_ALLMULTI) { 2978 mfilt[0] = ~0; 2979 mfilt[1] = ~0; 2980 } 2981 2982 /* This is the best we can do */ 2983 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL)) 2984 rfilt |= AR5K_RX_FILTER_PHYERR; 2985 2986 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons 2987 * and probes for any BSSID, this needs testing */ 2988 if (*new_flags & FIF_BCN_PRBRESP_PROMISC) 2989 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ; 2990 2991 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not 2992 * set we should only pass on control frames for this 2993 * station. This needs testing. I believe right now this 2994 * enables *all* control frames, which is OK.. but 2995 * but we should see if we can improve on granularity */ 2996 if (*new_flags & FIF_CONTROL) 2997 rfilt |= AR5K_RX_FILTER_CONTROL; 2998 2999 /* Additional settings per mode -- this is per ath5k */ 3000 3001 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */ 3002 3003 switch (sc->opmode) { 3004 case NL80211_IFTYPE_MESH_POINT: 3005 case NL80211_IFTYPE_MONITOR: 3006 rfilt |= AR5K_RX_FILTER_CONTROL | 3007 AR5K_RX_FILTER_BEACON | 3008 AR5K_RX_FILTER_PROBEREQ | 3009 AR5K_RX_FILTER_PROM; 3010 break; 3011 case NL80211_IFTYPE_AP: 3012 case NL80211_IFTYPE_ADHOC: 3013 rfilt |= AR5K_RX_FILTER_PROBEREQ | 3014 AR5K_RX_FILTER_BEACON; 3015 break; 3016 case NL80211_IFTYPE_STATION: 3017 if (sc->assoc) 3018 rfilt |= AR5K_RX_FILTER_BEACON; 3019 default: 3020 break; 3021 } 3022 3023 /* Set filters */ 3024 ath5k_hw_set_rx_filter(ah, rfilt); 3025 3026 /* Set multicast bits */ 3027 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); 3028 /* Set the cached hw filter flags, this will alter actually 3029 * be set in HW */ 3030 sc->filter_flags = rfilt; 3031 3032 mutex_unlock(&sc->lock); 3033 } 3034 3035 static int 3036 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 3037 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 3038 struct ieee80211_key_conf *key) 3039 { 3040 struct ath5k_softc *sc = hw->priv; 3041 int ret = 0; 3042 3043 if (modparam_nohwcrypt) 3044 return -EOPNOTSUPP; 3045 3046 if (sc->opmode == NL80211_IFTYPE_AP) 3047 return -EOPNOTSUPP; 3048 3049 switch (key->alg) { 3050 case ALG_WEP: 3051 case ALG_TKIP: 3052 break; 3053 case ALG_CCMP: 3054 if (sc->ah->ah_aes_support) 3055 break; 3056 3057 return -EOPNOTSUPP; 3058 default: 3059 WARN_ON(1); 3060 return -EINVAL; 3061 } 3062 3063 mutex_lock(&sc->lock); 3064 3065 switch (cmd) { 3066 case SET_KEY: 3067 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, 3068 sta ? sta->addr : NULL); 3069 if (ret) { 3070 ATH5K_ERR(sc, "can't set the key\n"); 3071 goto unlock; 3072 } 3073 __set_bit(key->keyidx, sc->keymap); 3074 key->hw_key_idx = key->keyidx; 3075 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV | 3076 IEEE80211_KEY_FLAG_GENERATE_MMIC); 3077 break; 3078 case DISABLE_KEY: 3079 ath5k_hw_reset_key(sc->ah, key->keyidx); 3080 __clear_bit(key->keyidx, sc->keymap); 3081 break; 3082 default: 3083 ret = -EINVAL; 3084 goto unlock; 3085 } 3086 3087 unlock: 3088 mmiowb(); 3089 mutex_unlock(&sc->lock); 3090 return ret; 3091 } 3092 3093 static int 3094 ath5k_get_stats(struct ieee80211_hw *hw, 3095 struct ieee80211_low_level_stats *stats) 3096 { 3097 struct ath5k_softc *sc = hw->priv; 3098 struct ath5k_hw *ah = sc->ah; 3099 3100 /* Force update */ 3101 ath5k_hw_update_mib_counters(ah, &sc->ll_stats); 3102 3103 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); 3104 3105 return 0; 3106 } 3107 3108 static int 3109 ath5k_get_tx_stats(struct ieee80211_hw *hw, 3110 struct ieee80211_tx_queue_stats *stats) 3111 { 3112 struct ath5k_softc *sc = hw->priv; 3113 3114 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats)); 3115 3116 return 0; 3117 } 3118 3119 static u64 3120 ath5k_get_tsf(struct ieee80211_hw *hw) 3121 { 3122 struct ath5k_softc *sc = hw->priv; 3123 3124 return ath5k_hw_get_tsf64(sc->ah); 3125 } 3126 3127 static void 3128 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf) 3129 { 3130 struct ath5k_softc *sc = hw->priv; 3131 3132 ath5k_hw_set_tsf64(sc->ah, tsf); 3133 } 3134 3135 static void 3136 ath5k_reset_tsf(struct ieee80211_hw *hw) 3137 { 3138 struct ath5k_softc *sc = hw->priv; 3139 3140 /* 3141 * in IBSS mode we need to update the beacon timers too. 3142 * this will also reset the TSF if we call it with 0 3143 */ 3144 if (sc->opmode == NL80211_IFTYPE_ADHOC) 3145 ath5k_beacon_update_timers(sc, 0); 3146 else 3147 ath5k_hw_reset_tsf(sc->ah); 3148 } 3149 3150 /* 3151 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 3152 * this is called only once at config_bss time, for AP we do it every 3153 * SWBA interrupt so that the TIM will reflect buffered frames. 3154 * 3155 * Called with the beacon lock. 3156 */ 3157 static int 3158 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 3159 { 3160 int ret; 3161 struct ath5k_softc *sc = hw->priv; 3162 struct sk_buff *skb; 3163 3164 if (WARN_ON(!vif)) { 3165 ret = -EINVAL; 3166 goto out; 3167 } 3168 3169 skb = ieee80211_beacon_get(hw, vif); 3170 3171 if (!skb) { 3172 ret = -ENOMEM; 3173 goto out; 3174 } 3175 3176 ath5k_debug_dump_skb(sc, skb, "BC ", 1); 3177 3178 ath5k_txbuf_free(sc, sc->bbuf); 3179 sc->bbuf->skb = skb; 3180 ret = ath5k_beacon_setup(sc, sc->bbuf); 3181 if (ret) 3182 sc->bbuf->skb = NULL; 3183 out: 3184 return ret; 3185 } 3186 3187 static void 3188 set_beacon_filter(struct ieee80211_hw *hw, bool enable) 3189 { 3190 struct ath5k_softc *sc = hw->priv; 3191 struct ath5k_hw *ah = sc->ah; 3192 u32 rfilt; 3193 rfilt = ath5k_hw_get_rx_filter(ah); 3194 if (enable) 3195 rfilt |= AR5K_RX_FILTER_BEACON; 3196 else 3197 rfilt &= ~AR5K_RX_FILTER_BEACON; 3198 ath5k_hw_set_rx_filter(ah, rfilt); 3199 sc->filter_flags = rfilt; 3200 } 3201 3202 static void ath5k_bss_info_changed(struct ieee80211_hw *hw, 3203 struct ieee80211_vif *vif, 3204 struct ieee80211_bss_conf *bss_conf, 3205 u32 changes) 3206 { 3207 struct ath5k_softc *sc = hw->priv; 3208 struct ath5k_hw *ah = sc->ah; 3209 struct ath_common *common = ath5k_hw_common(ah); 3210 unsigned long flags; 3211 3212 mutex_lock(&sc->lock); 3213 if (WARN_ON(sc->vif != vif)) 3214 goto unlock; 3215 3216 if (changes & BSS_CHANGED_BSSID) { 3217 /* Cache for later use during resets */ 3218 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 3219 common->curaid = 0; 3220 ath5k_hw_set_associd(ah); 3221 mmiowb(); 3222 } 3223 3224 if (changes & BSS_CHANGED_BEACON_INT) 3225 sc->bintval = bss_conf->beacon_int; 3226 3227 if (changes & BSS_CHANGED_ASSOC) { 3228 sc->assoc = bss_conf->assoc; 3229 if (sc->opmode == NL80211_IFTYPE_STATION) 3230 set_beacon_filter(hw, sc->assoc); 3231 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 3232 AR5K_LED_ASSOC : AR5K_LED_INIT); 3233 if (bss_conf->assoc) { 3234 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, 3235 "Bss Info ASSOC %d, bssid: %pM\n", 3236 bss_conf->aid, common->curbssid); 3237 common->curaid = bss_conf->aid; 3238 ath5k_hw_set_associd(ah); 3239 /* Once ANI is available you would start it here */ 3240 } 3241 } 3242 3243 if (changes & BSS_CHANGED_BEACON) { 3244 spin_lock_irqsave(&sc->block, flags); 3245 ath5k_beacon_update(hw, vif); 3246 spin_unlock_irqrestore(&sc->block, flags); 3247 } 3248 3249 if (changes & BSS_CHANGED_BEACON_ENABLED) 3250 sc->enable_beacon = bss_conf->enable_beacon; 3251 3252 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED | 3253 BSS_CHANGED_BEACON_INT)) 3254 ath5k_beacon_config(sc); 3255 3256 unlock: 3257 mutex_unlock(&sc->lock); 3258 } 3259 3260 static void ath5k_sw_scan_start(struct ieee80211_hw *hw) 3261 { 3262 struct ath5k_softc *sc = hw->priv; 3263 if (!sc->assoc) 3264 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN); 3265 } 3266 3267 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw) 3268 { 3269 struct ath5k_softc *sc = hw->priv; 3270 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 3271 AR5K_LED_ASSOC : AR5K_LED_INIT); 3272 } 3273