1 /* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _ATH5K_H 19 #define _ATH5K_H 20 21 /* TODO: Clean up channel debuging -doesn't work anyway- and start 22 * working on reg. control code using all available eeprom information 23 * -rev. engineering needed- */ 24 #define CHAN_DEBUG 0 25 26 #include <linux/io.h> 27 #include <linux/types.h> 28 #include <linux/average.h> 29 #include <net/mac80211.h> 30 31 /* RX/TX descriptor hw structs 32 * TODO: Driver part should only see sw structs */ 33 #include "desc.h" 34 35 /* EEPROM structs/offsets 36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 37 * and clean up common bits, then introduce set/get functions in eeprom.c */ 38 #include "eeprom.h" 39 #include "../ath.h" 40 41 /* PCI IDs */ 42 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 43 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 44 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 45 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 46 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 47 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 48 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 49 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 50 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 51 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 52 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 53 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 54 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 55 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 56 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 57 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 58 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 59 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 60 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 61 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 62 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 63 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 64 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 65 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 66 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 67 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 68 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 69 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 70 71 /****************************\ 72 GENERIC DRIVER DEFINITIONS 73 \****************************/ 74 75 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) 76 77 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 78 printk(_level "ath5k %s: " _fmt, \ 79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 80 ##__VA_ARGS__) 81 82 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 83 if (net_ratelimit()) \ 84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 85 } while (0) 86 87 #define ATH5K_INFO(_sc, _fmt, ...) \ 88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 89 90 #define ATH5K_WARN(_sc, _fmt, ...) \ 91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 92 93 #define ATH5K_ERR(_sc, _fmt, ...) \ 94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 95 96 /* 97 * AR5K REGISTER ACCESS 98 */ 99 100 /* Some macros to read/write fields */ 101 102 /* First shift, then mask */ 103 #define AR5K_REG_SM(_val, _flags) \ 104 (((_val) << _flags##_S) & (_flags)) 105 106 /* First mask, then shift */ 107 #define AR5K_REG_MS(_val, _flags) \ 108 (((_val) & (_flags)) >> _flags##_S) 109 110 /* Some registers can hold multiple values of interest. For this 111 * reason when we want to write to these registers we must first 112 * retrieve the values which we do not want to clear (lets call this 113 * old_data) and then set the register with this and our new_value: 114 * ( old_data | new_value) */ 115 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 117 (((_val) << _flags##_S) & (_flags)), _reg) 118 119 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 121 (_mask)) | (_flags), _reg) 122 123 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 125 126 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 128 129 /* Access to PHY registers */ 130 #define AR5K_PHY_READ(ah, _reg) \ 131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) 132 133 #define AR5K_PHY_WRITE(ah, _reg, _val) \ 134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) 135 136 /* Access QCU registers per queue */ 137 #define AR5K_REG_READ_Q(ah, _reg, _queue) \ 138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 139 140 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 141 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 142 143 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 144 _reg |= 1 << _queue; \ 145 } while (0) 146 147 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 148 _reg &= ~(1 << _queue); \ 149 } while (0) 150 151 /* Used while writing initvals */ 152 #define AR5K_REG_WAIT(_i) do { \ 153 if (_i % 64) \ 154 udelay(1); \ 155 } while (0) 156 157 /* Register dumps are done per operation mode */ 158 #define AR5K_INI_RFGAIN_5GHZ 0 159 #define AR5K_INI_RFGAIN_2GHZ 1 160 161 /* TODO: Clean this up */ 162 #define AR5K_INI_VAL_11A 0 163 #define AR5K_INI_VAL_11A_TURBO 1 164 #define AR5K_INI_VAL_11B 2 165 #define AR5K_INI_VAL_11G 3 166 #define AR5K_INI_VAL_11G_TURBO 4 167 #define AR5K_INI_VAL_XR 0 168 #define AR5K_INI_VAL_MAX 5 169 170 /* 171 * Some tuneable values (these should be changeable by the user) 172 * TODO: Make use of them and add more options OR use debug/configfs 173 */ 174 #define AR5K_TUNE_DMA_BEACON_RESP 2 175 #define AR5K_TUNE_SW_BEACON_RESP 10 176 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 177 #define AR5K_TUNE_RADAR_ALERT false 178 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1 179 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1) 180 #define AR5K_TUNE_REGISTER_TIMEOUT 20000 181 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to 182 * be the max value. */ 183 #define AR5K_TUNE_RSSI_THRES 129 184 /* This must be set when setting the RSSI threshold otherwise it can 185 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 186 * the BMISS_THRES will be seen as 0, seems harware doesn't keep 187 * track of it. Max value depends on harware. For AR5210 this is just 7. 188 * For AR5211+ this seems to be up to 255. */ 189 #define AR5K_TUNE_BMISS_THRES 7 190 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000 191 #define AR5K_TUNE_BEACON_INTERVAL 100 192 #define AR5K_TUNE_AIFS 2 193 #define AR5K_TUNE_AIFS_11B 2 194 #define AR5K_TUNE_AIFS_XR 0 195 #define AR5K_TUNE_CWMIN 15 196 #define AR5K_TUNE_CWMIN_11B 31 197 #define AR5K_TUNE_CWMIN_XR 3 198 #define AR5K_TUNE_CWMAX 1023 199 #define AR5K_TUNE_CWMAX_11B 1023 200 #define AR5K_TUNE_CWMAX_XR 7 201 #define AR5K_TUNE_NOISE_FLOOR -72 202 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95 203 #define AR5K_TUNE_MAX_TXPOWER 63 204 #define AR5K_TUNE_DEFAULT_TXPOWER 25 205 #define AR5K_TUNE_TPC_TXPOWER false 206 #define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */ 207 #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */ 208 #define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */ 209 210 #define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */ 211 212 #define AR5K_INIT_CARR_SENSE_EN 1 213 214 /*Swap RX/TX Descriptor for big endian archs*/ 215 #if defined(__BIG_ENDIAN) 216 #define AR5K_INIT_CFG ( \ 217 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 218 ) 219 #else 220 #define AR5K_INIT_CFG 0x00000000 221 #endif 222 223 /* Initial values */ 224 #define AR5K_INIT_CYCRSSI_THR1 2 225 226 /* Tx retry limits */ 227 #define AR5K_INIT_SH_RETRY 10 228 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY 229 /* For station mode */ 230 #define AR5K_INIT_SSH_RETRY 32 231 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY 232 #define AR5K_INIT_TX_RETRY 10 233 234 235 /* Slot time */ 236 #define AR5K_INIT_SLOT_TIME_TURBO 6 237 #define AR5K_INIT_SLOT_TIME_DEFAULT 9 238 #define AR5K_INIT_SLOT_TIME_HALF_RATE 13 239 #define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21 240 #define AR5K_INIT_SLOT_TIME_B 20 241 #define AR5K_SLOT_TIME_MAX 0xffff 242 243 /* SIFS */ 244 #define AR5K_INIT_SIFS_TURBO 6 245 /* XXX: 8 from initvals 10 from standard */ 246 #define AR5K_INIT_SIFS_DEFAULT_BG 8 247 #define AR5K_INIT_SIFS_DEFAULT_A 16 248 #define AR5K_INIT_SIFS_HALF_RATE 32 249 #define AR5K_INIT_SIFS_QUARTER_RATE 64 250 251 /* Used to calculate tx time for non 5/10/40MHz 252 * operation */ 253 /* It's preamble time + signal time (16 + 4) */ 254 #define AR5K_INIT_OFDM_PREAMPLE_TIME 20 255 /* Preamble time for 40MHz (turbo) operation (min ?) */ 256 #define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14 257 #define AR5K_INIT_OFDM_SYMBOL_TIME 4 258 #define AR5K_INIT_OFDM_PLCP_BITS 22 259 260 /* Rx latency for 5 and 10MHz operation (max ?) */ 261 #define AR5K_INIT_RX_LAT_MAX 63 262 /* Tx latencies from initvals (5212 only but no problem 263 * because we only tweak them on 5212) */ 264 #define AR5K_INIT_TX_LAT_A 54 265 #define AR5K_INIT_TX_LAT_BG 384 266 /* Tx latency for 40MHz (turbo) operation (min ?) */ 267 #define AR5K_INIT_TX_LAT_MIN 32 268 /* Default Tx/Rx latencies (same for 5211)*/ 269 #define AR5K_INIT_TX_LATENCY_5210 54 270 #define AR5K_INIT_RX_LATENCY_5210 29 271 272 /* Tx frame to Tx data start delay */ 273 #define AR5K_INIT_TXF2TXD_START_DEFAULT 14 274 #define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12 275 #define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13 276 277 /* We need to increase PHY switch and agc settling time 278 * on turbo mode */ 279 #define AR5K_SWITCH_SETTLING 5760 280 #define AR5K_SWITCH_SETTLING_TURBO 7168 281 282 #define AR5K_AGC_SETTLING 28 283 /* 38 on 5210 but shouldn't matter */ 284 #define AR5K_AGC_SETTLING_TURBO 37 285 286 287 /* GENERIC CHIPSET DEFINITIONS */ 288 289 /* MAC Chips */ 290 enum ath5k_version { 291 AR5K_AR5210 = 0, 292 AR5K_AR5211 = 1, 293 AR5K_AR5212 = 2, 294 }; 295 296 /* PHY Chips */ 297 enum ath5k_radio { 298 AR5K_RF5110 = 0, 299 AR5K_RF5111 = 1, 300 AR5K_RF5112 = 2, 301 AR5K_RF2413 = 3, 302 AR5K_RF5413 = 4, 303 AR5K_RF2316 = 5, 304 AR5K_RF2317 = 6, 305 AR5K_RF2425 = 7, 306 }; 307 308 /* 309 * Common silicon revision/version values 310 */ 311 312 enum ath5k_srev_type { 313 AR5K_VERSION_MAC, 314 AR5K_VERSION_RAD, 315 }; 316 317 struct ath5k_srev_name { 318 const char *sr_name; 319 enum ath5k_srev_type sr_type; 320 u_int sr_val; 321 }; 322 323 #define AR5K_SREV_UNKNOWN 0xffff 324 325 #define AR5K_SREV_AR5210 0x00 /* Crete */ 326 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 327 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 328 #define AR5K_SREV_AR5311B 0x30 /* Spirit */ 329 #define AR5K_SREV_AR5211 0x40 /* Oahu */ 330 #define AR5K_SREV_AR5212 0x50 /* Venice */ 331 #define AR5K_SREV_AR5212_V4 0x54 /* ??? */ 332 #define AR5K_SREV_AR5213 0x55 /* ??? */ 333 #define AR5K_SREV_AR5213A 0x59 /* Hainan */ 334 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 335 #define AR5K_SREV_AR2414 0x70 /* Griffin */ 336 #define AR5K_SREV_AR5424 0x90 /* Condor */ 337 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 338 #define AR5K_SREV_AR5414 0xa0 /* Eagle */ 339 #define AR5K_SREV_AR2415 0xb0 /* Talon */ 340 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 341 #define AR5K_SREV_AR5418 0xca /* PCI-E */ 342 #define AR5K_SREV_AR2425 0xe0 /* Swan */ 343 #define AR5K_SREV_AR2417 0xf0 /* Nala */ 344 345 #define AR5K_SREV_RAD_5110 0x00 346 #define AR5K_SREV_RAD_5111 0x10 347 #define AR5K_SREV_RAD_5111A 0x15 348 #define AR5K_SREV_RAD_2111 0x20 349 #define AR5K_SREV_RAD_5112 0x30 350 #define AR5K_SREV_RAD_5112A 0x35 351 #define AR5K_SREV_RAD_5112B 0x36 352 #define AR5K_SREV_RAD_2112 0x40 353 #define AR5K_SREV_RAD_2112A 0x45 354 #define AR5K_SREV_RAD_2112B 0x46 355 #define AR5K_SREV_RAD_2413 0x50 356 #define AR5K_SREV_RAD_5413 0x60 357 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 358 #define AR5K_SREV_RAD_2317 0x80 359 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 360 #define AR5K_SREV_RAD_2425 0xa2 361 #define AR5K_SREV_RAD_5133 0xc0 362 363 #define AR5K_SREV_PHY_5211 0x30 364 #define AR5K_SREV_PHY_5212 0x41 365 #define AR5K_SREV_PHY_5212A 0x42 366 #define AR5K_SREV_PHY_5212B 0x43 367 #define AR5K_SREV_PHY_2413 0x45 368 #define AR5K_SREV_PHY_5413 0x61 369 #define AR5K_SREV_PHY_2425 0x70 370 371 /* TODO add support to mac80211 for vendor-specific rates and modes */ 372 373 /* 374 * Some of this information is based on Documentation from: 375 * 376 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 377 * 378 * Modulation for Atheros' eXtended Range - range enhancing extension that is 379 * supposed to double the distance an Atheros client device can keep a 380 * connection with an Atheros access point. This is achieved by increasing 381 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 382 * the 802.11 specifications demand. In addition, new (proprietary) data rates 383 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 384 * 385 * Please note that can you either use XR or TURBO but you cannot use both, 386 * they are exclusive. 387 * 388 */ 389 #define MODULATION_XR 0x00000200 390 /* 391 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 392 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 393 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 394 * channels. To use this feature your Access Point must also suport it. 395 * There is also a distinction between "static" and "dynamic" turbo modes: 396 * 397 * - Static: is the dumb version: devices set to this mode stick to it until 398 * the mode is turned off. 399 * - Dynamic: is the intelligent version, the network decides itself if it 400 * is ok to use turbo. As soon as traffic is detected on adjacent channels 401 * (which would get used in turbo mode), or when a non-turbo station joins 402 * the network, turbo mode won't be used until the situation changes again. 403 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 404 * monitors the used radio band in order to decide whether turbo mode may 405 * be used or not. 406 * 407 * This article claims Super G sticks to bonding of channels 5 and 6 for 408 * USA: 409 * 410 * http://www.pcworld.com/article/id,113428-page,1/article.html 411 * 412 * The channel bonding seems to be driver specific though. In addition to 413 * deciding what channels will be used, these "Turbo" modes are accomplished 414 * by also enabling the following features: 415 * 416 * - Bursting: allows multiple frames to be sent at once, rather than pausing 417 * after each frame. Bursting is a standards-compliant feature that can be 418 * used with any Access Point. 419 * - Fast frames: increases the amount of information that can be sent per 420 * frame, also resulting in a reduction of transmission overhead. It is a 421 * proprietary feature that needs to be supported by the Access Point. 422 * - Compression: data frames are compressed in real time using a Lempel Ziv 423 * algorithm. This is done transparently. Once this feature is enabled, 424 * compression and decompression takes place inside the chipset, without 425 * putting additional load on the host CPU. 426 * 427 */ 428 #define MODULATION_TURBO 0x00000080 429 430 enum ath5k_driver_mode { 431 AR5K_MODE_11A = 0, 432 AR5K_MODE_11A_TURBO = 1, 433 AR5K_MODE_11B = 2, 434 AR5K_MODE_11G = 3, 435 AR5K_MODE_11G_TURBO = 4, 436 AR5K_MODE_XR = 0, 437 AR5K_MODE_MAX = 5 438 }; 439 440 enum ath5k_ant_mode { 441 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 442 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 443 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 444 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 445 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 446 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 447 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 448 AR5K_ANTMODE_MAX, 449 }; 450 451 enum ath5k_bw_mode { 452 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */ 453 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */ 454 AR5K_BWMODE_10MHZ = 2, /* Half rate */ 455 AR5K_BWMODE_40MHZ = 3 /* Turbo */ 456 }; 457 458 /****************\ 459 TX DEFINITIONS 460 \****************/ 461 462 /* 463 * TX Status descriptor 464 */ 465 struct ath5k_tx_status { 466 u16 ts_seqnum; 467 u16 ts_tstamp; 468 u8 ts_status; 469 u8 ts_rate[4]; 470 u8 ts_retry[4]; 471 u8 ts_final_idx; 472 s8 ts_rssi; 473 u8 ts_shortretry; 474 u8 ts_longretry; 475 u8 ts_virtcol; 476 u8 ts_antenna; 477 }; 478 479 #define AR5K_TXSTAT_ALTRATE 0x80 480 #define AR5K_TXERR_XRETRY 0x01 481 #define AR5K_TXERR_FILT 0x02 482 #define AR5K_TXERR_FIFO 0x04 483 484 /** 485 * enum ath5k_tx_queue - Queue types used to classify tx queues. 486 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 487 * @AR5K_TX_QUEUE_DATA: A normal data queue 488 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 489 * @AR5K_TX_QUEUE_BEACON: The beacon queue 490 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 491 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 492 */ 493 enum ath5k_tx_queue { 494 AR5K_TX_QUEUE_INACTIVE = 0, 495 AR5K_TX_QUEUE_DATA, 496 AR5K_TX_QUEUE_XR_DATA, 497 AR5K_TX_QUEUE_BEACON, 498 AR5K_TX_QUEUE_CAB, 499 AR5K_TX_QUEUE_UAPSD, 500 }; 501 502 #define AR5K_NUM_TX_QUEUES 10 503 #define AR5K_NUM_TX_QUEUES_NOQCU 2 504 505 /* 506 * Queue syb-types to classify normal data queues. 507 * These are the 4 Access Categories as defined in 508 * WME spec. 0 is the lowest priority and 4 is the 509 * highest. Normal data that hasn't been classified 510 * goes to the Best Effort AC. 511 */ 512 enum ath5k_tx_queue_subtype { 513 AR5K_WME_AC_BK = 0, /*Background traffic*/ 514 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 515 AR5K_WME_AC_VI, /*Video traffic*/ 516 AR5K_WME_AC_VO, /*Voice traffic*/ 517 }; 518 519 /* 520 * Queue ID numbers as returned by the hw functions, each number 521 * represents a hw queue. If hw does not support hw queues 522 * (eg 5210) all data goes in one queue. These match 523 * d80211 definitions (net80211/MadWiFi don't use them). 524 */ 525 enum ath5k_tx_queue_id { 526 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 527 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 528 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 529 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ 530 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 531 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 532 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 533 AR5K_TX_QUEUE_ID_UAPSD = 8, 534 AR5K_TX_QUEUE_ID_XR_DATA = 9, 535 }; 536 537 /* 538 * Flags to set hw queue's parameters... 539 */ 540 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 541 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 542 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 543 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 544 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 545 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 546 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 547 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 548 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 549 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 550 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 551 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 552 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 553 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 554 555 /* 556 * A struct to hold tx queue's parameters 557 */ 558 struct ath5k_txq_info { 559 enum ath5k_tx_queue tqi_type; 560 enum ath5k_tx_queue_subtype tqi_subtype; 561 u16 tqi_flags; /* Tx queue flags (see above) */ 562 u8 tqi_aifs; /* Arbitrated Interframe Space */ 563 u16 tqi_cw_min; /* Minimum Contention Window */ 564 u16 tqi_cw_max; /* Maximum Contention Window */ 565 u32 tqi_cbr_period; /* Constant bit rate period */ 566 u32 tqi_cbr_overflow_limit; 567 u32 tqi_burst_time; 568 u32 tqi_ready_time; /* Time queue waits after an event */ 569 }; 570 571 /* 572 * Transmit packet types. 573 * used on tx control descriptor 574 */ 575 enum ath5k_pkt_type { 576 AR5K_PKT_TYPE_NORMAL = 0, 577 AR5K_PKT_TYPE_ATIM = 1, 578 AR5K_PKT_TYPE_PSPOLL = 2, 579 AR5K_PKT_TYPE_BEACON = 3, 580 AR5K_PKT_TYPE_PROBE_RESP = 4, 581 AR5K_PKT_TYPE_PIFS = 5, 582 }; 583 584 /* 585 * TX power and TPC settings 586 */ 587 #define AR5K_TXPOWER_OFDM(_r, _v) ( \ 588 ((0 & 1) << ((_v) + 6)) | \ 589 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 590 ) 591 592 #define AR5K_TXPOWER_CCK(_r, _v) ( \ 593 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 594 ) 595 596 /* 597 * DMA size definitions (2^(n+2)) 598 */ 599 enum ath5k_dmasize { 600 AR5K_DMASIZE_4B = 0, 601 AR5K_DMASIZE_8B, 602 AR5K_DMASIZE_16B, 603 AR5K_DMASIZE_32B, 604 AR5K_DMASIZE_64B, 605 AR5K_DMASIZE_128B, 606 AR5K_DMASIZE_256B, 607 AR5K_DMASIZE_512B 608 }; 609 610 611 /****************\ 612 RX DEFINITIONS 613 \****************/ 614 615 /* 616 * RX Status descriptor 617 */ 618 struct ath5k_rx_status { 619 u16 rs_datalen; 620 u16 rs_tstamp; 621 u8 rs_status; 622 u8 rs_phyerr; 623 s8 rs_rssi; 624 u8 rs_keyix; 625 u8 rs_rate; 626 u8 rs_antenna; 627 u8 rs_more; 628 }; 629 630 #define AR5K_RXERR_CRC 0x01 631 #define AR5K_RXERR_PHY 0x02 632 #define AR5K_RXERR_FIFO 0x04 633 #define AR5K_RXERR_DECRYPT 0x08 634 #define AR5K_RXERR_MIC 0x10 635 #define AR5K_RXKEYIX_INVALID ((u8) - 1) 636 #define AR5K_TXKEYIX_INVALID ((u32) - 1) 637 638 639 /**************************\ 640 BEACON TIMERS DEFINITIONS 641 \**************************/ 642 643 #define AR5K_BEACON_PERIOD 0x0000ffff 644 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 645 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 646 647 648 /* 649 * TSF to TU conversion: 650 * 651 * TSF is a 64bit value in usec (microseconds). 652 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 653 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 654 */ 655 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 656 657 658 /*******************************\ 659 GAIN OPTIMIZATION DEFINITIONS 660 \*******************************/ 661 662 enum ath5k_rfgain { 663 AR5K_RFGAIN_INACTIVE = 0, 664 AR5K_RFGAIN_ACTIVE, 665 AR5K_RFGAIN_READ_REQUESTED, 666 AR5K_RFGAIN_NEED_CHANGE, 667 }; 668 669 struct ath5k_gain { 670 u8 g_step_idx; 671 u8 g_current; 672 u8 g_target; 673 u8 g_low; 674 u8 g_high; 675 u8 g_f_corr; 676 u8 g_state; 677 }; 678 679 /********************\ 680 COMMON DEFINITIONS 681 \********************/ 682 683 #define AR5K_SLOT_TIME_9 396 684 #define AR5K_SLOT_TIME_20 880 685 #define AR5K_SLOT_TIME_MAX 0xffff 686 687 /* channel_flags */ 688 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ 689 #define CHANNEL_CCK 0x0020 /* CCK channel */ 690 #define CHANNEL_OFDM 0x0040 /* OFDM channel */ 691 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ 692 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ 693 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ 694 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 695 #define CHANNEL_XR 0x0800 /* XR channel */ 696 697 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 698 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 699 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 700 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 701 702 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ) 703 704 #define CHANNEL_MODES CHANNEL_ALL 705 706 /* 707 * Used internaly for reset_tx_queue). 708 * Also see struct struct ieee80211_channel. 709 */ 710 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) 711 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) 712 713 /* 714 * The following structure is used to map 2GHz channels to 715 * 5GHz Atheros channels. 716 * TODO: Clean up 717 */ 718 struct ath5k_athchan_2ghz { 719 u32 a2_flags; 720 u16 a2_athchan; 721 }; 722 723 724 /******************\ 725 RATE DEFINITIONS 726 \******************/ 727 728 /** 729 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. 730 * 731 * The rate code is used to get the RX rate or set the TX rate on the 732 * hardware descriptors. It is also used for internal modulation control 733 * and settings. 734 * 735 * This is the hardware rate map we are aware of: 736 * 737 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 738 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 739 * 740 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 741 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 742 * 743 * rate_code 17 18 19 20 21 22 23 24 744 * rate_kbps ? ? ? ? ? ? ? 11000 745 * 746 * rate_code 25 26 27 28 29 30 31 32 747 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 748 * 749 * "S" indicates CCK rates with short preamble. 750 * 751 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 752 * lowest 4 bits, so they are the same as below with a 0xF mask. 753 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 754 * We handle this in ath5k_setup_bands(). 755 */ 756 #define AR5K_MAX_RATES 32 757 758 /* B */ 759 #define ATH5K_RATE_CODE_1M 0x1B 760 #define ATH5K_RATE_CODE_2M 0x1A 761 #define ATH5K_RATE_CODE_5_5M 0x19 762 #define ATH5K_RATE_CODE_11M 0x18 763 /* A and G */ 764 #define ATH5K_RATE_CODE_6M 0x0B 765 #define ATH5K_RATE_CODE_9M 0x0F 766 #define ATH5K_RATE_CODE_12M 0x0A 767 #define ATH5K_RATE_CODE_18M 0x0E 768 #define ATH5K_RATE_CODE_24M 0x09 769 #define ATH5K_RATE_CODE_36M 0x0D 770 #define ATH5K_RATE_CODE_48M 0x08 771 #define ATH5K_RATE_CODE_54M 0x0C 772 /* XR */ 773 #define ATH5K_RATE_CODE_XR_500K 0x07 774 #define ATH5K_RATE_CODE_XR_1M 0x02 775 #define ATH5K_RATE_CODE_XR_2M 0x06 776 #define ATH5K_RATE_CODE_XR_3M 0x01 777 778 /* adding this flag to rate_code enables short preamble */ 779 #define AR5K_SET_SHORT_PREAMBLE 0x04 780 781 /* 782 * Crypto definitions 783 */ 784 785 #define AR5K_KEYCACHE_SIZE 8 786 787 /***********************\ 788 HW RELATED DEFINITIONS 789 \***********************/ 790 791 /* 792 * Misc definitions 793 */ 794 #define AR5K_RSSI_EP_MULTIPLIER (1<<7) 795 796 #define AR5K_ASSERT_ENTRY(_e, _s) do { \ 797 if (_e >= _s) \ 798 return (false); \ 799 } while (0) 800 801 /* 802 * Hardware interrupt abstraction 803 */ 804 805 /** 806 * enum ath5k_int - Hardware interrupt masks helpers 807 * 808 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 809 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 810 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 811 * @AR5K_INT_RXNOFRM: No frame received (?) 812 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 813 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 814 * LinkPtr is NULL. For more details, refer to: 815 * http://www.freepatentsonline.com/20030225739.html 816 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 817 * Note that Rx overrun is not always fatal, on some chips we can continue 818 * operation without reseting the card, that's why int_fatal is not 819 * common for all chips. 820 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 821 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 822 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 823 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 824 * We currently do increments on interrupt by 825 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 826 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 827 * one of the PHY error counters reached the maximum value and should be 828 * read and cleared. 829 * @AR5K_INT_RXPHY: RX PHY Error 830 * @AR5K_INT_RXKCM: RX Key cache miss 831 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 832 * beacon that must be handled in software. The alternative is if you 833 * have VEOL support, in that case you let the hardware deal with things. 834 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 835 * beacons from the AP have associated with, we should probably try to 836 * reassociate. When in IBSS mode this might mean we have not received 837 * any beacons from any local stations. Note that every station in an 838 * IBSS schedules to send beacons at the Target Beacon Transmission Time 839 * (TBTT) with a random backoff. 840 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 841 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 842 * until properly handled 843 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 844 * errors. These types of errors we can enable seem to be of type 845 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 846 * @AR5K_INT_GLOBAL: Used to clear and set the IER 847 * @AR5K_INT_NOCARD: signals the card has been removed 848 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same 849 * bit value 850 * 851 * These are mapped to take advantage of some common bits 852 * between the MACs, to be able to set intr properties 853 * easier. Some of them are not used yet inside hw.c. Most map 854 * to the respective hw interrupt value as they are common amogst different 855 * MACs. 856 */ 857 enum ath5k_int { 858 AR5K_INT_RXOK = 0x00000001, 859 AR5K_INT_RXDESC = 0x00000002, 860 AR5K_INT_RXERR = 0x00000004, 861 AR5K_INT_RXNOFRM = 0x00000008, 862 AR5K_INT_RXEOL = 0x00000010, 863 AR5K_INT_RXORN = 0x00000020, 864 AR5K_INT_TXOK = 0x00000040, 865 AR5K_INT_TXDESC = 0x00000080, 866 AR5K_INT_TXERR = 0x00000100, 867 AR5K_INT_TXNOFRM = 0x00000200, 868 AR5K_INT_TXEOL = 0x00000400, 869 AR5K_INT_TXURN = 0x00000800, 870 AR5K_INT_MIB = 0x00001000, 871 AR5K_INT_SWI = 0x00002000, 872 AR5K_INT_RXPHY = 0x00004000, 873 AR5K_INT_RXKCM = 0x00008000, 874 AR5K_INT_SWBA = 0x00010000, 875 AR5K_INT_BRSSI = 0x00020000, 876 AR5K_INT_BMISS = 0x00040000, 877 AR5K_INT_FATAL = 0x00080000, /* Non common */ 878 AR5K_INT_BNR = 0x00100000, /* Non common */ 879 AR5K_INT_TIM = 0x00200000, /* Non common */ 880 AR5K_INT_DTIM = 0x00400000, /* Non common */ 881 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 882 AR5K_INT_GPIO = 0x01000000, 883 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 884 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 885 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 886 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 887 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 888 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 889 AR5K_INT_GLOBAL = 0x80000000, 890 891 AR5K_INT_COMMON = AR5K_INT_RXOK 892 | AR5K_INT_RXDESC 893 | AR5K_INT_RXERR 894 | AR5K_INT_RXNOFRM 895 | AR5K_INT_RXEOL 896 | AR5K_INT_RXORN 897 | AR5K_INT_TXOK 898 | AR5K_INT_TXDESC 899 | AR5K_INT_TXERR 900 | AR5K_INT_TXNOFRM 901 | AR5K_INT_TXEOL 902 | AR5K_INT_TXURN 903 | AR5K_INT_MIB 904 | AR5K_INT_SWI 905 | AR5K_INT_RXPHY 906 | AR5K_INT_RXKCM 907 | AR5K_INT_SWBA 908 | AR5K_INT_BRSSI 909 | AR5K_INT_BMISS 910 | AR5K_INT_GPIO 911 | AR5K_INT_GLOBAL, 912 913 AR5K_INT_NOCARD = 0xffffffff 914 }; 915 916 /* mask which calibration is active at the moment */ 917 enum ath5k_calibration_mask { 918 AR5K_CALIBRATION_FULL = 0x01, 919 AR5K_CALIBRATION_SHORT = 0x02, 920 AR5K_CALIBRATION_ANI = 0x04, 921 }; 922 923 /* 924 * Power management 925 */ 926 enum ath5k_power_mode { 927 AR5K_PM_UNDEFINED = 0, 928 AR5K_PM_AUTO, 929 AR5K_PM_AWAKE, 930 AR5K_PM_FULL_SLEEP, 931 AR5K_PM_NETWORK_SLEEP, 932 }; 933 934 /* 935 * These match net80211 definitions (not used in 936 * mac80211). 937 * TODO: Clean this up 938 */ 939 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 940 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 941 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 942 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 943 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 944 945 /* GPIO-controlled software LED */ 946 #define AR5K_SOFTLED_PIN 0 947 #define AR5K_SOFTLED_ON 0 948 #define AR5K_SOFTLED_OFF 1 949 950 /* 951 * Chipset capabilities -see ath5k_hw_get_capability- 952 * get_capability function is not yet fully implemented 953 * in ath5k so most of these don't work yet... 954 * TODO: Implement these & merge with _TUNE_ stuff above 955 */ 956 enum ath5k_capability_type { 957 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 958 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 959 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 960 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 961 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 962 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 963 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 964 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 965 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 966 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 967 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 968 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 969 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 970 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 971 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 972 AR5K_CAP_XR = 16, /* Supports XR mode */ 973 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 974 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 975 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 976 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 977 }; 978 979 980 /* XXX: we *may* move cap_range stuff to struct wiphy */ 981 struct ath5k_capabilities { 982 /* 983 * Supported PHY modes 984 * (ie. CHANNEL_A, CHANNEL_B, ...) 985 */ 986 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 987 988 /* 989 * Frequency range (without regulation restrictions) 990 */ 991 struct { 992 u16 range_2ghz_min; 993 u16 range_2ghz_max; 994 u16 range_5ghz_min; 995 u16 range_5ghz_max; 996 } cap_range; 997 998 /* 999 * Values stored in the EEPROM (some of them...) 1000 */ 1001 struct ath5k_eeprom_info cap_eeprom; 1002 1003 /* 1004 * Queue information 1005 */ 1006 struct { 1007 u8 q_tx_num; 1008 } cap_queues; 1009 1010 bool cap_has_phyerr_counters; 1011 }; 1012 1013 /* size of noise floor history (keep it a power of two) */ 1014 #define ATH5K_NF_CAL_HIST_MAX 8 1015 struct ath5k_nfcal_hist 1016 { 1017 s16 index; /* current index into nfval */ 1018 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ 1019 }; 1020 1021 /** 1022 * struct avg_val - Helper structure for average calculation 1023 * @avg: contains the actual average value 1024 * @avg_weight: is used internally during calculation to prevent rounding errors 1025 */ 1026 struct ath5k_avg_val { 1027 int avg; 1028 int avg_weight; 1029 }; 1030 1031 /***************************************\ 1032 HARDWARE ABSTRACTION LAYER STRUCTURE 1033 \***************************************/ 1034 1035 /* 1036 * Misc defines 1037 */ 1038 1039 #define AR5K_MAX_GPIO 10 1040 #define AR5K_MAX_RF_BANKS 8 1041 1042 /* TODO: Clean up and merge with ath5k_softc */ 1043 struct ath5k_hw { 1044 struct ath_common common; 1045 1046 struct ath5k_softc *ah_sc; 1047 void __iomem *ah_iobase; 1048 1049 enum ath5k_int ah_imr; 1050 1051 struct ieee80211_channel *ah_current_channel; 1052 bool ah_calibration; 1053 bool ah_single_chip; 1054 1055 enum ath5k_version ah_version; 1056 enum ath5k_radio ah_radio; 1057 u32 ah_phy; 1058 u32 ah_mac_srev; 1059 u16 ah_mac_version; 1060 u16 ah_phy_revision; 1061 u16 ah_radio_5ghz_revision; 1062 u16 ah_radio_2ghz_revision; 1063 1064 #define ah_modes ah_capabilities.cap_mode 1065 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1066 1067 u32 ah_limit_tx_retries; 1068 u8 ah_coverage_class; 1069 bool ah_ack_bitrate_high; 1070 u8 ah_bwmode; 1071 1072 /* Antenna Control */ 1073 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1074 u8 ah_ant_mode; 1075 u8 ah_tx_ant; 1076 u8 ah_def_ant; 1077 bool ah_software_retry; 1078 1079 struct ath5k_capabilities ah_capabilities; 1080 1081 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1082 u32 ah_txq_status; 1083 u32 ah_txq_imr_txok; 1084 u32 ah_txq_imr_txerr; 1085 u32 ah_txq_imr_txurn; 1086 u32 ah_txq_imr_txdesc; 1087 u32 ah_txq_imr_txeol; 1088 u32 ah_txq_imr_cbrorn; 1089 u32 ah_txq_imr_cbrurn; 1090 u32 ah_txq_imr_qtrig; 1091 u32 ah_txq_imr_nofrm; 1092 u32 ah_txq_isr; 1093 u32 *ah_rf_banks; 1094 size_t ah_rf_banks_size; 1095 size_t ah_rf_regs_count; 1096 struct ath5k_gain ah_gain; 1097 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1098 1099 1100 struct { 1101 /* Temporary tables used for interpolation */ 1102 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1103 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1104 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1105 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1106 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1107 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1108 u8 txp_min_idx; 1109 bool txp_tpc; 1110 /* Values in 0.25dB units */ 1111 s16 txp_min_pwr; 1112 s16 txp_max_pwr; 1113 /* Values in 0.5dB units */ 1114 s16 txp_offset; 1115 s16 txp_ofdm; 1116 s16 txp_cck_ofdm_gainf_delta; 1117 /* Value in dB units */ 1118 s16 txp_cck_ofdm_pwr_delta; 1119 } ah_txpower; 1120 1121 struct { 1122 bool r_enabled; 1123 int r_last_alert; 1124 struct ieee80211_channel r_last_channel; 1125 } ah_radar; 1126 1127 struct ath5k_nfcal_hist ah_nfcal_hist; 1128 1129 /* average beacon RSSI in our BSS (used by ANI) */ 1130 struct ewma ah_beacon_rssi_avg; 1131 1132 /* noise floor from last periodic calibration */ 1133 s32 ah_noise_floor; 1134 1135 /* Calibration timestamp */ 1136 unsigned long ah_cal_next_full; 1137 unsigned long ah_cal_next_ani; 1138 unsigned long ah_cal_next_nf; 1139 1140 /* Calibration mask */ 1141 u8 ah_cal_mask; 1142 1143 /* 1144 * Function pointers 1145 */ 1146 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1147 unsigned int, unsigned int, int, enum ath5k_pkt_type, 1148 unsigned int, unsigned int, unsigned int, unsigned int, 1149 unsigned int, unsigned int, unsigned int, unsigned int); 1150 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1151 struct ath5k_tx_status *); 1152 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1153 struct ath5k_rx_status *); 1154 }; 1155 1156 /* 1157 * Prototypes 1158 */ 1159 1160 /* Attach/Detach Functions */ 1161 int ath5k_hw_attach(struct ath5k_softc *sc); 1162 void ath5k_hw_detach(struct ath5k_hw *ah); 1163 1164 int ath5k_sysfs_register(struct ath5k_softc *sc); 1165 void ath5k_sysfs_unregister(struct ath5k_softc *sc); 1166 1167 1168 /* LED functions */ 1169 int ath5k_init_leds(struct ath5k_softc *sc); 1170 void ath5k_led_enable(struct ath5k_softc *sc); 1171 void ath5k_led_off(struct ath5k_softc *sc); 1172 void ath5k_unregister_leds(struct ath5k_softc *sc); 1173 1174 1175 /* Reset Functions */ 1176 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1177 int ath5k_hw_on_hold(struct ath5k_hw *ah); 1178 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1179 struct ieee80211_channel *channel, bool fast, bool skip_pcu); 1180 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 1181 bool is_set); 1182 /* Power management functions */ 1183 1184 1185 /* Clock rate related functions */ 1186 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); 1187 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1188 void ath5k_hw_set_clockrate(struct ath5k_hw *ah); 1189 1190 1191 /* DMA Related Functions */ 1192 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1193 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1194 int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1195 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1196 int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue); 1197 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1198 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1199 u32 phys_addr); 1200 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1201 /* Interrupt handling */ 1202 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1203 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1204 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); 1205 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); 1206 /* Init/Stop functions */ 1207 void ath5k_hw_dma_init(struct ath5k_hw *ah); 1208 int ath5k_hw_dma_stop(struct ath5k_hw *ah); 1209 1210 /* EEPROM access functions */ 1211 int ath5k_eeprom_init(struct ath5k_hw *ah); 1212 void ath5k_eeprom_detach(struct ath5k_hw *ah); 1213 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); 1214 1215 1216 /* Protocol Control Unit Functions */ 1217 /* Helpers */ 1218 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 1219 int len, struct ieee80211_rate *rate); 1220 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah); 1221 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah); 1222 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); 1223 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1224 /* RX filter control*/ 1225 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1226 void ath5k_hw_set_bssid(struct ath5k_hw *ah); 1227 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1228 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1229 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1230 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1231 /* Receive (DRU) start/stop functions */ 1232 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1233 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1234 /* Beacon control functions */ 1235 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1236 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1237 void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1238 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1239 bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); 1240 /* Init function */ 1241 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1242 u8 mode); 1243 1244 /* Queue Control Unit, DFS Control Unit Functions */ 1245 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 1246 struct ath5k_txq_info *queue_info); 1247 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1248 const struct ath5k_txq_info *queue_info); 1249 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1250 enum ath5k_tx_queue queue_type, 1251 struct ath5k_txq_info *queue_info); 1252 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1253 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1254 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1255 int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time); 1256 /* Init function */ 1257 int ath5k_hw_init_queues(struct ath5k_hw *ah); 1258 1259 /* Hardware Descriptor Functions */ 1260 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1261 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1262 u32 size, unsigned int flags); 1263 int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1264 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, 1265 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); 1266 1267 1268 /* GPIO Functions */ 1269 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1270 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1271 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1272 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1273 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1274 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, 1275 u32 interrupt_level); 1276 1277 1278 /* RFkill Functions */ 1279 void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1280 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1281 1282 1283 /* Misc functions TODO: Cleanup */ 1284 int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1285 int ath5k_hw_get_capability(struct ath5k_hw *ah, 1286 enum ath5k_capability_type cap_type, u32 capability, 1287 u32 *result); 1288 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1289 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1290 1291 1292 /* Initial register settings functions */ 1293 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1294 1295 1296 /* PHY functions */ 1297 /* Misc PHY functions */ 1298 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1299 int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1300 /* Gain_F optimization */ 1301 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1302 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1303 /* PHY/RF channel functions */ 1304 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1305 /* PHY calibration */ 1306 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); 1307 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1308 struct ieee80211_channel *channel); 1309 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); 1310 /* Spur mitigation */ 1311 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1312 struct ieee80211_channel *channel); 1313 /* Antenna control */ 1314 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1315 void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); 1316 /* TX power setup */ 1317 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1318 /* Init function */ 1319 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 1320 u8 mode, u8 ee_mode, u8 freq, bool fast); 1321 1322 /* 1323 * Functions used internaly 1324 */ 1325 1326 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) 1327 { 1328 return &ah->common; 1329 } 1330 1331 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) 1332 { 1333 return &(ath5k_hw_common(ah)->regulatory); 1334 } 1335 1336 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1337 { 1338 return ioread32(ah->ah_iobase + reg); 1339 } 1340 1341 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1342 { 1343 iowrite32(val, ah->ah_iobase + reg); 1344 } 1345 1346 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1347 { 1348 u32 retval = 0, bit, i; 1349 1350 for (i = 0; i < bits; i++) { 1351 bit = (val >> i) & 1; 1352 retval = (retval << 1) | bit; 1353 } 1354 1355 return retval; 1356 } 1357 1358 #endif 1359