1*d8899132SKalle Valo /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2*d8899132SKalle Valo /* 3*d8899132SKalle Valo * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4*d8899132SKalle Valo * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5*d8899132SKalle Valo */ 6*d8899132SKalle Valo 7*d8899132SKalle Valo #ifndef ATH12K_DP_MON_H 8*d8899132SKalle Valo #define ATH12K_DP_MON_H 9*d8899132SKalle Valo 10*d8899132SKalle Valo #include "core.h" 11*d8899132SKalle Valo 12*d8899132SKalle Valo enum dp_monitor_mode { 13*d8899132SKalle Valo ATH12K_DP_TX_MONITOR_MODE, 14*d8899132SKalle Valo ATH12K_DP_RX_MONITOR_MODE 15*d8899132SKalle Valo }; 16*d8899132SKalle Valo 17*d8899132SKalle Valo enum dp_mon_tx_ppdu_info_type { 18*d8899132SKalle Valo DP_MON_TX_PROT_PPDU_INFO, 19*d8899132SKalle Valo DP_MON_TX_DATA_PPDU_INFO 20*d8899132SKalle Valo }; 21*d8899132SKalle Valo 22*d8899132SKalle Valo enum dp_mon_tx_tlv_status { 23*d8899132SKalle Valo DP_MON_TX_FES_SETUP, 24*d8899132SKalle Valo DP_MON_TX_FES_STATUS_END, 25*d8899132SKalle Valo DP_MON_RX_RESPONSE_REQUIRED_INFO, 26*d8899132SKalle Valo DP_MON_RESPONSE_END_STATUS_INFO, 27*d8899132SKalle Valo DP_MON_TX_MPDU_START, 28*d8899132SKalle Valo DP_MON_TX_MSDU_START, 29*d8899132SKalle Valo DP_MON_TX_BUFFER_ADDR, 30*d8899132SKalle Valo DP_MON_TX_DATA, 31*d8899132SKalle Valo DP_MON_TX_STATUS_PPDU_NOT_DONE, 32*d8899132SKalle Valo }; 33*d8899132SKalle Valo 34*d8899132SKalle Valo enum dp_mon_tx_medium_protection_type { 35*d8899132SKalle Valo DP_MON_TX_MEDIUM_NO_PROTECTION, 36*d8899132SKalle Valo DP_MON_TX_MEDIUM_RTS_LEGACY, 37*d8899132SKalle Valo DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW, 38*d8899132SKalle Valo DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW, 39*d8899132SKalle Valo DP_MON_TX_MEDIUM_CTS2SELF, 40*d8899132SKalle Valo DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR, 41*d8899132SKalle Valo DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR 42*d8899132SKalle Valo }; 43*d8899132SKalle Valo 44*d8899132SKalle Valo struct dp_mon_qosframe_addr4 { 45*d8899132SKalle Valo __le16 frame_control; 46*d8899132SKalle Valo __le16 duration; 47*d8899132SKalle Valo u8 addr1[ETH_ALEN]; 48*d8899132SKalle Valo u8 addr2[ETH_ALEN]; 49*d8899132SKalle Valo u8 addr3[ETH_ALEN]; 50*d8899132SKalle Valo __le16 seq_ctrl; 51*d8899132SKalle Valo u8 addr4[ETH_ALEN]; 52*d8899132SKalle Valo __le16 qos_ctrl; 53*d8899132SKalle Valo } __packed; 54*d8899132SKalle Valo 55*d8899132SKalle Valo struct dp_mon_frame_min_one { 56*d8899132SKalle Valo __le16 frame_control; 57*d8899132SKalle Valo __le16 duration; 58*d8899132SKalle Valo u8 addr1[ETH_ALEN]; 59*d8899132SKalle Valo } __packed; 60*d8899132SKalle Valo 61*d8899132SKalle Valo struct dp_mon_packet_info { 62*d8899132SKalle Valo u64 cookie; 63*d8899132SKalle Valo u16 dma_length; 64*d8899132SKalle Valo bool msdu_continuation; 65*d8899132SKalle Valo bool truncated; 66*d8899132SKalle Valo }; 67*d8899132SKalle Valo 68*d8899132SKalle Valo struct dp_mon_tx_ppdu_info { 69*d8899132SKalle Valo u32 ppdu_id; 70*d8899132SKalle Valo u8 num_users; 71*d8899132SKalle Valo bool is_used; 72*d8899132SKalle Valo struct hal_rx_mon_ppdu_info rx_status; 73*d8899132SKalle Valo struct list_head dp_tx_mon_mpdu_list; 74*d8899132SKalle Valo struct dp_mon_mpdu *tx_mon_mpdu; 75*d8899132SKalle Valo }; 76*d8899132SKalle Valo 77*d8899132SKalle Valo enum hal_rx_mon_status 78*d8899132SKalle Valo ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar, 79*d8899132SKalle Valo struct ath12k_mon_data *pmon, 80*d8899132SKalle Valo int mac_id, struct sk_buff *skb, 81*d8899132SKalle Valo struct napi_struct *napi); 82*d8899132SKalle Valo int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab, 83*d8899132SKalle Valo struct dp_rxdma_ring *buf_ring, 84*d8899132SKalle Valo int req_entries); 85*d8899132SKalle Valo int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, 86*d8899132SKalle Valo int *budget, enum dp_monitor_mode monitor_mode, 87*d8899132SKalle Valo struct napi_struct *napi); 88*d8899132SKalle Valo int ath12k_dp_mon_process_ring(struct ath12k_base *ab, int mac_id, 89*d8899132SKalle Valo struct napi_struct *napi, int budget, 90*d8899132SKalle Valo enum dp_monitor_mode monitor_mode); 91*d8899132SKalle Valo struct sk_buff *ath12k_dp_mon_tx_alloc_skb(void); 92*d8899132SKalle Valo enum dp_mon_tx_tlv_status 93*d8899132SKalle Valo ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag, 94*d8899132SKalle Valo struct hal_tlv_hdr *tx_tlv, 95*d8899132SKalle Valo u8 *num_users); 96*d8899132SKalle Valo enum hal_rx_mon_status 97*d8899132SKalle Valo ath12k_dp_mon_tx_parse_mon_status(struct ath12k *ar, 98*d8899132SKalle Valo struct ath12k_mon_data *pmon, 99*d8899132SKalle Valo int mac_id, 100*d8899132SKalle Valo struct sk_buff *skb, 101*d8899132SKalle Valo struct napi_struct *napi, 102*d8899132SKalle Valo u32 ppdu_id); 103*d8899132SKalle Valo void ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info *ppdu_info); 104*d8899132SKalle Valo int ath12k_dp_mon_rx_process_stats(struct ath12k *ar, int mac_id, 105*d8899132SKalle Valo struct napi_struct *napi, int *budget); 106*d8899132SKalle Valo #endif 107