1*d8899132SKalle Valo /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2*d8899132SKalle Valo /* 3*d8899132SKalle Valo * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4*d8899132SKalle Valo * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5*d8899132SKalle Valo */ 6*d8899132SKalle Valo 7*d8899132SKalle Valo #ifndef ATH12K_DBRING_H 8*d8899132SKalle Valo #define ATH12K_DBRING_H 9*d8899132SKalle Valo 10*d8899132SKalle Valo #include <linux/types.h> 11*d8899132SKalle Valo #include <linux/idr.h> 12*d8899132SKalle Valo #include <linux/spinlock.h> 13*d8899132SKalle Valo #include "dp.h" 14*d8899132SKalle Valo 15*d8899132SKalle Valo struct ath12k_dbring_element { 16*d8899132SKalle Valo dma_addr_t paddr; 17*d8899132SKalle Valo u8 payload[]; 18*d8899132SKalle Valo }; 19*d8899132SKalle Valo 20*d8899132SKalle Valo struct ath12k_dbring_data { 21*d8899132SKalle Valo void *data; 22*d8899132SKalle Valo u32 data_sz; 23*d8899132SKalle Valo struct ath12k_wmi_dma_buf_release_meta_data_params meta; 24*d8899132SKalle Valo }; 25*d8899132SKalle Valo 26*d8899132SKalle Valo struct ath12k_dbring_buf_release_event { 27*d8899132SKalle Valo struct ath12k_wmi_dma_buf_release_fixed_params fixed; 28*d8899132SKalle Valo const struct ath12k_wmi_dma_buf_release_entry_params *buf_entry; 29*d8899132SKalle Valo const struct ath12k_wmi_dma_buf_release_meta_data_params *meta_data; 30*d8899132SKalle Valo u32 num_buf_entry; 31*d8899132SKalle Valo u32 num_meta; 32*d8899132SKalle Valo }; 33*d8899132SKalle Valo 34*d8899132SKalle Valo struct ath12k_dbring_cap { 35*d8899132SKalle Valo u32 pdev_id; 36*d8899132SKalle Valo enum wmi_direct_buffer_module id; 37*d8899132SKalle Valo u32 min_elem; 38*d8899132SKalle Valo u32 min_buf_sz; 39*d8899132SKalle Valo u32 min_buf_align; 40*d8899132SKalle Valo }; 41*d8899132SKalle Valo 42*d8899132SKalle Valo struct ath12k_dbring { 43*d8899132SKalle Valo struct dp_srng refill_srng; 44*d8899132SKalle Valo struct idr bufs_idr; 45*d8899132SKalle Valo /* Protects bufs_idr */ 46*d8899132SKalle Valo spinlock_t idr_lock; 47*d8899132SKalle Valo dma_addr_t tp_addr; 48*d8899132SKalle Valo dma_addr_t hp_addr; 49*d8899132SKalle Valo int bufs_max; 50*d8899132SKalle Valo u32 pdev_id; 51*d8899132SKalle Valo u32 buf_sz; 52*d8899132SKalle Valo u32 buf_align; 53*d8899132SKalle Valo u32 num_resp_per_event; 54*d8899132SKalle Valo u32 event_timeout_ms; 55*d8899132SKalle Valo int (*handler)(struct ath12k *ar, struct ath12k_dbring_data *data); 56*d8899132SKalle Valo }; 57*d8899132SKalle Valo 58*d8899132SKalle Valo int ath12k_dbring_set_cfg(struct ath12k *ar, 59*d8899132SKalle Valo struct ath12k_dbring *ring, 60*d8899132SKalle Valo u32 num_resp_per_event, 61*d8899132SKalle Valo u32 event_timeout_ms, 62*d8899132SKalle Valo int (*handler)(struct ath12k *, 63*d8899132SKalle Valo struct ath12k_dbring_data *)); 64*d8899132SKalle Valo int ath12k_dbring_wmi_cfg_setup(struct ath12k *ar, 65*d8899132SKalle Valo struct ath12k_dbring *ring, 66*d8899132SKalle Valo enum wmi_direct_buffer_module id); 67*d8899132SKalle Valo int ath12k_dbring_buf_setup(struct ath12k *ar, 68*d8899132SKalle Valo struct ath12k_dbring *ring, 69*d8899132SKalle Valo struct ath12k_dbring_cap *db_cap); 70*d8899132SKalle Valo int ath12k_dbring_srng_setup(struct ath12k *ar, struct ath12k_dbring *ring, 71*d8899132SKalle Valo int ring_num, int num_entries); 72*d8899132SKalle Valo int ath12k_dbring_buffer_release_event(struct ath12k_base *ab, 73*d8899132SKalle Valo struct ath12k_dbring_buf_release_event *ev); 74*d8899132SKalle Valo int ath12k_dbring_get_cap(struct ath12k_base *ab, 75*d8899132SKalle Valo u8 pdev_idx, 76*d8899132SKalle Valo enum wmi_direct_buffer_module id, 77*d8899132SKalle Valo struct ath12k_dbring_cap *db_cap); 78*d8899132SKalle Valo void ath12k_dbring_srng_cleanup(struct ath12k *ar, struct ath12k_dbring *ring); 79*d8899132SKalle Valo void ath12k_dbring_buf_cleanup(struct ath12k *ar, struct ath12k_dbring *ring); 80*d8899132SKalle Valo #endif /* ATH12K_DBRING_H */ 81